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61 SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
63 *******************************************************************************/
65 #include "gpp/mvGpp.h"
66 #include "ctrlEnv/mvCtrlEnvLib.h"
74 static MV_VOID
gppRegSet(MV_U32 group
, MV_U32 regOffs
,MV_U32 mask
,MV_U32 value
);
76 /*******************************************************************************
77 * mvGppTypeSet - Enable a GPP (OUT) pin
82 * group - GPP group number
83 * mask - 32bit mask value. Each set bit in the mask means that the type
84 * of corresponding GPP will be set. Other GPPs are ignored.
85 * value - 32bit value that describes GPP type per pin.
91 * Set GPP8 to input and GPP15 to output.
92 * mvGppTypeSet(0, (GPP8 | GPP15),
93 * ((MV_GPP_IN & GPP8) | (MV_GPP_OUT & GPP15)) );
98 *******************************************************************************/
99 MV_STATUS
mvGppTypeSet(MV_U32 group
, MV_U32 mask
, MV_U32 value
)
101 if (group
>= MV_GPP_MAX_GROUP
)
103 DB(mvOsPrintf("mvGppTypeSet: ERR. invalid group number \n"));
107 gppRegSet(group
, GPP_DATA_OUT_EN_REG(group
), mask
, value
);
109 /* Workaround for Erratum FE-MISC-70*/
110 if(mvCtrlRevGet()==MV_88F6XXX_A0_REV
&& (group
== 1))
113 gppRegSet(0, GPP_DATA_OUT_EN_REG(0), mask
, value
);
120 /*******************************************************************************
121 * mvGppBlinkEn - Set a GPP (IN) Pin list to blink every ~100ms
126 * group - GPP group number
127 * mask - 32bit mask value. Each set bit in the mask means that the type
128 * of corresponding GPP will be set. Other GPPs are ignored.
129 * value - 32bit value that describes GPP blink per pin.
135 * Set GPP8 to be static and GPP15 to be blinking.
136 * mvGppBlinkEn(0, (GPP8 | GPP15),
137 * ((MV_GPP_OUT_STATIC & GPP8) | (MV_GPP_OUT_BLINK & GPP15)) );
142 *******************************************************************************/
143 MV_STATUS
mvGppBlinkEn(MV_U32 group
, MV_U32 mask
, MV_U32 value
)
145 if (group
>= MV_GPP_MAX_GROUP
)
147 DB(mvOsPrintf("mvGppBlinkEn: ERR. invalid group number \n"));
151 gppRegSet(group
, GPP_BLINK_EN_REG(group
), mask
, value
);
156 /*******************************************************************************
157 * mvGppPolaritySet - Set a GPP (IN) Pin list Polarity mode
162 * group - GPP group number
163 * mask - 32bit mask value. Each set bit in the mask means that the type
164 * of corresponding GPP will be set. Other GPPs are ignored.
165 * value - 32bit value that describes GPP polarity per pin.
171 * Set GPP8 to the actual pin value and GPP15 to be inverted.
172 * mvGppPolaritySet(0, (GPP8 | GPP15),
173 * ((MV_GPP_IN_ORIGIN & GPP8) | (MV_GPP_IN_INVERT & GPP15)) );
178 *******************************************************************************/
179 MV_STATUS
mvGppPolaritySet(MV_U32 group
, MV_U32 mask
, MV_U32 value
)
181 if (group
>= MV_GPP_MAX_GROUP
)
183 DB(mvOsPrintf("mvGppPolaritySet: ERR. invalid group number \n"));
187 gppRegSet(group
, GPP_DATA_IN_POL_REG(group
), mask
, value
);
193 /*******************************************************************************
194 * mvGppPolarityGet - Get a value of relevant bits from GPP Polarity register.
199 * group - GPP group number
200 * mask - 32bit mask value. Each set bit in the mask means that the
201 * returned value is valid for it.
207 * Get GPP8 and GPP15 value.
208 * mvGppPolarityGet(0, (GPP8 | GPP15));
211 * 32bit value that describes GPP polatity mode per pin.
213 *******************************************************************************/
214 MV_U32
mvGppPolarityGet(MV_U32 group
, MV_U32 mask
)
218 if (group
>= MV_GPP_MAX_GROUP
)
220 DB(mvOsPrintf("mvGppActiveSet: Error invalid group number \n"));
223 regVal
= MV_REG_READ(GPP_DATA_IN_POL_REG(group
));
225 return (regVal
& mask
);
228 /*******************************************************************************
229 * mvGppValueGet - Get a GPP Pin list value.
232 * This function get GPP value.
235 * group - GPP group number
236 * mask - 32bit mask value. Each set bit in the mask means that the
237 * returned value is valid for it.
243 * Get GPP8 and GPP15 value.
244 * mvGppValueGet(0, (GPP8 | GPP15));
247 * 32bit value that describes GPP activity mode per pin.
249 *******************************************************************************/
250 MV_U32
mvGppValueGet(MV_U32 group
, MV_U32 mask
)
254 gppData
= MV_REG_READ(GPP_DATA_IN_REG(group
));
262 /*******************************************************************************
263 * mvGppValueSet - Set a GPP Pin list value.
266 * This function set value for given GPP pin list.
269 * group - GPP group number
270 * mask - 32bit mask value. Each set bit in the mask means that the
271 * value of corresponding GPP will be set accordingly. Other GPP
273 * value - 32bit value that describes GPP value per pin.
279 * Set GPP8 value of '0' and GPP15 value of '1'.
280 * mvGppActiveSet(0, (GPP8 | GPP15), ((0 & GPP8) | (GPP15)) );
285 *******************************************************************************/
286 MV_STATUS
mvGppValueSet (MV_U32 group
, MV_U32 mask
, MV_U32 value
)
288 MV_U32 outEnable
, tmp
;
291 if (group
>= MV_GPP_MAX_GROUP
)
293 DB(mvOsPrintf("mvGppValueSet: Error invalid group number \n"));
297 /* verify that the gpp pin is configured as output */
298 /* Note that in the register out enabled -> bit = '0'. */
299 outEnable
= ~MV_REG_READ(GPP_DATA_OUT_EN_REG(group
));
301 /* Workaround for Erratum FE-MISC-70*/
302 if(mvCtrlRevGet()==MV_88F6XXX_A0_REV
&& (group
== 1))
304 tmp
= ~MV_REG_READ(GPP_DATA_OUT_EN_REG(0));
305 outEnable
&= 0xfffffffd;
306 outEnable
|= (tmp
& 0x2);
309 for (i
= 0 ; i
< 32 ;i
++)
311 if (((mask
& (1 << i
)) & (outEnable
& (1 << i
))) != (mask
& (1 << i
)))
313 mvOsPrintf("mvGppValueSet: Err. An attempt to set output "\
314 "value to GPP %d in input mode.\n", i
);
319 gppRegSet(group
, GPP_DATA_OUT_REG(group
), mask
, value
);
324 /*******************************************************************************
325 * gppRegSet - Set a specific GPP pin on a specific GPP register
328 * This function set a specific GPP pin on a specific GPP register
331 * regOffs - GPP Register offset
332 * group - GPP group number
333 * mask - 32bit mask value. Each set bit in the mask means that the
334 * value of corresponding GPP will be set accordingly. Other GPP
336 * value - 32bit value that describes GPP value per pin.
342 * Set GPP8 value of '0' and GPP15 value of '1'.
343 * mvGppActiveSet(0, (GPP8 | GPP15), ((0 & GPP8) | (1 & GPP15)) );
348 *******************************************************************************/
349 static MV_VOID
gppRegSet (MV_U32 group
, MV_U32 regOffs
,MV_U32 mask
,MV_U32 value
)
353 gppData
= MV_REG_READ(regOffs
);
357 gppData
|= (value
& mask
);
359 MV_REG_WRITE(regOffs
, gppData
);