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028b98fc4015d3871a2ebd7a65f330aac6039682
[openwrt/staging/wigyori.git] / target / linux / generic / files / drivers / net / phy / ar8216.c
1 /*
2 * ar8216.c: AR8216 switch driver
3 *
4 * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18 #include <linux/if.h>
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/list.h>
22 #include <linux/if_ether.h>
23 #include <linux/skbuff.h>
24 #include <linux/netdevice.h>
25 #include <linux/netlink.h>
26 #include <linux/bitops.h>
27 #include <net/genetlink.h>
28 #include <linux/switch.h>
29 #include <linux/delay.h>
30 #include <linux/phy.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/lockdep.h>
34 #include <linux/ar8216_platform.h>
35 #include <linux/workqueue.h>
36 #include <linux/of_device.h>
37 #include <linux/leds.h>
38 #include <linux/gpio.h>
39 #include <linux/version.h>
40
41 #include "ar8216.h"
42
43 /* size of the vlan table */
44 #define AR8X16_MAX_VLANS 128
45 #define AR8X16_PROBE_RETRIES 10
46 #define AR8X16_MAX_PORTS 8
47
48 #define AR8XXX_MIB_WORK_DELAY 2000 /* msecs */
49
50 struct ar8xxx_priv;
51
52 #define AR8XXX_CAP_GIGE BIT(0)
53 #define AR8XXX_CAP_MIB_COUNTERS BIT(1)
54
55 #define AR8XXX_NUM_PHYS 5
56
57 enum {
58 AR8XXX_VER_AR8216 = 0x01,
59 AR8XXX_VER_AR8236 = 0x03,
60 AR8XXX_VER_AR8316 = 0x10,
61 AR8XXX_VER_AR8327 = 0x12,
62 AR8XXX_VER_AR8337 = 0x13,
63 };
64
65 struct ar8xxx_mib_desc {
66 unsigned int size;
67 unsigned int offset;
68 const char *name;
69 };
70
71 struct ar8xxx_chip {
72 unsigned long caps;
73 bool config_at_probe;
74
75 int (*hw_init)(struct ar8xxx_priv *priv);
76 void (*cleanup)(struct ar8xxx_priv *priv);
77
78 void (*init_globals)(struct ar8xxx_priv *priv);
79 void (*init_port)(struct ar8xxx_priv *priv, int port);
80 void (*setup_port)(struct ar8xxx_priv *priv, int port, u32 members);
81 u32 (*read_port_status)(struct ar8xxx_priv *priv, int port);
82 int (*atu_flush)(struct ar8xxx_priv *priv);
83 void (*vtu_flush)(struct ar8xxx_priv *priv);
84 void (*vtu_load_vlan)(struct ar8xxx_priv *priv, u32 vid, u32 port_mask);
85 void (*phy_fixup)(struct ar8xxx_priv *priv, int phy);
86
87 const struct ar8xxx_mib_desc *mib_decs;
88 unsigned num_mibs;
89 };
90
91 enum ar8327_led_pattern {
92 AR8327_LED_PATTERN_OFF = 0,
93 AR8327_LED_PATTERN_BLINK,
94 AR8327_LED_PATTERN_ON,
95 AR8327_LED_PATTERN_RULE,
96 };
97
98 struct ar8327_led_entry {
99 unsigned reg;
100 unsigned shift;
101 };
102
103 struct ar8327_led {
104 struct led_classdev cdev;
105 struct ar8xxx_priv *sw_priv;
106
107 char *name;
108 bool active_low;
109 u8 led_num;
110 enum ar8327_led_mode mode;
111
112 struct mutex mutex;
113 spinlock_t lock;
114 struct work_struct led_work;
115 bool enable_hw_mode;
116 enum ar8327_led_pattern pattern;
117 };
118
119 struct ar8327_data {
120 u32 port0_status;
121 u32 port6_status;
122
123 struct ar8327_led **leds;
124 unsigned int num_leds;
125 };
126
127 struct ar8xxx_priv {
128 struct switch_dev dev;
129 struct mii_bus *mii_bus;
130 struct phy_device *phy;
131
132 u32 (*read)(struct ar8xxx_priv *priv, int reg);
133 void (*write)(struct ar8xxx_priv *priv, int reg, u32 val);
134 u32 (*rmw)(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val);
135
136 int (*get_port_link)(unsigned port);
137
138 const struct net_device_ops *ndo_old;
139 struct net_device_ops ndo;
140 struct mutex reg_mutex;
141 u8 chip_ver;
142 u8 chip_rev;
143 const struct ar8xxx_chip *chip;
144 union {
145 struct ar8327_data ar8327;
146 } chip_data;
147 bool initialized;
148 bool port4_phy;
149 char buf[2048];
150
151 bool init;
152 bool mii_lo_first;
153
154 struct mutex mib_lock;
155 struct delayed_work mib_work;
156 int mib_next_port;
157 u64 *mib_stats;
158
159 struct list_head list;
160 unsigned int use_count;
161
162 /* all fields below are cleared on reset */
163 bool vlan;
164 u16 vlan_id[AR8X16_MAX_VLANS];
165 u8 vlan_table[AR8X16_MAX_VLANS];
166 u8 vlan_tagged;
167 u16 pvid[AR8X16_MAX_PORTS];
168
169 /* mirroring */
170 bool mirror_rx;
171 bool mirror_tx;
172 int source_port;
173 int monitor_port;
174 };
175
176 #define MIB_DESC(_s , _o, _n) \
177 { \
178 .size = (_s), \
179 .offset = (_o), \
180 .name = (_n), \
181 }
182
183 static const struct ar8xxx_mib_desc ar8216_mibs[] = {
184 MIB_DESC(1, AR8216_STATS_RXBROAD, "RxBroad"),
185 MIB_DESC(1, AR8216_STATS_RXPAUSE, "RxPause"),
186 MIB_DESC(1, AR8216_STATS_RXMULTI, "RxMulti"),
187 MIB_DESC(1, AR8216_STATS_RXFCSERR, "RxFcsErr"),
188 MIB_DESC(1, AR8216_STATS_RXALIGNERR, "RxAlignErr"),
189 MIB_DESC(1, AR8216_STATS_RXRUNT, "RxRunt"),
190 MIB_DESC(1, AR8216_STATS_RXFRAGMENT, "RxFragment"),
191 MIB_DESC(1, AR8216_STATS_RX64BYTE, "Rx64Byte"),
192 MIB_DESC(1, AR8216_STATS_RX128BYTE, "Rx128Byte"),
193 MIB_DESC(1, AR8216_STATS_RX256BYTE, "Rx256Byte"),
194 MIB_DESC(1, AR8216_STATS_RX512BYTE, "Rx512Byte"),
195 MIB_DESC(1, AR8216_STATS_RX1024BYTE, "Rx1024Byte"),
196 MIB_DESC(1, AR8216_STATS_RXMAXBYTE, "RxMaxByte"),
197 MIB_DESC(1, AR8216_STATS_RXTOOLONG, "RxTooLong"),
198 MIB_DESC(2, AR8216_STATS_RXGOODBYTE, "RxGoodByte"),
199 MIB_DESC(2, AR8216_STATS_RXBADBYTE, "RxBadByte"),
200 MIB_DESC(1, AR8216_STATS_RXOVERFLOW, "RxOverFlow"),
201 MIB_DESC(1, AR8216_STATS_FILTERED, "Filtered"),
202 MIB_DESC(1, AR8216_STATS_TXBROAD, "TxBroad"),
203 MIB_DESC(1, AR8216_STATS_TXPAUSE, "TxPause"),
204 MIB_DESC(1, AR8216_STATS_TXMULTI, "TxMulti"),
205 MIB_DESC(1, AR8216_STATS_TXUNDERRUN, "TxUnderRun"),
206 MIB_DESC(1, AR8216_STATS_TX64BYTE, "Tx64Byte"),
207 MIB_DESC(1, AR8216_STATS_TX128BYTE, "Tx128Byte"),
208 MIB_DESC(1, AR8216_STATS_TX256BYTE, "Tx256Byte"),
209 MIB_DESC(1, AR8216_STATS_TX512BYTE, "Tx512Byte"),
210 MIB_DESC(1, AR8216_STATS_TX1024BYTE, "Tx1024Byte"),
211 MIB_DESC(1, AR8216_STATS_TXMAXBYTE, "TxMaxByte"),
212 MIB_DESC(1, AR8216_STATS_TXOVERSIZE, "TxOverSize"),
213 MIB_DESC(2, AR8216_STATS_TXBYTE, "TxByte"),
214 MIB_DESC(1, AR8216_STATS_TXCOLLISION, "TxCollision"),
215 MIB_DESC(1, AR8216_STATS_TXABORTCOL, "TxAbortCol"),
216 MIB_DESC(1, AR8216_STATS_TXMULTICOL, "TxMultiCol"),
217 MIB_DESC(1, AR8216_STATS_TXSINGLECOL, "TxSingleCol"),
218 MIB_DESC(1, AR8216_STATS_TXEXCDEFER, "TxExcDefer"),
219 MIB_DESC(1, AR8216_STATS_TXDEFER, "TxDefer"),
220 MIB_DESC(1, AR8216_STATS_TXLATECOL, "TxLateCol"),
221 };
222
223 static const struct ar8xxx_mib_desc ar8236_mibs[] = {
224 MIB_DESC(1, AR8236_STATS_RXBROAD, "RxBroad"),
225 MIB_DESC(1, AR8236_STATS_RXPAUSE, "RxPause"),
226 MIB_DESC(1, AR8236_STATS_RXMULTI, "RxMulti"),
227 MIB_DESC(1, AR8236_STATS_RXFCSERR, "RxFcsErr"),
228 MIB_DESC(1, AR8236_STATS_RXALIGNERR, "RxAlignErr"),
229 MIB_DESC(1, AR8236_STATS_RXRUNT, "RxRunt"),
230 MIB_DESC(1, AR8236_STATS_RXFRAGMENT, "RxFragment"),
231 MIB_DESC(1, AR8236_STATS_RX64BYTE, "Rx64Byte"),
232 MIB_DESC(1, AR8236_STATS_RX128BYTE, "Rx128Byte"),
233 MIB_DESC(1, AR8236_STATS_RX256BYTE, "Rx256Byte"),
234 MIB_DESC(1, AR8236_STATS_RX512BYTE, "Rx512Byte"),
235 MIB_DESC(1, AR8236_STATS_RX1024BYTE, "Rx1024Byte"),
236 MIB_DESC(1, AR8236_STATS_RX1518BYTE, "Rx1518Byte"),
237 MIB_DESC(1, AR8236_STATS_RXMAXBYTE, "RxMaxByte"),
238 MIB_DESC(1, AR8236_STATS_RXTOOLONG, "RxTooLong"),
239 MIB_DESC(2, AR8236_STATS_RXGOODBYTE, "RxGoodByte"),
240 MIB_DESC(2, AR8236_STATS_RXBADBYTE, "RxBadByte"),
241 MIB_DESC(1, AR8236_STATS_RXOVERFLOW, "RxOverFlow"),
242 MIB_DESC(1, AR8236_STATS_FILTERED, "Filtered"),
243 MIB_DESC(1, AR8236_STATS_TXBROAD, "TxBroad"),
244 MIB_DESC(1, AR8236_STATS_TXPAUSE, "TxPause"),
245 MIB_DESC(1, AR8236_STATS_TXMULTI, "TxMulti"),
246 MIB_DESC(1, AR8236_STATS_TXUNDERRUN, "TxUnderRun"),
247 MIB_DESC(1, AR8236_STATS_TX64BYTE, "Tx64Byte"),
248 MIB_DESC(1, AR8236_STATS_TX128BYTE, "Tx128Byte"),
249 MIB_DESC(1, AR8236_STATS_TX256BYTE, "Tx256Byte"),
250 MIB_DESC(1, AR8236_STATS_TX512BYTE, "Tx512Byte"),
251 MIB_DESC(1, AR8236_STATS_TX1024BYTE, "Tx1024Byte"),
252 MIB_DESC(1, AR8236_STATS_TX1518BYTE, "Tx1518Byte"),
253 MIB_DESC(1, AR8236_STATS_TXMAXBYTE, "TxMaxByte"),
254 MIB_DESC(1, AR8236_STATS_TXOVERSIZE, "TxOverSize"),
255 MIB_DESC(2, AR8236_STATS_TXBYTE, "TxByte"),
256 MIB_DESC(1, AR8236_STATS_TXCOLLISION, "TxCollision"),
257 MIB_DESC(1, AR8236_STATS_TXABORTCOL, "TxAbortCol"),
258 MIB_DESC(1, AR8236_STATS_TXMULTICOL, "TxMultiCol"),
259 MIB_DESC(1, AR8236_STATS_TXSINGLECOL, "TxSingleCol"),
260 MIB_DESC(1, AR8236_STATS_TXEXCDEFER, "TxExcDefer"),
261 MIB_DESC(1, AR8236_STATS_TXDEFER, "TxDefer"),
262 MIB_DESC(1, AR8236_STATS_TXLATECOL, "TxLateCol"),
263 };
264
265 static DEFINE_MUTEX(ar8xxx_dev_list_lock);
266 static LIST_HEAD(ar8xxx_dev_list);
267
268 static inline struct ar8xxx_priv *
269 swdev_to_ar8xxx(struct switch_dev *swdev)
270 {
271 return container_of(swdev, struct ar8xxx_priv, dev);
272 }
273
274 static inline bool ar8xxx_has_gige(struct ar8xxx_priv *priv)
275 {
276 return priv->chip->caps & AR8XXX_CAP_GIGE;
277 }
278
279 static inline bool ar8xxx_has_mib_counters(struct ar8xxx_priv *priv)
280 {
281 return priv->chip->caps & AR8XXX_CAP_MIB_COUNTERS;
282 }
283
284 static inline bool chip_is_ar8216(struct ar8xxx_priv *priv)
285 {
286 return priv->chip_ver == AR8XXX_VER_AR8216;
287 }
288
289 static inline bool chip_is_ar8236(struct ar8xxx_priv *priv)
290 {
291 return priv->chip_ver == AR8XXX_VER_AR8236;
292 }
293
294 static inline bool chip_is_ar8316(struct ar8xxx_priv *priv)
295 {
296 return priv->chip_ver == AR8XXX_VER_AR8316;
297 }
298
299 static inline bool chip_is_ar8327(struct ar8xxx_priv *priv)
300 {
301 return priv->chip_ver == AR8XXX_VER_AR8327;
302 }
303
304 static inline bool chip_is_ar8337(struct ar8xxx_priv *priv)
305 {
306 return priv->chip_ver == AR8XXX_VER_AR8337;
307 }
308
309 static inline void
310 split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
311 {
312 regaddr >>= 1;
313 *r1 = regaddr & 0x1e;
314
315 regaddr >>= 5;
316 *r2 = regaddr & 0x7;
317
318 regaddr >>= 3;
319 *page = regaddr & 0x1ff;
320 }
321
322 /* inspired by phy_poll_reset in drivers/net/phy/phy_device.c */
323 static int
324 ar8xxx_phy_poll_reset(struct mii_bus *bus)
325 {
326 unsigned int sleep_msecs = 20;
327 int ret, elapsed, i;
328
329 for (elapsed = sleep_msecs; elapsed <= 600;
330 elapsed += sleep_msecs) {
331 msleep(sleep_msecs);
332 for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
333 ret = mdiobus_read(bus, i, MII_BMCR);
334 if (ret < 0)
335 return ret;
336 if (ret & BMCR_RESET)
337 break;
338 if (i == AR8XXX_NUM_PHYS - 1) {
339 usleep_range(1000, 2000);
340 return 0;
341 }
342 }
343 }
344 return -ETIMEDOUT;
345 }
346
347 static int
348 ar8xxx_phy_check_aneg(struct phy_device *phydev)
349 {
350 int ret;
351
352 if (phydev->autoneg != AUTONEG_ENABLE)
353 return 0;
354 /*
355 * BMCR_ANENABLE might have been cleared
356 * by phy_init_hw in certain kernel versions
357 * therefore check for it
358 */
359 ret = phy_read(phydev, MII_BMCR);
360 if (ret < 0)
361 return ret;
362 if (ret & BMCR_ANENABLE)
363 return 0;
364
365 dev_info(&phydev->dev, "ANEG disabled, re-enabling ...\n");
366 ret |= BMCR_ANENABLE | BMCR_ANRESTART;
367 return phy_write(phydev, MII_BMCR, ret);
368 }
369
370 static void
371 ar8xxx_phy_init(struct ar8xxx_priv *priv)
372 {
373 int i;
374 struct mii_bus *bus;
375
376 bus = priv->mii_bus;
377 for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
378 if (priv->chip->phy_fixup)
379 priv->chip->phy_fixup(priv, i);
380
381 /* initialize the port itself */
382 mdiobus_write(bus, i, MII_ADVERTISE,
383 ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
384 if (ar8xxx_has_gige(priv))
385 mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
386 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
387 }
388
389 ar8xxx_phy_poll_reset(bus);
390 }
391
392 static u32
393 ar8xxx_mii_read(struct ar8xxx_priv *priv, int reg)
394 {
395 struct mii_bus *bus = priv->mii_bus;
396 u16 r1, r2, page;
397 u16 lo, hi;
398
399 split_addr((u32) reg, &r1, &r2, &page);
400
401 mutex_lock(&bus->mdio_lock);
402
403 bus->write(bus, 0x18, 0, page);
404 usleep_range(1000, 2000); /* wait for the page switch to propagate */
405 lo = bus->read(bus, 0x10 | r2, r1);
406 hi = bus->read(bus, 0x10 | r2, r1 + 1);
407
408 mutex_unlock(&bus->mdio_lock);
409
410 return (hi << 16) | lo;
411 }
412
413 static void
414 ar8xxx_mii_write(struct ar8xxx_priv *priv, int reg, u32 val)
415 {
416 struct mii_bus *bus = priv->mii_bus;
417 u16 r1, r2, r3;
418 u16 lo, hi;
419
420 split_addr((u32) reg, &r1, &r2, &r3);
421 lo = val & 0xffff;
422 hi = (u16) (val >> 16);
423
424 mutex_lock(&bus->mdio_lock);
425
426 bus->write(bus, 0x18, 0, r3);
427 usleep_range(1000, 2000); /* wait for the page switch to propagate */
428 if (priv->mii_lo_first) {
429 bus->write(bus, 0x10 | r2, r1, lo);
430 bus->write(bus, 0x10 | r2, r1 + 1, hi);
431 } else {
432 bus->write(bus, 0x10 | r2, r1 + 1, hi);
433 bus->write(bus, 0x10 | r2, r1, lo);
434 }
435
436 mutex_unlock(&bus->mdio_lock);
437 }
438
439 static u32
440 ar8xxx_mii_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
441 {
442 struct mii_bus *bus = priv->mii_bus;
443 u16 r1, r2, page;
444 u16 lo, hi;
445 u32 ret;
446
447 split_addr((u32) reg, &r1, &r2, &page);
448
449 mutex_lock(&bus->mdio_lock);
450
451 bus->write(bus, 0x18, 0, page);
452 usleep_range(1000, 2000); /* wait for the page switch to propagate */
453
454 lo = bus->read(bus, 0x10 | r2, r1);
455 hi = bus->read(bus, 0x10 | r2, r1 + 1);
456
457 ret = hi << 16 | lo;
458 ret &= ~mask;
459 ret |= val;
460
461 lo = ret & 0xffff;
462 hi = (u16) (ret >> 16);
463
464 if (priv->mii_lo_first) {
465 bus->write(bus, 0x10 | r2, r1, lo);
466 bus->write(bus, 0x10 | r2, r1 + 1, hi);
467 } else {
468 bus->write(bus, 0x10 | r2, r1 + 1, hi);
469 bus->write(bus, 0x10 | r2, r1, lo);
470 }
471
472 mutex_unlock(&bus->mdio_lock);
473
474 return ret;
475 }
476
477
478 static void
479 ar8xxx_phy_dbg_write(struct ar8xxx_priv *priv, int phy_addr,
480 u16 dbg_addr, u16 dbg_data)
481 {
482 struct mii_bus *bus = priv->mii_bus;
483
484 mutex_lock(&bus->mdio_lock);
485 bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr);
486 bus->write(bus, phy_addr, MII_ATH_DBG_DATA, dbg_data);
487 mutex_unlock(&bus->mdio_lock);
488 }
489
490 static void
491 ar8xxx_phy_mmd_write(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 data)
492 {
493 struct mii_bus *bus = priv->mii_bus;
494
495 mutex_lock(&bus->mdio_lock);
496 bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr);
497 bus->write(bus, phy_addr, MII_ATH_MMD_DATA, data);
498 mutex_unlock(&bus->mdio_lock);
499 }
500
501 static inline u32
502 ar8xxx_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
503 {
504 return priv->rmw(priv, reg, mask, val);
505 }
506
507 static inline void
508 ar8xxx_reg_set(struct ar8xxx_priv *priv, int reg, u32 val)
509 {
510 priv->rmw(priv, reg, 0, val);
511 }
512
513 static int
514 ar8xxx_reg_wait(struct ar8xxx_priv *priv, u32 reg, u32 mask, u32 val,
515 unsigned timeout)
516 {
517 int i;
518
519 for (i = 0; i < timeout; i++) {
520 u32 t;
521
522 t = priv->read(priv, reg);
523 if ((t & mask) == val)
524 return 0;
525
526 usleep_range(1000, 2000);
527 }
528
529 return -ETIMEDOUT;
530 }
531
532 static int
533 ar8xxx_mib_op(struct ar8xxx_priv *priv, u32 op)
534 {
535 unsigned mib_func;
536 int ret;
537
538 lockdep_assert_held(&priv->mib_lock);
539
540 if (chip_is_ar8327(priv) || chip_is_ar8337(priv))
541 mib_func = AR8327_REG_MIB_FUNC;
542 else
543 mib_func = AR8216_REG_MIB_FUNC;
544
545 /* Capture the hardware statistics for all ports */
546 ar8xxx_rmw(priv, mib_func, AR8216_MIB_FUNC, (op << AR8216_MIB_FUNC_S));
547
548 /* Wait for the capturing to complete. */
549 ret = ar8xxx_reg_wait(priv, mib_func, AR8216_MIB_BUSY, 0, 10);
550 if (ret)
551 goto out;
552
553 ret = 0;
554
555 out:
556 return ret;
557 }
558
559 static int
560 ar8xxx_mib_capture(struct ar8xxx_priv *priv)
561 {
562 return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_CAPTURE);
563 }
564
565 static int
566 ar8xxx_mib_flush(struct ar8xxx_priv *priv)
567 {
568 return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_FLUSH);
569 }
570
571 static void
572 ar8xxx_mib_fetch_port_stat(struct ar8xxx_priv *priv, int port, bool flush)
573 {
574 unsigned int base;
575 u64 *mib_stats;
576 int i;
577
578 WARN_ON(port >= priv->dev.ports);
579
580 lockdep_assert_held(&priv->mib_lock);
581
582 if (chip_is_ar8327(priv) || chip_is_ar8337(priv))
583 base = AR8327_REG_PORT_STATS_BASE(port);
584 else if (chip_is_ar8236(priv) ||
585 chip_is_ar8316(priv))
586 base = AR8236_REG_PORT_STATS_BASE(port);
587 else
588 base = AR8216_REG_PORT_STATS_BASE(port);
589
590 mib_stats = &priv->mib_stats[port * priv->chip->num_mibs];
591 for (i = 0; i < priv->chip->num_mibs; i++) {
592 const struct ar8xxx_mib_desc *mib;
593 u64 t;
594
595 mib = &priv->chip->mib_decs[i];
596 t = priv->read(priv, base + mib->offset);
597 if (mib->size == 2) {
598 u64 hi;
599
600 hi = priv->read(priv, base + mib->offset + 4);
601 t |= hi << 32;
602 }
603
604 if (flush)
605 mib_stats[i] = 0;
606 else
607 mib_stats[i] += t;
608 }
609 }
610
611 static void
612 ar8216_read_port_link(struct ar8xxx_priv *priv, int port,
613 struct switch_port_link *link)
614 {
615 u32 status;
616 u32 speed;
617
618 memset(link, '\0', sizeof(*link));
619
620 status = priv->chip->read_port_status(priv, port);
621
622 link->aneg = !!(status & AR8216_PORT_STATUS_LINK_AUTO);
623 if (link->aneg) {
624 link->link = !!(status & AR8216_PORT_STATUS_LINK_UP);
625 } else {
626 link->link = true;
627
628 if (priv->get_port_link) {
629 int err;
630
631 err = priv->get_port_link(port);
632 if (err >= 0)
633 link->link = !!err;
634 }
635 }
636
637 if (!link->link)
638 return;
639
640 link->duplex = !!(status & AR8216_PORT_STATUS_DUPLEX);
641 link->tx_flow = !!(status & AR8216_PORT_STATUS_TXFLOW);
642 link->rx_flow = !!(status & AR8216_PORT_STATUS_RXFLOW);
643
644 speed = (status & AR8216_PORT_STATUS_SPEED) >>
645 AR8216_PORT_STATUS_SPEED_S;
646
647 switch (speed) {
648 case AR8216_PORT_SPEED_10M:
649 link->speed = SWITCH_PORT_SPEED_10;
650 break;
651 case AR8216_PORT_SPEED_100M:
652 link->speed = SWITCH_PORT_SPEED_100;
653 break;
654 case AR8216_PORT_SPEED_1000M:
655 link->speed = SWITCH_PORT_SPEED_1000;
656 break;
657 default:
658 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
659 break;
660 }
661 }
662
663 static struct sk_buff *
664 ar8216_mangle_tx(struct net_device *dev, struct sk_buff *skb)
665 {
666 struct ar8xxx_priv *priv = dev->phy_ptr;
667 unsigned char *buf;
668
669 if (unlikely(!priv))
670 goto error;
671
672 if (!priv->vlan)
673 goto send;
674
675 if (unlikely(skb_headroom(skb) < 2)) {
676 if (pskb_expand_head(skb, 2, 0, GFP_ATOMIC) < 0)
677 goto error;
678 }
679
680 buf = skb_push(skb, 2);
681 buf[0] = 0x10;
682 buf[1] = 0x80;
683
684 send:
685 return skb;
686
687 error:
688 dev_kfree_skb_any(skb);
689 return NULL;
690 }
691
692 static void
693 ar8216_mangle_rx(struct net_device *dev, struct sk_buff *skb)
694 {
695 struct ar8xxx_priv *priv;
696 unsigned char *buf;
697 int port, vlan;
698
699 priv = dev->phy_ptr;
700 if (!priv)
701 return;
702
703 /* don't strip the header if vlan mode is disabled */
704 if (!priv->vlan)
705 return;
706
707 /* strip header, get vlan id */
708 buf = skb->data;
709 skb_pull(skb, 2);
710
711 /* check for vlan header presence */
712 if ((buf[12 + 2] != 0x81) || (buf[13 + 2] != 0x00))
713 return;
714
715 port = buf[0] & 0xf;
716
717 /* no need to fix up packets coming from a tagged source */
718 if (priv->vlan_tagged & (1 << port))
719 return;
720
721 /* lookup port vid from local table, the switch passes an invalid vlan id */
722 vlan = priv->vlan_id[priv->pvid[port]];
723
724 buf[14 + 2] &= 0xf0;
725 buf[14 + 2] |= vlan >> 8;
726 buf[15 + 2] = vlan & 0xff;
727 }
728
729 static int
730 ar8216_wait_bit(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
731 {
732 int timeout = 20;
733 u32 t = 0;
734
735 while (1) {
736 t = priv->read(priv, reg);
737 if ((t & mask) == val)
738 return 0;
739
740 if (timeout-- <= 0)
741 break;
742
743 udelay(10);
744 }
745
746 pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
747 (unsigned int) reg, t, mask, val);
748 return -ETIMEDOUT;
749 }
750
751 static void
752 ar8216_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
753 {
754 if (ar8216_wait_bit(priv, AR8216_REG_VTU, AR8216_VTU_ACTIVE, 0))
755 return;
756 if ((op & AR8216_VTU_OP) == AR8216_VTU_OP_LOAD) {
757 val &= AR8216_VTUDATA_MEMBER;
758 val |= AR8216_VTUDATA_VALID;
759 priv->write(priv, AR8216_REG_VTU_DATA, val);
760 }
761 op |= AR8216_VTU_ACTIVE;
762 priv->write(priv, AR8216_REG_VTU, op);
763 }
764
765 static void
766 ar8216_vtu_flush(struct ar8xxx_priv *priv)
767 {
768 ar8216_vtu_op(priv, AR8216_VTU_OP_FLUSH, 0);
769 }
770
771 static void
772 ar8216_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)
773 {
774 u32 op;
775
776 op = AR8216_VTU_OP_LOAD | (vid << AR8216_VTU_VID_S);
777 ar8216_vtu_op(priv, op, port_mask);
778 }
779
780 static int
781 ar8216_atu_flush(struct ar8xxx_priv *priv)
782 {
783 int ret;
784
785 ret = ar8216_wait_bit(priv, AR8216_REG_ATU, AR8216_ATU_ACTIVE, 0);
786 if (!ret)
787 priv->write(priv, AR8216_REG_ATU, AR8216_ATU_OP_FLUSH);
788
789 return ret;
790 }
791
792 static u32
793 ar8216_read_port_status(struct ar8xxx_priv *priv, int port)
794 {
795 return priv->read(priv, AR8216_REG_PORT_STATUS(port));
796 }
797
798 static void
799 ar8216_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
800 {
801 u32 header;
802 u32 egress, ingress;
803 u32 pvid;
804
805 if (priv->vlan) {
806 pvid = priv->vlan_id[priv->pvid[port]];
807 if (priv->vlan_tagged & (1 << port))
808 egress = AR8216_OUT_ADD_VLAN;
809 else
810 egress = AR8216_OUT_STRIP_VLAN;
811 ingress = AR8216_IN_SECURE;
812 } else {
813 pvid = port;
814 egress = AR8216_OUT_KEEP;
815 ingress = AR8216_IN_PORT_ONLY;
816 }
817
818 if (chip_is_ar8216(priv) && priv->vlan && port == AR8216_PORT_CPU)
819 header = AR8216_PORT_CTRL_HEADER;
820 else
821 header = 0;
822
823 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
824 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
825 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
826 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
827 AR8216_PORT_CTRL_LEARN | header |
828 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
829 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
830
831 ar8xxx_rmw(priv, AR8216_REG_PORT_VLAN(port),
832 AR8216_PORT_VLAN_DEST_PORTS | AR8216_PORT_VLAN_MODE |
833 AR8216_PORT_VLAN_DEFAULT_ID,
834 (members << AR8216_PORT_VLAN_DEST_PORTS_S) |
835 (ingress << AR8216_PORT_VLAN_MODE_S) |
836 (pvid << AR8216_PORT_VLAN_DEFAULT_ID_S));
837 }
838
839 static int
840 ar8216_hw_init(struct ar8xxx_priv *priv)
841 {
842 if (priv->initialized)
843 return 0;
844
845 ar8xxx_phy_init(priv);
846
847 priv->initialized = true;
848 return 0;
849 }
850
851 static void
852 ar8216_init_globals(struct ar8xxx_priv *priv)
853 {
854 /* standard atheros magic */
855 priv->write(priv, 0x38, 0xc000050e);
856
857 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
858 AR8216_GCTRL_MTU, 1518 + 8 + 2);
859 }
860
861 static void
862 ar8216_init_port(struct ar8xxx_priv *priv, int port)
863 {
864 /* Enable port learning and tx */
865 priv->write(priv, AR8216_REG_PORT_CTRL(port),
866 AR8216_PORT_CTRL_LEARN |
867 (4 << AR8216_PORT_CTRL_STATE_S));
868
869 priv->write(priv, AR8216_REG_PORT_VLAN(port), 0);
870
871 if (port == AR8216_PORT_CPU) {
872 priv->write(priv, AR8216_REG_PORT_STATUS(port),
873 AR8216_PORT_STATUS_LINK_UP |
874 (ar8xxx_has_gige(priv) ?
875 AR8216_PORT_SPEED_1000M : AR8216_PORT_SPEED_100M) |
876 AR8216_PORT_STATUS_TXMAC |
877 AR8216_PORT_STATUS_RXMAC |
878 (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_RXFLOW : 0) |
879 (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_TXFLOW : 0) |
880 AR8216_PORT_STATUS_DUPLEX);
881 } else {
882 priv->write(priv, AR8216_REG_PORT_STATUS(port),
883 AR8216_PORT_STATUS_LINK_AUTO);
884 }
885 }
886
887 static const struct ar8xxx_chip ar8216_chip = {
888 .caps = AR8XXX_CAP_MIB_COUNTERS,
889
890 .hw_init = ar8216_hw_init,
891 .init_globals = ar8216_init_globals,
892 .init_port = ar8216_init_port,
893 .setup_port = ar8216_setup_port,
894 .read_port_status = ar8216_read_port_status,
895 .atu_flush = ar8216_atu_flush,
896 .vtu_flush = ar8216_vtu_flush,
897 .vtu_load_vlan = ar8216_vtu_load_vlan,
898
899 .num_mibs = ARRAY_SIZE(ar8216_mibs),
900 .mib_decs = ar8216_mibs,
901 };
902
903 static void
904 ar8236_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
905 {
906 u32 egress, ingress;
907 u32 pvid;
908
909 if (priv->vlan) {
910 pvid = priv->vlan_id[priv->pvid[port]];
911 if (priv->vlan_tagged & (1 << port))
912 egress = AR8216_OUT_ADD_VLAN;
913 else
914 egress = AR8216_OUT_STRIP_VLAN;
915 ingress = AR8216_IN_SECURE;
916 } else {
917 pvid = port;
918 egress = AR8216_OUT_KEEP;
919 ingress = AR8216_IN_PORT_ONLY;
920 }
921
922 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
923 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
924 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
925 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
926 AR8216_PORT_CTRL_LEARN |
927 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
928 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
929
930 ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN(port),
931 AR8236_PORT_VLAN_DEFAULT_ID,
932 (pvid << AR8236_PORT_VLAN_DEFAULT_ID_S));
933
934 ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN2(port),
935 AR8236_PORT_VLAN2_VLAN_MODE |
936 AR8236_PORT_VLAN2_MEMBER,
937 (ingress << AR8236_PORT_VLAN2_VLAN_MODE_S) |
938 (members << AR8236_PORT_VLAN2_MEMBER_S));
939 }
940
941 static void
942 ar8236_init_globals(struct ar8xxx_priv *priv)
943 {
944 /* enable jumbo frames */
945 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
946 AR8316_GCTRL_MTU, 9018 + 8 + 2);
947
948 /* Enable MIB counters */
949 ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
950 (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
951 AR8236_MIB_EN);
952 }
953
954 static const struct ar8xxx_chip ar8236_chip = {
955 .caps = AR8XXX_CAP_MIB_COUNTERS,
956 .hw_init = ar8216_hw_init,
957 .init_globals = ar8236_init_globals,
958 .init_port = ar8216_init_port,
959 .setup_port = ar8236_setup_port,
960 .read_port_status = ar8216_read_port_status,
961 .atu_flush = ar8216_atu_flush,
962 .vtu_flush = ar8216_vtu_flush,
963 .vtu_load_vlan = ar8216_vtu_load_vlan,
964
965 .num_mibs = ARRAY_SIZE(ar8236_mibs),
966 .mib_decs = ar8236_mibs,
967 };
968
969 static int
970 ar8316_hw_init(struct ar8xxx_priv *priv)
971 {
972 u32 val, newval;
973
974 val = priv->read(priv, AR8316_REG_POSTRIP);
975
976 if (priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
977 if (priv->port4_phy) {
978 /* value taken from Ubiquiti RouterStation Pro */
979 newval = 0x81461bea;
980 pr_info("ar8316: Using port 4 as PHY\n");
981 } else {
982 newval = 0x01261be2;
983 pr_info("ar8316: Using port 4 as switch port\n");
984 }
985 } else if (priv->phy->interface == PHY_INTERFACE_MODE_GMII) {
986 /* value taken from AVM Fritz!Box 7390 sources */
987 newval = 0x010e5b71;
988 } else {
989 /* no known value for phy interface */
990 pr_err("ar8316: unsupported mii mode: %d.\n",
991 priv->phy->interface);
992 return -EINVAL;
993 }
994
995 if (val == newval)
996 goto out;
997
998 priv->write(priv, AR8316_REG_POSTRIP, newval);
999
1000 if (priv->port4_phy &&
1001 priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
1002 /* work around for phy4 rgmii mode */
1003 ar8xxx_phy_dbg_write(priv, 4, 0x12, 0x480c);
1004 /* rx delay */
1005 ar8xxx_phy_dbg_write(priv, 4, 0x0, 0x824e);
1006 /* tx delay */
1007 ar8xxx_phy_dbg_write(priv, 4, 0x5, 0x3d47);
1008 msleep(1000);
1009 }
1010
1011 ar8xxx_phy_init(priv);
1012
1013 out:
1014 priv->initialized = true;
1015 return 0;
1016 }
1017
1018 static void
1019 ar8316_init_globals(struct ar8xxx_priv *priv)
1020 {
1021 /* standard atheros magic */
1022 priv->write(priv, 0x38, 0xc000050e);
1023
1024 /* enable cpu port to receive multicast and broadcast frames */
1025 priv->write(priv, AR8216_REG_FLOOD_MASK, 0x003f003f);
1026
1027 /* enable jumbo frames */
1028 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
1029 AR8316_GCTRL_MTU, 9018 + 8 + 2);
1030
1031 /* Enable MIB counters */
1032 ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
1033 (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
1034 AR8236_MIB_EN);
1035 }
1036
1037 static const struct ar8xxx_chip ar8316_chip = {
1038 .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
1039 .hw_init = ar8316_hw_init,
1040 .init_globals = ar8316_init_globals,
1041 .init_port = ar8216_init_port,
1042 .setup_port = ar8216_setup_port,
1043 .read_port_status = ar8216_read_port_status,
1044 .atu_flush = ar8216_atu_flush,
1045 .vtu_flush = ar8216_vtu_flush,
1046 .vtu_load_vlan = ar8216_vtu_load_vlan,
1047
1048 .num_mibs = ARRAY_SIZE(ar8236_mibs),
1049 .mib_decs = ar8236_mibs,
1050 };
1051
1052 static u32
1053 ar8327_get_pad_cfg(struct ar8327_pad_cfg *cfg)
1054 {
1055 u32 t;
1056
1057 if (!cfg)
1058 return 0;
1059
1060 t = 0;
1061 switch (cfg->mode) {
1062 case AR8327_PAD_NC:
1063 break;
1064
1065 case AR8327_PAD_MAC2MAC_MII:
1066 t = AR8327_PAD_MAC_MII_EN;
1067 if (cfg->rxclk_sel)
1068 t |= AR8327_PAD_MAC_MII_RXCLK_SEL;
1069 if (cfg->txclk_sel)
1070 t |= AR8327_PAD_MAC_MII_TXCLK_SEL;
1071 break;
1072
1073 case AR8327_PAD_MAC2MAC_GMII:
1074 t = AR8327_PAD_MAC_GMII_EN;
1075 if (cfg->rxclk_sel)
1076 t |= AR8327_PAD_MAC_GMII_RXCLK_SEL;
1077 if (cfg->txclk_sel)
1078 t |= AR8327_PAD_MAC_GMII_TXCLK_SEL;
1079 break;
1080
1081 case AR8327_PAD_MAC_SGMII:
1082 t = AR8327_PAD_SGMII_EN;
1083
1084 /*
1085 * WAR for the QUalcomm Atheros AP136 board.
1086 * It seems that RGMII TX/RX delay settings needs to be
1087 * applied for SGMII mode as well, The ethernet is not
1088 * reliable without this.
1089 */
1090 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
1091 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
1092 if (cfg->rxclk_delay_en)
1093 t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
1094 if (cfg->txclk_delay_en)
1095 t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
1096
1097 if (cfg->sgmii_delay_en)
1098 t |= AR8327_PAD_SGMII_DELAY_EN;
1099
1100 break;
1101
1102 case AR8327_PAD_MAC2PHY_MII:
1103 t = AR8327_PAD_PHY_MII_EN;
1104 if (cfg->rxclk_sel)
1105 t |= AR8327_PAD_PHY_MII_RXCLK_SEL;
1106 if (cfg->txclk_sel)
1107 t |= AR8327_PAD_PHY_MII_TXCLK_SEL;
1108 break;
1109
1110 case AR8327_PAD_MAC2PHY_GMII:
1111 t = AR8327_PAD_PHY_GMII_EN;
1112 if (cfg->pipe_rxclk_sel)
1113 t |= AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL;
1114 if (cfg->rxclk_sel)
1115 t |= AR8327_PAD_PHY_GMII_RXCLK_SEL;
1116 if (cfg->txclk_sel)
1117 t |= AR8327_PAD_PHY_GMII_TXCLK_SEL;
1118 break;
1119
1120 case AR8327_PAD_MAC_RGMII:
1121 t = AR8327_PAD_RGMII_EN;
1122 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
1123 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
1124 if (cfg->rxclk_delay_en)
1125 t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
1126 if (cfg->txclk_delay_en)
1127 t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
1128 break;
1129
1130 case AR8327_PAD_PHY_GMII:
1131 t = AR8327_PAD_PHYX_GMII_EN;
1132 break;
1133
1134 case AR8327_PAD_PHY_RGMII:
1135 t = AR8327_PAD_PHYX_RGMII_EN;
1136 break;
1137
1138 case AR8327_PAD_PHY_MII:
1139 t = AR8327_PAD_PHYX_MII_EN;
1140 break;
1141 }
1142
1143 return t;
1144 }
1145
1146 static void
1147 ar8327_phy_fixup(struct ar8xxx_priv *priv, int phy)
1148 {
1149 switch (priv->chip_rev) {
1150 case 1:
1151 /* For 100M waveform */
1152 ar8xxx_phy_dbg_write(priv, phy, 0, 0x02ea);
1153 /* Turn on Gigabit clock */
1154 ar8xxx_phy_dbg_write(priv, phy, 0x3d, 0x68a0);
1155 break;
1156
1157 case 2:
1158 ar8xxx_phy_mmd_write(priv, phy, 0x7, 0x3c);
1159 ar8xxx_phy_mmd_write(priv, phy, 0x4007, 0x0);
1160 /* fallthrough */
1161 case 4:
1162 ar8xxx_phy_mmd_write(priv, phy, 0x3, 0x800d);
1163 ar8xxx_phy_mmd_write(priv, phy, 0x4003, 0x803f);
1164
1165 ar8xxx_phy_dbg_write(priv, phy, 0x3d, 0x6860);
1166 ar8xxx_phy_dbg_write(priv, phy, 0x5, 0x2c46);
1167 ar8xxx_phy_dbg_write(priv, phy, 0x3c, 0x6000);
1168 break;
1169 }
1170 }
1171
1172 static u32
1173 ar8327_get_port_init_status(struct ar8327_port_cfg *cfg)
1174 {
1175 u32 t;
1176
1177 if (!cfg->force_link)
1178 return AR8216_PORT_STATUS_LINK_AUTO;
1179
1180 t = AR8216_PORT_STATUS_TXMAC | AR8216_PORT_STATUS_RXMAC;
1181 t |= cfg->duplex ? AR8216_PORT_STATUS_DUPLEX : 0;
1182 t |= cfg->rxpause ? AR8216_PORT_STATUS_RXFLOW : 0;
1183 t |= cfg->txpause ? AR8216_PORT_STATUS_TXFLOW : 0;
1184
1185 switch (cfg->speed) {
1186 case AR8327_PORT_SPEED_10:
1187 t |= AR8216_PORT_SPEED_10M;
1188 break;
1189 case AR8327_PORT_SPEED_100:
1190 t |= AR8216_PORT_SPEED_100M;
1191 break;
1192 case AR8327_PORT_SPEED_1000:
1193 t |= AR8216_PORT_SPEED_1000M;
1194 break;
1195 }
1196
1197 return t;
1198 }
1199
1200 #define AR8327_LED_ENTRY(_num, _reg, _shift) \
1201 [_num] = { .reg = (_reg), .shift = (_shift) }
1202
1203 static const struct ar8327_led_entry
1204 ar8327_led_map[AR8327_NUM_LEDS] = {
1205 AR8327_LED_ENTRY(AR8327_LED_PHY0_0, 0, 14),
1206 AR8327_LED_ENTRY(AR8327_LED_PHY0_1, 1, 14),
1207 AR8327_LED_ENTRY(AR8327_LED_PHY0_2, 2, 14),
1208
1209 AR8327_LED_ENTRY(AR8327_LED_PHY1_0, 3, 8),
1210 AR8327_LED_ENTRY(AR8327_LED_PHY1_1, 3, 10),
1211 AR8327_LED_ENTRY(AR8327_LED_PHY1_2, 3, 12),
1212
1213 AR8327_LED_ENTRY(AR8327_LED_PHY2_0, 3, 14),
1214 AR8327_LED_ENTRY(AR8327_LED_PHY2_1, 3, 16),
1215 AR8327_LED_ENTRY(AR8327_LED_PHY2_2, 3, 18),
1216
1217 AR8327_LED_ENTRY(AR8327_LED_PHY3_0, 3, 20),
1218 AR8327_LED_ENTRY(AR8327_LED_PHY3_1, 3, 22),
1219 AR8327_LED_ENTRY(AR8327_LED_PHY3_2, 3, 24),
1220
1221 AR8327_LED_ENTRY(AR8327_LED_PHY4_0, 0, 30),
1222 AR8327_LED_ENTRY(AR8327_LED_PHY4_1, 1, 30),
1223 AR8327_LED_ENTRY(AR8327_LED_PHY4_2, 2, 30),
1224 };
1225
1226 static void
1227 ar8327_set_led_pattern(struct ar8xxx_priv *priv, unsigned int led_num,
1228 enum ar8327_led_pattern pattern)
1229 {
1230 const struct ar8327_led_entry *entry;
1231
1232 entry = &ar8327_led_map[led_num];
1233 ar8xxx_rmw(priv, AR8327_REG_LED_CTRL(entry->reg),
1234 (3 << entry->shift), pattern << entry->shift);
1235 }
1236
1237 static void
1238 ar8327_led_work_func(struct work_struct *work)
1239 {
1240 struct ar8327_led *aled;
1241 u8 pattern;
1242
1243 aled = container_of(work, struct ar8327_led, led_work);
1244
1245 spin_lock(&aled->lock);
1246 pattern = aled->pattern;
1247 spin_unlock(&aled->lock);
1248
1249 ar8327_set_led_pattern(aled->sw_priv, aled->led_num,
1250 pattern);
1251 }
1252
1253 static void
1254 ar8327_led_schedule_change(struct ar8327_led *aled, u8 pattern)
1255 {
1256 if (aled->pattern == pattern)
1257 return;
1258
1259 aled->pattern = pattern;
1260 schedule_work(&aled->led_work);
1261 }
1262
1263 static inline struct ar8327_led *
1264 led_cdev_to_ar8327_led(struct led_classdev *led_cdev)
1265 {
1266 return container_of(led_cdev, struct ar8327_led, cdev);
1267 }
1268
1269 static int
1270 ar8327_led_blink_set(struct led_classdev *led_cdev,
1271 unsigned long *delay_on,
1272 unsigned long *delay_off)
1273 {
1274 struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
1275
1276 if (*delay_on == 0 && *delay_off == 0) {
1277 *delay_on = 125;
1278 *delay_off = 125;
1279 }
1280
1281 if (*delay_on != 125 || *delay_off != 125) {
1282 /*
1283 * The hardware only supports blinking at 4Hz. Fall back
1284 * to software implementation in other cases.
1285 */
1286 return -EINVAL;
1287 }
1288
1289 spin_lock(&aled->lock);
1290
1291 aled->enable_hw_mode = false;
1292 ar8327_led_schedule_change(aled, AR8327_LED_PATTERN_BLINK);
1293
1294 spin_unlock(&aled->lock);
1295
1296 return 0;
1297 }
1298
1299 static void
1300 ar8327_led_set_brightness(struct led_classdev *led_cdev,
1301 enum led_brightness brightness)
1302 {
1303 struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
1304 u8 pattern;
1305 bool active;
1306
1307 active = (brightness != LED_OFF);
1308 active ^= aled->active_low;
1309
1310 pattern = (active) ? AR8327_LED_PATTERN_ON :
1311 AR8327_LED_PATTERN_OFF;
1312
1313 spin_lock(&aled->lock);
1314
1315 aled->enable_hw_mode = false;
1316 ar8327_led_schedule_change(aled, pattern);
1317
1318 spin_unlock(&aled->lock);
1319 }
1320
1321 static ssize_t
1322 ar8327_led_enable_hw_mode_show(struct device *dev,
1323 struct device_attribute *attr,
1324 char *buf)
1325 {
1326 struct led_classdev *led_cdev = dev_get_drvdata(dev);
1327 struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
1328 ssize_t ret = 0;
1329
1330 spin_lock(&aled->lock);
1331 ret += sprintf(buf, "%d\n", aled->enable_hw_mode);
1332 spin_unlock(&aled->lock);
1333
1334 return ret;
1335 }
1336
1337 static ssize_t
1338 ar8327_led_enable_hw_mode_store(struct device *dev,
1339 struct device_attribute *attr,
1340 const char *buf,
1341 size_t size)
1342 {
1343 struct led_classdev *led_cdev = dev_get_drvdata(dev);
1344 struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
1345 u8 pattern;
1346 u8 value;
1347 int ret;
1348
1349 ret = kstrtou8(buf, 10, &value);
1350 if (ret < 0)
1351 return -EINVAL;
1352
1353 spin_lock(&aled->lock);
1354
1355 aled->enable_hw_mode = !!value;
1356 if (aled->enable_hw_mode)
1357 pattern = AR8327_LED_PATTERN_RULE;
1358 else
1359 pattern = AR8327_LED_PATTERN_OFF;
1360
1361 ar8327_led_schedule_change(aled, pattern);
1362
1363 spin_unlock(&aled->lock);
1364
1365 return size;
1366 }
1367
1368 static DEVICE_ATTR(enable_hw_mode, S_IRUGO | S_IWUSR,
1369 ar8327_led_enable_hw_mode_show,
1370 ar8327_led_enable_hw_mode_store);
1371
1372 static int
1373 ar8327_led_register(struct ar8xxx_priv *priv, struct ar8327_led *aled)
1374 {
1375 int ret;
1376
1377 ret = led_classdev_register(NULL, &aled->cdev);
1378 if (ret < 0)
1379 return ret;
1380
1381 if (aled->mode == AR8327_LED_MODE_HW) {
1382 ret = device_create_file(aled->cdev.dev,
1383 &dev_attr_enable_hw_mode);
1384 if (ret)
1385 goto err_unregister;
1386 }
1387
1388 return 0;
1389
1390 err_unregister:
1391 led_classdev_unregister(&aled->cdev);
1392 return ret;
1393 }
1394
1395 static void
1396 ar8327_led_unregister(struct ar8327_led *aled)
1397 {
1398 if (aled->mode == AR8327_LED_MODE_HW)
1399 device_remove_file(aled->cdev.dev, &dev_attr_enable_hw_mode);
1400
1401 led_classdev_unregister(&aled->cdev);
1402 cancel_work_sync(&aled->led_work);
1403 }
1404
1405 static int
1406 ar8327_led_create(struct ar8xxx_priv *priv,
1407 const struct ar8327_led_info *led_info)
1408 {
1409 struct ar8327_data *data = &priv->chip_data.ar8327;
1410 struct ar8327_led *aled;
1411 int ret;
1412
1413 if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS))
1414 return 0;
1415
1416 if (!led_info->name)
1417 return -EINVAL;
1418
1419 if (led_info->led_num >= AR8327_NUM_LEDS)
1420 return -EINVAL;
1421
1422 aled = kzalloc(sizeof(*aled) + strlen(led_info->name) + 1,
1423 GFP_KERNEL);
1424 if (!aled)
1425 return -ENOMEM;
1426
1427 aled->sw_priv = priv;
1428 aled->led_num = led_info->led_num;
1429 aled->active_low = led_info->active_low;
1430 aled->mode = led_info->mode;
1431
1432 if (aled->mode == AR8327_LED_MODE_HW)
1433 aled->enable_hw_mode = true;
1434
1435 aled->name = (char *)(aled + 1);
1436 strcpy(aled->name, led_info->name);
1437
1438 aled->cdev.name = aled->name;
1439 aled->cdev.brightness_set = ar8327_led_set_brightness;
1440 aled->cdev.blink_set = ar8327_led_blink_set;
1441 aled->cdev.default_trigger = led_info->default_trigger;
1442
1443 spin_lock_init(&aled->lock);
1444 mutex_init(&aled->mutex);
1445 INIT_WORK(&aled->led_work, ar8327_led_work_func);
1446
1447 ret = ar8327_led_register(priv, aled);
1448 if (ret)
1449 goto err_free;
1450
1451 data->leds[data->num_leds++] = aled;
1452
1453 return 0;
1454
1455 err_free:
1456 kfree(aled);
1457 return ret;
1458 }
1459
1460 static void
1461 ar8327_led_destroy(struct ar8327_led *aled)
1462 {
1463 ar8327_led_unregister(aled);
1464 kfree(aled);
1465 }
1466
1467 static void
1468 ar8327_leds_init(struct ar8xxx_priv *priv)
1469 {
1470 struct ar8327_data *data;
1471 unsigned i;
1472
1473 if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS))
1474 return;
1475
1476 data = &priv->chip_data.ar8327;
1477
1478 for (i = 0; i < data->num_leds; i++) {
1479 struct ar8327_led *aled;
1480
1481 aled = data->leds[i];
1482
1483 if (aled->enable_hw_mode)
1484 aled->pattern = AR8327_LED_PATTERN_RULE;
1485 else
1486 aled->pattern = AR8327_LED_PATTERN_OFF;
1487
1488 ar8327_set_led_pattern(priv, aled->led_num, aled->pattern);
1489 }
1490 }
1491
1492 static void
1493 ar8327_leds_cleanup(struct ar8xxx_priv *priv)
1494 {
1495 struct ar8327_data *data = &priv->chip_data.ar8327;
1496 unsigned i;
1497
1498 if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS))
1499 return;
1500
1501 for (i = 0; i < data->num_leds; i++) {
1502 struct ar8327_led *aled;
1503
1504 aled = data->leds[i];
1505 ar8327_led_destroy(aled);
1506 }
1507
1508 kfree(data->leds);
1509 }
1510
1511 static int
1512 ar8327_hw_config_pdata(struct ar8xxx_priv *priv,
1513 struct ar8327_platform_data *pdata)
1514 {
1515 struct ar8327_led_cfg *led_cfg;
1516 struct ar8327_data *data;
1517 u32 pos, new_pos;
1518 u32 t;
1519
1520 if (!pdata)
1521 return -EINVAL;
1522
1523 priv->get_port_link = pdata->get_port_link;
1524
1525 data = &priv->chip_data.ar8327;
1526
1527 data->port0_status = ar8327_get_port_init_status(&pdata->port0_cfg);
1528 data->port6_status = ar8327_get_port_init_status(&pdata->port6_cfg);
1529
1530 t = ar8327_get_pad_cfg(pdata->pad0_cfg);
1531 if (chip_is_ar8337(priv))
1532 t |= AR8337_PAD_MAC06_EXCHANGE_EN;
1533
1534 priv->write(priv, AR8327_REG_PAD0_MODE, t);
1535 t = ar8327_get_pad_cfg(pdata->pad5_cfg);
1536 priv->write(priv, AR8327_REG_PAD5_MODE, t);
1537 t = ar8327_get_pad_cfg(pdata->pad6_cfg);
1538 priv->write(priv, AR8327_REG_PAD6_MODE, t);
1539
1540 pos = priv->read(priv, AR8327_REG_POWER_ON_STRIP);
1541 new_pos = pos;
1542
1543 led_cfg = pdata->led_cfg;
1544 if (led_cfg) {
1545 if (led_cfg->open_drain)
1546 new_pos |= AR8327_POWER_ON_STRIP_LED_OPEN_EN;
1547 else
1548 new_pos &= ~AR8327_POWER_ON_STRIP_LED_OPEN_EN;
1549
1550 priv->write(priv, AR8327_REG_LED_CTRL0, led_cfg->led_ctrl0);
1551 priv->write(priv, AR8327_REG_LED_CTRL1, led_cfg->led_ctrl1);
1552 priv->write(priv, AR8327_REG_LED_CTRL2, led_cfg->led_ctrl2);
1553 priv->write(priv, AR8327_REG_LED_CTRL3, led_cfg->led_ctrl3);
1554
1555 if (new_pos != pos)
1556 new_pos |= AR8327_POWER_ON_STRIP_POWER_ON_SEL;
1557 }
1558
1559 if (pdata->sgmii_cfg) {
1560 t = pdata->sgmii_cfg->sgmii_ctrl;
1561 if (priv->chip_rev == 1)
1562 t |= AR8327_SGMII_CTRL_EN_PLL |
1563 AR8327_SGMII_CTRL_EN_RX |
1564 AR8327_SGMII_CTRL_EN_TX;
1565 else
1566 t &= ~(AR8327_SGMII_CTRL_EN_PLL |
1567 AR8327_SGMII_CTRL_EN_RX |
1568 AR8327_SGMII_CTRL_EN_TX);
1569
1570 priv->write(priv, AR8327_REG_SGMII_CTRL, t);
1571
1572 if (pdata->sgmii_cfg->serdes_aen)
1573 new_pos &= ~AR8327_POWER_ON_STRIP_SERDES_AEN;
1574 else
1575 new_pos |= AR8327_POWER_ON_STRIP_SERDES_AEN;
1576 }
1577
1578 priv->write(priv, AR8327_REG_POWER_ON_STRIP, new_pos);
1579
1580 if (pdata->leds && pdata->num_leds) {
1581 int i;
1582
1583 data->leds = kzalloc(pdata->num_leds * sizeof(void *),
1584 GFP_KERNEL);
1585 if (!data->leds)
1586 return -ENOMEM;
1587
1588 for (i = 0; i < pdata->num_leds; i++)
1589 ar8327_led_create(priv, &pdata->leds[i]);
1590 }
1591
1592 return 0;
1593 }
1594
1595 #ifdef CONFIG_OF
1596 static int
1597 ar8327_hw_config_of(struct ar8xxx_priv *priv, struct device_node *np)
1598 {
1599 const __be32 *paddr;
1600 int len;
1601 int i;
1602
1603 paddr = of_get_property(np, "qca,ar8327-initvals", &len);
1604 if (!paddr || len < (2 * sizeof(*paddr)))
1605 return -EINVAL;
1606
1607 len /= sizeof(*paddr);
1608
1609 for (i = 0; i < len - 1; i += 2) {
1610 u32 reg;
1611 u32 val;
1612
1613 reg = be32_to_cpup(paddr + i);
1614 val = be32_to_cpup(paddr + i + 1);
1615
1616 switch (reg) {
1617 case AR8327_REG_PORT_STATUS(0):
1618 priv->chip_data.ar8327.port0_status = val;
1619 break;
1620 case AR8327_REG_PORT_STATUS(6):
1621 priv->chip_data.ar8327.port6_status = val;
1622 break;
1623 default:
1624 priv->write(priv, reg, val);
1625 break;
1626 }
1627 }
1628
1629 return 0;
1630 }
1631 #else
1632 static inline int
1633 ar8327_hw_config_of(struct ar8xxx_priv *priv, struct device_node *np)
1634 {
1635 return -EINVAL;
1636 }
1637 #endif
1638
1639 static int
1640 ar8327_hw_init(struct ar8xxx_priv *priv)
1641 {
1642 int ret;
1643
1644 if (priv->phy->dev.of_node)
1645 ret = ar8327_hw_config_of(priv, priv->phy->dev.of_node);
1646 else
1647 ret = ar8327_hw_config_pdata(priv,
1648 priv->phy->dev.platform_data);
1649
1650 if (ret)
1651 return ret;
1652
1653 ar8327_leds_init(priv);
1654
1655 ar8xxx_phy_init(priv);
1656
1657 return 0;
1658 }
1659
1660 static void
1661 ar8327_cleanup(struct ar8xxx_priv *priv)
1662 {
1663 ar8327_leds_cleanup(priv);
1664 }
1665
1666 static void
1667 ar8327_init_globals(struct ar8xxx_priv *priv)
1668 {
1669 u32 t;
1670
1671 /* enable CPU port and disable mirror port */
1672 t = AR8327_FWD_CTRL0_CPU_PORT_EN |
1673 AR8327_FWD_CTRL0_MIRROR_PORT;
1674 priv->write(priv, AR8327_REG_FWD_CTRL0, t);
1675
1676 /* forward multicast and broadcast frames to CPU */
1677 t = (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_UC_FLOOD_S) |
1678 (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_MC_FLOOD_S) |
1679 (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_BC_FLOOD_S);
1680 priv->write(priv, AR8327_REG_FWD_CTRL1, t);
1681
1682 /* enable jumbo frames */
1683 ar8xxx_rmw(priv, AR8327_REG_MAX_FRAME_SIZE,
1684 AR8327_MAX_FRAME_SIZE_MTU, 9018 + 8 + 2);
1685
1686 /* Enable MIB counters */
1687 ar8xxx_reg_set(priv, AR8327_REG_MODULE_EN,
1688 AR8327_MODULE_EN_MIB);
1689
1690 /* Disable EEE on all ports due to stability issues */
1691 t = priv->read(priv, AR8327_REG_EEE_CTRL);
1692 t |= AR8327_EEE_CTRL_DISABLE_PHY(0) |
1693 AR8327_EEE_CTRL_DISABLE_PHY(1) |
1694 AR8327_EEE_CTRL_DISABLE_PHY(2) |
1695 AR8327_EEE_CTRL_DISABLE_PHY(3) |
1696 AR8327_EEE_CTRL_DISABLE_PHY(4);
1697 priv->write(priv, AR8327_REG_EEE_CTRL, t);
1698 }
1699
1700 static void
1701 ar8327_init_port(struct ar8xxx_priv *priv, int port)
1702 {
1703 u32 t;
1704
1705 if (port == AR8216_PORT_CPU)
1706 t = priv->chip_data.ar8327.port0_status;
1707 else if (port == 6)
1708 t = priv->chip_data.ar8327.port6_status;
1709 else
1710 t = AR8216_PORT_STATUS_LINK_AUTO;
1711
1712 priv->write(priv, AR8327_REG_PORT_STATUS(port), t);
1713 priv->write(priv, AR8327_REG_PORT_HEADER(port), 0);
1714
1715 t = 1 << AR8327_PORT_VLAN0_DEF_SVID_S;
1716 t |= 1 << AR8327_PORT_VLAN0_DEF_CVID_S;
1717 priv->write(priv, AR8327_REG_PORT_VLAN0(port), t);
1718
1719 t = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH << AR8327_PORT_VLAN1_OUT_MODE_S;
1720 priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
1721
1722 t = AR8327_PORT_LOOKUP_LEARN;
1723 t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
1724 priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
1725 }
1726
1727 static u32
1728 ar8327_read_port_status(struct ar8xxx_priv *priv, int port)
1729 {
1730 return priv->read(priv, AR8327_REG_PORT_STATUS(port));
1731 }
1732
1733 static int
1734 ar8327_atu_flush(struct ar8xxx_priv *priv)
1735 {
1736 int ret;
1737
1738 ret = ar8216_wait_bit(priv, AR8327_REG_ATU_FUNC,
1739 AR8327_ATU_FUNC_BUSY, 0);
1740 if (!ret)
1741 priv->write(priv, AR8327_REG_ATU_FUNC,
1742 AR8327_ATU_FUNC_OP_FLUSH);
1743
1744 return ret;
1745 }
1746
1747 static void
1748 ar8327_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
1749 {
1750 if (ar8216_wait_bit(priv, AR8327_REG_VTU_FUNC1,
1751 AR8327_VTU_FUNC1_BUSY, 0))
1752 return;
1753
1754 if ((op & AR8327_VTU_FUNC1_OP) == AR8327_VTU_FUNC1_OP_LOAD)
1755 priv->write(priv, AR8327_REG_VTU_FUNC0, val);
1756
1757 op |= AR8327_VTU_FUNC1_BUSY;
1758 priv->write(priv, AR8327_REG_VTU_FUNC1, op);
1759 }
1760
1761 static void
1762 ar8327_vtu_flush(struct ar8xxx_priv *priv)
1763 {
1764 ar8327_vtu_op(priv, AR8327_VTU_FUNC1_OP_FLUSH, 0);
1765 }
1766
1767 static void
1768 ar8327_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)
1769 {
1770 u32 op;
1771 u32 val;
1772 int i;
1773
1774 op = AR8327_VTU_FUNC1_OP_LOAD | (vid << AR8327_VTU_FUNC1_VID_S);
1775 val = AR8327_VTU_FUNC0_VALID | AR8327_VTU_FUNC0_IVL;
1776 for (i = 0; i < AR8327_NUM_PORTS; i++) {
1777 u32 mode;
1778
1779 if ((port_mask & BIT(i)) == 0)
1780 mode = AR8327_VTU_FUNC0_EG_MODE_NOT;
1781 else if (priv->vlan == 0)
1782 mode = AR8327_VTU_FUNC0_EG_MODE_KEEP;
1783 else if ((priv->vlan_tagged & BIT(i)) || (priv->vlan_id[priv->pvid[i]] != vid))
1784 mode = AR8327_VTU_FUNC0_EG_MODE_TAG;
1785 else
1786 mode = AR8327_VTU_FUNC0_EG_MODE_UNTAG;
1787
1788 val |= mode << AR8327_VTU_FUNC0_EG_MODE_S(i);
1789 }
1790 ar8327_vtu_op(priv, op, val);
1791 }
1792
1793 static void
1794 ar8327_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
1795 {
1796 u32 t;
1797 u32 egress, ingress;
1798 u32 pvid = priv->vlan_id[priv->pvid[port]];
1799
1800 if (priv->vlan) {
1801 egress = AR8327_PORT_VLAN1_OUT_MODE_UNMOD;
1802 ingress = AR8216_IN_SECURE;
1803 } else {
1804 egress = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH;
1805 ingress = AR8216_IN_PORT_ONLY;
1806 }
1807
1808 t = pvid << AR8327_PORT_VLAN0_DEF_SVID_S;
1809 t |= pvid << AR8327_PORT_VLAN0_DEF_CVID_S;
1810 priv->write(priv, AR8327_REG_PORT_VLAN0(port), t);
1811
1812 t = AR8327_PORT_VLAN1_PORT_VLAN_PROP;
1813 t |= egress << AR8327_PORT_VLAN1_OUT_MODE_S;
1814 priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
1815
1816 t = members;
1817 t |= AR8327_PORT_LOOKUP_LEARN;
1818 t |= ingress << AR8327_PORT_LOOKUP_IN_MODE_S;
1819 t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
1820 priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
1821 }
1822
1823 static const struct ar8xxx_chip ar8327_chip = {
1824 .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
1825 .config_at_probe = true,
1826 .hw_init = ar8327_hw_init,
1827 .cleanup = ar8327_cleanup,
1828 .init_globals = ar8327_init_globals,
1829 .init_port = ar8327_init_port,
1830 .setup_port = ar8327_setup_port,
1831 .read_port_status = ar8327_read_port_status,
1832 .atu_flush = ar8327_atu_flush,
1833 .vtu_flush = ar8327_vtu_flush,
1834 .vtu_load_vlan = ar8327_vtu_load_vlan,
1835 .phy_fixup = ar8327_phy_fixup,
1836
1837 .num_mibs = ARRAY_SIZE(ar8236_mibs),
1838 .mib_decs = ar8236_mibs,
1839 };
1840
1841 static int
1842 ar8xxx_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
1843 struct switch_val *val)
1844 {
1845 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1846 priv->vlan = !!val->value.i;
1847 return 0;
1848 }
1849
1850 static int
1851 ar8xxx_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
1852 struct switch_val *val)
1853 {
1854 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1855 val->value.i = priv->vlan;
1856 return 0;
1857 }
1858
1859
1860 static int
1861 ar8xxx_sw_set_pvid(struct switch_dev *dev, int port, int vlan)
1862 {
1863 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1864
1865 /* make sure no invalid PVIDs get set */
1866
1867 if (vlan >= dev->vlans)
1868 return -EINVAL;
1869
1870 priv->pvid[port] = vlan;
1871 return 0;
1872 }
1873
1874 static int
1875 ar8xxx_sw_get_pvid(struct switch_dev *dev, int port, int *vlan)
1876 {
1877 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1878 *vlan = priv->pvid[port];
1879 return 0;
1880 }
1881
1882 static int
1883 ar8xxx_sw_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
1884 struct switch_val *val)
1885 {
1886 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1887 priv->vlan_id[val->port_vlan] = val->value.i;
1888 return 0;
1889 }
1890
1891 static int
1892 ar8xxx_sw_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
1893 struct switch_val *val)
1894 {
1895 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1896 val->value.i = priv->vlan_id[val->port_vlan];
1897 return 0;
1898 }
1899
1900 static int
1901 ar8xxx_sw_get_port_link(struct switch_dev *dev, int port,
1902 struct switch_port_link *link)
1903 {
1904 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1905
1906 ar8216_read_port_link(priv, port, link);
1907 return 0;
1908 }
1909
1910 static int
1911 ar8xxx_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
1912 {
1913 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1914 u8 ports = priv->vlan_table[val->port_vlan];
1915 int i;
1916
1917 val->len = 0;
1918 for (i = 0; i < dev->ports; i++) {
1919 struct switch_port *p;
1920
1921 if (!(ports & (1 << i)))
1922 continue;
1923
1924 p = &val->value.ports[val->len++];
1925 p->id = i;
1926 if (priv->vlan_tagged & (1 << i))
1927 p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
1928 else
1929 p->flags = 0;
1930 }
1931 return 0;
1932 }
1933
1934 static int
1935 ar8327_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
1936 {
1937 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1938 u8 ports = priv->vlan_table[val->port_vlan];
1939 int i;
1940
1941 val->len = 0;
1942 for (i = 0; i < dev->ports; i++) {
1943 struct switch_port *p;
1944
1945 if (!(ports & (1 << i)))
1946 continue;
1947
1948 p = &val->value.ports[val->len++];
1949 p->id = i;
1950 if ((priv->vlan_tagged & (1 << i)) || (priv->pvid[i] != val->port_vlan))
1951 p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
1952 else
1953 p->flags = 0;
1954 }
1955 return 0;
1956 }
1957
1958 static int
1959 ar8xxx_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
1960 {
1961 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1962 u8 *vt = &priv->vlan_table[val->port_vlan];
1963 int i, j;
1964
1965 *vt = 0;
1966 for (i = 0; i < val->len; i++) {
1967 struct switch_port *p = &val->value.ports[i];
1968
1969 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
1970 priv->vlan_tagged |= (1 << p->id);
1971 } else {
1972 priv->vlan_tagged &= ~(1 << p->id);
1973 priv->pvid[p->id] = val->port_vlan;
1974
1975 /* make sure that an untagged port does not
1976 * appear in other vlans */
1977 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1978 if (j == val->port_vlan)
1979 continue;
1980 priv->vlan_table[j] &= ~(1 << p->id);
1981 }
1982 }
1983
1984 *vt |= 1 << p->id;
1985 }
1986 return 0;
1987 }
1988
1989 static int
1990 ar8327_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
1991 {
1992 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1993 u8 *vt = &priv->vlan_table[val->port_vlan];
1994 int i;
1995
1996 *vt = 0;
1997 for (i = 0; i < val->len; i++) {
1998 struct switch_port *p = &val->value.ports[i];
1999
2000 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
2001 if (val->port_vlan == priv->pvid[p->id]) {
2002 priv->vlan_tagged |= (1 << p->id);
2003 }
2004 } else {
2005 priv->vlan_tagged &= ~(1 << p->id);
2006 priv->pvid[p->id] = val->port_vlan;
2007 }
2008
2009 *vt |= 1 << p->id;
2010 }
2011 return 0;
2012 }
2013
2014 static void
2015 ar8327_set_mirror_regs(struct ar8xxx_priv *priv)
2016 {
2017 int port;
2018
2019 /* reset all mirror registers */
2020 ar8xxx_rmw(priv, AR8327_REG_FWD_CTRL0,
2021 AR8327_FWD_CTRL0_MIRROR_PORT,
2022 (0xF << AR8327_FWD_CTRL0_MIRROR_PORT_S));
2023 for (port = 0; port < AR8327_NUM_PORTS; port++) {
2024 ar8xxx_rmw(priv, AR8327_REG_PORT_LOOKUP(port),
2025 AR8327_PORT_LOOKUP_ING_MIRROR_EN,
2026 0);
2027
2028 ar8xxx_rmw(priv, AR8327_REG_PORT_HOL_CTRL1(port),
2029 AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN,
2030 0);
2031 }
2032
2033 /* now enable mirroring if necessary */
2034 if (priv->source_port >= AR8327_NUM_PORTS ||
2035 priv->monitor_port >= AR8327_NUM_PORTS ||
2036 priv->source_port == priv->monitor_port) {
2037 return;
2038 }
2039
2040 ar8xxx_rmw(priv, AR8327_REG_FWD_CTRL0,
2041 AR8327_FWD_CTRL0_MIRROR_PORT,
2042 (priv->monitor_port << AR8327_FWD_CTRL0_MIRROR_PORT_S));
2043
2044 if (priv->mirror_rx)
2045 ar8xxx_rmw(priv, AR8327_REG_PORT_LOOKUP(priv->source_port),
2046 AR8327_PORT_LOOKUP_ING_MIRROR_EN,
2047 AR8327_PORT_LOOKUP_ING_MIRROR_EN);
2048
2049 if (priv->mirror_tx)
2050 ar8xxx_rmw(priv, AR8327_REG_PORT_HOL_CTRL1(priv->source_port),
2051 AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN,
2052 AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN);
2053 }
2054
2055 static void
2056 ar8216_set_mirror_regs(struct ar8xxx_priv *priv)
2057 {
2058 int port;
2059
2060 /* reset all mirror registers */
2061 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
2062 AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
2063 (0xF << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
2064 for (port = 0; port < AR8216_NUM_PORTS; port++) {
2065 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
2066 AR8216_PORT_CTRL_MIRROR_RX,
2067 0);
2068
2069 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
2070 AR8216_PORT_CTRL_MIRROR_TX,
2071 0);
2072 }
2073
2074 /* now enable mirroring if necessary */
2075 if (priv->source_port >= AR8216_NUM_PORTS ||
2076 priv->monitor_port >= AR8216_NUM_PORTS ||
2077 priv->source_port == priv->monitor_port) {
2078 return;
2079 }
2080
2081 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
2082 AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
2083 (priv->monitor_port << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
2084
2085 if (priv->mirror_rx)
2086 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(priv->source_port),
2087 AR8216_PORT_CTRL_MIRROR_RX,
2088 AR8216_PORT_CTRL_MIRROR_RX);
2089
2090 if (priv->mirror_tx)
2091 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(priv->source_port),
2092 AR8216_PORT_CTRL_MIRROR_TX,
2093 AR8216_PORT_CTRL_MIRROR_TX);
2094 }
2095
2096 static void
2097 ar8xxx_set_mirror_regs(struct ar8xxx_priv *priv)
2098 {
2099 if (chip_is_ar8327(priv) || chip_is_ar8337(priv)) {
2100 ar8327_set_mirror_regs(priv);
2101 } else {
2102 ar8216_set_mirror_regs(priv);
2103 }
2104 }
2105
2106 static int
2107 ar8xxx_sw_hw_apply(struct switch_dev *dev)
2108 {
2109 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2110 u8 portmask[AR8X16_MAX_PORTS];
2111 int i, j;
2112
2113 mutex_lock(&priv->reg_mutex);
2114 /* flush all vlan translation unit entries */
2115 priv->chip->vtu_flush(priv);
2116
2117 memset(portmask, 0, sizeof(portmask));
2118 if (!priv->init) {
2119 /* calculate the port destination masks and load vlans
2120 * into the vlan translation unit */
2121 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
2122 u8 vp = priv->vlan_table[j];
2123
2124 if (!vp)
2125 continue;
2126
2127 for (i = 0; i < dev->ports; i++) {
2128 u8 mask = (1 << i);
2129 if (vp & mask)
2130 portmask[i] |= vp & ~mask;
2131 }
2132
2133 priv->chip->vtu_load_vlan(priv, priv->vlan_id[j],
2134 priv->vlan_table[j]);
2135 }
2136 } else {
2137 /* vlan disabled:
2138 * isolate all ports, but connect them to the cpu port */
2139 for (i = 0; i < dev->ports; i++) {
2140 if (i == AR8216_PORT_CPU)
2141 continue;
2142
2143 portmask[i] = 1 << AR8216_PORT_CPU;
2144 portmask[AR8216_PORT_CPU] |= (1 << i);
2145 }
2146 }
2147
2148 /* update the port destination mask registers and tag settings */
2149 for (i = 0; i < dev->ports; i++) {
2150 priv->chip->setup_port(priv, i, portmask[i]);
2151 }
2152
2153 ar8xxx_set_mirror_regs(priv);
2154
2155 mutex_unlock(&priv->reg_mutex);
2156 return 0;
2157 }
2158
2159 static int
2160 ar8xxx_sw_reset_switch(struct switch_dev *dev)
2161 {
2162 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2163 int i;
2164
2165 mutex_lock(&priv->reg_mutex);
2166 memset(&priv->vlan, 0, sizeof(struct ar8xxx_priv) -
2167 offsetof(struct ar8xxx_priv, vlan));
2168
2169 for (i = 0; i < AR8X16_MAX_VLANS; i++)
2170 priv->vlan_id[i] = i;
2171
2172 /* Configure all ports */
2173 for (i = 0; i < dev->ports; i++)
2174 priv->chip->init_port(priv, i);
2175
2176 priv->mirror_rx = false;
2177 priv->mirror_tx = false;
2178 priv->source_port = 0;
2179 priv->monitor_port = 0;
2180
2181 priv->chip->init_globals(priv);
2182
2183 mutex_unlock(&priv->reg_mutex);
2184
2185 return ar8xxx_sw_hw_apply(dev);
2186 }
2187
2188 static int
2189 ar8xxx_sw_set_reset_mibs(struct switch_dev *dev,
2190 const struct switch_attr *attr,
2191 struct switch_val *val)
2192 {
2193 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2194 unsigned int len;
2195 int ret;
2196
2197 if (!ar8xxx_has_mib_counters(priv))
2198 return -EOPNOTSUPP;
2199
2200 mutex_lock(&priv->mib_lock);
2201
2202 len = priv->dev.ports * priv->chip->num_mibs *
2203 sizeof(*priv->mib_stats);
2204 memset(priv->mib_stats, '\0', len);
2205 ret = ar8xxx_mib_flush(priv);
2206 if (ret)
2207 goto unlock;
2208
2209 ret = 0;
2210
2211 unlock:
2212 mutex_unlock(&priv->mib_lock);
2213 return ret;
2214 }
2215
2216 static int
2217 ar8xxx_sw_set_mirror_rx_enable(struct switch_dev *dev,
2218 const struct switch_attr *attr,
2219 struct switch_val *val)
2220 {
2221 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2222
2223 mutex_lock(&priv->reg_mutex);
2224 priv->mirror_rx = !!val->value.i;
2225 ar8xxx_set_mirror_regs(priv);
2226 mutex_unlock(&priv->reg_mutex);
2227
2228 return 0;
2229 }
2230
2231 static int
2232 ar8xxx_sw_get_mirror_rx_enable(struct switch_dev *dev,
2233 const struct switch_attr *attr,
2234 struct switch_val *val)
2235 {
2236 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2237 val->value.i = priv->mirror_rx;
2238 return 0;
2239 }
2240
2241 static int
2242 ar8xxx_sw_set_mirror_tx_enable(struct switch_dev *dev,
2243 const struct switch_attr *attr,
2244 struct switch_val *val)
2245 {
2246 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2247
2248 mutex_lock(&priv->reg_mutex);
2249 priv->mirror_tx = !!val->value.i;
2250 ar8xxx_set_mirror_regs(priv);
2251 mutex_unlock(&priv->reg_mutex);
2252
2253 return 0;
2254 }
2255
2256 static int
2257 ar8xxx_sw_get_mirror_tx_enable(struct switch_dev *dev,
2258 const struct switch_attr *attr,
2259 struct switch_val *val)
2260 {
2261 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2262 val->value.i = priv->mirror_tx;
2263 return 0;
2264 }
2265
2266 static int
2267 ar8xxx_sw_set_mirror_monitor_port(struct switch_dev *dev,
2268 const struct switch_attr *attr,
2269 struct switch_val *val)
2270 {
2271 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2272
2273 mutex_lock(&priv->reg_mutex);
2274 priv->monitor_port = val->value.i;
2275 ar8xxx_set_mirror_regs(priv);
2276 mutex_unlock(&priv->reg_mutex);
2277
2278 return 0;
2279 }
2280
2281 static int
2282 ar8xxx_sw_get_mirror_monitor_port(struct switch_dev *dev,
2283 const struct switch_attr *attr,
2284 struct switch_val *val)
2285 {
2286 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2287 val->value.i = priv->monitor_port;
2288 return 0;
2289 }
2290
2291 static int
2292 ar8xxx_sw_set_mirror_source_port(struct switch_dev *dev,
2293 const struct switch_attr *attr,
2294 struct switch_val *val)
2295 {
2296 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2297
2298 mutex_lock(&priv->reg_mutex);
2299 priv->source_port = val->value.i;
2300 ar8xxx_set_mirror_regs(priv);
2301 mutex_unlock(&priv->reg_mutex);
2302
2303 return 0;
2304 }
2305
2306 static int
2307 ar8xxx_sw_get_mirror_source_port(struct switch_dev *dev,
2308 const struct switch_attr *attr,
2309 struct switch_val *val)
2310 {
2311 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2312 val->value.i = priv->source_port;
2313 return 0;
2314 }
2315
2316 static int
2317 ar8xxx_sw_set_port_reset_mib(struct switch_dev *dev,
2318 const struct switch_attr *attr,
2319 struct switch_val *val)
2320 {
2321 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2322 int port;
2323 int ret;
2324
2325 if (!ar8xxx_has_mib_counters(priv))
2326 return -EOPNOTSUPP;
2327
2328 port = val->port_vlan;
2329 if (port >= dev->ports)
2330 return -EINVAL;
2331
2332 mutex_lock(&priv->mib_lock);
2333 ret = ar8xxx_mib_capture(priv);
2334 if (ret)
2335 goto unlock;
2336
2337 ar8xxx_mib_fetch_port_stat(priv, port, true);
2338
2339 ret = 0;
2340
2341 unlock:
2342 mutex_unlock(&priv->mib_lock);
2343 return ret;
2344 }
2345
2346 static int
2347 ar8xxx_sw_get_port_mib(struct switch_dev *dev,
2348 const struct switch_attr *attr,
2349 struct switch_val *val)
2350 {
2351 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2352 const struct ar8xxx_chip *chip = priv->chip;
2353 u64 *mib_stats;
2354 int port;
2355 int ret;
2356 char *buf = priv->buf;
2357 int i, len = 0;
2358
2359 if (!ar8xxx_has_mib_counters(priv))
2360 return -EOPNOTSUPP;
2361
2362 port = val->port_vlan;
2363 if (port >= dev->ports)
2364 return -EINVAL;
2365
2366 mutex_lock(&priv->mib_lock);
2367 ret = ar8xxx_mib_capture(priv);
2368 if (ret)
2369 goto unlock;
2370
2371 ar8xxx_mib_fetch_port_stat(priv, port, false);
2372
2373 len += snprintf(buf + len, sizeof(priv->buf) - len,
2374 "Port %d MIB counters\n",
2375 port);
2376
2377 mib_stats = &priv->mib_stats[port * chip->num_mibs];
2378 for (i = 0; i < chip->num_mibs; i++)
2379 len += snprintf(buf + len, sizeof(priv->buf) - len,
2380 "%-12s: %llu\n",
2381 chip->mib_decs[i].name,
2382 mib_stats[i]);
2383
2384 val->value.s = buf;
2385 val->len = len;
2386
2387 ret = 0;
2388
2389 unlock:
2390 mutex_unlock(&priv->mib_lock);
2391 return ret;
2392 }
2393
2394 static struct switch_attr ar8xxx_sw_attr_globals[] = {
2395 {
2396 .type = SWITCH_TYPE_INT,
2397 .name = "enable_vlan",
2398 .description = "Enable VLAN mode",
2399 .set = ar8xxx_sw_set_vlan,
2400 .get = ar8xxx_sw_get_vlan,
2401 .max = 1
2402 },
2403 {
2404 .type = SWITCH_TYPE_NOVAL,
2405 .name = "reset_mibs",
2406 .description = "Reset all MIB counters",
2407 .set = ar8xxx_sw_set_reset_mibs,
2408 },
2409 {
2410 .type = SWITCH_TYPE_INT,
2411 .name = "enable_mirror_rx",
2412 .description = "Enable mirroring of RX packets",
2413 .set = ar8xxx_sw_set_mirror_rx_enable,
2414 .get = ar8xxx_sw_get_mirror_rx_enable,
2415 .max = 1
2416 },
2417 {
2418 .type = SWITCH_TYPE_INT,
2419 .name = "enable_mirror_tx",
2420 .description = "Enable mirroring of TX packets",
2421 .set = ar8xxx_sw_set_mirror_tx_enable,
2422 .get = ar8xxx_sw_get_mirror_tx_enable,
2423 .max = 1
2424 },
2425 {
2426 .type = SWITCH_TYPE_INT,
2427 .name = "mirror_monitor_port",
2428 .description = "Mirror monitor port",
2429 .set = ar8xxx_sw_set_mirror_monitor_port,
2430 .get = ar8xxx_sw_get_mirror_monitor_port,
2431 .max = AR8216_NUM_PORTS - 1
2432 },
2433 {
2434 .type = SWITCH_TYPE_INT,
2435 .name = "mirror_source_port",
2436 .description = "Mirror source port",
2437 .set = ar8xxx_sw_set_mirror_source_port,
2438 .get = ar8xxx_sw_get_mirror_source_port,
2439 .max = AR8216_NUM_PORTS - 1
2440 },
2441 };
2442
2443 static struct switch_attr ar8327_sw_attr_globals[] = {
2444 {
2445 .type = SWITCH_TYPE_INT,
2446 .name = "enable_vlan",
2447 .description = "Enable VLAN mode",
2448 .set = ar8xxx_sw_set_vlan,
2449 .get = ar8xxx_sw_get_vlan,
2450 .max = 1
2451 },
2452 {
2453 .type = SWITCH_TYPE_NOVAL,
2454 .name = "reset_mibs",
2455 .description = "Reset all MIB counters",
2456 .set = ar8xxx_sw_set_reset_mibs,
2457 },
2458 {
2459 .type = SWITCH_TYPE_INT,
2460 .name = "enable_mirror_rx",
2461 .description = "Enable mirroring of RX packets",
2462 .set = ar8xxx_sw_set_mirror_rx_enable,
2463 .get = ar8xxx_sw_get_mirror_rx_enable,
2464 .max = 1
2465 },
2466 {
2467 .type = SWITCH_TYPE_INT,
2468 .name = "enable_mirror_tx",
2469 .description = "Enable mirroring of TX packets",
2470 .set = ar8xxx_sw_set_mirror_tx_enable,
2471 .get = ar8xxx_sw_get_mirror_tx_enable,
2472 .max = 1
2473 },
2474 {
2475 .type = SWITCH_TYPE_INT,
2476 .name = "mirror_monitor_port",
2477 .description = "Mirror monitor port",
2478 .set = ar8xxx_sw_set_mirror_monitor_port,
2479 .get = ar8xxx_sw_get_mirror_monitor_port,
2480 .max = AR8327_NUM_PORTS - 1
2481 },
2482 {
2483 .type = SWITCH_TYPE_INT,
2484 .name = "mirror_source_port",
2485 .description = "Mirror source port",
2486 .set = ar8xxx_sw_set_mirror_source_port,
2487 .get = ar8xxx_sw_get_mirror_source_port,
2488 .max = AR8327_NUM_PORTS - 1
2489 },
2490 };
2491
2492 static struct switch_attr ar8xxx_sw_attr_port[] = {
2493 {
2494 .type = SWITCH_TYPE_NOVAL,
2495 .name = "reset_mib",
2496 .description = "Reset single port MIB counters",
2497 .set = ar8xxx_sw_set_port_reset_mib,
2498 },
2499 {
2500 .type = SWITCH_TYPE_STRING,
2501 .name = "mib",
2502 .description = "Get port's MIB counters",
2503 .set = NULL,
2504 .get = ar8xxx_sw_get_port_mib,
2505 },
2506 };
2507
2508 static struct switch_attr ar8xxx_sw_attr_vlan[] = {
2509 {
2510 .type = SWITCH_TYPE_INT,
2511 .name = "vid",
2512 .description = "VLAN ID (0-4094)",
2513 .set = ar8xxx_sw_set_vid,
2514 .get = ar8xxx_sw_get_vid,
2515 .max = 4094,
2516 },
2517 };
2518
2519 static const struct switch_dev_ops ar8xxx_sw_ops = {
2520 .attr_global = {
2521 .attr = ar8xxx_sw_attr_globals,
2522 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_globals),
2523 },
2524 .attr_port = {
2525 .attr = ar8xxx_sw_attr_port,
2526 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_port),
2527 },
2528 .attr_vlan = {
2529 .attr = ar8xxx_sw_attr_vlan,
2530 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan),
2531 },
2532 .get_port_pvid = ar8xxx_sw_get_pvid,
2533 .set_port_pvid = ar8xxx_sw_set_pvid,
2534 .get_vlan_ports = ar8xxx_sw_get_ports,
2535 .set_vlan_ports = ar8xxx_sw_set_ports,
2536 .apply_config = ar8xxx_sw_hw_apply,
2537 .reset_switch = ar8xxx_sw_reset_switch,
2538 .get_port_link = ar8xxx_sw_get_port_link,
2539 };
2540
2541 static const struct switch_dev_ops ar8327_sw_ops = {
2542 .attr_global = {
2543 .attr = ar8327_sw_attr_globals,
2544 .n_attr = ARRAY_SIZE(ar8327_sw_attr_globals),
2545 },
2546 .attr_port = {
2547 .attr = ar8xxx_sw_attr_port,
2548 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_port),
2549 },
2550 .attr_vlan = {
2551 .attr = ar8xxx_sw_attr_vlan,
2552 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan),
2553 },
2554 .get_port_pvid = ar8xxx_sw_get_pvid,
2555 .set_port_pvid = ar8xxx_sw_set_pvid,
2556 .get_vlan_ports = ar8327_sw_get_ports,
2557 .set_vlan_ports = ar8327_sw_set_ports,
2558 .apply_config = ar8xxx_sw_hw_apply,
2559 .reset_switch = ar8xxx_sw_reset_switch,
2560 .get_port_link = ar8xxx_sw_get_port_link,
2561 };
2562
2563 static int
2564 ar8xxx_id_chip(struct ar8xxx_priv *priv)
2565 {
2566 u32 val;
2567 u16 id;
2568 int i;
2569
2570 val = priv->read(priv, AR8216_REG_CTRL);
2571 if (val == ~0)
2572 return -ENODEV;
2573
2574 id = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
2575 for (i = 0; i < AR8X16_PROBE_RETRIES; i++) {
2576 u16 t;
2577
2578 val = priv->read(priv, AR8216_REG_CTRL);
2579 if (val == ~0)
2580 return -ENODEV;
2581
2582 t = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
2583 if (t != id)
2584 return -ENODEV;
2585 }
2586
2587 priv->chip_ver = (id & AR8216_CTRL_VERSION) >> AR8216_CTRL_VERSION_S;
2588 priv->chip_rev = (id & AR8216_CTRL_REVISION);
2589
2590 switch (priv->chip_ver) {
2591 case AR8XXX_VER_AR8216:
2592 priv->chip = &ar8216_chip;
2593 break;
2594 case AR8XXX_VER_AR8236:
2595 priv->chip = &ar8236_chip;
2596 break;
2597 case AR8XXX_VER_AR8316:
2598 priv->chip = &ar8316_chip;
2599 break;
2600 case AR8XXX_VER_AR8327:
2601 priv->mii_lo_first = true;
2602 priv->chip = &ar8327_chip;
2603 break;
2604 case AR8XXX_VER_AR8337:
2605 priv->mii_lo_first = true;
2606 priv->chip = &ar8327_chip;
2607 break;
2608 default:
2609 pr_err("ar8216: Unknown Atheros device [ver=%d, rev=%d]\n",
2610 priv->chip_ver, priv->chip_rev);
2611
2612 return -ENODEV;
2613 }
2614
2615 return 0;
2616 }
2617
2618 static void
2619 ar8xxx_mib_work_func(struct work_struct *work)
2620 {
2621 struct ar8xxx_priv *priv;
2622 int err;
2623
2624 priv = container_of(work, struct ar8xxx_priv, mib_work.work);
2625
2626 mutex_lock(&priv->mib_lock);
2627
2628 err = ar8xxx_mib_capture(priv);
2629 if (err)
2630 goto next_port;
2631
2632 ar8xxx_mib_fetch_port_stat(priv, priv->mib_next_port, false);
2633
2634 next_port:
2635 priv->mib_next_port++;
2636 if (priv->mib_next_port >= priv->dev.ports)
2637 priv->mib_next_port = 0;
2638
2639 mutex_unlock(&priv->mib_lock);
2640 schedule_delayed_work(&priv->mib_work,
2641 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
2642 }
2643
2644 static int
2645 ar8xxx_mib_init(struct ar8xxx_priv *priv)
2646 {
2647 unsigned int len;
2648
2649 if (!ar8xxx_has_mib_counters(priv))
2650 return 0;
2651
2652 BUG_ON(!priv->chip->mib_decs || !priv->chip->num_mibs);
2653
2654 len = priv->dev.ports * priv->chip->num_mibs *
2655 sizeof(*priv->mib_stats);
2656 priv->mib_stats = kzalloc(len, GFP_KERNEL);
2657
2658 if (!priv->mib_stats)
2659 return -ENOMEM;
2660
2661 return 0;
2662 }
2663
2664 static void
2665 ar8xxx_mib_start(struct ar8xxx_priv *priv)
2666 {
2667 if (!ar8xxx_has_mib_counters(priv))
2668 return;
2669
2670 schedule_delayed_work(&priv->mib_work,
2671 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
2672 }
2673
2674 static void
2675 ar8xxx_mib_stop(struct ar8xxx_priv *priv)
2676 {
2677 if (!ar8xxx_has_mib_counters(priv))
2678 return;
2679
2680 cancel_delayed_work(&priv->mib_work);
2681 }
2682
2683 static struct ar8xxx_priv *
2684 ar8xxx_create(void)
2685 {
2686 struct ar8xxx_priv *priv;
2687
2688 priv = kzalloc(sizeof(struct ar8xxx_priv), GFP_KERNEL);
2689 if (priv == NULL)
2690 return NULL;
2691
2692 mutex_init(&priv->reg_mutex);
2693 mutex_init(&priv->mib_lock);
2694 INIT_DELAYED_WORK(&priv->mib_work, ar8xxx_mib_work_func);
2695
2696 return priv;
2697 }
2698
2699 static void
2700 ar8xxx_free(struct ar8xxx_priv *priv)
2701 {
2702 if (priv->chip && priv->chip->cleanup)
2703 priv->chip->cleanup(priv);
2704
2705 kfree(priv->mib_stats);
2706 kfree(priv);
2707 }
2708
2709 static struct ar8xxx_priv *
2710 ar8xxx_create_mii(struct mii_bus *bus)
2711 {
2712 struct ar8xxx_priv *priv;
2713
2714 priv = ar8xxx_create();
2715 if (priv) {
2716 priv->mii_bus = bus;
2717 priv->read = ar8xxx_mii_read;
2718 priv->write = ar8xxx_mii_write;
2719 priv->rmw = ar8xxx_mii_rmw;
2720 }
2721
2722 return priv;
2723 }
2724
2725 static int
2726 ar8xxx_probe_switch(struct ar8xxx_priv *priv)
2727 {
2728 struct switch_dev *swdev;
2729 int ret;
2730
2731 ret = ar8xxx_id_chip(priv);
2732 if (ret)
2733 return ret;
2734
2735 swdev = &priv->dev;
2736 swdev->cpu_port = AR8216_PORT_CPU;
2737 swdev->ops = &ar8xxx_sw_ops;
2738
2739 if (chip_is_ar8316(priv)) {
2740 swdev->name = "Atheros AR8316";
2741 swdev->vlans = AR8X16_MAX_VLANS;
2742 swdev->ports = AR8216_NUM_PORTS;
2743 } else if (chip_is_ar8236(priv)) {
2744 swdev->name = "Atheros AR8236";
2745 swdev->vlans = AR8216_NUM_VLANS;
2746 swdev->ports = AR8216_NUM_PORTS;
2747 } else if (chip_is_ar8327(priv)) {
2748 swdev->name = "Atheros AR8327";
2749 swdev->vlans = AR8X16_MAX_VLANS;
2750 swdev->ports = AR8327_NUM_PORTS;
2751 swdev->ops = &ar8327_sw_ops;
2752 } else if (chip_is_ar8337(priv)) {
2753 swdev->name = "Atheros AR8337";
2754 swdev->vlans = AR8X16_MAX_VLANS;
2755 swdev->ports = AR8327_NUM_PORTS;
2756 swdev->ops = &ar8327_sw_ops;
2757 } else {
2758 swdev->name = "Atheros AR8216";
2759 swdev->vlans = AR8216_NUM_VLANS;
2760 swdev->ports = AR8216_NUM_PORTS;
2761 }
2762
2763 ret = ar8xxx_mib_init(priv);
2764 if (ret)
2765 return ret;
2766
2767 return 0;
2768 }
2769
2770 static int
2771 ar8xxx_start(struct ar8xxx_priv *priv)
2772 {
2773 int ret;
2774
2775 priv->init = true;
2776
2777 ret = priv->chip->hw_init(priv);
2778 if (ret)
2779 return ret;
2780
2781 ret = ar8xxx_sw_reset_switch(&priv->dev);
2782 if (ret)
2783 return ret;
2784
2785 priv->init = false;
2786
2787 ar8xxx_mib_start(priv);
2788
2789 return 0;
2790 }
2791
2792 static int
2793 ar8xxx_phy_config_init(struct phy_device *phydev)
2794 {
2795 struct ar8xxx_priv *priv = phydev->priv;
2796 struct net_device *dev = phydev->attached_dev;
2797 int ret;
2798
2799 if (WARN_ON(!priv))
2800 return -ENODEV;
2801
2802 if (priv->chip->config_at_probe)
2803 return ar8xxx_phy_check_aneg(phydev);
2804
2805 priv->phy = phydev;
2806
2807 if (phydev->addr != 0) {
2808 if (chip_is_ar8316(priv)) {
2809 /* switch device has been initialized, reinit */
2810 priv->dev.ports = (AR8216_NUM_PORTS - 1);
2811 priv->initialized = false;
2812 priv->port4_phy = true;
2813 ar8316_hw_init(priv);
2814 return 0;
2815 }
2816
2817 return 0;
2818 }
2819
2820 ret = ar8xxx_start(priv);
2821 if (ret)
2822 return ret;
2823
2824 /* VID fixup only needed on ar8216 */
2825 if (chip_is_ar8216(priv)) {
2826 dev->phy_ptr = priv;
2827 dev->priv_flags |= IFF_NO_IP_ALIGN;
2828 dev->eth_mangle_rx = ar8216_mangle_rx;
2829 dev->eth_mangle_tx = ar8216_mangle_tx;
2830 }
2831
2832 return 0;
2833 }
2834
2835 static int
2836 ar8xxx_phy_read_status(struct phy_device *phydev)
2837 {
2838 struct ar8xxx_priv *priv = phydev->priv;
2839 struct switch_port_link link;
2840 int ret;
2841
2842 if (phydev->addr != 0)
2843 return genphy_read_status(phydev);
2844
2845 ar8216_read_port_link(priv, phydev->addr, &link);
2846 phydev->link = !!link.link;
2847 if (!phydev->link)
2848 return 0;
2849
2850 switch (link.speed) {
2851 case SWITCH_PORT_SPEED_10:
2852 phydev->speed = SPEED_10;
2853 break;
2854 case SWITCH_PORT_SPEED_100:
2855 phydev->speed = SPEED_100;
2856 break;
2857 case SWITCH_PORT_SPEED_1000:
2858 phydev->speed = SPEED_1000;
2859 break;
2860 default:
2861 phydev->speed = 0;
2862 }
2863 phydev->duplex = link.duplex ? DUPLEX_FULL : DUPLEX_HALF;
2864
2865 /* flush the address translation unit */
2866 mutex_lock(&priv->reg_mutex);
2867 ret = priv->chip->atu_flush(priv);
2868 mutex_unlock(&priv->reg_mutex);
2869
2870 phydev->state = PHY_RUNNING;
2871 netif_carrier_on(phydev->attached_dev);
2872 phydev->adjust_link(phydev->attached_dev);
2873
2874 return ret;
2875 }
2876
2877 static int
2878 ar8xxx_phy_config_aneg(struct phy_device *phydev)
2879 {
2880 if (phydev->addr == 0)
2881 return 0;
2882
2883 return genphy_config_aneg(phydev);
2884 }
2885
2886 static const u32 ar8xxx_phy_ids[] = {
2887 0x004dd033,
2888 0x004dd034, /* AR8327 */
2889 0x004dd036, /* AR8337 */
2890 0x004dd041,
2891 0x004dd042,
2892 0x004dd043, /* AR8236 */
2893 };
2894
2895 static bool
2896 ar8xxx_phy_match(u32 phy_id)
2897 {
2898 int i;
2899
2900 for (i = 0; i < ARRAY_SIZE(ar8xxx_phy_ids); i++)
2901 if (phy_id == ar8xxx_phy_ids[i])
2902 return true;
2903
2904 return false;
2905 }
2906
2907 static bool
2908 ar8xxx_is_possible(struct mii_bus *bus)
2909 {
2910 unsigned i;
2911
2912 for (i = 0; i < 4; i++) {
2913 u32 phy_id;
2914
2915 phy_id = mdiobus_read(bus, i, MII_PHYSID1) << 16;
2916 phy_id |= mdiobus_read(bus, i, MII_PHYSID2);
2917 if (!ar8xxx_phy_match(phy_id)) {
2918 pr_debug("ar8xxx: unknown PHY at %s:%02x id:%08x\n",
2919 dev_name(&bus->dev), i, phy_id);
2920 return false;
2921 }
2922 }
2923
2924 return true;
2925 }
2926
2927 static int
2928 ar8xxx_phy_probe(struct phy_device *phydev)
2929 {
2930 struct ar8xxx_priv *priv;
2931 struct switch_dev *swdev;
2932 int ret;
2933
2934 /* skip PHYs at unused adresses */
2935 if (phydev->addr != 0 && phydev->addr != 4)
2936 return -ENODEV;
2937
2938 if (!ar8xxx_is_possible(phydev->bus))
2939 return -ENODEV;
2940
2941 mutex_lock(&ar8xxx_dev_list_lock);
2942 list_for_each_entry(priv, &ar8xxx_dev_list, list)
2943 if (priv->mii_bus == phydev->bus)
2944 goto found;
2945
2946 priv = ar8xxx_create_mii(phydev->bus);
2947 if (priv == NULL) {
2948 ret = -ENOMEM;
2949 goto unlock;
2950 }
2951
2952 ret = ar8xxx_probe_switch(priv);
2953 if (ret)
2954 goto free_priv;
2955
2956 swdev = &priv->dev;
2957 swdev->alias = dev_name(&priv->mii_bus->dev);
2958 ret = register_switch(swdev, NULL);
2959 if (ret)
2960 goto free_priv;
2961
2962 pr_info("%s: %s rev. %u switch registered on %s\n",
2963 swdev->devname, swdev->name, priv->chip_rev,
2964 dev_name(&priv->mii_bus->dev));
2965
2966 found:
2967 priv->use_count++;
2968
2969 if (phydev->addr == 0) {
2970 if (ar8xxx_has_gige(priv)) {
2971 phydev->supported = SUPPORTED_1000baseT_Full;
2972 phydev->advertising = ADVERTISED_1000baseT_Full;
2973 } else {
2974 phydev->supported = SUPPORTED_100baseT_Full;
2975 phydev->advertising = ADVERTISED_100baseT_Full;
2976 }
2977
2978 if (priv->chip->config_at_probe) {
2979 priv->phy = phydev;
2980
2981 ret = ar8xxx_start(priv);
2982 if (ret)
2983 goto err_unregister_switch;
2984 }
2985 } else {
2986 if (ar8xxx_has_gige(priv)) {
2987 phydev->supported |= SUPPORTED_1000baseT_Full;
2988 phydev->advertising |= ADVERTISED_1000baseT_Full;
2989 }
2990 }
2991
2992 phydev->priv = priv;
2993
2994 list_add(&priv->list, &ar8xxx_dev_list);
2995
2996 mutex_unlock(&ar8xxx_dev_list_lock);
2997
2998 return 0;
2999
3000 err_unregister_switch:
3001 if (--priv->use_count)
3002 goto unlock;
3003
3004 unregister_switch(&priv->dev);
3005
3006 free_priv:
3007 ar8xxx_free(priv);
3008 unlock:
3009 mutex_unlock(&ar8xxx_dev_list_lock);
3010 return ret;
3011 }
3012
3013 static void
3014 ar8xxx_phy_detach(struct phy_device *phydev)
3015 {
3016 struct net_device *dev = phydev->attached_dev;
3017
3018 if (!dev)
3019 return;
3020
3021 dev->phy_ptr = NULL;
3022 dev->priv_flags &= ~IFF_NO_IP_ALIGN;
3023 dev->eth_mangle_rx = NULL;
3024 dev->eth_mangle_tx = NULL;
3025 }
3026
3027 static void
3028 ar8xxx_phy_remove(struct phy_device *phydev)
3029 {
3030 struct ar8xxx_priv *priv = phydev->priv;
3031
3032 if (WARN_ON(!priv))
3033 return;
3034
3035 phydev->priv = NULL;
3036 if (--priv->use_count > 0)
3037 return;
3038
3039 mutex_lock(&ar8xxx_dev_list_lock);
3040 list_del(&priv->list);
3041 mutex_unlock(&ar8xxx_dev_list_lock);
3042
3043 unregister_switch(&priv->dev);
3044 ar8xxx_mib_stop(priv);
3045 ar8xxx_free(priv);
3046 }
3047
3048 #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)
3049 static int
3050 ar8xxx_phy_soft_reset(struct phy_device *phydev)
3051 {
3052 /* we don't need an extra reset */
3053 return 0;
3054 }
3055 #endif
3056
3057 static struct phy_driver ar8xxx_phy_driver = {
3058 .phy_id = 0x004d0000,
3059 .name = "Atheros AR8216/AR8236/AR8316",
3060 .phy_id_mask = 0xffff0000,
3061 .features = PHY_BASIC_FEATURES,
3062 .probe = ar8xxx_phy_probe,
3063 .remove = ar8xxx_phy_remove,
3064 .detach = ar8xxx_phy_detach,
3065 .config_init = ar8xxx_phy_config_init,
3066 .config_aneg = ar8xxx_phy_config_aneg,
3067 .read_status = ar8xxx_phy_read_status,
3068 #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)
3069 .soft_reset = ar8xxx_phy_soft_reset,
3070 #endif
3071 .driver = { .owner = THIS_MODULE },
3072 };
3073
3074 int __init
3075 ar8xxx_init(void)
3076 {
3077 return phy_driver_register(&ar8xxx_phy_driver);
3078 }
3079
3080 void __exit
3081 ar8xxx_exit(void)
3082 {
3083 phy_driver_unregister(&ar8xxx_phy_driver);
3084 }
3085
3086 module_init(ar8xxx_init);
3087 module_exit(ar8xxx_exit);
3088 MODULE_LICENSE("GPL");
3089
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