2 * ar8216.c: AR8216 switch driver
4 * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>
5 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/list.h>
22 #include <linux/if_ether.h>
23 #include <linux/skbuff.h>
24 #include <linux/netdevice.h>
25 #include <linux/netlink.h>
26 #include <linux/of_device.h>
27 #include <linux/of_mdio.h>
28 #include <linux/of_net.h>
29 #include <linux/bitops.h>
30 #include <net/genetlink.h>
31 #include <linux/switch.h>
32 #include <linux/delay.h>
33 #include <linux/phy.h>
34 #include <linux/etherdevice.h>
35 #include <linux/lockdep.h>
36 #include <linux/ar8216_platform.h>
37 #include <linux/workqueue.h>
38 #include <linux/version.h>
42 extern const struct ar8xxx_chip ar8327_chip
;
43 extern const struct ar8xxx_chip ar8337_chip
;
45 #define MIB_DESC_BASIC(_s , _o, _n) \
50 .type = AR8XXX_MIB_BASIC, \
53 #define MIB_DESC_EXT(_s , _o, _n) \
58 .type = AR8XXX_MIB_EXTENDED, \
61 static const struct ar8xxx_mib_desc ar8216_mibs
[] = {
62 MIB_DESC_EXT(1, AR8216_STATS_RXBROAD
, "RxBroad"),
63 MIB_DESC_EXT(1, AR8216_STATS_RXPAUSE
, "RxPause"),
64 MIB_DESC_EXT(1, AR8216_STATS_RXMULTI
, "RxMulti"),
65 MIB_DESC_EXT(1, AR8216_STATS_RXFCSERR
, "RxFcsErr"),
66 MIB_DESC_EXT(1, AR8216_STATS_RXALIGNERR
, "RxAlignErr"),
67 MIB_DESC_EXT(1, AR8216_STATS_RXRUNT
, "RxRunt"),
68 MIB_DESC_EXT(1, AR8216_STATS_RXFRAGMENT
, "RxFragment"),
69 MIB_DESC_EXT(1, AR8216_STATS_RX64BYTE
, "Rx64Byte"),
70 MIB_DESC_EXT(1, AR8216_STATS_RX128BYTE
, "Rx128Byte"),
71 MIB_DESC_EXT(1, AR8216_STATS_RX256BYTE
, "Rx256Byte"),
72 MIB_DESC_EXT(1, AR8216_STATS_RX512BYTE
, "Rx512Byte"),
73 MIB_DESC_EXT(1, AR8216_STATS_RX1024BYTE
, "Rx1024Byte"),
74 MIB_DESC_EXT(1, AR8216_STATS_RXMAXBYTE
, "RxMaxByte"),
75 MIB_DESC_EXT(1, AR8216_STATS_RXTOOLONG
, "RxTooLong"),
76 MIB_DESC_BASIC(2, AR8216_STATS_RXGOODBYTE
, "RxGoodByte"),
77 MIB_DESC_EXT(2, AR8216_STATS_RXBADBYTE
, "RxBadByte"),
78 MIB_DESC_EXT(1, AR8216_STATS_RXOVERFLOW
, "RxOverFlow"),
79 MIB_DESC_EXT(1, AR8216_STATS_FILTERED
, "Filtered"),
80 MIB_DESC_EXT(1, AR8216_STATS_TXBROAD
, "TxBroad"),
81 MIB_DESC_EXT(1, AR8216_STATS_TXPAUSE
, "TxPause"),
82 MIB_DESC_EXT(1, AR8216_STATS_TXMULTI
, "TxMulti"),
83 MIB_DESC_EXT(1, AR8216_STATS_TXUNDERRUN
, "TxUnderRun"),
84 MIB_DESC_EXT(1, AR8216_STATS_TX64BYTE
, "Tx64Byte"),
85 MIB_DESC_EXT(1, AR8216_STATS_TX128BYTE
, "Tx128Byte"),
86 MIB_DESC_EXT(1, AR8216_STATS_TX256BYTE
, "Tx256Byte"),
87 MIB_DESC_EXT(1, AR8216_STATS_TX512BYTE
, "Tx512Byte"),
88 MIB_DESC_EXT(1, AR8216_STATS_TX1024BYTE
, "Tx1024Byte"),
89 MIB_DESC_EXT(1, AR8216_STATS_TXMAXBYTE
, "TxMaxByte"),
90 MIB_DESC_EXT(1, AR8216_STATS_TXOVERSIZE
, "TxOverSize"),
91 MIB_DESC_BASIC(2, AR8216_STATS_TXBYTE
, "TxByte"),
92 MIB_DESC_EXT(1, AR8216_STATS_TXCOLLISION
, "TxCollision"),
93 MIB_DESC_EXT(1, AR8216_STATS_TXABORTCOL
, "TxAbortCol"),
94 MIB_DESC_EXT(1, AR8216_STATS_TXMULTICOL
, "TxMultiCol"),
95 MIB_DESC_EXT(1, AR8216_STATS_TXSINGLECOL
, "TxSingleCol"),
96 MIB_DESC_EXT(1, AR8216_STATS_TXEXCDEFER
, "TxExcDefer"),
97 MIB_DESC_EXT(1, AR8216_STATS_TXDEFER
, "TxDefer"),
98 MIB_DESC_EXT(1, AR8216_STATS_TXLATECOL
, "TxLateCol"),
101 const struct ar8xxx_mib_desc ar8236_mibs
[39] = {
102 MIB_DESC_EXT(1, AR8236_STATS_RXBROAD
, "RxBroad"),
103 MIB_DESC_EXT(1, AR8236_STATS_RXPAUSE
, "RxPause"),
104 MIB_DESC_EXT(1, AR8236_STATS_RXMULTI
, "RxMulti"),
105 MIB_DESC_EXT(1, AR8236_STATS_RXFCSERR
, "RxFcsErr"),
106 MIB_DESC_EXT(1, AR8236_STATS_RXALIGNERR
, "RxAlignErr"),
107 MIB_DESC_EXT(1, AR8236_STATS_RXRUNT
, "RxRunt"),
108 MIB_DESC_EXT(1, AR8236_STATS_RXFRAGMENT
, "RxFragment"),
109 MIB_DESC_EXT(1, AR8236_STATS_RX64BYTE
, "Rx64Byte"),
110 MIB_DESC_EXT(1, AR8236_STATS_RX128BYTE
, "Rx128Byte"),
111 MIB_DESC_EXT(1, AR8236_STATS_RX256BYTE
, "Rx256Byte"),
112 MIB_DESC_EXT(1, AR8236_STATS_RX512BYTE
, "Rx512Byte"),
113 MIB_DESC_EXT(1, AR8236_STATS_RX1024BYTE
, "Rx1024Byte"),
114 MIB_DESC_EXT(1, AR8236_STATS_RX1518BYTE
, "Rx1518Byte"),
115 MIB_DESC_EXT(1, AR8236_STATS_RXMAXBYTE
, "RxMaxByte"),
116 MIB_DESC_EXT(1, AR8236_STATS_RXTOOLONG
, "RxTooLong"),
117 MIB_DESC_BASIC(2, AR8236_STATS_RXGOODBYTE
, "RxGoodByte"),
118 MIB_DESC_EXT(2, AR8236_STATS_RXBADBYTE
, "RxBadByte"),
119 MIB_DESC_EXT(1, AR8236_STATS_RXOVERFLOW
, "RxOverFlow"),
120 MIB_DESC_EXT(1, AR8236_STATS_FILTERED
, "Filtered"),
121 MIB_DESC_EXT(1, AR8236_STATS_TXBROAD
, "TxBroad"),
122 MIB_DESC_EXT(1, AR8236_STATS_TXPAUSE
, "TxPause"),
123 MIB_DESC_EXT(1, AR8236_STATS_TXMULTI
, "TxMulti"),
124 MIB_DESC_EXT(1, AR8236_STATS_TXUNDERRUN
, "TxUnderRun"),
125 MIB_DESC_EXT(1, AR8236_STATS_TX64BYTE
, "Tx64Byte"),
126 MIB_DESC_EXT(1, AR8236_STATS_TX128BYTE
, "Tx128Byte"),
127 MIB_DESC_EXT(1, AR8236_STATS_TX256BYTE
, "Tx256Byte"),
128 MIB_DESC_EXT(1, AR8236_STATS_TX512BYTE
, "Tx512Byte"),
129 MIB_DESC_EXT(1, AR8236_STATS_TX1024BYTE
, "Tx1024Byte"),
130 MIB_DESC_EXT(1, AR8236_STATS_TX1518BYTE
, "Tx1518Byte"),
131 MIB_DESC_EXT(1, AR8236_STATS_TXMAXBYTE
, "TxMaxByte"),
132 MIB_DESC_EXT(1, AR8236_STATS_TXOVERSIZE
, "TxOverSize"),
133 MIB_DESC_BASIC(2, AR8236_STATS_TXBYTE
, "TxByte"),
134 MIB_DESC_EXT(1, AR8236_STATS_TXCOLLISION
, "TxCollision"),
135 MIB_DESC_EXT(1, AR8236_STATS_TXABORTCOL
, "TxAbortCol"),
136 MIB_DESC_EXT(1, AR8236_STATS_TXMULTICOL
, "TxMultiCol"),
137 MIB_DESC_EXT(1, AR8236_STATS_TXSINGLECOL
, "TxSingleCol"),
138 MIB_DESC_EXT(1, AR8236_STATS_TXEXCDEFER
, "TxExcDefer"),
139 MIB_DESC_EXT(1, AR8236_STATS_TXDEFER
, "TxDefer"),
140 MIB_DESC_EXT(1, AR8236_STATS_TXLATECOL
, "TxLateCol"),
143 static DEFINE_MUTEX(ar8xxx_dev_list_lock
);
144 static LIST_HEAD(ar8xxx_dev_list
);
147 ar8xxx_mib_start(struct ar8xxx_priv
*priv
);
149 ar8xxx_mib_stop(struct ar8xxx_priv
*priv
);
151 /* inspired by phy_poll_reset in drivers/net/phy/phy_device.c */
153 ar8xxx_phy_poll_reset(struct mii_bus
*bus
)
155 unsigned int sleep_msecs
= 20;
158 for (elapsed
= sleep_msecs
; elapsed
<= 600;
159 elapsed
+= sleep_msecs
) {
161 for (i
= 0; i
< AR8XXX_NUM_PHYS
; i
++) {
162 ret
= mdiobus_read(bus
, i
, MII_BMCR
);
165 if (ret
& BMCR_RESET
)
167 if (i
== AR8XXX_NUM_PHYS
- 1) {
168 usleep_range(1000, 2000);
177 ar8xxx_phy_check_aneg(struct phy_device
*phydev
)
181 if (phydev
->autoneg
!= AUTONEG_ENABLE
)
184 * BMCR_ANENABLE might have been cleared
185 * by phy_init_hw in certain kernel versions
186 * therefore check for it
188 ret
= phy_read(phydev
, MII_BMCR
);
191 if (ret
& BMCR_ANENABLE
)
194 dev_info(&phydev
->mdio
.dev
, "ANEG disabled, re-enabling ...\n");
195 ret
|= BMCR_ANENABLE
| BMCR_ANRESTART
;
196 return phy_write(phydev
, MII_BMCR
, ret
);
200 ar8xxx_phy_init(struct ar8xxx_priv
*priv
)
205 bus
= priv
->sw_mii_bus
?: priv
->mii_bus
;
206 for (i
= 0; i
< AR8XXX_NUM_PHYS
; i
++) {
207 if (priv
->chip
->phy_fixup
)
208 priv
->chip
->phy_fixup(priv
, i
);
210 /* initialize the port itself */
211 mdiobus_write(bus
, i
, MII_ADVERTISE
,
212 ADVERTISE_ALL
| ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
);
213 if (ar8xxx_has_gige(priv
))
214 mdiobus_write(bus
, i
, MII_CTRL1000
, ADVERTISE_1000FULL
);
215 mdiobus_write(bus
, i
, MII_BMCR
, BMCR_RESET
| BMCR_ANENABLE
);
218 ar8xxx_phy_poll_reset(bus
);
222 ar8xxx_mii_read32(struct ar8xxx_priv
*priv
, int phy_id
, int regnum
)
224 struct mii_bus
*bus
= priv
->mii_bus
;
227 lo
= bus
->read(bus
, phy_id
, regnum
);
228 hi
= bus
->read(bus
, phy_id
, regnum
+ 1);
230 return (hi
<< 16) | lo
;
234 ar8xxx_mii_write32(struct ar8xxx_priv
*priv
, int phy_id
, int regnum
, u32 val
)
236 struct mii_bus
*bus
= priv
->mii_bus
;
240 hi
= (u16
) (val
>> 16);
242 if (priv
->chip
->mii_lo_first
)
244 bus
->write(bus
, phy_id
, regnum
, lo
);
245 bus
->write(bus
, phy_id
, regnum
+ 1, hi
);
247 bus
->write(bus
, phy_id
, regnum
+ 1, hi
);
248 bus
->write(bus
, phy_id
, regnum
, lo
);
253 ar8xxx_read(struct ar8xxx_priv
*priv
, int reg
)
255 struct mii_bus
*bus
= priv
->mii_bus
;
259 split_addr((u32
) reg
, &r1
, &r2
, &page
);
261 mutex_lock(&bus
->mdio_lock
);
263 bus
->write(bus
, 0x18, 0, page
);
264 wait_for_page_switch();
265 val
= ar8xxx_mii_read32(priv
, 0x10 | r2
, r1
);
267 mutex_unlock(&bus
->mdio_lock
);
273 ar8xxx_write(struct ar8xxx_priv
*priv
, int reg
, u32 val
)
275 struct mii_bus
*bus
= priv
->mii_bus
;
278 split_addr((u32
) reg
, &r1
, &r2
, &page
);
280 mutex_lock(&bus
->mdio_lock
);
282 bus
->write(bus
, 0x18, 0, page
);
283 wait_for_page_switch();
284 ar8xxx_mii_write32(priv
, 0x10 | r2
, r1
, val
);
286 mutex_unlock(&bus
->mdio_lock
);
290 ar8xxx_rmw(struct ar8xxx_priv
*priv
, int reg
, u32 mask
, u32 val
)
292 struct mii_bus
*bus
= priv
->mii_bus
;
296 split_addr((u32
) reg
, &r1
, &r2
, &page
);
298 mutex_lock(&bus
->mdio_lock
);
300 bus
->write(bus
, 0x18, 0, page
);
301 wait_for_page_switch();
303 ret
= ar8xxx_mii_read32(priv
, 0x10 | r2
, r1
);
306 ar8xxx_mii_write32(priv
, 0x10 | r2
, r1
, ret
);
308 mutex_unlock(&bus
->mdio_lock
);
313 ar8xxx_phy_dbg_read(struct ar8xxx_priv
*priv
, int phy_addr
,
314 u16 dbg_addr
, u16
*dbg_data
)
316 struct mii_bus
*bus
= priv
->mii_bus
;
318 mutex_lock(&bus
->mdio_lock
);
319 bus
->write(bus
, phy_addr
, MII_ATH_DBG_ADDR
, dbg_addr
);
320 *dbg_data
= bus
->read(bus
, phy_addr
, MII_ATH_DBG_DATA
);
321 mutex_unlock(&bus
->mdio_lock
);
325 ar8xxx_phy_dbg_write(struct ar8xxx_priv
*priv
, int phy_addr
,
326 u16 dbg_addr
, u16 dbg_data
)
328 struct mii_bus
*bus
= priv
->mii_bus
;
330 mutex_lock(&bus
->mdio_lock
);
331 bus
->write(bus
, phy_addr
, MII_ATH_DBG_ADDR
, dbg_addr
);
332 bus
->write(bus
, phy_addr
, MII_ATH_DBG_DATA
, dbg_data
);
333 mutex_unlock(&bus
->mdio_lock
);
337 ar8xxx_phy_mmd_prep(struct mii_bus
*bus
, int phy_addr
, u16 addr
, u16 reg
)
339 bus
->write(bus
, phy_addr
, MII_ATH_MMD_ADDR
, addr
);
340 bus
->write(bus
, phy_addr
, MII_ATH_MMD_DATA
, reg
);
341 bus
->write(bus
, phy_addr
, MII_ATH_MMD_ADDR
, addr
| 0x4000);
345 ar8xxx_phy_mmd_write(struct ar8xxx_priv
*priv
, int phy_addr
, u16 addr
, u16 reg
, u16 data
)
347 struct mii_bus
*bus
= priv
->mii_bus
;
349 mutex_lock(&bus
->mdio_lock
);
350 ar8xxx_phy_mmd_prep(bus
, phy_addr
, addr
, reg
);
351 bus
->write(bus
, phy_addr
, MII_ATH_MMD_DATA
, data
);
352 mutex_unlock(&bus
->mdio_lock
);
356 ar8xxx_phy_mmd_read(struct ar8xxx_priv
*priv
, int phy_addr
, u16 addr
, u16 reg
)
358 struct mii_bus
*bus
= priv
->mii_bus
;
361 mutex_lock(&bus
->mdio_lock
);
362 ar8xxx_phy_mmd_prep(bus
, phy_addr
, addr
, reg
);
363 data
= bus
->read(bus
, phy_addr
, MII_ATH_MMD_DATA
);
364 mutex_unlock(&bus
->mdio_lock
);
370 ar8xxx_reg_wait(struct ar8xxx_priv
*priv
, u32 reg
, u32 mask
, u32 val
,
375 for (i
= 0; i
< timeout
; i
++) {
378 t
= ar8xxx_read(priv
, reg
);
379 if ((t
& mask
) == val
)
382 usleep_range(1000, 2000);
390 ar8xxx_mib_op(struct ar8xxx_priv
*priv
, u32 op
)
392 unsigned mib_func
= priv
->chip
->mib_func
;
395 lockdep_assert_held(&priv
->mib_lock
);
397 /* Capture the hardware statistics for all ports */
398 ar8xxx_rmw(priv
, mib_func
, AR8216_MIB_FUNC
, (op
<< AR8216_MIB_FUNC_S
));
400 /* Wait for the capturing to complete. */
401 ret
= ar8xxx_reg_wait(priv
, mib_func
, AR8216_MIB_BUSY
, 0, 10);
412 ar8xxx_mib_capture(struct ar8xxx_priv
*priv
)
414 return ar8xxx_mib_op(priv
, AR8216_MIB_FUNC_CAPTURE
);
418 ar8xxx_mib_flush(struct ar8xxx_priv
*priv
)
420 return ar8xxx_mib_op(priv
, AR8216_MIB_FUNC_FLUSH
);
424 ar8xxx_mib_fetch_port_stat(struct ar8xxx_priv
*priv
, int port
, bool flush
)
430 WARN_ON(port
>= priv
->dev
.ports
);
432 lockdep_assert_held(&priv
->mib_lock
);
434 base
= priv
->chip
->reg_port_stats_start
+
435 priv
->chip
->reg_port_stats_length
* port
;
437 mib_stats
= &priv
->mib_stats
[port
* priv
->chip
->num_mibs
];
438 for (i
= 0; i
< priv
->chip
->num_mibs
; i
++) {
439 const struct ar8xxx_mib_desc
*mib
;
442 mib
= &priv
->chip
->mib_decs
[i
];
443 if (mib
->type
> priv
->mib_type
)
445 t
= ar8xxx_read(priv
, base
+ mib
->offset
);
446 if (mib
->size
== 2) {
449 hi
= ar8xxx_read(priv
, base
+ mib
->offset
+ 4);
462 ar8216_read_port_link(struct ar8xxx_priv
*priv
, int port
,
463 struct switch_port_link
*link
)
468 memset(link
, '\0', sizeof(*link
));
470 status
= priv
->chip
->read_port_status(priv
, port
);
472 link
->aneg
= !!(status
& AR8216_PORT_STATUS_LINK_AUTO
);
474 link
->link
= !!(status
& AR8216_PORT_STATUS_LINK_UP
);
478 if (priv
->get_port_link
) {
481 err
= priv
->get_port_link(port
);
490 link
->duplex
= !!(status
& AR8216_PORT_STATUS_DUPLEX
);
491 link
->tx_flow
= !!(status
& AR8216_PORT_STATUS_TXFLOW
);
492 link
->rx_flow
= !!(status
& AR8216_PORT_STATUS_RXFLOW
);
494 if (link
->aneg
&& link
->duplex
&& priv
->chip
->read_port_eee_status
)
495 link
->eee
= priv
->chip
->read_port_eee_status(priv
, port
);
497 speed
= (status
& AR8216_PORT_STATUS_SPEED
) >>
498 AR8216_PORT_STATUS_SPEED_S
;
501 case AR8216_PORT_SPEED_10M
:
502 link
->speed
= SWITCH_PORT_SPEED_10
;
504 case AR8216_PORT_SPEED_100M
:
505 link
->speed
= SWITCH_PORT_SPEED_100
;
507 case AR8216_PORT_SPEED_1000M
:
508 link
->speed
= SWITCH_PORT_SPEED_1000
;
511 link
->speed
= SWITCH_PORT_SPEED_UNKNOWN
;
516 static struct sk_buff
*
517 ar8216_mangle_tx(struct net_device
*dev
, struct sk_buff
*skb
)
519 struct ar8xxx_priv
*priv
= dev
->phy_ptr
;
528 if (unlikely(skb_headroom(skb
) < 2)) {
529 if (pskb_expand_head(skb
, 2, 0, GFP_ATOMIC
) < 0)
533 buf
= skb_push(skb
, 2);
541 dev_kfree_skb_any(skb
);
546 ar8216_mangle_rx(struct net_device
*dev
, struct sk_buff
*skb
)
548 struct ar8xxx_priv
*priv
;
556 /* don't strip the header if vlan mode is disabled */
560 /* strip header, get vlan id */
564 /* check for vlan header presence */
565 if ((buf
[12 + 2] != 0x81) || (buf
[13 + 2] != 0x00))
570 /* no need to fix up packets coming from a tagged source */
571 if (priv
->vlan_tagged
& (1 << port
))
574 /* lookup port vid from local table, the switch passes an invalid vlan id */
575 vlan
= priv
->vlan_id
[priv
->pvid
[port
]];
578 buf
[14 + 2] |= vlan
>> 8;
579 buf
[15 + 2] = vlan
& 0xff;
583 ar8216_wait_bit(struct ar8xxx_priv
*priv
, int reg
, u32 mask
, u32 val
)
589 t
= ar8xxx_read(priv
, reg
);
590 if ((t
& mask
) == val
)
600 pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
601 (unsigned int) reg
, t
, mask
, val
);
606 ar8216_vtu_op(struct ar8xxx_priv
*priv
, u32 op
, u32 val
)
608 if (ar8216_wait_bit(priv
, AR8216_REG_VTU
, AR8216_VTU_ACTIVE
, 0))
610 if ((op
& AR8216_VTU_OP
) == AR8216_VTU_OP_LOAD
) {
611 val
&= AR8216_VTUDATA_MEMBER
;
612 val
|= AR8216_VTUDATA_VALID
;
613 ar8xxx_write(priv
, AR8216_REG_VTU_DATA
, val
);
615 op
|= AR8216_VTU_ACTIVE
;
616 ar8xxx_write(priv
, AR8216_REG_VTU
, op
);
620 ar8216_vtu_flush(struct ar8xxx_priv
*priv
)
622 ar8216_vtu_op(priv
, AR8216_VTU_OP_FLUSH
, 0);
626 ar8216_vtu_load_vlan(struct ar8xxx_priv
*priv
, u32 vid
, u32 port_mask
)
630 op
= AR8216_VTU_OP_LOAD
| (vid
<< AR8216_VTU_VID_S
);
631 ar8216_vtu_op(priv
, op
, port_mask
);
635 ar8216_atu_flush(struct ar8xxx_priv
*priv
)
639 ret
= ar8216_wait_bit(priv
, AR8216_REG_ATU_FUNC0
, AR8216_ATU_ACTIVE
, 0);
641 ar8xxx_write(priv
, AR8216_REG_ATU_FUNC0
, AR8216_ATU_OP_FLUSH
|
648 ar8216_atu_flush_port(struct ar8xxx_priv
*priv
, int port
)
653 ret
= ar8216_wait_bit(priv
, AR8216_REG_ATU_FUNC0
, AR8216_ATU_ACTIVE
, 0);
655 t
= (port
<< AR8216_ATU_PORT_NUM_S
) | AR8216_ATU_OP_FLUSH_PORT
;
656 t
|= AR8216_ATU_ACTIVE
;
657 ar8xxx_write(priv
, AR8216_REG_ATU_FUNC0
, t
);
664 ar8216_read_port_status(struct ar8xxx_priv
*priv
, int port
)
666 return ar8xxx_read(priv
, AR8216_REG_PORT_STATUS(port
));
670 __ar8216_setup_port(struct ar8xxx_priv
*priv
, int port
, u32 members
,
678 pvid
= priv
->vlan_id
[priv
->pvid
[port
]];
679 if (priv
->vlan_tagged
& (1 << port
))
680 egress
= AR8216_OUT_ADD_VLAN
;
682 egress
= AR8216_OUT_STRIP_VLAN
;
683 ingress
= AR8216_IN_SECURE
;
686 egress
= AR8216_OUT_KEEP
;
687 ingress
= AR8216_IN_PORT_ONLY
;
690 header
= ath_hdr_en
? AR8216_PORT_CTRL_HEADER
: 0;
692 ar8xxx_rmw(priv
, AR8216_REG_PORT_CTRL(port
),
693 AR8216_PORT_CTRL_LEARN
| AR8216_PORT_CTRL_VLAN_MODE
|
694 AR8216_PORT_CTRL_SINGLE_VLAN
| AR8216_PORT_CTRL_STATE
|
695 AR8216_PORT_CTRL_HEADER
| AR8216_PORT_CTRL_LEARN_LOCK
,
696 AR8216_PORT_CTRL_LEARN
| header
|
697 (egress
<< AR8216_PORT_CTRL_VLAN_MODE_S
) |
698 (AR8216_PORT_STATE_FORWARD
<< AR8216_PORT_CTRL_STATE_S
));
700 ar8xxx_rmw(priv
, AR8216_REG_PORT_VLAN(port
),
701 AR8216_PORT_VLAN_DEST_PORTS
| AR8216_PORT_VLAN_MODE
|
702 AR8216_PORT_VLAN_DEFAULT_ID
,
703 (members
<< AR8216_PORT_VLAN_DEST_PORTS_S
) |
704 (ingress
<< AR8216_PORT_VLAN_MODE_S
) |
705 (pvid
<< AR8216_PORT_VLAN_DEFAULT_ID_S
));
709 ar8216_setup_port(struct ar8xxx_priv
*priv
, int port
, u32 members
)
711 return __ar8216_setup_port(priv
, port
, members
,
712 chip_is_ar8216(priv
) && priv
->vlan
&&
713 port
== AR8216_PORT_CPU
);
717 ar8216_hw_init(struct ar8xxx_priv
*priv
)
719 if (priv
->initialized
)
722 ar8xxx_write(priv
, AR8216_REG_CTRL
, AR8216_CTRL_RESET
);
723 ar8xxx_reg_wait(priv
, AR8216_REG_CTRL
, AR8216_CTRL_RESET
, 0, 1000);
725 ar8xxx_phy_init(priv
);
727 priv
->initialized
= true;
732 ar8216_init_globals(struct ar8xxx_priv
*priv
)
734 /* standard atheros magic */
735 ar8xxx_write(priv
, 0x38, 0xc000050e);
737 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
738 AR8216_GCTRL_MTU
, 1518 + 8 + 2);
742 __ar8216_init_port(struct ar8xxx_priv
*priv
, int port
,
743 bool cpu_ge
, bool flow_en
)
745 /* Enable port learning and tx */
746 ar8xxx_write(priv
, AR8216_REG_PORT_CTRL(port
),
747 AR8216_PORT_CTRL_LEARN
|
748 (4 << AR8216_PORT_CTRL_STATE_S
));
750 ar8xxx_write(priv
, AR8216_REG_PORT_VLAN(port
), 0);
752 if (port
== AR8216_PORT_CPU
) {
753 ar8xxx_write(priv
, AR8216_REG_PORT_STATUS(port
),
754 AR8216_PORT_STATUS_LINK_UP
|
755 (cpu_ge
? AR8216_PORT_SPEED_1000M
: AR8216_PORT_SPEED_100M
) |
756 AR8216_PORT_STATUS_TXMAC
|
757 AR8216_PORT_STATUS_RXMAC
|
758 (flow_en
? AR8216_PORT_STATUS_RXFLOW
: 0) |
759 (flow_en
? AR8216_PORT_STATUS_TXFLOW
: 0) |
760 AR8216_PORT_STATUS_DUPLEX
);
762 ar8xxx_write(priv
, AR8216_REG_PORT_STATUS(port
),
763 AR8216_PORT_STATUS_LINK_AUTO
);
768 ar8216_init_port(struct ar8xxx_priv
*priv
, int port
)
770 __ar8216_init_port(priv
, port
, ar8xxx_has_gige(priv
),
771 chip_is_ar8316(priv
));
775 ar8216_wait_atu_ready(struct ar8xxx_priv
*priv
, u16 r2
, u16 r1
)
779 while (ar8xxx_mii_read32(priv
, r2
, r1
) & AR8216_ATU_ACTIVE
&& --timeout
) {
785 pr_err("ar8216: timeout waiting for atu to become ready\n");
788 static void ar8216_get_arl_entry(struct ar8xxx_priv
*priv
,
789 struct arl_entry
*a
, u32
*status
, enum arl_op op
)
791 struct mii_bus
*bus
= priv
->mii_bus
;
793 u16 r1_func0
, r1_func1
, r1_func2
;
794 u32 t
, val0
, val1
, val2
;
796 split_addr(AR8216_REG_ATU_FUNC0
, &r1_func0
, &r2
, &page
);
799 r1_func1
= (AR8216_REG_ATU_FUNC1
>> 1) & 0x1e;
800 r1_func2
= (AR8216_REG_ATU_FUNC2
>> 1) & 0x1e;
803 case AR8XXX_ARL_INITIALIZE
:
804 /* all ATU registers are on the same page
805 * therefore set page only once
807 bus
->write(bus
, 0x18, 0, page
);
808 wait_for_page_switch();
810 ar8216_wait_atu_ready(priv
, r2
, r1_func0
);
812 ar8xxx_mii_write32(priv
, r2
, r1_func0
, AR8216_ATU_OP_GET_NEXT
);
813 ar8xxx_mii_write32(priv
, r2
, r1_func1
, 0);
814 ar8xxx_mii_write32(priv
, r2
, r1_func2
, 0);
816 case AR8XXX_ARL_GET_NEXT
:
817 t
= ar8xxx_mii_read32(priv
, r2
, r1_func0
);
818 t
|= AR8216_ATU_ACTIVE
;
819 ar8xxx_mii_write32(priv
, r2
, r1_func0
, t
);
820 ar8216_wait_atu_ready(priv
, r2
, r1_func0
);
822 val0
= ar8xxx_mii_read32(priv
, r2
, r1_func0
);
823 val1
= ar8xxx_mii_read32(priv
, r2
, r1_func1
);
824 val2
= ar8xxx_mii_read32(priv
, r2
, r1_func2
);
826 *status
= (val2
& AR8216_ATU_STATUS
) >> AR8216_ATU_STATUS_S
;
830 a
->portmap
= (val2
& AR8216_ATU_PORTS
) >> AR8216_ATU_PORTS_S
;
831 a
->mac
[0] = (val0
& AR8216_ATU_ADDR5
) >> AR8216_ATU_ADDR5_S
;
832 a
->mac
[1] = (val0
& AR8216_ATU_ADDR4
) >> AR8216_ATU_ADDR4_S
;
833 a
->mac
[2] = (val1
& AR8216_ATU_ADDR3
) >> AR8216_ATU_ADDR3_S
;
834 a
->mac
[3] = (val1
& AR8216_ATU_ADDR2
) >> AR8216_ATU_ADDR2_S
;
835 a
->mac
[4] = (val1
& AR8216_ATU_ADDR1
) >> AR8216_ATU_ADDR1_S
;
836 a
->mac
[5] = (val1
& AR8216_ATU_ADDR0
) >> AR8216_ATU_ADDR0_S
;
842 ar8216_phy_read(struct ar8xxx_priv
*priv
, int addr
, int regnum
)
847 if (addr
>= AR8216_NUM_PORTS
)
849 t
= (regnum
<< AR8216_MDIO_CTRL_REG_ADDR_S
) |
850 (addr
<< AR8216_MDIO_CTRL_PHY_ADDR_S
) |
851 AR8216_MDIO_CTRL_MASTER_EN
|
852 AR8216_MDIO_CTRL_BUSY
|
853 AR8216_MDIO_CTRL_CMD_READ
;
855 ar8xxx_write(priv
, AR8216_REG_MDIO_CTRL
, t
);
856 err
= ar8xxx_reg_wait(priv
, AR8216_REG_MDIO_CTRL
,
857 AR8216_MDIO_CTRL_BUSY
, 0, 5);
859 val
= ar8xxx_read(priv
, AR8216_REG_MDIO_CTRL
);
861 return val
& AR8216_MDIO_CTRL_DATA_M
;
865 ar8216_phy_write(struct ar8xxx_priv
*priv
, int addr
, int regnum
, u16 val
)
870 if (addr
>= AR8216_NUM_PORTS
)
873 t
= (addr
<< AR8216_MDIO_CTRL_PHY_ADDR_S
) |
874 (regnum
<< AR8216_MDIO_CTRL_REG_ADDR_S
) |
875 AR8216_MDIO_CTRL_MASTER_EN
|
876 AR8216_MDIO_CTRL_BUSY
|
877 AR8216_MDIO_CTRL_CMD_WRITE
|
880 ar8xxx_write(priv
, AR8216_REG_MDIO_CTRL
, t
);
881 ret
= ar8xxx_reg_wait(priv
, AR8216_REG_MDIO_CTRL
,
882 AR8216_MDIO_CTRL_BUSY
, 0, 5);
888 ar8229_hw_init(struct ar8xxx_priv
*priv
)
892 if (priv
->initialized
)
895 ar8xxx_write(priv
, AR8216_REG_CTRL
, AR8216_CTRL_RESET
);
896 ar8xxx_reg_wait(priv
, AR8216_REG_CTRL
, AR8216_CTRL_RESET
, 0, 1000);
898 phy_if_mode
= of_get_phy_mode(priv
->pdev
->of_node
);
900 if (phy_if_mode
== PHY_INTERFACE_MODE_GMII
) {
901 ar8xxx_write(priv
, AR8229_REG_OPER_MODE0
,
902 AR8229_OPER_MODE0_MAC_GMII_EN
);
903 } else if (phy_if_mode
== PHY_INTERFACE_MODE_MII
) {
904 ar8xxx_write(priv
, AR8229_REG_OPER_MODE0
,
905 AR8229_OPER_MODE0_PHY_MII_EN
);
907 pr_err("ar8229: unsupported mii mode\n");
911 if (priv
->port4_phy
) {
912 ar8xxx_write(priv
, AR8229_REG_OPER_MODE1
,
913 AR8229_REG_OPER_MODE1_PHY4_MII_EN
);
914 /* disable port5 to prevent mii conflict */
915 ar8xxx_write(priv
, AR8216_REG_PORT_STATUS(5), 0);
918 ar8xxx_phy_init(priv
);
920 priv
->initialized
= true;
925 ar8229_init_globals(struct ar8xxx_priv
*priv
)
928 /* Enable CPU port, and disable mirror port */
929 ar8xxx_write(priv
, AR8216_REG_GLOBAL_CPUPORT
,
930 AR8216_GLOBAL_CPUPORT_EN
|
931 (15 << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S
));
933 /* Setup TAG priority mapping */
934 ar8xxx_write(priv
, AR8216_REG_TAG_PRIORITY
, 0xfa50);
936 /* Enable aging, MAC replacing */
937 ar8xxx_write(priv
, AR8216_REG_ATU_CTRL
,
938 0x2b /* 5 min age time */ |
939 AR8216_ATU_CTRL_AGE_EN
|
940 AR8216_ATU_CTRL_LEARN_CHANGE
);
942 /* Enable ARP frame acknowledge */
943 ar8xxx_reg_set(priv
, AR8229_REG_QM_CTRL
,
944 AR8229_QM_CTRL_ARP_EN
);
947 * Enable Broadcast/unknown multicast and unicast frames
948 * transmitted to the CPU port.
950 ar8xxx_reg_set(priv
, AR8216_REG_FLOOD_MASK
,
951 AR8229_FLOOD_MASK_BC_DP(0) |
952 AR8229_FLOOD_MASK_MC_DP(0) |
953 AR8229_FLOOD_MASK_UC_DP(0));
956 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
957 AR8236_GCTRL_MTU
, AR8236_GCTRL_MTU
);
959 /* Enable MIB counters */
960 ar8xxx_reg_set(priv
, AR8216_REG_MIB_FUNC
,
963 /* setup Service TAG */
964 ar8xxx_rmw(priv
, AR8216_REG_SERVICE_TAG
, AR8216_SERVICE_TAG_M
, 0);
968 ar8229_init_port(struct ar8xxx_priv
*priv
, int port
)
970 __ar8216_init_port(priv
, port
, true, true);
975 ar7240sw_hw_init(struct ar8xxx_priv
*priv
)
977 if (priv
->initialized
)
980 ar8xxx_write(priv
, AR8216_REG_CTRL
, AR8216_CTRL_RESET
);
981 ar8xxx_reg_wait(priv
, AR8216_REG_CTRL
, AR8216_CTRL_RESET
, 0, 1000);
984 /* disable port5 to prevent mii conflict */
985 ar8xxx_write(priv
, AR8216_REG_PORT_STATUS(5), 0);
987 ar8xxx_phy_init(priv
);
989 priv
->initialized
= true;
994 ar7240sw_init_globals(struct ar8xxx_priv
*priv
)
997 /* Enable CPU port, and disable mirror port */
998 ar8xxx_write(priv
, AR8216_REG_GLOBAL_CPUPORT
,
999 AR8216_GLOBAL_CPUPORT_EN
|
1000 (15 << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S
));
1002 /* Setup TAG priority mapping */
1003 ar8xxx_write(priv
, AR8216_REG_TAG_PRIORITY
, 0xfa50);
1005 /* Enable ARP frame acknowledge, aging, MAC replacing */
1006 ar8xxx_write(priv
, AR8216_REG_ATU_CTRL
,
1007 AR8216_ATU_CTRL_RESERVED
|
1008 0x2b /* 5 min age time */ |
1009 AR8216_ATU_CTRL_AGE_EN
|
1010 AR8216_ATU_CTRL_ARP_EN
|
1011 AR8216_ATU_CTRL_LEARN_CHANGE
);
1013 /* Enable Broadcast frames transmitted to the CPU */
1014 ar8xxx_reg_set(priv
, AR8216_REG_FLOOD_MASK
,
1015 AR8216_FM_CPU_BROADCAST_EN
);
1018 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
1022 /* setup Service TAG */
1023 ar8xxx_rmw(priv
, AR8216_REG_SERVICE_TAG
, AR8216_SERVICE_TAG_M
, 0);
1027 ar7240sw_setup_port(struct ar8xxx_priv
*priv
, int port
, u32 members
)
1029 return __ar8216_setup_port(priv
, port
, members
, false);
1033 ar8236_setup_port(struct ar8xxx_priv
*priv
, int port
, u32 members
)
1035 u32 egress
, ingress
;
1039 pvid
= priv
->vlan_id
[priv
->pvid
[port
]];
1040 if (priv
->vlan_tagged
& (1 << port
))
1041 egress
= AR8216_OUT_ADD_VLAN
;
1043 egress
= AR8216_OUT_STRIP_VLAN
;
1044 ingress
= AR8216_IN_SECURE
;
1047 egress
= AR8216_OUT_KEEP
;
1048 ingress
= AR8216_IN_PORT_ONLY
;
1051 ar8xxx_rmw(priv
, AR8216_REG_PORT_CTRL(port
),
1052 AR8216_PORT_CTRL_LEARN
| AR8216_PORT_CTRL_VLAN_MODE
|
1053 AR8216_PORT_CTRL_SINGLE_VLAN
| AR8216_PORT_CTRL_STATE
|
1054 AR8216_PORT_CTRL_HEADER
| AR8216_PORT_CTRL_LEARN_LOCK
,
1055 AR8216_PORT_CTRL_LEARN
|
1056 (egress
<< AR8216_PORT_CTRL_VLAN_MODE_S
) |
1057 (AR8216_PORT_STATE_FORWARD
<< AR8216_PORT_CTRL_STATE_S
));
1059 ar8xxx_rmw(priv
, AR8236_REG_PORT_VLAN(port
),
1060 AR8236_PORT_VLAN_DEFAULT_ID
,
1061 (pvid
<< AR8236_PORT_VLAN_DEFAULT_ID_S
));
1063 ar8xxx_rmw(priv
, AR8236_REG_PORT_VLAN2(port
),
1064 AR8236_PORT_VLAN2_VLAN_MODE
|
1065 AR8236_PORT_VLAN2_MEMBER
,
1066 (ingress
<< AR8236_PORT_VLAN2_VLAN_MODE_S
) |
1067 (members
<< AR8236_PORT_VLAN2_MEMBER_S
));
1071 ar8236_init_globals(struct ar8xxx_priv
*priv
)
1073 /* enable jumbo frames */
1074 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
1075 AR8316_GCTRL_MTU
, 9018 + 8 + 2);
1077 /* enable cpu port to receive arp frames */
1078 ar8xxx_reg_set(priv
, AR8216_REG_ATU_CTRL
,
1079 AR8236_ATU_CTRL_RES
);
1082 * Enable Broadcast/unknown multicast and unicast frames
1083 * transmitted to the CPU port.
1085 ar8xxx_reg_set(priv
, AR8216_REG_FLOOD_MASK
,
1086 AR8229_FLOOD_MASK_BC_DP(0) |
1087 AR8229_FLOOD_MASK_MC_DP(0) |
1088 AR8229_FLOOD_MASK_UC_DP(0));
1090 /* Enable MIB counters */
1091 ar8xxx_rmw(priv
, AR8216_REG_MIB_FUNC
, AR8216_MIB_FUNC
| AR8236_MIB_EN
,
1092 (AR8216_MIB_FUNC_NO_OP
<< AR8216_MIB_FUNC_S
) |
1097 ar8316_hw_init(struct ar8xxx_priv
*priv
)
1101 val
= ar8xxx_read(priv
, AR8316_REG_POSTRIP
);
1103 if (priv
->phy
->interface
== PHY_INTERFACE_MODE_RGMII
) {
1104 if (priv
->port4_phy
) {
1105 /* value taken from Ubiquiti RouterStation Pro */
1106 newval
= 0x81461bea;
1107 pr_info("ar8316: Using port 4 as PHY\n");
1109 newval
= 0x01261be2;
1110 pr_info("ar8316: Using port 4 as switch port\n");
1112 } else if (priv
->phy
->interface
== PHY_INTERFACE_MODE_GMII
) {
1113 /* value taken from AVM Fritz!Box 7390 sources */
1114 newval
= 0x010e5b71;
1116 /* no known value for phy interface */
1117 pr_err("ar8316: unsupported mii mode: %d.\n",
1118 priv
->phy
->interface
);
1125 ar8xxx_write(priv
, AR8316_REG_POSTRIP
, newval
);
1127 if (priv
->port4_phy
&&
1128 priv
->phy
->interface
== PHY_INTERFACE_MODE_RGMII
) {
1129 /* work around for phy4 rgmii mode */
1130 ar8xxx_phy_dbg_write(priv
, 4, 0x12, 0x480c);
1132 ar8xxx_phy_dbg_write(priv
, 4, 0x0, 0x824e);
1134 ar8xxx_phy_dbg_write(priv
, 4, 0x5, 0x3d47);
1138 ar8xxx_phy_init(priv
);
1141 priv
->initialized
= true;
1146 ar8316_init_globals(struct ar8xxx_priv
*priv
)
1148 /* standard atheros magic */
1149 ar8xxx_write(priv
, 0x38, 0xc000050e);
1151 /* enable cpu port to receive multicast and broadcast frames */
1152 ar8xxx_write(priv
, AR8216_REG_FLOOD_MASK
, 0x003f003f);
1154 /* enable jumbo frames */
1155 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
1156 AR8316_GCTRL_MTU
, 9018 + 8 + 2);
1158 /* Enable MIB counters */
1159 ar8xxx_rmw(priv
, AR8216_REG_MIB_FUNC
, AR8216_MIB_FUNC
| AR8236_MIB_EN
,
1160 (AR8216_MIB_FUNC_NO_OP
<< AR8216_MIB_FUNC_S
) |
1165 ar8xxx_sw_set_vlan(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1166 struct switch_val
*val
)
1168 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1169 priv
->vlan
= !!val
->value
.i
;
1174 ar8xxx_sw_get_vlan(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1175 struct switch_val
*val
)
1177 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1178 val
->value
.i
= priv
->vlan
;
1184 ar8xxx_sw_set_pvid(struct switch_dev
*dev
, int port
, int vlan
)
1186 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1188 /* make sure no invalid PVIDs get set */
1190 if (vlan
< 0 || vlan
>= dev
->vlans
||
1191 port
< 0 || port
>= AR8X16_MAX_PORTS
)
1194 priv
->pvid
[port
] = vlan
;
1199 ar8xxx_sw_get_pvid(struct switch_dev
*dev
, int port
, int *vlan
)
1201 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1203 if (port
< 0 || port
>= AR8X16_MAX_PORTS
)
1206 *vlan
= priv
->pvid
[port
];
1211 ar8xxx_sw_set_vid(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1212 struct switch_val
*val
)
1214 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1216 if (val
->port_vlan
>= dev
->vlans
)
1219 priv
->vlan_id
[val
->port_vlan
] = val
->value
.i
;
1224 ar8xxx_sw_get_vid(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1225 struct switch_val
*val
)
1227 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1228 val
->value
.i
= priv
->vlan_id
[val
->port_vlan
];
1233 ar8xxx_sw_get_port_link(struct switch_dev
*dev
, int port
,
1234 struct switch_port_link
*link
)
1236 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1238 ar8216_read_port_link(priv
, port
, link
);
1243 ar8xxx_sw_get_ports(struct switch_dev
*dev
, struct switch_val
*val
)
1245 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1249 if (val
->port_vlan
>= dev
->vlans
)
1252 ports
= priv
->vlan_table
[val
->port_vlan
];
1254 for (i
= 0; i
< dev
->ports
; i
++) {
1255 struct switch_port
*p
;
1257 if (!(ports
& (1 << i
)))
1260 p
= &val
->value
.ports
[val
->len
++];
1262 if (priv
->vlan_tagged
& (1 << i
))
1263 p
->flags
= (1 << SWITCH_PORT_FLAG_TAGGED
);
1271 ar8xxx_sw_set_ports(struct switch_dev
*dev
, struct switch_val
*val
)
1273 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1274 u8
*vt
= &priv
->vlan_table
[val
->port_vlan
];
1278 for (i
= 0; i
< val
->len
; i
++) {
1279 struct switch_port
*p
= &val
->value
.ports
[i
];
1281 if (p
->flags
& (1 << SWITCH_PORT_FLAG_TAGGED
)) {
1282 priv
->vlan_tagged
|= (1 << p
->id
);
1284 priv
->vlan_tagged
&= ~(1 << p
->id
);
1285 priv
->pvid
[p
->id
] = val
->port_vlan
;
1287 /* make sure that an untagged port does not
1288 * appear in other vlans */
1289 for (j
= 0; j
< dev
->vlans
; j
++) {
1290 if (j
== val
->port_vlan
)
1292 priv
->vlan_table
[j
] &= ~(1 << p
->id
);
1302 ar8216_set_mirror_regs(struct ar8xxx_priv
*priv
)
1306 /* reset all mirror registers */
1307 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CPUPORT
,
1308 AR8216_GLOBAL_CPUPORT_MIRROR_PORT
,
1309 (0xF << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S
));
1310 for (port
= 0; port
< AR8216_NUM_PORTS
; port
++) {
1311 ar8xxx_reg_clear(priv
, AR8216_REG_PORT_CTRL(port
),
1312 AR8216_PORT_CTRL_MIRROR_RX
);
1314 ar8xxx_reg_clear(priv
, AR8216_REG_PORT_CTRL(port
),
1315 AR8216_PORT_CTRL_MIRROR_TX
);
1318 /* now enable mirroring if necessary */
1319 if (priv
->source_port
>= AR8216_NUM_PORTS
||
1320 priv
->monitor_port
>= AR8216_NUM_PORTS
||
1321 priv
->source_port
== priv
->monitor_port
) {
1325 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CPUPORT
,
1326 AR8216_GLOBAL_CPUPORT_MIRROR_PORT
,
1327 (priv
->monitor_port
<< AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S
));
1329 if (priv
->mirror_rx
)
1330 ar8xxx_reg_set(priv
, AR8216_REG_PORT_CTRL(priv
->source_port
),
1331 AR8216_PORT_CTRL_MIRROR_RX
);
1333 if (priv
->mirror_tx
)
1334 ar8xxx_reg_set(priv
, AR8216_REG_PORT_CTRL(priv
->source_port
),
1335 AR8216_PORT_CTRL_MIRROR_TX
);
1339 ar8xxx_age_time_val(int age_time
)
1341 return (age_time
+ AR8XXX_REG_ARL_CTRL_AGE_TIME_SECS
/ 2) /
1342 AR8XXX_REG_ARL_CTRL_AGE_TIME_SECS
;
1346 ar8xxx_set_age_time(struct ar8xxx_priv
*priv
, int reg
)
1348 u32 age_time
= ar8xxx_age_time_val(priv
->arl_age_time
);
1349 ar8xxx_rmw(priv
, reg
, AR8216_ATU_CTRL_AGE_TIME
, age_time
<< AR8216_ATU_CTRL_AGE_TIME_S
);
1353 ar8xxx_sw_hw_apply(struct switch_dev
*dev
)
1355 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1356 const struct ar8xxx_chip
*chip
= priv
->chip
;
1357 u8 portmask
[AR8X16_MAX_PORTS
];
1360 mutex_lock(&priv
->reg_mutex
);
1361 /* flush all vlan translation unit entries */
1362 priv
->chip
->vtu_flush(priv
);
1364 memset(portmask
, 0, sizeof(portmask
));
1366 /* calculate the port destination masks and load vlans
1367 * into the vlan translation unit */
1368 for (j
= 0; j
< dev
->vlans
; j
++) {
1369 u8 vp
= priv
->vlan_table
[j
];
1374 for (i
= 0; i
< dev
->ports
; i
++) {
1377 portmask
[i
] |= vp
& ~mask
;
1380 chip
->vtu_load_vlan(priv
, priv
->vlan_id
[j
],
1381 priv
->vlan_table
[j
]);
1385 * isolate all ports, but connect them to the cpu port */
1386 for (i
= 0; i
< dev
->ports
; i
++) {
1387 if (i
== AR8216_PORT_CPU
)
1390 portmask
[i
] = 1 << AR8216_PORT_CPU
;
1391 portmask
[AR8216_PORT_CPU
] |= (1 << i
);
1395 /* update the port destination mask registers and tag settings */
1396 for (i
= 0; i
< dev
->ports
; i
++) {
1397 chip
->setup_port(priv
, i
, portmask
[i
]);
1400 chip
->set_mirror_regs(priv
);
1403 if (chip
->reg_arl_ctrl
)
1404 ar8xxx_set_age_time(priv
, chip
->reg_arl_ctrl
);
1406 mutex_unlock(&priv
->reg_mutex
);
1411 ar8xxx_sw_reset_switch(struct switch_dev
*dev
)
1413 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1414 const struct ar8xxx_chip
*chip
= priv
->chip
;
1417 mutex_lock(&priv
->reg_mutex
);
1418 memset(&priv
->vlan
, 0, sizeof(struct ar8xxx_priv
) -
1419 offsetof(struct ar8xxx_priv
, vlan
));
1421 for (i
= 0; i
< dev
->vlans
; i
++)
1422 priv
->vlan_id
[i
] = i
;
1424 /* Configure all ports */
1425 for (i
= 0; i
< dev
->ports
; i
++)
1426 chip
->init_port(priv
, i
);
1428 priv
->mirror_rx
= false;
1429 priv
->mirror_tx
= false;
1430 priv
->source_port
= 0;
1431 priv
->monitor_port
= 0;
1432 priv
->arl_age_time
= AR8XXX_DEFAULT_ARL_AGE_TIME
;
1434 chip
->init_globals(priv
);
1435 chip
->atu_flush(priv
);
1437 mutex_unlock(&priv
->reg_mutex
);
1439 return chip
->sw_hw_apply(dev
);
1443 ar8xxx_sw_set_reset_mibs(struct switch_dev
*dev
,
1444 const struct switch_attr
*attr
,
1445 struct switch_val
*val
)
1447 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1451 if (!ar8xxx_has_mib_counters(priv
))
1454 mutex_lock(&priv
->mib_lock
);
1456 len
= priv
->dev
.ports
* priv
->chip
->num_mibs
*
1457 sizeof(*priv
->mib_stats
);
1458 memset(priv
->mib_stats
, '\0', len
);
1459 ret
= ar8xxx_mib_flush(priv
);
1466 mutex_unlock(&priv
->mib_lock
);
1471 ar8xxx_sw_set_mib_poll_interval(struct switch_dev
*dev
,
1472 const struct switch_attr
*attr
,
1473 struct switch_val
*val
)
1475 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1477 if (!ar8xxx_has_mib_counters(priv
))
1480 ar8xxx_mib_stop(priv
);
1481 priv
->mib_poll_interval
= val
->value
.i
;
1482 ar8xxx_mib_start(priv
);
1488 ar8xxx_sw_get_mib_poll_interval(struct switch_dev
*dev
,
1489 const struct switch_attr
*attr
,
1490 struct switch_val
*val
)
1492 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1494 if (!ar8xxx_has_mib_counters(priv
))
1496 val
->value
.i
= priv
->mib_poll_interval
;
1501 ar8xxx_sw_set_mib_type(struct switch_dev
*dev
,
1502 const struct switch_attr
*attr
,
1503 struct switch_val
*val
)
1505 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1507 if (!ar8xxx_has_mib_counters(priv
))
1509 priv
->mib_type
= val
->value
.i
;
1514 ar8xxx_sw_get_mib_type(struct switch_dev
*dev
,
1515 const struct switch_attr
*attr
,
1516 struct switch_val
*val
)
1518 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1520 if (!ar8xxx_has_mib_counters(priv
))
1522 val
->value
.i
= priv
->mib_type
;
1527 ar8xxx_sw_set_mirror_rx_enable(struct switch_dev
*dev
,
1528 const struct switch_attr
*attr
,
1529 struct switch_val
*val
)
1531 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1533 mutex_lock(&priv
->reg_mutex
);
1534 priv
->mirror_rx
= !!val
->value
.i
;
1535 priv
->chip
->set_mirror_regs(priv
);
1536 mutex_unlock(&priv
->reg_mutex
);
1542 ar8xxx_sw_get_mirror_rx_enable(struct switch_dev
*dev
,
1543 const struct switch_attr
*attr
,
1544 struct switch_val
*val
)
1546 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1547 val
->value
.i
= priv
->mirror_rx
;
1552 ar8xxx_sw_set_mirror_tx_enable(struct switch_dev
*dev
,
1553 const struct switch_attr
*attr
,
1554 struct switch_val
*val
)
1556 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1558 mutex_lock(&priv
->reg_mutex
);
1559 priv
->mirror_tx
= !!val
->value
.i
;
1560 priv
->chip
->set_mirror_regs(priv
);
1561 mutex_unlock(&priv
->reg_mutex
);
1567 ar8xxx_sw_get_mirror_tx_enable(struct switch_dev
*dev
,
1568 const struct switch_attr
*attr
,
1569 struct switch_val
*val
)
1571 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1572 val
->value
.i
= priv
->mirror_tx
;
1577 ar8xxx_sw_set_mirror_monitor_port(struct switch_dev
*dev
,
1578 const struct switch_attr
*attr
,
1579 struct switch_val
*val
)
1581 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1583 mutex_lock(&priv
->reg_mutex
);
1584 priv
->monitor_port
= val
->value
.i
;
1585 priv
->chip
->set_mirror_regs(priv
);
1586 mutex_unlock(&priv
->reg_mutex
);
1592 ar8xxx_sw_get_mirror_monitor_port(struct switch_dev
*dev
,
1593 const struct switch_attr
*attr
,
1594 struct switch_val
*val
)
1596 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1597 val
->value
.i
= priv
->monitor_port
;
1602 ar8xxx_sw_set_mirror_source_port(struct switch_dev
*dev
,
1603 const struct switch_attr
*attr
,
1604 struct switch_val
*val
)
1606 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1608 mutex_lock(&priv
->reg_mutex
);
1609 priv
->source_port
= val
->value
.i
;
1610 priv
->chip
->set_mirror_regs(priv
);
1611 mutex_unlock(&priv
->reg_mutex
);
1617 ar8xxx_sw_get_mirror_source_port(struct switch_dev
*dev
,
1618 const struct switch_attr
*attr
,
1619 struct switch_val
*val
)
1621 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1622 val
->value
.i
= priv
->source_port
;
1627 ar8xxx_sw_set_port_reset_mib(struct switch_dev
*dev
,
1628 const struct switch_attr
*attr
,
1629 struct switch_val
*val
)
1631 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1635 if (!ar8xxx_has_mib_counters(priv
))
1638 port
= val
->port_vlan
;
1639 if (port
>= dev
->ports
)
1642 mutex_lock(&priv
->mib_lock
);
1643 ret
= ar8xxx_mib_capture(priv
);
1647 ar8xxx_mib_fetch_port_stat(priv
, port
, true);
1652 mutex_unlock(&priv
->mib_lock
);
1657 ar8xxx_byte_to_str(char *buf
, int len
, u64 byte
)
1662 if (byte
>= 0x40000000) { /* 1 GiB */
1663 b
= byte
* 10 / 0x40000000;
1665 } else if (byte
>= 0x100000) { /* 1 MiB */
1666 b
= byte
* 10 / 0x100000;
1668 } else if (byte
>= 0x400) { /* 1 KiB */
1669 b
= byte
* 10 / 0x400;
1675 if (strcmp(unit
, "Byte"))
1676 snprintf(buf
, len
, "%lu.%lu %s", b
/ 10, b
% 10, unit
);
1678 snprintf(buf
, len
, "%lu %s", b
, unit
);
1682 ar8xxx_sw_get_port_mib(struct switch_dev
*dev
,
1683 const struct switch_attr
*attr
,
1684 struct switch_val
*val
)
1686 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1687 const struct ar8xxx_chip
*chip
= priv
->chip
;
1688 u64
*mib_stats
, mib_data
;
1691 char *buf
= priv
->buf
;
1693 const char *mib_name
;
1695 bool mib_stats_empty
= true;
1697 if (!ar8xxx_has_mib_counters(priv
) || !priv
->mib_poll_interval
)
1700 port
= val
->port_vlan
;
1701 if (port
>= dev
->ports
)
1704 mutex_lock(&priv
->mib_lock
);
1705 ret
= ar8xxx_mib_capture(priv
);
1709 ar8xxx_mib_fetch_port_stat(priv
, port
, false);
1711 len
+= snprintf(buf
+ len
, sizeof(priv
->buf
) - len
,
1714 mib_stats
= &priv
->mib_stats
[port
* chip
->num_mibs
];
1715 for (i
= 0; i
< chip
->num_mibs
; i
++) {
1716 if (chip
->mib_decs
[i
].type
> priv
->mib_type
)
1718 mib_name
= chip
->mib_decs
[i
].name
;
1719 mib_data
= mib_stats
[i
];
1720 len
+= snprintf(buf
+ len
, sizeof(priv
->buf
) - len
,
1721 "%-12s: %llu\n", mib_name
, mib_data
);
1722 if ((!strcmp(mib_name
, "TxByte") ||
1723 !strcmp(mib_name
, "RxGoodByte")) &&
1725 ar8xxx_byte_to_str(buf1
, sizeof(buf1
), mib_data
);
1726 --len
; /* discard newline at the end of buf */
1727 len
+= snprintf(buf
+ len
, sizeof(priv
->buf
) - len
,
1730 if (mib_stats_empty
&& mib_data
)
1731 mib_stats_empty
= false;
1734 if (mib_stats_empty
)
1735 len
= snprintf(buf
, sizeof(priv
->buf
), "No MIB data");
1743 mutex_unlock(&priv
->mib_lock
);
1748 ar8xxx_sw_set_arl_age_time(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1749 struct switch_val
*val
)
1751 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1752 int age_time
= val
->value
.i
;
1758 age_time_val
= ar8xxx_age_time_val(age_time
);
1759 if (age_time_val
== 0 || age_time_val
> 0xffff)
1762 priv
->arl_age_time
= age_time
;
1767 ar8xxx_sw_get_arl_age_time(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1768 struct switch_val
*val
)
1770 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1771 val
->value
.i
= priv
->arl_age_time
;
1776 ar8xxx_sw_get_arl_table(struct switch_dev
*dev
,
1777 const struct switch_attr
*attr
,
1778 struct switch_val
*val
)
1780 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1781 struct mii_bus
*bus
= priv
->mii_bus
;
1782 const struct ar8xxx_chip
*chip
= priv
->chip
;
1783 char *buf
= priv
->arl_buf
;
1784 int i
, j
, k
, len
= 0;
1785 struct arl_entry
*a
, *a1
;
1788 if (!chip
->get_arl_entry
)
1791 mutex_lock(&priv
->reg_mutex
);
1792 mutex_lock(&bus
->mdio_lock
);
1794 chip
->get_arl_entry(priv
, NULL
, NULL
, AR8XXX_ARL_INITIALIZE
);
1796 for(i
= 0; i
< AR8XXX_NUM_ARL_RECORDS
; ++i
) {
1797 a
= &priv
->arl_table
[i
];
1799 chip
->get_arl_entry(priv
, a
, &status
, AR8XXX_ARL_GET_NEXT
);
1805 * ARL table can include multiple valid entries
1806 * per MAC, just with differing status codes
1808 for (j
= 0; j
< i
; ++j
) {
1809 a1
= &priv
->arl_table
[j
];
1810 if (!memcmp(a
->mac
, a1
->mac
, sizeof(a
->mac
))) {
1811 /* ignore ports already seen in former entry */
1812 a
->portmap
&= ~a1
->portmap
;
1819 mutex_unlock(&bus
->mdio_lock
);
1821 len
+= snprintf(buf
+ len
, sizeof(priv
->arl_buf
) - len
,
1822 "address resolution table\n");
1824 if (i
== AR8XXX_NUM_ARL_RECORDS
)
1825 len
+= snprintf(buf
+ len
, sizeof(priv
->arl_buf
) - len
,
1826 "Too many entries found, displaying the first %d only!\n",
1827 AR8XXX_NUM_ARL_RECORDS
);
1829 for (j
= 0; j
< priv
->dev
.ports
; ++j
) {
1830 for (k
= 0; k
< i
; ++k
) {
1831 a
= &priv
->arl_table
[k
];
1832 if (!(a
->portmap
& BIT(j
)))
1834 len
+= snprintf(buf
+ len
, sizeof(priv
->arl_buf
) - len
,
1835 "Port %d: MAC %02x:%02x:%02x:%02x:%02x:%02x\n",
1837 a
->mac
[5], a
->mac
[4], a
->mac
[3],
1838 a
->mac
[2], a
->mac
[1], a
->mac
[0]);
1845 mutex_unlock(&priv
->reg_mutex
);
1851 ar8xxx_sw_set_flush_arl_table(struct switch_dev
*dev
,
1852 const struct switch_attr
*attr
,
1853 struct switch_val
*val
)
1855 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1858 mutex_lock(&priv
->reg_mutex
);
1859 ret
= priv
->chip
->atu_flush(priv
);
1860 mutex_unlock(&priv
->reg_mutex
);
1866 ar8xxx_sw_set_flush_port_arl_table(struct switch_dev
*dev
,
1867 const struct switch_attr
*attr
,
1868 struct switch_val
*val
)
1870 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1873 port
= val
->port_vlan
;
1874 if (port
>= dev
->ports
)
1877 mutex_lock(&priv
->reg_mutex
);
1878 ret
= priv
->chip
->atu_flush_port(priv
, port
);
1879 mutex_unlock(&priv
->reg_mutex
);
1885 ar8xxx_sw_get_port_stats(struct switch_dev
*dev
, int port
,
1886 struct switch_port_stats
*stats
)
1888 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1891 if (!ar8xxx_has_mib_counters(priv
) || !priv
->mib_poll_interval
)
1894 if (!(priv
->chip
->mib_rxb_id
|| priv
->chip
->mib_txb_id
))
1897 if (port
>= dev
->ports
)
1900 mutex_lock(&priv
->mib_lock
);
1902 mib_stats
= &priv
->mib_stats
[port
* priv
->chip
->num_mibs
];
1904 stats
->tx_bytes
= mib_stats
[priv
->chip
->mib_txb_id
];
1905 stats
->rx_bytes
= mib_stats
[priv
->chip
->mib_rxb_id
];
1907 mutex_unlock(&priv
->mib_lock
);
1912 ar8xxx_phy_read(struct mii_bus
*bus
, int phy_addr
, int reg_addr
)
1914 struct ar8xxx_priv
*priv
= bus
->priv
;
1915 return priv
->chip
->phy_read(priv
, phy_addr
, reg_addr
);
1919 ar8xxx_phy_write(struct mii_bus
*bus
, int phy_addr
, int reg_addr
,
1922 struct ar8xxx_priv
*priv
= bus
->priv
;
1923 return priv
->chip
->phy_write(priv
, phy_addr
, reg_addr
, reg_val
);
1926 static const struct switch_attr ar8xxx_sw_attr_globals
[] = {
1928 .type
= SWITCH_TYPE_INT
,
1929 .name
= "enable_vlan",
1930 .description
= "Enable VLAN mode",
1931 .set
= ar8xxx_sw_set_vlan
,
1932 .get
= ar8xxx_sw_get_vlan
,
1936 .type
= SWITCH_TYPE_NOVAL
,
1937 .name
= "reset_mibs",
1938 .description
= "Reset all MIB counters",
1939 .set
= ar8xxx_sw_set_reset_mibs
,
1942 .type
= SWITCH_TYPE_INT
,
1943 .name
= "ar8xxx_mib_poll_interval",
1944 .description
= "MIB polling interval in msecs (0 to disable)",
1945 .set
= ar8xxx_sw_set_mib_poll_interval
,
1946 .get
= ar8xxx_sw_get_mib_poll_interval
1949 .type
= SWITCH_TYPE_INT
,
1950 .name
= "ar8xxx_mib_type",
1951 .description
= "MIB type (0=basic 1=extended)",
1952 .set
= ar8xxx_sw_set_mib_type
,
1953 .get
= ar8xxx_sw_get_mib_type
1956 .type
= SWITCH_TYPE_INT
,
1957 .name
= "enable_mirror_rx",
1958 .description
= "Enable mirroring of RX packets",
1959 .set
= ar8xxx_sw_set_mirror_rx_enable
,
1960 .get
= ar8xxx_sw_get_mirror_rx_enable
,
1964 .type
= SWITCH_TYPE_INT
,
1965 .name
= "enable_mirror_tx",
1966 .description
= "Enable mirroring of TX packets",
1967 .set
= ar8xxx_sw_set_mirror_tx_enable
,
1968 .get
= ar8xxx_sw_get_mirror_tx_enable
,
1972 .type
= SWITCH_TYPE_INT
,
1973 .name
= "mirror_monitor_port",
1974 .description
= "Mirror monitor port",
1975 .set
= ar8xxx_sw_set_mirror_monitor_port
,
1976 .get
= ar8xxx_sw_get_mirror_monitor_port
,
1977 .max
= AR8216_NUM_PORTS
- 1
1980 .type
= SWITCH_TYPE_INT
,
1981 .name
= "mirror_source_port",
1982 .description
= "Mirror source port",
1983 .set
= ar8xxx_sw_set_mirror_source_port
,
1984 .get
= ar8xxx_sw_get_mirror_source_port
,
1985 .max
= AR8216_NUM_PORTS
- 1
1988 .type
= SWITCH_TYPE_STRING
,
1989 .name
= "arl_table",
1990 .description
= "Get ARL table",
1992 .get
= ar8xxx_sw_get_arl_table
,
1995 .type
= SWITCH_TYPE_NOVAL
,
1996 .name
= "flush_arl_table",
1997 .description
= "Flush ARL table",
1998 .set
= ar8xxx_sw_set_flush_arl_table
,
2002 const struct switch_attr ar8xxx_sw_attr_port
[] = {
2004 .type
= SWITCH_TYPE_NOVAL
,
2005 .name
= "reset_mib",
2006 .description
= "Reset single port MIB counters",
2007 .set
= ar8xxx_sw_set_port_reset_mib
,
2010 .type
= SWITCH_TYPE_STRING
,
2012 .description
= "Get port's MIB counters",
2014 .get
= ar8xxx_sw_get_port_mib
,
2017 .type
= SWITCH_TYPE_NOVAL
,
2018 .name
= "flush_arl_table",
2019 .description
= "Flush port's ARL table entries",
2020 .set
= ar8xxx_sw_set_flush_port_arl_table
,
2024 const struct switch_attr ar8xxx_sw_attr_vlan
[1] = {
2026 .type
= SWITCH_TYPE_INT
,
2028 .description
= "VLAN ID (0-4094)",
2029 .set
= ar8xxx_sw_set_vid
,
2030 .get
= ar8xxx_sw_get_vid
,
2035 static const struct switch_dev_ops ar8xxx_sw_ops
= {
2037 .attr
= ar8xxx_sw_attr_globals
,
2038 .n_attr
= ARRAY_SIZE(ar8xxx_sw_attr_globals
),
2041 .attr
= ar8xxx_sw_attr_port
,
2042 .n_attr
= ARRAY_SIZE(ar8xxx_sw_attr_port
),
2045 .attr
= ar8xxx_sw_attr_vlan
,
2046 .n_attr
= ARRAY_SIZE(ar8xxx_sw_attr_vlan
),
2048 .get_port_pvid
= ar8xxx_sw_get_pvid
,
2049 .set_port_pvid
= ar8xxx_sw_set_pvid
,
2050 .get_vlan_ports
= ar8xxx_sw_get_ports
,
2051 .set_vlan_ports
= ar8xxx_sw_set_ports
,
2052 .apply_config
= ar8xxx_sw_hw_apply
,
2053 .reset_switch
= ar8xxx_sw_reset_switch
,
2054 .get_port_link
= ar8xxx_sw_get_port_link
,
2055 .get_port_stats
= ar8xxx_sw_get_port_stats
,
2058 static const struct ar8xxx_chip ar7240sw_chip
= {
2059 .caps
= AR8XXX_CAP_MIB_COUNTERS
,
2061 .reg_port_stats_start
= 0x20000,
2062 .reg_port_stats_length
= 0x100,
2063 .reg_arl_ctrl
= AR8216_REG_ATU_CTRL
,
2065 .name
= "Atheros AR724X/AR933X built-in",
2066 .ports
= AR7240SW_NUM_PORTS
,
2067 .vlans
= AR8216_NUM_VLANS
,
2068 .swops
= &ar8xxx_sw_ops
,
2070 .hw_init
= ar7240sw_hw_init
,
2071 .init_globals
= ar7240sw_init_globals
,
2072 .init_port
= ar8229_init_port
,
2073 .phy_read
= ar8216_phy_read
,
2074 .phy_write
= ar8216_phy_write
,
2075 .setup_port
= ar7240sw_setup_port
,
2076 .read_port_status
= ar8216_read_port_status
,
2077 .atu_flush
= ar8216_atu_flush
,
2078 .atu_flush_port
= ar8216_atu_flush_port
,
2079 .vtu_flush
= ar8216_vtu_flush
,
2080 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
2081 .set_mirror_regs
= ar8216_set_mirror_regs
,
2082 .get_arl_entry
= ar8216_get_arl_entry
,
2083 .sw_hw_apply
= ar8xxx_sw_hw_apply
,
2085 .num_mibs
= ARRAY_SIZE(ar8236_mibs
),
2086 .mib_decs
= ar8236_mibs
,
2087 .mib_func
= AR8216_REG_MIB_FUNC
,
2088 .mib_rxb_id
= AR8236_MIB_RXB_ID
,
2089 .mib_txb_id
= AR8236_MIB_TXB_ID
,
2092 static const struct ar8xxx_chip ar8216_chip
= {
2093 .caps
= AR8XXX_CAP_MIB_COUNTERS
,
2095 .reg_port_stats_start
= 0x19000,
2096 .reg_port_stats_length
= 0xa0,
2097 .reg_arl_ctrl
= AR8216_REG_ATU_CTRL
,
2099 .name
= "Atheros AR8216",
2100 .ports
= AR8216_NUM_PORTS
,
2101 .vlans
= AR8216_NUM_VLANS
,
2102 .swops
= &ar8xxx_sw_ops
,
2104 .hw_init
= ar8216_hw_init
,
2105 .init_globals
= ar8216_init_globals
,
2106 .init_port
= ar8216_init_port
,
2107 .setup_port
= ar8216_setup_port
,
2108 .read_port_status
= ar8216_read_port_status
,
2109 .atu_flush
= ar8216_atu_flush
,
2110 .atu_flush_port
= ar8216_atu_flush_port
,
2111 .vtu_flush
= ar8216_vtu_flush
,
2112 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
2113 .set_mirror_regs
= ar8216_set_mirror_regs
,
2114 .get_arl_entry
= ar8216_get_arl_entry
,
2115 .sw_hw_apply
= ar8xxx_sw_hw_apply
,
2117 .num_mibs
= ARRAY_SIZE(ar8216_mibs
),
2118 .mib_decs
= ar8216_mibs
,
2119 .mib_func
= AR8216_REG_MIB_FUNC
,
2120 .mib_rxb_id
= AR8216_MIB_RXB_ID
,
2121 .mib_txb_id
= AR8216_MIB_TXB_ID
,
2124 static const struct ar8xxx_chip ar8229_chip
= {
2125 .caps
= AR8XXX_CAP_MIB_COUNTERS
,
2127 .reg_port_stats_start
= 0x20000,
2128 .reg_port_stats_length
= 0x100,
2129 .reg_arl_ctrl
= AR8216_REG_ATU_CTRL
,
2131 .name
= "Atheros AR8229",
2132 .ports
= AR8216_NUM_PORTS
,
2133 .vlans
= AR8216_NUM_VLANS
,
2134 .swops
= &ar8xxx_sw_ops
,
2136 .hw_init
= ar8229_hw_init
,
2137 .init_globals
= ar8229_init_globals
,
2138 .init_port
= ar8229_init_port
,
2139 .phy_read
= ar8216_phy_read
,
2140 .phy_write
= ar8216_phy_write
,
2141 .setup_port
= ar8236_setup_port
,
2142 .read_port_status
= ar8216_read_port_status
,
2143 .atu_flush
= ar8216_atu_flush
,
2144 .atu_flush_port
= ar8216_atu_flush_port
,
2145 .vtu_flush
= ar8216_vtu_flush
,
2146 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
2147 .set_mirror_regs
= ar8216_set_mirror_regs
,
2148 .get_arl_entry
= ar8216_get_arl_entry
,
2149 .sw_hw_apply
= ar8xxx_sw_hw_apply
,
2151 .num_mibs
= ARRAY_SIZE(ar8236_mibs
),
2152 .mib_decs
= ar8236_mibs
,
2153 .mib_func
= AR8216_REG_MIB_FUNC
,
2154 .mib_rxb_id
= AR8236_MIB_RXB_ID
,
2155 .mib_txb_id
= AR8236_MIB_TXB_ID
,
2158 static const struct ar8xxx_chip ar8236_chip
= {
2159 .caps
= AR8XXX_CAP_MIB_COUNTERS
,
2161 .reg_port_stats_start
= 0x20000,
2162 .reg_port_stats_length
= 0x100,
2163 .reg_arl_ctrl
= AR8216_REG_ATU_CTRL
,
2165 .name
= "Atheros AR8236",
2166 .ports
= AR8216_NUM_PORTS
,
2167 .vlans
= AR8216_NUM_VLANS
,
2168 .swops
= &ar8xxx_sw_ops
,
2170 .hw_init
= ar8216_hw_init
,
2171 .init_globals
= ar8236_init_globals
,
2172 .init_port
= ar8216_init_port
,
2173 .setup_port
= ar8236_setup_port
,
2174 .read_port_status
= ar8216_read_port_status
,
2175 .atu_flush
= ar8216_atu_flush
,
2176 .atu_flush_port
= ar8216_atu_flush_port
,
2177 .vtu_flush
= ar8216_vtu_flush
,
2178 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
2179 .set_mirror_regs
= ar8216_set_mirror_regs
,
2180 .get_arl_entry
= ar8216_get_arl_entry
,
2181 .sw_hw_apply
= ar8xxx_sw_hw_apply
,
2183 .num_mibs
= ARRAY_SIZE(ar8236_mibs
),
2184 .mib_decs
= ar8236_mibs
,
2185 .mib_func
= AR8216_REG_MIB_FUNC
,
2186 .mib_rxb_id
= AR8236_MIB_RXB_ID
,
2187 .mib_txb_id
= AR8236_MIB_TXB_ID
,
2190 static const struct ar8xxx_chip ar8316_chip
= {
2191 .caps
= AR8XXX_CAP_GIGE
| AR8XXX_CAP_MIB_COUNTERS
,
2193 .reg_port_stats_start
= 0x20000,
2194 .reg_port_stats_length
= 0x100,
2195 .reg_arl_ctrl
= AR8216_REG_ATU_CTRL
,
2197 .name
= "Atheros AR8316",
2198 .ports
= AR8216_NUM_PORTS
,
2199 .vlans
= AR8X16_MAX_VLANS
,
2200 .swops
= &ar8xxx_sw_ops
,
2202 .hw_init
= ar8316_hw_init
,
2203 .init_globals
= ar8316_init_globals
,
2204 .init_port
= ar8216_init_port
,
2205 .setup_port
= ar8216_setup_port
,
2206 .read_port_status
= ar8216_read_port_status
,
2207 .atu_flush
= ar8216_atu_flush
,
2208 .atu_flush_port
= ar8216_atu_flush_port
,
2209 .vtu_flush
= ar8216_vtu_flush
,
2210 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
2211 .set_mirror_regs
= ar8216_set_mirror_regs
,
2212 .get_arl_entry
= ar8216_get_arl_entry
,
2213 .sw_hw_apply
= ar8xxx_sw_hw_apply
,
2215 .num_mibs
= ARRAY_SIZE(ar8236_mibs
),
2216 .mib_decs
= ar8236_mibs
,
2217 .mib_func
= AR8216_REG_MIB_FUNC
,
2218 .mib_rxb_id
= AR8236_MIB_RXB_ID
,
2219 .mib_txb_id
= AR8236_MIB_TXB_ID
,
2223 ar8xxx_read_id(struct ar8xxx_priv
*priv
)
2229 val
= ar8xxx_read(priv
, AR8216_REG_CTRL
);
2233 id
= val
& (AR8216_CTRL_REVISION
| AR8216_CTRL_VERSION
);
2234 for (i
= 0; i
< AR8X16_PROBE_RETRIES
; i
++) {
2237 val
= ar8xxx_read(priv
, AR8216_REG_CTRL
);
2241 t
= val
& (AR8216_CTRL_REVISION
| AR8216_CTRL_VERSION
);
2246 priv
->chip_ver
= (id
& AR8216_CTRL_VERSION
) >> AR8216_CTRL_VERSION_S
;
2247 priv
->chip_rev
= (id
& AR8216_CTRL_REVISION
);
2252 ar8xxx_id_chip(struct ar8xxx_priv
*priv
)
2256 ret
= ar8xxx_read_id(priv
);
2260 switch (priv
->chip_ver
) {
2261 case AR8XXX_VER_AR8216
:
2262 priv
->chip
= &ar8216_chip
;
2264 case AR8XXX_VER_AR8236
:
2265 priv
->chip
= &ar8236_chip
;
2267 case AR8XXX_VER_AR8316
:
2268 priv
->chip
= &ar8316_chip
;
2270 case AR8XXX_VER_AR8327
:
2271 priv
->chip
= &ar8327_chip
;
2273 case AR8XXX_VER_AR8337
:
2274 priv
->chip
= &ar8337_chip
;
2277 pr_err("ar8216: Unknown Atheros device [ver=%d, rev=%d]\n",
2278 priv
->chip_ver
, priv
->chip_rev
);
2287 ar8xxx_mib_work_func(struct work_struct
*work
)
2289 struct ar8xxx_priv
*priv
;
2292 priv
= container_of(work
, struct ar8xxx_priv
, mib_work
.work
);
2294 mutex_lock(&priv
->mib_lock
);
2296 err
= ar8xxx_mib_capture(priv
);
2300 for (i
= 0; i
< priv
->dev
.ports
; i
++)
2301 ar8xxx_mib_fetch_port_stat(priv
, i
, false);
2304 mutex_unlock(&priv
->mib_lock
);
2305 schedule_delayed_work(&priv
->mib_work
,
2306 msecs_to_jiffies(priv
->mib_poll_interval
));
2310 ar8xxx_mib_init(struct ar8xxx_priv
*priv
)
2314 if (!ar8xxx_has_mib_counters(priv
))
2317 BUG_ON(!priv
->chip
->mib_decs
|| !priv
->chip
->num_mibs
);
2319 len
= priv
->dev
.ports
* priv
->chip
->num_mibs
*
2320 sizeof(*priv
->mib_stats
);
2321 priv
->mib_stats
= kzalloc(len
, GFP_KERNEL
);
2323 if (!priv
->mib_stats
)
2330 ar8xxx_mib_start(struct ar8xxx_priv
*priv
)
2332 if (!ar8xxx_has_mib_counters(priv
) || !priv
->mib_poll_interval
)
2335 schedule_delayed_work(&priv
->mib_work
,
2336 msecs_to_jiffies(priv
->mib_poll_interval
));
2340 ar8xxx_mib_stop(struct ar8xxx_priv
*priv
)
2342 if (!ar8xxx_has_mib_counters(priv
) || !priv
->mib_poll_interval
)
2345 cancel_delayed_work_sync(&priv
->mib_work
);
2348 static struct ar8xxx_priv
*
2351 struct ar8xxx_priv
*priv
;
2353 priv
= kzalloc(sizeof(struct ar8xxx_priv
), GFP_KERNEL
);
2357 mutex_init(&priv
->reg_mutex
);
2358 mutex_init(&priv
->mib_lock
);
2359 INIT_DELAYED_WORK(&priv
->mib_work
, ar8xxx_mib_work_func
);
2365 ar8xxx_free(struct ar8xxx_priv
*priv
)
2367 if (priv
->chip
&& priv
->chip
->cleanup
)
2368 priv
->chip
->cleanup(priv
);
2370 kfree(priv
->chip_data
);
2371 kfree(priv
->mib_stats
);
2376 ar8xxx_probe_switch(struct ar8xxx_priv
*priv
)
2378 const struct ar8xxx_chip
*chip
;
2379 struct switch_dev
*swdev
;
2385 swdev
->cpu_port
= AR8216_PORT_CPU
;
2386 swdev
->name
= chip
->name
;
2387 swdev
->vlans
= chip
->vlans
;
2388 swdev
->ports
= chip
->ports
;
2389 swdev
->ops
= chip
->swops
;
2391 ret
= ar8xxx_mib_init(priv
);
2399 ar8xxx_start(struct ar8xxx_priv
*priv
)
2405 ret
= priv
->chip
->hw_init(priv
);
2409 ret
= ar8xxx_sw_reset_switch(&priv
->dev
);
2415 ar8xxx_mib_start(priv
);
2421 ar8xxx_phy_config_init(struct phy_device
*phydev
)
2423 struct ar8xxx_priv
*priv
= phydev
->priv
;
2424 struct net_device
*dev
= phydev
->attached_dev
;
2430 if (priv
->chip
->config_at_probe
)
2431 return ar8xxx_phy_check_aneg(phydev
);
2435 if (phydev
->mdio
.addr
!= 0) {
2436 if (chip_is_ar8316(priv
)) {
2437 /* switch device has been initialized, reinit */
2438 priv
->dev
.ports
= (AR8216_NUM_PORTS
- 1);
2439 priv
->initialized
= false;
2440 priv
->port4_phy
= true;
2441 ar8316_hw_init(priv
);
2448 ret
= ar8xxx_start(priv
);
2452 /* VID fixup only needed on ar8216 */
2453 if (chip_is_ar8216(priv
)) {
2454 dev
->phy_ptr
= priv
;
2455 dev
->priv_flags
|= IFF_NO_IP_ALIGN
;
2456 dev
->eth_mangle_rx
= ar8216_mangle_rx
;
2457 dev
->eth_mangle_tx
= ar8216_mangle_tx
;
2464 ar8xxx_check_link_states(struct ar8xxx_priv
*priv
)
2466 bool link_new
, changed
= false;
2470 mutex_lock(&priv
->reg_mutex
);
2472 for (i
= 0; i
< priv
->dev
.ports
; i
++) {
2473 status
= priv
->chip
->read_port_status(priv
, i
);
2474 link_new
= !!(status
& AR8216_PORT_STATUS_LINK_UP
);
2475 if (link_new
== priv
->link_up
[i
])
2478 priv
->link_up
[i
] = link_new
;
2480 /* flush ARL entries for this port if it went down*/
2482 priv
->chip
->atu_flush_port(priv
, i
);
2483 dev_info(&priv
->phy
->mdio
.dev
, "Port %d is %s\n",
2484 i
, link_new
? "up" : "down");
2487 mutex_unlock(&priv
->reg_mutex
);
2493 ar8xxx_phy_read_status(struct phy_device
*phydev
)
2495 struct ar8xxx_priv
*priv
= phydev
->priv
;
2496 struct switch_port_link link
;
2498 /* check for switch port link changes */
2499 ar8xxx_check_link_states(priv
);
2501 if (phydev
->mdio
.addr
!= 0)
2502 return genphy_read_status(phydev
);
2504 ar8216_read_port_link(priv
, phydev
->mdio
.addr
, &link
);
2505 phydev
->link
= !!link
.link
;
2509 switch (link
.speed
) {
2510 case SWITCH_PORT_SPEED_10
:
2511 phydev
->speed
= SPEED_10
;
2513 case SWITCH_PORT_SPEED_100
:
2514 phydev
->speed
= SPEED_100
;
2516 case SWITCH_PORT_SPEED_1000
:
2517 phydev
->speed
= SPEED_1000
;
2522 phydev
->duplex
= link
.duplex
? DUPLEX_FULL
: DUPLEX_HALF
;
2524 phydev
->state
= PHY_RUNNING
;
2525 netif_carrier_on(phydev
->attached_dev
);
2526 if (phydev
->adjust_link
)
2527 phydev
->adjust_link(phydev
->attached_dev
);
2533 ar8xxx_phy_config_aneg(struct phy_device
*phydev
)
2535 if (phydev
->mdio
.addr
== 0)
2538 return genphy_config_aneg(phydev
);
2541 static const u32 ar8xxx_phy_ids
[] = {
2543 0x004dd034, /* AR8327 */
2544 0x004dd036, /* AR8337 */
2547 0x004dd043, /* AR8236 */
2551 ar8xxx_phy_match(u32 phy_id
)
2555 for (i
= 0; i
< ARRAY_SIZE(ar8xxx_phy_ids
); i
++)
2556 if (phy_id
== ar8xxx_phy_ids
[i
])
2563 ar8xxx_is_possible(struct mii_bus
*bus
)
2565 unsigned int i
, found_phys
= 0;
2567 for (i
= 0; i
< 5; i
++) {
2570 phy_id
= mdiobus_read(bus
, i
, MII_PHYSID1
) << 16;
2571 phy_id
|= mdiobus_read(bus
, i
, MII_PHYSID2
);
2572 if (ar8xxx_phy_match(phy_id
)) {
2574 } else if (phy_id
) {
2575 pr_debug("ar8xxx: unknown PHY at %s:%02x id:%08x\n",
2576 dev_name(&bus
->dev
), i
, phy_id
);
2579 return !!found_phys
;
2583 ar8xxx_phy_probe(struct phy_device
*phydev
)
2585 struct ar8xxx_priv
*priv
;
2586 struct switch_dev
*swdev
;
2589 /* skip PHYs at unused adresses */
2590 if (phydev
->mdio
.addr
!= 0 && phydev
->mdio
.addr
!= 3 && phydev
->mdio
.addr
!= 4)
2593 if (!ar8xxx_is_possible(phydev
->mdio
.bus
))
2596 mutex_lock(&ar8xxx_dev_list_lock
);
2597 list_for_each_entry(priv
, &ar8xxx_dev_list
, list
)
2598 if (priv
->mii_bus
== phydev
->mdio
.bus
)
2601 priv
= ar8xxx_create();
2607 priv
->mii_bus
= phydev
->mdio
.bus
;
2608 priv
->pdev
= &phydev
->mdio
.dev
;
2610 ret
= of_property_read_u32(priv
->pdev
->of_node
, "qca,mib-poll-interval",
2611 &priv
->mib_poll_interval
);
2613 priv
->mib_poll_interval
= 0;
2615 ret
= ar8xxx_id_chip(priv
);
2619 ret
= ar8xxx_probe_switch(priv
);
2624 swdev
->alias
= dev_name(&priv
->mii_bus
->dev
);
2625 ret
= register_switch(swdev
, NULL
);
2629 pr_info("%s: %s rev. %u switch registered on %s\n",
2630 swdev
->devname
, swdev
->name
, priv
->chip_rev
,
2631 dev_name(&priv
->mii_bus
->dev
));
2633 list_add(&priv
->list
, &ar8xxx_dev_list
);
2638 if (phydev
->mdio
.addr
== 0) {
2639 linkmode_zero(phydev
->supported
);
2640 if (ar8xxx_has_gige(priv
))
2641 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT
, phydev
->supported
);
2643 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT
, phydev
->supported
);
2644 linkmode_copy(phydev
->advertising
, phydev
->supported
);
2646 if (priv
->chip
->config_at_probe
) {
2649 ret
= ar8xxx_start(priv
);
2651 goto err_unregister_switch
;
2654 if (ar8xxx_has_gige(priv
)) {
2655 linkmode_zero(phydev
->supported
);
2656 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT
, phydev
->supported
);
2657 linkmode_copy(phydev
->advertising
, phydev
->supported
);
2659 if (priv
->chip
->phy_rgmii_set
)
2660 priv
->chip
->phy_rgmii_set(priv
, phydev
);
2663 phydev
->priv
= priv
;
2665 mutex_unlock(&ar8xxx_dev_list_lock
);
2669 err_unregister_switch
:
2670 if (--priv
->use_count
)
2673 unregister_switch(&priv
->dev
);
2678 mutex_unlock(&ar8xxx_dev_list_lock
);
2683 ar8xxx_phy_detach(struct phy_device
*phydev
)
2685 struct net_device
*dev
= phydev
->attached_dev
;
2690 dev
->phy_ptr
= NULL
;
2691 dev
->priv_flags
&= ~IFF_NO_IP_ALIGN
;
2692 dev
->eth_mangle_rx
= NULL
;
2693 dev
->eth_mangle_tx
= NULL
;
2697 ar8xxx_phy_remove(struct phy_device
*phydev
)
2699 struct ar8xxx_priv
*priv
= phydev
->priv
;
2704 phydev
->priv
= NULL
;
2706 mutex_lock(&ar8xxx_dev_list_lock
);
2708 if (--priv
->use_count
> 0) {
2709 mutex_unlock(&ar8xxx_dev_list_lock
);
2713 list_del(&priv
->list
);
2714 mutex_unlock(&ar8xxx_dev_list_lock
);
2716 unregister_switch(&priv
->dev
);
2717 ar8xxx_mib_stop(priv
);
2722 ar8xxx_phy_soft_reset(struct phy_device
*phydev
)
2724 /* we don't need an extra reset */
2728 static struct phy_driver ar8xxx_phy_driver
[] = {
2730 .phy_id
= 0x004d0000,
2731 .name
= "Atheros AR8216/AR8236/AR8316",
2732 .phy_id_mask
= 0xffff0000,
2733 .features
= PHY_BASIC_FEATURES
,
2734 .probe
= ar8xxx_phy_probe
,
2735 .remove
= ar8xxx_phy_remove
,
2736 .detach
= ar8xxx_phy_detach
,
2737 .config_init
= ar8xxx_phy_config_init
,
2738 .config_aneg
= ar8xxx_phy_config_aneg
,
2739 .read_status
= ar8xxx_phy_read_status
,
2740 .soft_reset
= ar8xxx_phy_soft_reset
,
2744 static const struct of_device_id ar8xxx_mdiodev_of_match
[] = {
2746 .compatible
= "qca,ar7240sw",
2747 .data
= &ar7240sw_chip
,
2749 .compatible
= "qca,ar8229",
2750 .data
= &ar8229_chip
,
2752 .compatible
= "qca,ar8236",
2753 .data
= &ar8236_chip
,
2755 .compatible
= "qca,ar8327",
2756 .data
= &ar8327_chip
,
2762 ar8xxx_mdiodev_probe(struct mdio_device
*mdiodev
)
2764 const struct of_device_id
*match
;
2765 struct ar8xxx_priv
*priv
;
2766 struct switch_dev
*swdev
;
2767 struct device_node
*mdio_node
;
2770 match
= of_match_device(ar8xxx_mdiodev_of_match
, &mdiodev
->dev
);
2774 priv
= ar8xxx_create();
2778 priv
->mii_bus
= mdiodev
->bus
;
2779 priv
->pdev
= &mdiodev
->dev
;
2780 priv
->chip
= (const struct ar8xxx_chip
*) match
->data
;
2782 ret
= of_property_read_u32(priv
->pdev
->of_node
, "qca,mib-poll-interval",
2783 &priv
->mib_poll_interval
);
2785 priv
->mib_poll_interval
= 0;
2787 ret
= ar8xxx_read_id(priv
);
2791 ret
= ar8xxx_probe_switch(priv
);
2795 if (priv
->chip
->phy_read
&& priv
->chip
->phy_write
) {
2796 priv
->sw_mii_bus
= devm_mdiobus_alloc(&mdiodev
->dev
);
2797 priv
->sw_mii_bus
->name
= "ar8xxx-mdio";
2798 priv
->sw_mii_bus
->read
= ar8xxx_phy_read
;
2799 priv
->sw_mii_bus
->write
= ar8xxx_phy_write
;
2800 priv
->sw_mii_bus
->priv
= priv
;
2801 priv
->sw_mii_bus
->parent
= &mdiodev
->dev
;
2802 snprintf(priv
->sw_mii_bus
->id
, MII_BUS_ID_SIZE
, "%s",
2803 dev_name(&mdiodev
->dev
));
2804 mdio_node
= of_get_child_by_name(priv
->pdev
->of_node
, "mdio-bus");
2805 ret
= of_mdiobus_register(priv
->sw_mii_bus
, mdio_node
);
2811 swdev
->alias
= dev_name(&mdiodev
->dev
);
2813 if (of_property_read_bool(priv
->pdev
->of_node
, "qca,phy4-mii-enable")) {
2814 priv
->port4_phy
= true;
2818 ret
= register_switch(swdev
, NULL
);
2822 pr_info("%s: %s rev. %u switch registered on %s\n",
2823 swdev
->devname
, swdev
->name
, priv
->chip_rev
,
2824 dev_name(&priv
->mii_bus
->dev
));
2826 mutex_lock(&ar8xxx_dev_list_lock
);
2827 list_add(&priv
->list
, &ar8xxx_dev_list
);
2828 mutex_unlock(&ar8xxx_dev_list_lock
);
2832 ret
= ar8xxx_start(priv
);
2834 goto err_unregister_switch
;
2836 dev_set_drvdata(&mdiodev
->dev
, priv
);
2840 err_unregister_switch
:
2841 if (--priv
->use_count
)
2844 unregister_switch(&priv
->dev
);
2852 ar8xxx_mdiodev_remove(struct mdio_device
*mdiodev
)
2854 struct ar8xxx_priv
*priv
= dev_get_drvdata(&mdiodev
->dev
);
2859 mutex_lock(&ar8xxx_dev_list_lock
);
2861 if (--priv
->use_count
> 0) {
2862 mutex_unlock(&ar8xxx_dev_list_lock
);
2866 list_del(&priv
->list
);
2867 mutex_unlock(&ar8xxx_dev_list_lock
);
2869 unregister_switch(&priv
->dev
);
2870 ar8xxx_mib_stop(priv
);
2871 if(priv
->sw_mii_bus
)
2872 mdiobus_unregister(priv
->sw_mii_bus
);
2876 static struct mdio_driver ar8xxx_mdio_driver
= {
2877 .probe
= ar8xxx_mdiodev_probe
,
2878 .remove
= ar8xxx_mdiodev_remove
,
2880 .name
= "ar8xxx-switch",
2881 .of_match_table
= ar8xxx_mdiodev_of_match
,
2885 static int __init
ar8216_init(void)
2889 ret
= phy_drivers_register(ar8xxx_phy_driver
,
2890 ARRAY_SIZE(ar8xxx_phy_driver
),
2895 ret
= mdio_driver_register(&ar8xxx_mdio_driver
);
2897 phy_drivers_unregister(ar8xxx_phy_driver
,
2898 ARRAY_SIZE(ar8xxx_phy_driver
));
2902 module_init(ar8216_init
);
2904 static void __exit
ar8216_exit(void)
2906 mdio_driver_unregister(&ar8xxx_mdio_driver
);
2907 phy_drivers_unregister(ar8xxx_phy_driver
,
2908 ARRAY_SIZE(ar8xxx_phy_driver
));
2910 module_exit(ar8216_exit
);
2912 MODULE_LICENSE("GPL");