2 * ar8216.c: AR8216 switch driver
4 * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/list.h>
22 #include <linux/if_ether.h>
23 #include <linux/skbuff.h>
24 #include <linux/netdevice.h>
25 #include <linux/netlink.h>
26 #include <linux/bitops.h>
27 #include <net/genetlink.h>
28 #include <linux/switch.h>
29 #include <linux/delay.h>
30 #include <linux/phy.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/lockdep.h>
34 #include <linux/ar8216_platform.h>
35 #include <linux/workqueue.h>
36 #include <linux/of_device.h>
37 #include <linux/leds.h>
38 #include <linux/gpio.h>
39 #include <linux/version.h>
43 /* size of the vlan table */
44 #define AR8X16_MAX_VLANS 128
45 #define AR8X16_PROBE_RETRIES 10
46 #define AR8X16_MAX_PORTS 8
48 #define AR8XXX_MIB_WORK_DELAY 2000 /* msecs */
52 #define AR8XXX_CAP_GIGE BIT(0)
53 #define AR8XXX_CAP_MIB_COUNTERS BIT(1)
55 #define AR8XXX_NUM_PHYS 5
58 AR8XXX_VER_AR8216
= 0x01,
59 AR8XXX_VER_AR8236
= 0x03,
60 AR8XXX_VER_AR8316
= 0x10,
61 AR8XXX_VER_AR8327
= 0x12,
62 AR8XXX_VER_AR8337
= 0x13,
65 struct ar8xxx_mib_desc
{
76 /* parameters to calculate REG_PORT_STATS_BASE */
77 unsigned reg_port_stats_start
;
78 unsigned reg_port_stats_length
;
80 int (*hw_init
)(struct ar8xxx_priv
*priv
);
81 void (*cleanup
)(struct ar8xxx_priv
*priv
);
86 const struct switch_dev_ops
*swops
;
88 void (*init_globals
)(struct ar8xxx_priv
*priv
);
89 void (*init_port
)(struct ar8xxx_priv
*priv
, int port
);
90 void (*setup_port
)(struct ar8xxx_priv
*priv
, int port
, u32 members
);
91 u32 (*read_port_status
)(struct ar8xxx_priv
*priv
, int port
);
92 int (*atu_flush
)(struct ar8xxx_priv
*priv
);
93 void (*vtu_flush
)(struct ar8xxx_priv
*priv
);
94 void (*vtu_load_vlan
)(struct ar8xxx_priv
*priv
, u32 vid
, u32 port_mask
);
95 void (*phy_fixup
)(struct ar8xxx_priv
*priv
, int phy
);
96 void (*set_mirror_regs
)(struct ar8xxx_priv
*priv
);
98 const struct ar8xxx_mib_desc
*mib_decs
;
103 enum ar8327_led_pattern
{
104 AR8327_LED_PATTERN_OFF
= 0,
105 AR8327_LED_PATTERN_BLINK
,
106 AR8327_LED_PATTERN_ON
,
107 AR8327_LED_PATTERN_RULE
,
110 struct ar8327_led_entry
{
116 struct led_classdev cdev
;
117 struct ar8xxx_priv
*sw_priv
;
122 enum ar8327_led_mode mode
;
126 struct work_struct led_work
;
128 enum ar8327_led_pattern pattern
;
135 struct ar8327_led
**leds
;
136 unsigned int num_leds
;
140 struct switch_dev dev
;
141 struct mii_bus
*mii_bus
;
142 struct phy_device
*phy
;
144 u32 (*read
)(struct ar8xxx_priv
*priv
, int reg
);
145 void (*write
)(struct ar8xxx_priv
*priv
, int reg
, u32 val
);
146 u32 (*rmw
)(struct ar8xxx_priv
*priv
, int reg
, u32 mask
, u32 val
);
148 int (*get_port_link
)(unsigned port
);
150 const struct net_device_ops
*ndo_old
;
151 struct net_device_ops ndo
;
152 struct mutex reg_mutex
;
155 const struct ar8xxx_chip
*chip
;
163 struct mutex mib_lock
;
164 struct delayed_work mib_work
;
168 struct list_head list
;
169 unsigned int use_count
;
171 /* all fields below are cleared on reset */
173 u16 vlan_id
[AR8X16_MAX_VLANS
];
174 u8 vlan_table
[AR8X16_MAX_VLANS
];
176 u16 pvid
[AR8X16_MAX_PORTS
];
185 #define MIB_DESC(_s , _o, _n) \
192 static const struct ar8xxx_mib_desc ar8216_mibs
[] = {
193 MIB_DESC(1, AR8216_STATS_RXBROAD
, "RxBroad"),
194 MIB_DESC(1, AR8216_STATS_RXPAUSE
, "RxPause"),
195 MIB_DESC(1, AR8216_STATS_RXMULTI
, "RxMulti"),
196 MIB_DESC(1, AR8216_STATS_RXFCSERR
, "RxFcsErr"),
197 MIB_DESC(1, AR8216_STATS_RXALIGNERR
, "RxAlignErr"),
198 MIB_DESC(1, AR8216_STATS_RXRUNT
, "RxRunt"),
199 MIB_DESC(1, AR8216_STATS_RXFRAGMENT
, "RxFragment"),
200 MIB_DESC(1, AR8216_STATS_RX64BYTE
, "Rx64Byte"),
201 MIB_DESC(1, AR8216_STATS_RX128BYTE
, "Rx128Byte"),
202 MIB_DESC(1, AR8216_STATS_RX256BYTE
, "Rx256Byte"),
203 MIB_DESC(1, AR8216_STATS_RX512BYTE
, "Rx512Byte"),
204 MIB_DESC(1, AR8216_STATS_RX1024BYTE
, "Rx1024Byte"),
205 MIB_DESC(1, AR8216_STATS_RXMAXBYTE
, "RxMaxByte"),
206 MIB_DESC(1, AR8216_STATS_RXTOOLONG
, "RxTooLong"),
207 MIB_DESC(2, AR8216_STATS_RXGOODBYTE
, "RxGoodByte"),
208 MIB_DESC(2, AR8216_STATS_RXBADBYTE
, "RxBadByte"),
209 MIB_DESC(1, AR8216_STATS_RXOVERFLOW
, "RxOverFlow"),
210 MIB_DESC(1, AR8216_STATS_FILTERED
, "Filtered"),
211 MIB_DESC(1, AR8216_STATS_TXBROAD
, "TxBroad"),
212 MIB_DESC(1, AR8216_STATS_TXPAUSE
, "TxPause"),
213 MIB_DESC(1, AR8216_STATS_TXMULTI
, "TxMulti"),
214 MIB_DESC(1, AR8216_STATS_TXUNDERRUN
, "TxUnderRun"),
215 MIB_DESC(1, AR8216_STATS_TX64BYTE
, "Tx64Byte"),
216 MIB_DESC(1, AR8216_STATS_TX128BYTE
, "Tx128Byte"),
217 MIB_DESC(1, AR8216_STATS_TX256BYTE
, "Tx256Byte"),
218 MIB_DESC(1, AR8216_STATS_TX512BYTE
, "Tx512Byte"),
219 MIB_DESC(1, AR8216_STATS_TX1024BYTE
, "Tx1024Byte"),
220 MIB_DESC(1, AR8216_STATS_TXMAXBYTE
, "TxMaxByte"),
221 MIB_DESC(1, AR8216_STATS_TXOVERSIZE
, "TxOverSize"),
222 MIB_DESC(2, AR8216_STATS_TXBYTE
, "TxByte"),
223 MIB_DESC(1, AR8216_STATS_TXCOLLISION
, "TxCollision"),
224 MIB_DESC(1, AR8216_STATS_TXABORTCOL
, "TxAbortCol"),
225 MIB_DESC(1, AR8216_STATS_TXMULTICOL
, "TxMultiCol"),
226 MIB_DESC(1, AR8216_STATS_TXSINGLECOL
, "TxSingleCol"),
227 MIB_DESC(1, AR8216_STATS_TXEXCDEFER
, "TxExcDefer"),
228 MIB_DESC(1, AR8216_STATS_TXDEFER
, "TxDefer"),
229 MIB_DESC(1, AR8216_STATS_TXLATECOL
, "TxLateCol"),
232 static const struct ar8xxx_mib_desc ar8236_mibs
[] = {
233 MIB_DESC(1, AR8236_STATS_RXBROAD
, "RxBroad"),
234 MIB_DESC(1, AR8236_STATS_RXPAUSE
, "RxPause"),
235 MIB_DESC(1, AR8236_STATS_RXMULTI
, "RxMulti"),
236 MIB_DESC(1, AR8236_STATS_RXFCSERR
, "RxFcsErr"),
237 MIB_DESC(1, AR8236_STATS_RXALIGNERR
, "RxAlignErr"),
238 MIB_DESC(1, AR8236_STATS_RXRUNT
, "RxRunt"),
239 MIB_DESC(1, AR8236_STATS_RXFRAGMENT
, "RxFragment"),
240 MIB_DESC(1, AR8236_STATS_RX64BYTE
, "Rx64Byte"),
241 MIB_DESC(1, AR8236_STATS_RX128BYTE
, "Rx128Byte"),
242 MIB_DESC(1, AR8236_STATS_RX256BYTE
, "Rx256Byte"),
243 MIB_DESC(1, AR8236_STATS_RX512BYTE
, "Rx512Byte"),
244 MIB_DESC(1, AR8236_STATS_RX1024BYTE
, "Rx1024Byte"),
245 MIB_DESC(1, AR8236_STATS_RX1518BYTE
, "Rx1518Byte"),
246 MIB_DESC(1, AR8236_STATS_RXMAXBYTE
, "RxMaxByte"),
247 MIB_DESC(1, AR8236_STATS_RXTOOLONG
, "RxTooLong"),
248 MIB_DESC(2, AR8236_STATS_RXGOODBYTE
, "RxGoodByte"),
249 MIB_DESC(2, AR8236_STATS_RXBADBYTE
, "RxBadByte"),
250 MIB_DESC(1, AR8236_STATS_RXOVERFLOW
, "RxOverFlow"),
251 MIB_DESC(1, AR8236_STATS_FILTERED
, "Filtered"),
252 MIB_DESC(1, AR8236_STATS_TXBROAD
, "TxBroad"),
253 MIB_DESC(1, AR8236_STATS_TXPAUSE
, "TxPause"),
254 MIB_DESC(1, AR8236_STATS_TXMULTI
, "TxMulti"),
255 MIB_DESC(1, AR8236_STATS_TXUNDERRUN
, "TxUnderRun"),
256 MIB_DESC(1, AR8236_STATS_TX64BYTE
, "Tx64Byte"),
257 MIB_DESC(1, AR8236_STATS_TX128BYTE
, "Tx128Byte"),
258 MIB_DESC(1, AR8236_STATS_TX256BYTE
, "Tx256Byte"),
259 MIB_DESC(1, AR8236_STATS_TX512BYTE
, "Tx512Byte"),
260 MIB_DESC(1, AR8236_STATS_TX1024BYTE
, "Tx1024Byte"),
261 MIB_DESC(1, AR8236_STATS_TX1518BYTE
, "Tx1518Byte"),
262 MIB_DESC(1, AR8236_STATS_TXMAXBYTE
, "TxMaxByte"),
263 MIB_DESC(1, AR8236_STATS_TXOVERSIZE
, "TxOverSize"),
264 MIB_DESC(2, AR8236_STATS_TXBYTE
, "TxByte"),
265 MIB_DESC(1, AR8236_STATS_TXCOLLISION
, "TxCollision"),
266 MIB_DESC(1, AR8236_STATS_TXABORTCOL
, "TxAbortCol"),
267 MIB_DESC(1, AR8236_STATS_TXMULTICOL
, "TxMultiCol"),
268 MIB_DESC(1, AR8236_STATS_TXSINGLECOL
, "TxSingleCol"),
269 MIB_DESC(1, AR8236_STATS_TXEXCDEFER
, "TxExcDefer"),
270 MIB_DESC(1, AR8236_STATS_TXDEFER
, "TxDefer"),
271 MIB_DESC(1, AR8236_STATS_TXLATECOL
, "TxLateCol"),
274 static DEFINE_MUTEX(ar8xxx_dev_list_lock
);
275 static LIST_HEAD(ar8xxx_dev_list
);
277 static inline struct ar8xxx_priv
*
278 swdev_to_ar8xxx(struct switch_dev
*swdev
)
280 return container_of(swdev
, struct ar8xxx_priv
, dev
);
283 static inline bool ar8xxx_has_gige(struct ar8xxx_priv
*priv
)
285 return priv
->chip
->caps
& AR8XXX_CAP_GIGE
;
288 static inline bool ar8xxx_has_mib_counters(struct ar8xxx_priv
*priv
)
290 return priv
->chip
->caps
& AR8XXX_CAP_MIB_COUNTERS
;
293 static inline bool chip_is_ar8216(struct ar8xxx_priv
*priv
)
295 return priv
->chip_ver
== AR8XXX_VER_AR8216
;
298 static inline bool chip_is_ar8236(struct ar8xxx_priv
*priv
)
300 return priv
->chip_ver
== AR8XXX_VER_AR8236
;
303 static inline bool chip_is_ar8316(struct ar8xxx_priv
*priv
)
305 return priv
->chip_ver
== AR8XXX_VER_AR8316
;
308 static inline bool chip_is_ar8327(struct ar8xxx_priv
*priv
)
310 return priv
->chip_ver
== AR8XXX_VER_AR8327
;
313 static inline bool chip_is_ar8337(struct ar8xxx_priv
*priv
)
315 return priv
->chip_ver
== AR8XXX_VER_AR8337
;
319 split_addr(u32 regaddr
, u16
*r1
, u16
*r2
, u16
*page
)
322 *r1
= regaddr
& 0x1e;
328 *page
= regaddr
& 0x1ff;
331 /* inspired by phy_poll_reset in drivers/net/phy/phy_device.c */
333 ar8xxx_phy_poll_reset(struct mii_bus
*bus
)
335 unsigned int sleep_msecs
= 20;
338 for (elapsed
= sleep_msecs
; elapsed
<= 600;
339 elapsed
+= sleep_msecs
) {
341 for (i
= 0; i
< AR8XXX_NUM_PHYS
; i
++) {
342 ret
= mdiobus_read(bus
, i
, MII_BMCR
);
345 if (ret
& BMCR_RESET
)
347 if (i
== AR8XXX_NUM_PHYS
- 1) {
348 usleep_range(1000, 2000);
357 ar8xxx_phy_check_aneg(struct phy_device
*phydev
)
361 if (phydev
->autoneg
!= AUTONEG_ENABLE
)
364 * BMCR_ANENABLE might have been cleared
365 * by phy_init_hw in certain kernel versions
366 * therefore check for it
368 ret
= phy_read(phydev
, MII_BMCR
);
371 if (ret
& BMCR_ANENABLE
)
374 dev_info(&phydev
->dev
, "ANEG disabled, re-enabling ...\n");
375 ret
|= BMCR_ANENABLE
| BMCR_ANRESTART
;
376 return phy_write(phydev
, MII_BMCR
, ret
);
380 ar8xxx_phy_init(struct ar8xxx_priv
*priv
)
386 for (i
= 0; i
< AR8XXX_NUM_PHYS
; i
++) {
387 if (priv
->chip
->phy_fixup
)
388 priv
->chip
->phy_fixup(priv
, i
);
390 /* initialize the port itself */
391 mdiobus_write(bus
, i
, MII_ADVERTISE
,
392 ADVERTISE_ALL
| ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
);
393 if (ar8xxx_has_gige(priv
))
394 mdiobus_write(bus
, i
, MII_CTRL1000
, ADVERTISE_1000FULL
);
395 mdiobus_write(bus
, i
, MII_BMCR
, BMCR_RESET
| BMCR_ANENABLE
);
398 ar8xxx_phy_poll_reset(bus
);
402 mii_read32(struct ar8xxx_priv
*priv
, int phy_id
, int regnum
)
404 struct mii_bus
*bus
= priv
->mii_bus
;
407 lo
= bus
->read(bus
, phy_id
, regnum
);
408 hi
= bus
->read(bus
, phy_id
, regnum
+ 1);
410 return (hi
<< 16) | lo
;
414 mii_write32(struct ar8xxx_priv
*priv
, int phy_id
, int regnum
, u32 val
)
416 struct mii_bus
*bus
= priv
->mii_bus
;
420 hi
= (u16
) (val
>> 16);
422 if (priv
->chip
->mii_lo_first
)
424 bus
->write(bus
, phy_id
, regnum
, lo
);
425 bus
->write(bus
, phy_id
, regnum
+ 1, hi
);
427 bus
->write(bus
, phy_id
, regnum
+ 1, hi
);
428 bus
->write(bus
, phy_id
, regnum
, lo
);
433 ar8xxx_mii_read(struct ar8xxx_priv
*priv
, int reg
)
435 struct mii_bus
*bus
= priv
->mii_bus
;
439 split_addr((u32
) reg
, &r1
, &r2
, &page
);
441 mutex_lock(&bus
->mdio_lock
);
443 bus
->write(bus
, 0x18, 0, page
);
444 usleep_range(1000, 2000); /* wait for the page switch to propagate */
445 val
= mii_read32(priv
, 0x10 | r2
, r1
);
447 mutex_unlock(&bus
->mdio_lock
);
453 ar8xxx_mii_write(struct ar8xxx_priv
*priv
, int reg
, u32 val
)
455 struct mii_bus
*bus
= priv
->mii_bus
;
458 split_addr((u32
) reg
, &r1
, &r2
, &page
);
460 mutex_lock(&bus
->mdio_lock
);
462 bus
->write(bus
, 0x18, 0, page
);
463 usleep_range(1000, 2000); /* wait for the page switch to propagate */
464 mii_write32(priv
, 0x10 | r2
, r1
, val
);
466 mutex_unlock(&bus
->mdio_lock
);
470 ar8xxx_mii_rmw(struct ar8xxx_priv
*priv
, int reg
, u32 mask
, u32 val
)
472 struct mii_bus
*bus
= priv
->mii_bus
;
476 split_addr((u32
) reg
, &r1
, &r2
, &page
);
478 mutex_lock(&bus
->mdio_lock
);
480 bus
->write(bus
, 0x18, 0, page
);
481 usleep_range(1000, 2000); /* wait for the page switch to propagate */
483 ret
= mii_read32(priv
, 0x10 | r2
, r1
);
486 mii_write32(priv
, 0x10 | r2
, r1
, ret
);
488 mutex_unlock(&bus
->mdio_lock
);
494 ar8xxx_phy_dbg_write(struct ar8xxx_priv
*priv
, int phy_addr
,
495 u16 dbg_addr
, u16 dbg_data
)
497 struct mii_bus
*bus
= priv
->mii_bus
;
499 mutex_lock(&bus
->mdio_lock
);
500 bus
->write(bus
, phy_addr
, MII_ATH_DBG_ADDR
, dbg_addr
);
501 bus
->write(bus
, phy_addr
, MII_ATH_DBG_DATA
, dbg_data
);
502 mutex_unlock(&bus
->mdio_lock
);
506 ar8xxx_phy_mmd_write(struct ar8xxx_priv
*priv
, int phy_addr
, u16 addr
, u16 data
)
508 struct mii_bus
*bus
= priv
->mii_bus
;
510 mutex_lock(&bus
->mdio_lock
);
511 bus
->write(bus
, phy_addr
, MII_ATH_MMD_ADDR
, addr
);
512 bus
->write(bus
, phy_addr
, MII_ATH_MMD_DATA
, data
);
513 mutex_unlock(&bus
->mdio_lock
);
517 ar8xxx_rmw(struct ar8xxx_priv
*priv
, int reg
, u32 mask
, u32 val
)
519 return priv
->rmw(priv
, reg
, mask
, val
);
523 ar8xxx_reg_set(struct ar8xxx_priv
*priv
, int reg
, u32 val
)
525 priv
->rmw(priv
, reg
, 0, val
);
529 ar8xxx_reg_wait(struct ar8xxx_priv
*priv
, u32 reg
, u32 mask
, u32 val
,
534 for (i
= 0; i
< timeout
; i
++) {
537 t
= priv
->read(priv
, reg
);
538 if ((t
& mask
) == val
)
541 usleep_range(1000, 2000);
548 ar8xxx_mib_op(struct ar8xxx_priv
*priv
, u32 op
)
550 unsigned mib_func
= priv
->chip
->mib_func
;
553 lockdep_assert_held(&priv
->mib_lock
);
555 /* Capture the hardware statistics for all ports */
556 ar8xxx_rmw(priv
, mib_func
, AR8216_MIB_FUNC
, (op
<< AR8216_MIB_FUNC_S
));
558 /* Wait for the capturing to complete. */
559 ret
= ar8xxx_reg_wait(priv
, mib_func
, AR8216_MIB_BUSY
, 0, 10);
570 ar8xxx_mib_capture(struct ar8xxx_priv
*priv
)
572 return ar8xxx_mib_op(priv
, AR8216_MIB_FUNC_CAPTURE
);
576 ar8xxx_mib_flush(struct ar8xxx_priv
*priv
)
578 return ar8xxx_mib_op(priv
, AR8216_MIB_FUNC_FLUSH
);
582 ar8xxx_mib_fetch_port_stat(struct ar8xxx_priv
*priv
, int port
, bool flush
)
588 WARN_ON(port
>= priv
->dev
.ports
);
590 lockdep_assert_held(&priv
->mib_lock
);
592 base
= priv
->chip
->reg_port_stats_start
+
593 priv
->chip
->reg_port_stats_length
* port
;
595 mib_stats
= &priv
->mib_stats
[port
* priv
->chip
->num_mibs
];
596 for (i
= 0; i
< priv
->chip
->num_mibs
; i
++) {
597 const struct ar8xxx_mib_desc
*mib
;
600 mib
= &priv
->chip
->mib_decs
[i
];
601 t
= priv
->read(priv
, base
+ mib
->offset
);
602 if (mib
->size
== 2) {
605 hi
= priv
->read(priv
, base
+ mib
->offset
+ 4);
617 ar8216_read_port_link(struct ar8xxx_priv
*priv
, int port
,
618 struct switch_port_link
*link
)
623 memset(link
, '\0', sizeof(*link
));
625 status
= priv
->chip
->read_port_status(priv
, port
);
627 link
->aneg
= !!(status
& AR8216_PORT_STATUS_LINK_AUTO
);
629 link
->link
= !!(status
& AR8216_PORT_STATUS_LINK_UP
);
633 if (priv
->get_port_link
) {
636 err
= priv
->get_port_link(port
);
645 link
->duplex
= !!(status
& AR8216_PORT_STATUS_DUPLEX
);
646 link
->tx_flow
= !!(status
& AR8216_PORT_STATUS_TXFLOW
);
647 link
->rx_flow
= !!(status
& AR8216_PORT_STATUS_RXFLOW
);
649 speed
= (status
& AR8216_PORT_STATUS_SPEED
) >>
650 AR8216_PORT_STATUS_SPEED_S
;
653 case AR8216_PORT_SPEED_10M
:
654 link
->speed
= SWITCH_PORT_SPEED_10
;
656 case AR8216_PORT_SPEED_100M
:
657 link
->speed
= SWITCH_PORT_SPEED_100
;
659 case AR8216_PORT_SPEED_1000M
:
660 link
->speed
= SWITCH_PORT_SPEED_1000
;
663 link
->speed
= SWITCH_PORT_SPEED_UNKNOWN
;
668 static struct sk_buff
*
669 ar8216_mangle_tx(struct net_device
*dev
, struct sk_buff
*skb
)
671 struct ar8xxx_priv
*priv
= dev
->phy_ptr
;
680 if (unlikely(skb_headroom(skb
) < 2)) {
681 if (pskb_expand_head(skb
, 2, 0, GFP_ATOMIC
) < 0)
685 buf
= skb_push(skb
, 2);
693 dev_kfree_skb_any(skb
);
698 ar8216_mangle_rx(struct net_device
*dev
, struct sk_buff
*skb
)
700 struct ar8xxx_priv
*priv
;
708 /* don't strip the header if vlan mode is disabled */
712 /* strip header, get vlan id */
716 /* check for vlan header presence */
717 if ((buf
[12 + 2] != 0x81) || (buf
[13 + 2] != 0x00))
722 /* no need to fix up packets coming from a tagged source */
723 if (priv
->vlan_tagged
& (1 << port
))
726 /* lookup port vid from local table, the switch passes an invalid vlan id */
727 vlan
= priv
->vlan_id
[priv
->pvid
[port
]];
730 buf
[14 + 2] |= vlan
>> 8;
731 buf
[15 + 2] = vlan
& 0xff;
735 ar8216_wait_bit(struct ar8xxx_priv
*priv
, int reg
, u32 mask
, u32 val
)
741 t
= priv
->read(priv
, reg
);
742 if ((t
& mask
) == val
)
751 pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
752 (unsigned int) reg
, t
, mask
, val
);
757 ar8216_vtu_op(struct ar8xxx_priv
*priv
, u32 op
, u32 val
)
759 if (ar8216_wait_bit(priv
, AR8216_REG_VTU
, AR8216_VTU_ACTIVE
, 0))
761 if ((op
& AR8216_VTU_OP
) == AR8216_VTU_OP_LOAD
) {
762 val
&= AR8216_VTUDATA_MEMBER
;
763 val
|= AR8216_VTUDATA_VALID
;
764 priv
->write(priv
, AR8216_REG_VTU_DATA
, val
);
766 op
|= AR8216_VTU_ACTIVE
;
767 priv
->write(priv
, AR8216_REG_VTU
, op
);
771 ar8216_vtu_flush(struct ar8xxx_priv
*priv
)
773 ar8216_vtu_op(priv
, AR8216_VTU_OP_FLUSH
, 0);
777 ar8216_vtu_load_vlan(struct ar8xxx_priv
*priv
, u32 vid
, u32 port_mask
)
781 op
= AR8216_VTU_OP_LOAD
| (vid
<< AR8216_VTU_VID_S
);
782 ar8216_vtu_op(priv
, op
, port_mask
);
786 ar8216_atu_flush(struct ar8xxx_priv
*priv
)
790 ret
= ar8216_wait_bit(priv
, AR8216_REG_ATU
, AR8216_ATU_ACTIVE
, 0);
792 priv
->write(priv
, AR8216_REG_ATU
, AR8216_ATU_OP_FLUSH
);
798 ar8216_read_port_status(struct ar8xxx_priv
*priv
, int port
)
800 return priv
->read(priv
, AR8216_REG_PORT_STATUS(port
));
804 ar8216_setup_port(struct ar8xxx_priv
*priv
, int port
, u32 members
)
811 pvid
= priv
->vlan_id
[priv
->pvid
[port
]];
812 if (priv
->vlan_tagged
& (1 << port
))
813 egress
= AR8216_OUT_ADD_VLAN
;
815 egress
= AR8216_OUT_STRIP_VLAN
;
816 ingress
= AR8216_IN_SECURE
;
819 egress
= AR8216_OUT_KEEP
;
820 ingress
= AR8216_IN_PORT_ONLY
;
823 if (chip_is_ar8216(priv
) && priv
->vlan
&& port
== AR8216_PORT_CPU
)
824 header
= AR8216_PORT_CTRL_HEADER
;
828 ar8xxx_rmw(priv
, AR8216_REG_PORT_CTRL(port
),
829 AR8216_PORT_CTRL_LEARN
| AR8216_PORT_CTRL_VLAN_MODE
|
830 AR8216_PORT_CTRL_SINGLE_VLAN
| AR8216_PORT_CTRL_STATE
|
831 AR8216_PORT_CTRL_HEADER
| AR8216_PORT_CTRL_LEARN_LOCK
,
832 AR8216_PORT_CTRL_LEARN
| header
|
833 (egress
<< AR8216_PORT_CTRL_VLAN_MODE_S
) |
834 (AR8216_PORT_STATE_FORWARD
<< AR8216_PORT_CTRL_STATE_S
));
836 ar8xxx_rmw(priv
, AR8216_REG_PORT_VLAN(port
),
837 AR8216_PORT_VLAN_DEST_PORTS
| AR8216_PORT_VLAN_MODE
|
838 AR8216_PORT_VLAN_DEFAULT_ID
,
839 (members
<< AR8216_PORT_VLAN_DEST_PORTS_S
) |
840 (ingress
<< AR8216_PORT_VLAN_MODE_S
) |
841 (pvid
<< AR8216_PORT_VLAN_DEFAULT_ID_S
));
845 ar8216_hw_init(struct ar8xxx_priv
*priv
)
847 if (priv
->initialized
)
850 ar8xxx_phy_init(priv
);
852 priv
->initialized
= true;
857 ar8216_init_globals(struct ar8xxx_priv
*priv
)
859 /* standard atheros magic */
860 priv
->write(priv
, 0x38, 0xc000050e);
862 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
863 AR8216_GCTRL_MTU
, 1518 + 8 + 2);
867 ar8216_init_port(struct ar8xxx_priv
*priv
, int port
)
869 /* Enable port learning and tx */
870 priv
->write(priv
, AR8216_REG_PORT_CTRL(port
),
871 AR8216_PORT_CTRL_LEARN
|
872 (4 << AR8216_PORT_CTRL_STATE_S
));
874 priv
->write(priv
, AR8216_REG_PORT_VLAN(port
), 0);
876 if (port
== AR8216_PORT_CPU
) {
877 priv
->write(priv
, AR8216_REG_PORT_STATUS(port
),
878 AR8216_PORT_STATUS_LINK_UP
|
879 (ar8xxx_has_gige(priv
) ?
880 AR8216_PORT_SPEED_1000M
: AR8216_PORT_SPEED_100M
) |
881 AR8216_PORT_STATUS_TXMAC
|
882 AR8216_PORT_STATUS_RXMAC
|
883 (chip_is_ar8316(priv
) ? AR8216_PORT_STATUS_RXFLOW
: 0) |
884 (chip_is_ar8316(priv
) ? AR8216_PORT_STATUS_TXFLOW
: 0) |
885 AR8216_PORT_STATUS_DUPLEX
);
887 priv
->write(priv
, AR8216_REG_PORT_STATUS(port
),
888 AR8216_PORT_STATUS_LINK_AUTO
);
893 ar8236_setup_port(struct ar8xxx_priv
*priv
, int port
, u32 members
)
899 pvid
= priv
->vlan_id
[priv
->pvid
[port
]];
900 if (priv
->vlan_tagged
& (1 << port
))
901 egress
= AR8216_OUT_ADD_VLAN
;
903 egress
= AR8216_OUT_STRIP_VLAN
;
904 ingress
= AR8216_IN_SECURE
;
907 egress
= AR8216_OUT_KEEP
;
908 ingress
= AR8216_IN_PORT_ONLY
;
911 ar8xxx_rmw(priv
, AR8216_REG_PORT_CTRL(port
),
912 AR8216_PORT_CTRL_LEARN
| AR8216_PORT_CTRL_VLAN_MODE
|
913 AR8216_PORT_CTRL_SINGLE_VLAN
| AR8216_PORT_CTRL_STATE
|
914 AR8216_PORT_CTRL_HEADER
| AR8216_PORT_CTRL_LEARN_LOCK
,
915 AR8216_PORT_CTRL_LEARN
|
916 (egress
<< AR8216_PORT_CTRL_VLAN_MODE_S
) |
917 (AR8216_PORT_STATE_FORWARD
<< AR8216_PORT_CTRL_STATE_S
));
919 ar8xxx_rmw(priv
, AR8236_REG_PORT_VLAN(port
),
920 AR8236_PORT_VLAN_DEFAULT_ID
,
921 (pvid
<< AR8236_PORT_VLAN_DEFAULT_ID_S
));
923 ar8xxx_rmw(priv
, AR8236_REG_PORT_VLAN2(port
),
924 AR8236_PORT_VLAN2_VLAN_MODE
|
925 AR8236_PORT_VLAN2_MEMBER
,
926 (ingress
<< AR8236_PORT_VLAN2_VLAN_MODE_S
) |
927 (members
<< AR8236_PORT_VLAN2_MEMBER_S
));
931 ar8236_init_globals(struct ar8xxx_priv
*priv
)
933 /* enable jumbo frames */
934 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
935 AR8316_GCTRL_MTU
, 9018 + 8 + 2);
937 /* enable cpu port to receive arp frames */
938 ar8xxx_rmw(priv
, AR8216_REG_ATU_CTRL
,
939 AR8236_ATU_CTRL_RES
, AR8236_ATU_CTRL_RES
);
941 /* enable cpu port to receive multicast and broadcast frames */
942 ar8xxx_rmw(priv
, AR8216_REG_FLOOD_MASK
,
943 AR8236_FM_CPU_BROADCAST_EN
| AR8236_FM_CPU_BCAST_FWD_EN
,
944 AR8236_FM_CPU_BROADCAST_EN
| AR8236_FM_CPU_BCAST_FWD_EN
);
946 /* Enable MIB counters */
947 ar8xxx_rmw(priv
, AR8216_REG_MIB_FUNC
, AR8216_MIB_FUNC
| AR8236_MIB_EN
,
948 (AR8216_MIB_FUNC_NO_OP
<< AR8216_MIB_FUNC_S
) |
953 ar8316_hw_init(struct ar8xxx_priv
*priv
)
957 val
= priv
->read(priv
, AR8316_REG_POSTRIP
);
959 if (priv
->phy
->interface
== PHY_INTERFACE_MODE_RGMII
) {
960 if (priv
->port4_phy
) {
961 /* value taken from Ubiquiti RouterStation Pro */
963 pr_info("ar8316: Using port 4 as PHY\n");
966 pr_info("ar8316: Using port 4 as switch port\n");
968 } else if (priv
->phy
->interface
== PHY_INTERFACE_MODE_GMII
) {
969 /* value taken from AVM Fritz!Box 7390 sources */
972 /* no known value for phy interface */
973 pr_err("ar8316: unsupported mii mode: %d.\n",
974 priv
->phy
->interface
);
981 priv
->write(priv
, AR8316_REG_POSTRIP
, newval
);
983 if (priv
->port4_phy
&&
984 priv
->phy
->interface
== PHY_INTERFACE_MODE_RGMII
) {
985 /* work around for phy4 rgmii mode */
986 ar8xxx_phy_dbg_write(priv
, 4, 0x12, 0x480c);
988 ar8xxx_phy_dbg_write(priv
, 4, 0x0, 0x824e);
990 ar8xxx_phy_dbg_write(priv
, 4, 0x5, 0x3d47);
994 ar8xxx_phy_init(priv
);
997 priv
->initialized
= true;
1002 ar8316_init_globals(struct ar8xxx_priv
*priv
)
1004 /* standard atheros magic */
1005 priv
->write(priv
, 0x38, 0xc000050e);
1007 /* enable cpu port to receive multicast and broadcast frames */
1008 priv
->write(priv
, AR8216_REG_FLOOD_MASK
, 0x003f003f);
1010 /* enable jumbo frames */
1011 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
1012 AR8316_GCTRL_MTU
, 9018 + 8 + 2);
1014 /* Enable MIB counters */
1015 ar8xxx_rmw(priv
, AR8216_REG_MIB_FUNC
, AR8216_MIB_FUNC
| AR8236_MIB_EN
,
1016 (AR8216_MIB_FUNC_NO_OP
<< AR8216_MIB_FUNC_S
) |
1021 ar8327_get_pad_cfg(struct ar8327_pad_cfg
*cfg
)
1029 switch (cfg
->mode
) {
1033 case AR8327_PAD_MAC2MAC_MII
:
1034 t
= AR8327_PAD_MAC_MII_EN
;
1036 t
|= AR8327_PAD_MAC_MII_RXCLK_SEL
;
1038 t
|= AR8327_PAD_MAC_MII_TXCLK_SEL
;
1041 case AR8327_PAD_MAC2MAC_GMII
:
1042 t
= AR8327_PAD_MAC_GMII_EN
;
1044 t
|= AR8327_PAD_MAC_GMII_RXCLK_SEL
;
1046 t
|= AR8327_PAD_MAC_GMII_TXCLK_SEL
;
1049 case AR8327_PAD_MAC_SGMII
:
1050 t
= AR8327_PAD_SGMII_EN
;
1053 * WAR for the QUalcomm Atheros AP136 board.
1054 * It seems that RGMII TX/RX delay settings needs to be
1055 * applied for SGMII mode as well, The ethernet is not
1056 * reliable without this.
1058 t
|= cfg
->txclk_delay_sel
<< AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S
;
1059 t
|= cfg
->rxclk_delay_sel
<< AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S
;
1060 if (cfg
->rxclk_delay_en
)
1061 t
|= AR8327_PAD_RGMII_RXCLK_DELAY_EN
;
1062 if (cfg
->txclk_delay_en
)
1063 t
|= AR8327_PAD_RGMII_TXCLK_DELAY_EN
;
1065 if (cfg
->sgmii_delay_en
)
1066 t
|= AR8327_PAD_SGMII_DELAY_EN
;
1070 case AR8327_PAD_MAC2PHY_MII
:
1071 t
= AR8327_PAD_PHY_MII_EN
;
1073 t
|= AR8327_PAD_PHY_MII_RXCLK_SEL
;
1075 t
|= AR8327_PAD_PHY_MII_TXCLK_SEL
;
1078 case AR8327_PAD_MAC2PHY_GMII
:
1079 t
= AR8327_PAD_PHY_GMII_EN
;
1080 if (cfg
->pipe_rxclk_sel
)
1081 t
|= AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL
;
1083 t
|= AR8327_PAD_PHY_GMII_RXCLK_SEL
;
1085 t
|= AR8327_PAD_PHY_GMII_TXCLK_SEL
;
1088 case AR8327_PAD_MAC_RGMII
:
1089 t
= AR8327_PAD_RGMII_EN
;
1090 t
|= cfg
->txclk_delay_sel
<< AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S
;
1091 t
|= cfg
->rxclk_delay_sel
<< AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S
;
1092 if (cfg
->rxclk_delay_en
)
1093 t
|= AR8327_PAD_RGMII_RXCLK_DELAY_EN
;
1094 if (cfg
->txclk_delay_en
)
1095 t
|= AR8327_PAD_RGMII_TXCLK_DELAY_EN
;
1098 case AR8327_PAD_PHY_GMII
:
1099 t
= AR8327_PAD_PHYX_GMII_EN
;
1102 case AR8327_PAD_PHY_RGMII
:
1103 t
= AR8327_PAD_PHYX_RGMII_EN
;
1106 case AR8327_PAD_PHY_MII
:
1107 t
= AR8327_PAD_PHYX_MII_EN
;
1115 ar8327_phy_fixup(struct ar8xxx_priv
*priv
, int phy
)
1117 switch (priv
->chip_rev
) {
1119 /* For 100M waveform */
1120 ar8xxx_phy_dbg_write(priv
, phy
, 0, 0x02ea);
1121 /* Turn on Gigabit clock */
1122 ar8xxx_phy_dbg_write(priv
, phy
, 0x3d, 0x68a0);
1126 ar8xxx_phy_mmd_write(priv
, phy
, 0x7, 0x3c);
1127 ar8xxx_phy_mmd_write(priv
, phy
, 0x4007, 0x0);
1130 ar8xxx_phy_mmd_write(priv
, phy
, 0x3, 0x800d);
1131 ar8xxx_phy_mmd_write(priv
, phy
, 0x4003, 0x803f);
1133 ar8xxx_phy_dbg_write(priv
, phy
, 0x3d, 0x6860);
1134 ar8xxx_phy_dbg_write(priv
, phy
, 0x5, 0x2c46);
1135 ar8xxx_phy_dbg_write(priv
, phy
, 0x3c, 0x6000);
1141 ar8327_get_port_init_status(struct ar8327_port_cfg
*cfg
)
1145 if (!cfg
->force_link
)
1146 return AR8216_PORT_STATUS_LINK_AUTO
;
1148 t
= AR8216_PORT_STATUS_TXMAC
| AR8216_PORT_STATUS_RXMAC
;
1149 t
|= cfg
->duplex
? AR8216_PORT_STATUS_DUPLEX
: 0;
1150 t
|= cfg
->rxpause
? AR8216_PORT_STATUS_RXFLOW
: 0;
1151 t
|= cfg
->txpause
? AR8216_PORT_STATUS_TXFLOW
: 0;
1153 switch (cfg
->speed
) {
1154 case AR8327_PORT_SPEED_10
:
1155 t
|= AR8216_PORT_SPEED_10M
;
1157 case AR8327_PORT_SPEED_100
:
1158 t
|= AR8216_PORT_SPEED_100M
;
1160 case AR8327_PORT_SPEED_1000
:
1161 t
|= AR8216_PORT_SPEED_1000M
;
1168 #define AR8327_LED_ENTRY(_num, _reg, _shift) \
1169 [_num] = { .reg = (_reg), .shift = (_shift) }
1171 static const struct ar8327_led_entry
1172 ar8327_led_map
[AR8327_NUM_LEDS
] = {
1173 AR8327_LED_ENTRY(AR8327_LED_PHY0_0
, 0, 14),
1174 AR8327_LED_ENTRY(AR8327_LED_PHY0_1
, 1, 14),
1175 AR8327_LED_ENTRY(AR8327_LED_PHY0_2
, 2, 14),
1177 AR8327_LED_ENTRY(AR8327_LED_PHY1_0
, 3, 8),
1178 AR8327_LED_ENTRY(AR8327_LED_PHY1_1
, 3, 10),
1179 AR8327_LED_ENTRY(AR8327_LED_PHY1_2
, 3, 12),
1181 AR8327_LED_ENTRY(AR8327_LED_PHY2_0
, 3, 14),
1182 AR8327_LED_ENTRY(AR8327_LED_PHY2_1
, 3, 16),
1183 AR8327_LED_ENTRY(AR8327_LED_PHY2_2
, 3, 18),
1185 AR8327_LED_ENTRY(AR8327_LED_PHY3_0
, 3, 20),
1186 AR8327_LED_ENTRY(AR8327_LED_PHY3_1
, 3, 22),
1187 AR8327_LED_ENTRY(AR8327_LED_PHY3_2
, 3, 24),
1189 AR8327_LED_ENTRY(AR8327_LED_PHY4_0
, 0, 30),
1190 AR8327_LED_ENTRY(AR8327_LED_PHY4_1
, 1, 30),
1191 AR8327_LED_ENTRY(AR8327_LED_PHY4_2
, 2, 30),
1195 ar8327_set_led_pattern(struct ar8xxx_priv
*priv
, unsigned int led_num
,
1196 enum ar8327_led_pattern pattern
)
1198 const struct ar8327_led_entry
*entry
;
1200 entry
= &ar8327_led_map
[led_num
];
1201 ar8xxx_rmw(priv
, AR8327_REG_LED_CTRL(entry
->reg
),
1202 (3 << entry
->shift
), pattern
<< entry
->shift
);
1206 ar8327_led_work_func(struct work_struct
*work
)
1208 struct ar8327_led
*aled
;
1211 aled
= container_of(work
, struct ar8327_led
, led_work
);
1213 spin_lock(&aled
->lock
);
1214 pattern
= aled
->pattern
;
1215 spin_unlock(&aled
->lock
);
1217 ar8327_set_led_pattern(aled
->sw_priv
, aled
->led_num
,
1222 ar8327_led_schedule_change(struct ar8327_led
*aled
, u8 pattern
)
1224 if (aled
->pattern
== pattern
)
1227 aled
->pattern
= pattern
;
1228 schedule_work(&aled
->led_work
);
1231 static inline struct ar8327_led
*
1232 led_cdev_to_ar8327_led(struct led_classdev
*led_cdev
)
1234 return container_of(led_cdev
, struct ar8327_led
, cdev
);
1238 ar8327_led_blink_set(struct led_classdev
*led_cdev
,
1239 unsigned long *delay_on
,
1240 unsigned long *delay_off
)
1242 struct ar8327_led
*aled
= led_cdev_to_ar8327_led(led_cdev
);
1244 if (*delay_on
== 0 && *delay_off
== 0) {
1249 if (*delay_on
!= 125 || *delay_off
!= 125) {
1251 * The hardware only supports blinking at 4Hz. Fall back
1252 * to software implementation in other cases.
1257 spin_lock(&aled
->lock
);
1259 aled
->enable_hw_mode
= false;
1260 ar8327_led_schedule_change(aled
, AR8327_LED_PATTERN_BLINK
);
1262 spin_unlock(&aled
->lock
);
1268 ar8327_led_set_brightness(struct led_classdev
*led_cdev
,
1269 enum led_brightness brightness
)
1271 struct ar8327_led
*aled
= led_cdev_to_ar8327_led(led_cdev
);
1275 active
= (brightness
!= LED_OFF
);
1276 active
^= aled
->active_low
;
1278 pattern
= (active
) ? AR8327_LED_PATTERN_ON
:
1279 AR8327_LED_PATTERN_OFF
;
1281 spin_lock(&aled
->lock
);
1283 aled
->enable_hw_mode
= false;
1284 ar8327_led_schedule_change(aled
, pattern
);
1286 spin_unlock(&aled
->lock
);
1290 ar8327_led_enable_hw_mode_show(struct device
*dev
,
1291 struct device_attribute
*attr
,
1294 struct led_classdev
*led_cdev
= dev_get_drvdata(dev
);
1295 struct ar8327_led
*aled
= led_cdev_to_ar8327_led(led_cdev
);
1298 spin_lock(&aled
->lock
);
1299 ret
+= sprintf(buf
, "%d\n", aled
->enable_hw_mode
);
1300 spin_unlock(&aled
->lock
);
1306 ar8327_led_enable_hw_mode_store(struct device
*dev
,
1307 struct device_attribute
*attr
,
1311 struct led_classdev
*led_cdev
= dev_get_drvdata(dev
);
1312 struct ar8327_led
*aled
= led_cdev_to_ar8327_led(led_cdev
);
1317 ret
= kstrtou8(buf
, 10, &value
);
1321 spin_lock(&aled
->lock
);
1323 aled
->enable_hw_mode
= !!value
;
1324 if (aled
->enable_hw_mode
)
1325 pattern
= AR8327_LED_PATTERN_RULE
;
1327 pattern
= AR8327_LED_PATTERN_OFF
;
1329 ar8327_led_schedule_change(aled
, pattern
);
1331 spin_unlock(&aled
->lock
);
1336 static DEVICE_ATTR(enable_hw_mode
, S_IRUGO
| S_IWUSR
,
1337 ar8327_led_enable_hw_mode_show
,
1338 ar8327_led_enable_hw_mode_store
);
1341 ar8327_led_register(struct ar8327_led
*aled
)
1345 ret
= led_classdev_register(NULL
, &aled
->cdev
);
1349 if (aled
->mode
== AR8327_LED_MODE_HW
) {
1350 ret
= device_create_file(aled
->cdev
.dev
,
1351 &dev_attr_enable_hw_mode
);
1353 goto err_unregister
;
1359 led_classdev_unregister(&aled
->cdev
);
1364 ar8327_led_unregister(struct ar8327_led
*aled
)
1366 if (aled
->mode
== AR8327_LED_MODE_HW
)
1367 device_remove_file(aled
->cdev
.dev
, &dev_attr_enable_hw_mode
);
1369 led_classdev_unregister(&aled
->cdev
);
1370 cancel_work_sync(&aled
->led_work
);
1374 ar8327_led_create(struct ar8xxx_priv
*priv
,
1375 const struct ar8327_led_info
*led_info
)
1377 struct ar8327_data
*data
= priv
->chip_data
;
1378 struct ar8327_led
*aled
;
1381 if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS
))
1384 if (!led_info
->name
)
1387 if (led_info
->led_num
>= AR8327_NUM_LEDS
)
1390 aled
= kzalloc(sizeof(*aled
) + strlen(led_info
->name
) + 1,
1395 aled
->sw_priv
= priv
;
1396 aled
->led_num
= led_info
->led_num
;
1397 aled
->active_low
= led_info
->active_low
;
1398 aled
->mode
= led_info
->mode
;
1400 if (aled
->mode
== AR8327_LED_MODE_HW
)
1401 aled
->enable_hw_mode
= true;
1403 aled
->name
= (char *)(aled
+ 1);
1404 strcpy(aled
->name
, led_info
->name
);
1406 aled
->cdev
.name
= aled
->name
;
1407 aled
->cdev
.brightness_set
= ar8327_led_set_brightness
;
1408 aled
->cdev
.blink_set
= ar8327_led_blink_set
;
1409 aled
->cdev
.default_trigger
= led_info
->default_trigger
;
1411 spin_lock_init(&aled
->lock
);
1412 mutex_init(&aled
->mutex
);
1413 INIT_WORK(&aled
->led_work
, ar8327_led_work_func
);
1415 ret
= ar8327_led_register(aled
);
1419 data
->leds
[data
->num_leds
++] = aled
;
1429 ar8327_led_destroy(struct ar8327_led
*aled
)
1431 ar8327_led_unregister(aled
);
1436 ar8327_leds_init(struct ar8xxx_priv
*priv
)
1438 struct ar8327_data
*data
= priv
->chip_data
;
1441 if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS
))
1444 for (i
= 0; i
< data
->num_leds
; i
++) {
1445 struct ar8327_led
*aled
;
1447 aled
= data
->leds
[i
];
1449 if (aled
->enable_hw_mode
)
1450 aled
->pattern
= AR8327_LED_PATTERN_RULE
;
1452 aled
->pattern
= AR8327_LED_PATTERN_OFF
;
1454 ar8327_set_led_pattern(priv
, aled
->led_num
, aled
->pattern
);
1459 ar8327_leds_cleanup(struct ar8xxx_priv
*priv
)
1461 struct ar8327_data
*data
= priv
->chip_data
;
1464 if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS
))
1467 for (i
= 0; i
< data
->num_leds
; i
++) {
1468 struct ar8327_led
*aled
;
1470 aled
= data
->leds
[i
];
1471 ar8327_led_destroy(aled
);
1478 ar8327_hw_config_pdata(struct ar8xxx_priv
*priv
,
1479 struct ar8327_platform_data
*pdata
)
1481 struct ar8327_led_cfg
*led_cfg
;
1482 struct ar8327_data
*data
= priv
->chip_data
;
1489 priv
->get_port_link
= pdata
->get_port_link
;
1491 data
->port0_status
= ar8327_get_port_init_status(&pdata
->port0_cfg
);
1492 data
->port6_status
= ar8327_get_port_init_status(&pdata
->port6_cfg
);
1494 t
= ar8327_get_pad_cfg(pdata
->pad0_cfg
);
1495 if (chip_is_ar8337(priv
))
1496 t
|= AR8337_PAD_MAC06_EXCHANGE_EN
;
1498 priv
->write(priv
, AR8327_REG_PAD0_MODE
, t
);
1499 t
= ar8327_get_pad_cfg(pdata
->pad5_cfg
);
1500 priv
->write(priv
, AR8327_REG_PAD5_MODE
, t
);
1501 t
= ar8327_get_pad_cfg(pdata
->pad6_cfg
);
1502 priv
->write(priv
, AR8327_REG_PAD6_MODE
, t
);
1504 pos
= priv
->read(priv
, AR8327_REG_POWER_ON_STRIP
);
1507 led_cfg
= pdata
->led_cfg
;
1509 if (led_cfg
->open_drain
)
1510 new_pos
|= AR8327_POWER_ON_STRIP_LED_OPEN_EN
;
1512 new_pos
&= ~AR8327_POWER_ON_STRIP_LED_OPEN_EN
;
1514 priv
->write(priv
, AR8327_REG_LED_CTRL0
, led_cfg
->led_ctrl0
);
1515 priv
->write(priv
, AR8327_REG_LED_CTRL1
, led_cfg
->led_ctrl1
);
1516 priv
->write(priv
, AR8327_REG_LED_CTRL2
, led_cfg
->led_ctrl2
);
1517 priv
->write(priv
, AR8327_REG_LED_CTRL3
, led_cfg
->led_ctrl3
);
1520 new_pos
|= AR8327_POWER_ON_STRIP_POWER_ON_SEL
;
1523 if (pdata
->sgmii_cfg
) {
1524 t
= pdata
->sgmii_cfg
->sgmii_ctrl
;
1525 if (priv
->chip_rev
== 1)
1526 t
|= AR8327_SGMII_CTRL_EN_PLL
|
1527 AR8327_SGMII_CTRL_EN_RX
|
1528 AR8327_SGMII_CTRL_EN_TX
;
1530 t
&= ~(AR8327_SGMII_CTRL_EN_PLL
|
1531 AR8327_SGMII_CTRL_EN_RX
|
1532 AR8327_SGMII_CTRL_EN_TX
);
1534 priv
->write(priv
, AR8327_REG_SGMII_CTRL
, t
);
1536 if (pdata
->sgmii_cfg
->serdes_aen
)
1537 new_pos
&= ~AR8327_POWER_ON_STRIP_SERDES_AEN
;
1539 new_pos
|= AR8327_POWER_ON_STRIP_SERDES_AEN
;
1542 priv
->write(priv
, AR8327_REG_POWER_ON_STRIP
, new_pos
);
1544 if (pdata
->leds
&& pdata
->num_leds
) {
1547 data
->leds
= kzalloc(pdata
->num_leds
* sizeof(void *),
1552 for (i
= 0; i
< pdata
->num_leds
; i
++)
1553 ar8327_led_create(priv
, &pdata
->leds
[i
]);
1561 ar8327_hw_config_of(struct ar8xxx_priv
*priv
, struct device_node
*np
)
1563 struct ar8327_data
*data
= priv
->chip_data
;
1564 const __be32
*paddr
;
1568 paddr
= of_get_property(np
, "qca,ar8327-initvals", &len
);
1569 if (!paddr
|| len
< (2 * sizeof(*paddr
)))
1572 len
/= sizeof(*paddr
);
1574 for (i
= 0; i
< len
- 1; i
+= 2) {
1578 reg
= be32_to_cpup(paddr
+ i
);
1579 val
= be32_to_cpup(paddr
+ i
+ 1);
1582 case AR8327_REG_PORT_STATUS(0):
1583 data
->port0_status
= val
;
1585 case AR8327_REG_PORT_STATUS(6):
1586 data
->port6_status
= val
;
1589 priv
->write(priv
, reg
, val
);
1598 ar8327_hw_config_of(struct ar8xxx_priv
*priv
, struct device_node
*np
)
1605 ar8327_hw_init(struct ar8xxx_priv
*priv
)
1609 priv
->chip_data
= kzalloc(sizeof(struct ar8327_data
), GFP_KERNEL
);
1610 if (!priv
->chip_data
)
1613 if (priv
->phy
->dev
.of_node
)
1614 ret
= ar8327_hw_config_of(priv
, priv
->phy
->dev
.of_node
);
1616 ret
= ar8327_hw_config_pdata(priv
,
1617 priv
->phy
->dev
.platform_data
);
1622 ar8327_leds_init(priv
);
1624 ar8xxx_phy_init(priv
);
1630 ar8327_cleanup(struct ar8xxx_priv
*priv
)
1632 ar8327_leds_cleanup(priv
);
1636 ar8327_init_globals(struct ar8xxx_priv
*priv
)
1640 /* enable CPU port and disable mirror port */
1641 t
= AR8327_FWD_CTRL0_CPU_PORT_EN
|
1642 AR8327_FWD_CTRL0_MIRROR_PORT
;
1643 priv
->write(priv
, AR8327_REG_FWD_CTRL0
, t
);
1645 /* forward multicast and broadcast frames to CPU */
1646 t
= (AR8327_PORTS_ALL
<< AR8327_FWD_CTRL1_UC_FLOOD_S
) |
1647 (AR8327_PORTS_ALL
<< AR8327_FWD_CTRL1_MC_FLOOD_S
) |
1648 (AR8327_PORTS_ALL
<< AR8327_FWD_CTRL1_BC_FLOOD_S
);
1649 priv
->write(priv
, AR8327_REG_FWD_CTRL1
, t
);
1651 /* enable jumbo frames */
1652 ar8xxx_rmw(priv
, AR8327_REG_MAX_FRAME_SIZE
,
1653 AR8327_MAX_FRAME_SIZE_MTU
, 9018 + 8 + 2);
1655 /* Enable MIB counters */
1656 ar8xxx_reg_set(priv
, AR8327_REG_MODULE_EN
,
1657 AR8327_MODULE_EN_MIB
);
1659 /* Disable EEE on all ports due to stability issues */
1660 t
= priv
->read(priv
, AR8327_REG_EEE_CTRL
);
1661 t
|= AR8327_EEE_CTRL_DISABLE_PHY(0) |
1662 AR8327_EEE_CTRL_DISABLE_PHY(1) |
1663 AR8327_EEE_CTRL_DISABLE_PHY(2) |
1664 AR8327_EEE_CTRL_DISABLE_PHY(3) |
1665 AR8327_EEE_CTRL_DISABLE_PHY(4);
1666 priv
->write(priv
, AR8327_REG_EEE_CTRL
, t
);
1670 ar8327_init_port(struct ar8xxx_priv
*priv
, int port
)
1672 struct ar8327_data
*data
= priv
->chip_data
;
1675 if (port
== AR8216_PORT_CPU
)
1676 t
= data
->port0_status
;
1678 t
= data
->port6_status
;
1680 t
= AR8216_PORT_STATUS_LINK_AUTO
;
1682 priv
->write(priv
, AR8327_REG_PORT_STATUS(port
), t
);
1683 priv
->write(priv
, AR8327_REG_PORT_HEADER(port
), 0);
1685 t
= 1 << AR8327_PORT_VLAN0_DEF_SVID_S
;
1686 t
|= 1 << AR8327_PORT_VLAN0_DEF_CVID_S
;
1687 priv
->write(priv
, AR8327_REG_PORT_VLAN0(port
), t
);
1689 t
= AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH
<< AR8327_PORT_VLAN1_OUT_MODE_S
;
1690 priv
->write(priv
, AR8327_REG_PORT_VLAN1(port
), t
);
1692 t
= AR8327_PORT_LOOKUP_LEARN
;
1693 t
|= AR8216_PORT_STATE_FORWARD
<< AR8327_PORT_LOOKUP_STATE_S
;
1694 priv
->write(priv
, AR8327_REG_PORT_LOOKUP(port
), t
);
1698 ar8327_read_port_status(struct ar8xxx_priv
*priv
, int port
)
1700 return priv
->read(priv
, AR8327_REG_PORT_STATUS(port
));
1704 ar8327_atu_flush(struct ar8xxx_priv
*priv
)
1708 ret
= ar8216_wait_bit(priv
, AR8327_REG_ATU_FUNC
,
1709 AR8327_ATU_FUNC_BUSY
, 0);
1711 priv
->write(priv
, AR8327_REG_ATU_FUNC
,
1712 AR8327_ATU_FUNC_OP_FLUSH
);
1718 ar8327_vtu_op(struct ar8xxx_priv
*priv
, u32 op
, u32 val
)
1720 if (ar8216_wait_bit(priv
, AR8327_REG_VTU_FUNC1
,
1721 AR8327_VTU_FUNC1_BUSY
, 0))
1724 if ((op
& AR8327_VTU_FUNC1_OP
) == AR8327_VTU_FUNC1_OP_LOAD
)
1725 priv
->write(priv
, AR8327_REG_VTU_FUNC0
, val
);
1727 op
|= AR8327_VTU_FUNC1_BUSY
;
1728 priv
->write(priv
, AR8327_REG_VTU_FUNC1
, op
);
1732 ar8327_vtu_flush(struct ar8xxx_priv
*priv
)
1734 ar8327_vtu_op(priv
, AR8327_VTU_FUNC1_OP_FLUSH
, 0);
1738 ar8327_vtu_load_vlan(struct ar8xxx_priv
*priv
, u32 vid
, u32 port_mask
)
1744 op
= AR8327_VTU_FUNC1_OP_LOAD
| (vid
<< AR8327_VTU_FUNC1_VID_S
);
1745 val
= AR8327_VTU_FUNC0_VALID
| AR8327_VTU_FUNC0_IVL
;
1746 for (i
= 0; i
< AR8327_NUM_PORTS
; i
++) {
1749 if ((port_mask
& BIT(i
)) == 0)
1750 mode
= AR8327_VTU_FUNC0_EG_MODE_NOT
;
1751 else if (priv
->vlan
== 0)
1752 mode
= AR8327_VTU_FUNC0_EG_MODE_KEEP
;
1753 else if ((priv
->vlan_tagged
& BIT(i
)) || (priv
->vlan_id
[priv
->pvid
[i
]] != vid
))
1754 mode
= AR8327_VTU_FUNC0_EG_MODE_TAG
;
1756 mode
= AR8327_VTU_FUNC0_EG_MODE_UNTAG
;
1758 val
|= mode
<< AR8327_VTU_FUNC0_EG_MODE_S(i
);
1760 ar8327_vtu_op(priv
, op
, val
);
1764 ar8327_setup_port(struct ar8xxx_priv
*priv
, int port
, u32 members
)
1767 u32 egress
, ingress
;
1768 u32 pvid
= priv
->vlan_id
[priv
->pvid
[port
]];
1771 egress
= AR8327_PORT_VLAN1_OUT_MODE_UNMOD
;
1772 ingress
= AR8216_IN_SECURE
;
1774 egress
= AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH
;
1775 ingress
= AR8216_IN_PORT_ONLY
;
1778 t
= pvid
<< AR8327_PORT_VLAN0_DEF_SVID_S
;
1779 t
|= pvid
<< AR8327_PORT_VLAN0_DEF_CVID_S
;
1780 priv
->write(priv
, AR8327_REG_PORT_VLAN0(port
), t
);
1782 t
= AR8327_PORT_VLAN1_PORT_VLAN_PROP
;
1783 t
|= egress
<< AR8327_PORT_VLAN1_OUT_MODE_S
;
1784 priv
->write(priv
, AR8327_REG_PORT_VLAN1(port
), t
);
1787 t
|= AR8327_PORT_LOOKUP_LEARN
;
1788 t
|= ingress
<< AR8327_PORT_LOOKUP_IN_MODE_S
;
1789 t
|= AR8216_PORT_STATE_FORWARD
<< AR8327_PORT_LOOKUP_STATE_S
;
1790 priv
->write(priv
, AR8327_REG_PORT_LOOKUP(port
), t
);
1794 ar8xxx_sw_set_vlan(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1795 struct switch_val
*val
)
1797 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1798 priv
->vlan
= !!val
->value
.i
;
1803 ar8xxx_sw_get_vlan(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1804 struct switch_val
*val
)
1806 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1807 val
->value
.i
= priv
->vlan
;
1813 ar8xxx_sw_set_pvid(struct switch_dev
*dev
, int port
, int vlan
)
1815 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1817 /* make sure no invalid PVIDs get set */
1819 if (vlan
>= dev
->vlans
)
1822 priv
->pvid
[port
] = vlan
;
1827 ar8xxx_sw_get_pvid(struct switch_dev
*dev
, int port
, int *vlan
)
1829 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1830 *vlan
= priv
->pvid
[port
];
1835 ar8xxx_sw_set_vid(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1836 struct switch_val
*val
)
1838 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1839 priv
->vlan_id
[val
->port_vlan
] = val
->value
.i
;
1844 ar8xxx_sw_get_vid(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1845 struct switch_val
*val
)
1847 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1848 val
->value
.i
= priv
->vlan_id
[val
->port_vlan
];
1853 ar8xxx_sw_get_port_link(struct switch_dev
*dev
, int port
,
1854 struct switch_port_link
*link
)
1856 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1858 ar8216_read_port_link(priv
, port
, link
);
1863 ar8xxx_sw_get_ports(struct switch_dev
*dev
, struct switch_val
*val
)
1865 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1866 u8 ports
= priv
->vlan_table
[val
->port_vlan
];
1870 for (i
= 0; i
< dev
->ports
; i
++) {
1871 struct switch_port
*p
;
1873 if (!(ports
& (1 << i
)))
1876 p
= &val
->value
.ports
[val
->len
++];
1878 if (priv
->vlan_tagged
& (1 << i
))
1879 p
->flags
= (1 << SWITCH_PORT_FLAG_TAGGED
);
1887 ar8327_sw_get_ports(struct switch_dev
*dev
, struct switch_val
*val
)
1889 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1890 u8 ports
= priv
->vlan_table
[val
->port_vlan
];
1894 for (i
= 0; i
< dev
->ports
; i
++) {
1895 struct switch_port
*p
;
1897 if (!(ports
& (1 << i
)))
1900 p
= &val
->value
.ports
[val
->len
++];
1902 if ((priv
->vlan_tagged
& (1 << i
)) || (priv
->pvid
[i
] != val
->port_vlan
))
1903 p
->flags
= (1 << SWITCH_PORT_FLAG_TAGGED
);
1911 ar8xxx_sw_set_ports(struct switch_dev
*dev
, struct switch_val
*val
)
1913 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1914 u8
*vt
= &priv
->vlan_table
[val
->port_vlan
];
1918 for (i
= 0; i
< val
->len
; i
++) {
1919 struct switch_port
*p
= &val
->value
.ports
[i
];
1921 if (p
->flags
& (1 << SWITCH_PORT_FLAG_TAGGED
)) {
1922 priv
->vlan_tagged
|= (1 << p
->id
);
1924 priv
->vlan_tagged
&= ~(1 << p
->id
);
1925 priv
->pvid
[p
->id
] = val
->port_vlan
;
1927 /* make sure that an untagged port does not
1928 * appear in other vlans */
1929 for (j
= 0; j
< AR8X16_MAX_VLANS
; j
++) {
1930 if (j
== val
->port_vlan
)
1932 priv
->vlan_table
[j
] &= ~(1 << p
->id
);
1942 ar8327_sw_set_ports(struct switch_dev
*dev
, struct switch_val
*val
)
1944 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1945 u8
*vt
= &priv
->vlan_table
[val
->port_vlan
];
1949 for (i
= 0; i
< val
->len
; i
++) {
1950 struct switch_port
*p
= &val
->value
.ports
[i
];
1952 if (p
->flags
& (1 << SWITCH_PORT_FLAG_TAGGED
)) {
1953 if (val
->port_vlan
== priv
->pvid
[p
->id
]) {
1954 priv
->vlan_tagged
|= (1 << p
->id
);
1957 priv
->vlan_tagged
&= ~(1 << p
->id
);
1958 priv
->pvid
[p
->id
] = val
->port_vlan
;
1967 ar8327_set_mirror_regs(struct ar8xxx_priv
*priv
)
1971 /* reset all mirror registers */
1972 ar8xxx_rmw(priv
, AR8327_REG_FWD_CTRL0
,
1973 AR8327_FWD_CTRL0_MIRROR_PORT
,
1974 (0xF << AR8327_FWD_CTRL0_MIRROR_PORT_S
));
1975 for (port
= 0; port
< AR8327_NUM_PORTS
; port
++) {
1976 ar8xxx_rmw(priv
, AR8327_REG_PORT_LOOKUP(port
),
1977 AR8327_PORT_LOOKUP_ING_MIRROR_EN
,
1980 ar8xxx_rmw(priv
, AR8327_REG_PORT_HOL_CTRL1(port
),
1981 AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN
,
1985 /* now enable mirroring if necessary */
1986 if (priv
->source_port
>= AR8327_NUM_PORTS
||
1987 priv
->monitor_port
>= AR8327_NUM_PORTS
||
1988 priv
->source_port
== priv
->monitor_port
) {
1992 ar8xxx_rmw(priv
, AR8327_REG_FWD_CTRL0
,
1993 AR8327_FWD_CTRL0_MIRROR_PORT
,
1994 (priv
->monitor_port
<< AR8327_FWD_CTRL0_MIRROR_PORT_S
));
1996 if (priv
->mirror_rx
)
1997 ar8xxx_rmw(priv
, AR8327_REG_PORT_LOOKUP(priv
->source_port
),
1998 AR8327_PORT_LOOKUP_ING_MIRROR_EN
,
1999 AR8327_PORT_LOOKUP_ING_MIRROR_EN
);
2001 if (priv
->mirror_tx
)
2002 ar8xxx_rmw(priv
, AR8327_REG_PORT_HOL_CTRL1(priv
->source_port
),
2003 AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN
,
2004 AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN
);
2008 ar8216_set_mirror_regs(struct ar8xxx_priv
*priv
)
2012 /* reset all mirror registers */
2013 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CPUPORT
,
2014 AR8216_GLOBAL_CPUPORT_MIRROR_PORT
,
2015 (0xF << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S
));
2016 for (port
= 0; port
< AR8216_NUM_PORTS
; port
++) {
2017 ar8xxx_rmw(priv
, AR8216_REG_PORT_CTRL(port
),
2018 AR8216_PORT_CTRL_MIRROR_RX
,
2021 ar8xxx_rmw(priv
, AR8216_REG_PORT_CTRL(port
),
2022 AR8216_PORT_CTRL_MIRROR_TX
,
2026 /* now enable mirroring if necessary */
2027 if (priv
->source_port
>= AR8216_NUM_PORTS
||
2028 priv
->monitor_port
>= AR8216_NUM_PORTS
||
2029 priv
->source_port
== priv
->monitor_port
) {
2033 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CPUPORT
,
2034 AR8216_GLOBAL_CPUPORT_MIRROR_PORT
,
2035 (priv
->monitor_port
<< AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S
));
2037 if (priv
->mirror_rx
)
2038 ar8xxx_rmw(priv
, AR8216_REG_PORT_CTRL(priv
->source_port
),
2039 AR8216_PORT_CTRL_MIRROR_RX
,
2040 AR8216_PORT_CTRL_MIRROR_RX
);
2042 if (priv
->mirror_tx
)
2043 ar8xxx_rmw(priv
, AR8216_REG_PORT_CTRL(priv
->source_port
),
2044 AR8216_PORT_CTRL_MIRROR_TX
,
2045 AR8216_PORT_CTRL_MIRROR_TX
);
2049 ar8xxx_sw_hw_apply(struct switch_dev
*dev
)
2051 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
2052 u8 portmask
[AR8X16_MAX_PORTS
];
2055 mutex_lock(&priv
->reg_mutex
);
2056 /* flush all vlan translation unit entries */
2057 priv
->chip
->vtu_flush(priv
);
2059 memset(portmask
, 0, sizeof(portmask
));
2061 /* calculate the port destination masks and load vlans
2062 * into the vlan translation unit */
2063 for (j
= 0; j
< AR8X16_MAX_VLANS
; j
++) {
2064 u8 vp
= priv
->vlan_table
[j
];
2069 for (i
= 0; i
< dev
->ports
; i
++) {
2072 portmask
[i
] |= vp
& ~mask
;
2075 priv
->chip
->vtu_load_vlan(priv
, priv
->vlan_id
[j
],
2076 priv
->vlan_table
[j
]);
2080 * isolate all ports, but connect them to the cpu port */
2081 for (i
= 0; i
< dev
->ports
; i
++) {
2082 if (i
== AR8216_PORT_CPU
)
2085 portmask
[i
] = 1 << AR8216_PORT_CPU
;
2086 portmask
[AR8216_PORT_CPU
] |= (1 << i
);
2090 /* update the port destination mask registers and tag settings */
2091 for (i
= 0; i
< dev
->ports
; i
++) {
2092 priv
->chip
->setup_port(priv
, i
, portmask
[i
]);
2095 priv
->chip
->set_mirror_regs(priv
);
2097 mutex_unlock(&priv
->reg_mutex
);
2102 ar8xxx_sw_reset_switch(struct switch_dev
*dev
)
2104 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
2107 mutex_lock(&priv
->reg_mutex
);
2108 memset(&priv
->vlan
, 0, sizeof(struct ar8xxx_priv
) -
2109 offsetof(struct ar8xxx_priv
, vlan
));
2111 for (i
= 0; i
< AR8X16_MAX_VLANS
; i
++)
2112 priv
->vlan_id
[i
] = i
;
2114 /* Configure all ports */
2115 for (i
= 0; i
< dev
->ports
; i
++)
2116 priv
->chip
->init_port(priv
, i
);
2118 priv
->mirror_rx
= false;
2119 priv
->mirror_tx
= false;
2120 priv
->source_port
= 0;
2121 priv
->monitor_port
= 0;
2123 priv
->chip
->init_globals(priv
);
2125 mutex_unlock(&priv
->reg_mutex
);
2127 return ar8xxx_sw_hw_apply(dev
);
2131 ar8xxx_sw_set_reset_mibs(struct switch_dev
*dev
,
2132 const struct switch_attr
*attr
,
2133 struct switch_val
*val
)
2135 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
2139 if (!ar8xxx_has_mib_counters(priv
))
2142 mutex_lock(&priv
->mib_lock
);
2144 len
= priv
->dev
.ports
* priv
->chip
->num_mibs
*
2145 sizeof(*priv
->mib_stats
);
2146 memset(priv
->mib_stats
, '\0', len
);
2147 ret
= ar8xxx_mib_flush(priv
);
2154 mutex_unlock(&priv
->mib_lock
);
2159 ar8xxx_sw_set_mirror_rx_enable(struct switch_dev
*dev
,
2160 const struct switch_attr
*attr
,
2161 struct switch_val
*val
)
2163 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
2165 mutex_lock(&priv
->reg_mutex
);
2166 priv
->mirror_rx
= !!val
->value
.i
;
2167 priv
->chip
->set_mirror_regs(priv
);
2168 mutex_unlock(&priv
->reg_mutex
);
2174 ar8xxx_sw_get_mirror_rx_enable(struct switch_dev
*dev
,
2175 const struct switch_attr
*attr
,
2176 struct switch_val
*val
)
2178 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
2179 val
->value
.i
= priv
->mirror_rx
;
2184 ar8xxx_sw_set_mirror_tx_enable(struct switch_dev
*dev
,
2185 const struct switch_attr
*attr
,
2186 struct switch_val
*val
)
2188 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
2190 mutex_lock(&priv
->reg_mutex
);
2191 priv
->mirror_tx
= !!val
->value
.i
;
2192 priv
->chip
->set_mirror_regs(priv
);
2193 mutex_unlock(&priv
->reg_mutex
);
2199 ar8xxx_sw_get_mirror_tx_enable(struct switch_dev
*dev
,
2200 const struct switch_attr
*attr
,
2201 struct switch_val
*val
)
2203 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
2204 val
->value
.i
= priv
->mirror_tx
;
2209 ar8xxx_sw_set_mirror_monitor_port(struct switch_dev
*dev
,
2210 const struct switch_attr
*attr
,
2211 struct switch_val
*val
)
2213 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
2215 mutex_lock(&priv
->reg_mutex
);
2216 priv
->monitor_port
= val
->value
.i
;
2217 priv
->chip
->set_mirror_regs(priv
);
2218 mutex_unlock(&priv
->reg_mutex
);
2224 ar8xxx_sw_get_mirror_monitor_port(struct switch_dev
*dev
,
2225 const struct switch_attr
*attr
,
2226 struct switch_val
*val
)
2228 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
2229 val
->value
.i
= priv
->monitor_port
;
2234 ar8xxx_sw_set_mirror_source_port(struct switch_dev
*dev
,
2235 const struct switch_attr
*attr
,
2236 struct switch_val
*val
)
2238 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
2240 mutex_lock(&priv
->reg_mutex
);
2241 priv
->source_port
= val
->value
.i
;
2242 priv
->chip
->set_mirror_regs(priv
);
2243 mutex_unlock(&priv
->reg_mutex
);
2249 ar8xxx_sw_get_mirror_source_port(struct switch_dev
*dev
,
2250 const struct switch_attr
*attr
,
2251 struct switch_val
*val
)
2253 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
2254 val
->value
.i
= priv
->source_port
;
2259 ar8xxx_sw_set_port_reset_mib(struct switch_dev
*dev
,
2260 const struct switch_attr
*attr
,
2261 struct switch_val
*val
)
2263 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
2267 if (!ar8xxx_has_mib_counters(priv
))
2270 port
= val
->port_vlan
;
2271 if (port
>= dev
->ports
)
2274 mutex_lock(&priv
->mib_lock
);
2275 ret
= ar8xxx_mib_capture(priv
);
2279 ar8xxx_mib_fetch_port_stat(priv
, port
, true);
2284 mutex_unlock(&priv
->mib_lock
);
2289 ar8xxx_sw_get_port_mib(struct switch_dev
*dev
,
2290 const struct switch_attr
*attr
,
2291 struct switch_val
*val
)
2293 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
2294 const struct ar8xxx_chip
*chip
= priv
->chip
;
2298 char *buf
= priv
->buf
;
2301 if (!ar8xxx_has_mib_counters(priv
))
2304 port
= val
->port_vlan
;
2305 if (port
>= dev
->ports
)
2308 mutex_lock(&priv
->mib_lock
);
2309 ret
= ar8xxx_mib_capture(priv
);
2313 ar8xxx_mib_fetch_port_stat(priv
, port
, false);
2315 len
+= snprintf(buf
+ len
, sizeof(priv
->buf
) - len
,
2316 "Port %d MIB counters\n",
2319 mib_stats
= &priv
->mib_stats
[port
* chip
->num_mibs
];
2320 for (i
= 0; i
< chip
->num_mibs
; i
++)
2321 len
+= snprintf(buf
+ len
, sizeof(priv
->buf
) - len
,
2323 chip
->mib_decs
[i
].name
,
2332 mutex_unlock(&priv
->mib_lock
);
2336 static struct switch_attr ar8xxx_sw_attr_globals
[] = {
2338 .type
= SWITCH_TYPE_INT
,
2339 .name
= "enable_vlan",
2340 .description
= "Enable VLAN mode",
2341 .set
= ar8xxx_sw_set_vlan
,
2342 .get
= ar8xxx_sw_get_vlan
,
2346 .type
= SWITCH_TYPE_NOVAL
,
2347 .name
= "reset_mibs",
2348 .description
= "Reset all MIB counters",
2349 .set
= ar8xxx_sw_set_reset_mibs
,
2352 .type
= SWITCH_TYPE_INT
,
2353 .name
= "enable_mirror_rx",
2354 .description
= "Enable mirroring of RX packets",
2355 .set
= ar8xxx_sw_set_mirror_rx_enable
,
2356 .get
= ar8xxx_sw_get_mirror_rx_enable
,
2360 .type
= SWITCH_TYPE_INT
,
2361 .name
= "enable_mirror_tx",
2362 .description
= "Enable mirroring of TX packets",
2363 .set
= ar8xxx_sw_set_mirror_tx_enable
,
2364 .get
= ar8xxx_sw_get_mirror_tx_enable
,
2368 .type
= SWITCH_TYPE_INT
,
2369 .name
= "mirror_monitor_port",
2370 .description
= "Mirror monitor port",
2371 .set
= ar8xxx_sw_set_mirror_monitor_port
,
2372 .get
= ar8xxx_sw_get_mirror_monitor_port
,
2373 .max
= AR8216_NUM_PORTS
- 1
2376 .type
= SWITCH_TYPE_INT
,
2377 .name
= "mirror_source_port",
2378 .description
= "Mirror source port",
2379 .set
= ar8xxx_sw_set_mirror_source_port
,
2380 .get
= ar8xxx_sw_get_mirror_source_port
,
2381 .max
= AR8216_NUM_PORTS
- 1
2385 static struct switch_attr ar8327_sw_attr_globals
[] = {
2387 .type
= SWITCH_TYPE_INT
,
2388 .name
= "enable_vlan",
2389 .description
= "Enable VLAN mode",
2390 .set
= ar8xxx_sw_set_vlan
,
2391 .get
= ar8xxx_sw_get_vlan
,
2395 .type
= SWITCH_TYPE_NOVAL
,
2396 .name
= "reset_mibs",
2397 .description
= "Reset all MIB counters",
2398 .set
= ar8xxx_sw_set_reset_mibs
,
2401 .type
= SWITCH_TYPE_INT
,
2402 .name
= "enable_mirror_rx",
2403 .description
= "Enable mirroring of RX packets",
2404 .set
= ar8xxx_sw_set_mirror_rx_enable
,
2405 .get
= ar8xxx_sw_get_mirror_rx_enable
,
2409 .type
= SWITCH_TYPE_INT
,
2410 .name
= "enable_mirror_tx",
2411 .description
= "Enable mirroring of TX packets",
2412 .set
= ar8xxx_sw_set_mirror_tx_enable
,
2413 .get
= ar8xxx_sw_get_mirror_tx_enable
,
2417 .type
= SWITCH_TYPE_INT
,
2418 .name
= "mirror_monitor_port",
2419 .description
= "Mirror monitor port",
2420 .set
= ar8xxx_sw_set_mirror_monitor_port
,
2421 .get
= ar8xxx_sw_get_mirror_monitor_port
,
2422 .max
= AR8327_NUM_PORTS
- 1
2425 .type
= SWITCH_TYPE_INT
,
2426 .name
= "mirror_source_port",
2427 .description
= "Mirror source port",
2428 .set
= ar8xxx_sw_set_mirror_source_port
,
2429 .get
= ar8xxx_sw_get_mirror_source_port
,
2430 .max
= AR8327_NUM_PORTS
- 1
2434 static struct switch_attr ar8xxx_sw_attr_port
[] = {
2436 .type
= SWITCH_TYPE_NOVAL
,
2437 .name
= "reset_mib",
2438 .description
= "Reset single port MIB counters",
2439 .set
= ar8xxx_sw_set_port_reset_mib
,
2442 .type
= SWITCH_TYPE_STRING
,
2444 .description
= "Get port's MIB counters",
2446 .get
= ar8xxx_sw_get_port_mib
,
2450 static struct switch_attr ar8xxx_sw_attr_vlan
[] = {
2452 .type
= SWITCH_TYPE_INT
,
2454 .description
= "VLAN ID (0-4094)",
2455 .set
= ar8xxx_sw_set_vid
,
2456 .get
= ar8xxx_sw_get_vid
,
2461 static const struct switch_dev_ops ar8xxx_sw_ops
= {
2463 .attr
= ar8xxx_sw_attr_globals
,
2464 .n_attr
= ARRAY_SIZE(ar8xxx_sw_attr_globals
),
2467 .attr
= ar8xxx_sw_attr_port
,
2468 .n_attr
= ARRAY_SIZE(ar8xxx_sw_attr_port
),
2471 .attr
= ar8xxx_sw_attr_vlan
,
2472 .n_attr
= ARRAY_SIZE(ar8xxx_sw_attr_vlan
),
2474 .get_port_pvid
= ar8xxx_sw_get_pvid
,
2475 .set_port_pvid
= ar8xxx_sw_set_pvid
,
2476 .get_vlan_ports
= ar8xxx_sw_get_ports
,
2477 .set_vlan_ports
= ar8xxx_sw_set_ports
,
2478 .apply_config
= ar8xxx_sw_hw_apply
,
2479 .reset_switch
= ar8xxx_sw_reset_switch
,
2480 .get_port_link
= ar8xxx_sw_get_port_link
,
2483 static const struct switch_dev_ops ar8327_sw_ops
= {
2485 .attr
= ar8327_sw_attr_globals
,
2486 .n_attr
= ARRAY_SIZE(ar8327_sw_attr_globals
),
2489 .attr
= ar8xxx_sw_attr_port
,
2490 .n_attr
= ARRAY_SIZE(ar8xxx_sw_attr_port
),
2493 .attr
= ar8xxx_sw_attr_vlan
,
2494 .n_attr
= ARRAY_SIZE(ar8xxx_sw_attr_vlan
),
2496 .get_port_pvid
= ar8xxx_sw_get_pvid
,
2497 .set_port_pvid
= ar8xxx_sw_set_pvid
,
2498 .get_vlan_ports
= ar8327_sw_get_ports
,
2499 .set_vlan_ports
= ar8327_sw_set_ports
,
2500 .apply_config
= ar8xxx_sw_hw_apply
,
2501 .reset_switch
= ar8xxx_sw_reset_switch
,
2502 .get_port_link
= ar8xxx_sw_get_port_link
,
2505 static const struct ar8xxx_chip ar8216_chip
= {
2506 .caps
= AR8XXX_CAP_MIB_COUNTERS
,
2508 .reg_port_stats_start
= 0x19000,
2509 .reg_port_stats_length
= 0xa0,
2511 .name
= "Atheros AR8216",
2512 .ports
= AR8216_NUM_PORTS
,
2513 .vlans
= AR8216_NUM_VLANS
,
2514 .swops
= &ar8xxx_sw_ops
,
2516 .hw_init
= ar8216_hw_init
,
2517 .init_globals
= ar8216_init_globals
,
2518 .init_port
= ar8216_init_port
,
2519 .setup_port
= ar8216_setup_port
,
2520 .read_port_status
= ar8216_read_port_status
,
2521 .atu_flush
= ar8216_atu_flush
,
2522 .vtu_flush
= ar8216_vtu_flush
,
2523 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
2524 .set_mirror_regs
= ar8216_set_mirror_regs
,
2526 .num_mibs
= ARRAY_SIZE(ar8216_mibs
),
2527 .mib_decs
= ar8216_mibs
,
2528 .mib_func
= AR8216_REG_MIB_FUNC
2531 static const struct ar8xxx_chip ar8236_chip
= {
2532 .caps
= AR8XXX_CAP_MIB_COUNTERS
,
2534 .reg_port_stats_start
= 0x20000,
2535 .reg_port_stats_length
= 0x100,
2537 .name
= "Atheros AR8236",
2538 .ports
= AR8216_NUM_PORTS
,
2539 .vlans
= AR8216_NUM_VLANS
,
2540 .swops
= &ar8xxx_sw_ops
,
2542 .hw_init
= ar8216_hw_init
,
2543 .init_globals
= ar8236_init_globals
,
2544 .init_port
= ar8216_init_port
,
2545 .setup_port
= ar8236_setup_port
,
2546 .read_port_status
= ar8216_read_port_status
,
2547 .atu_flush
= ar8216_atu_flush
,
2548 .vtu_flush
= ar8216_vtu_flush
,
2549 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
2550 .set_mirror_regs
= ar8216_set_mirror_regs
,
2552 .num_mibs
= ARRAY_SIZE(ar8236_mibs
),
2553 .mib_decs
= ar8236_mibs
,
2554 .mib_func
= AR8216_REG_MIB_FUNC
2557 static const struct ar8xxx_chip ar8316_chip
= {
2558 .caps
= AR8XXX_CAP_GIGE
| AR8XXX_CAP_MIB_COUNTERS
,
2560 .reg_port_stats_start
= 0x20000,
2561 .reg_port_stats_length
= 0x100,
2563 .name
= "Atheros AR8316",
2564 .ports
= AR8216_NUM_PORTS
,
2565 .vlans
= AR8X16_MAX_VLANS
,
2566 .swops
= &ar8xxx_sw_ops
,
2568 .hw_init
= ar8316_hw_init
,
2569 .init_globals
= ar8316_init_globals
,
2570 .init_port
= ar8216_init_port
,
2571 .setup_port
= ar8216_setup_port
,
2572 .read_port_status
= ar8216_read_port_status
,
2573 .atu_flush
= ar8216_atu_flush
,
2574 .vtu_flush
= ar8216_vtu_flush
,
2575 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
2576 .set_mirror_regs
= ar8216_set_mirror_regs
,
2578 .num_mibs
= ARRAY_SIZE(ar8236_mibs
),
2579 .mib_decs
= ar8236_mibs
,
2580 .mib_func
= AR8216_REG_MIB_FUNC
2583 static const struct ar8xxx_chip ar8327_chip
= {
2584 .caps
= AR8XXX_CAP_GIGE
| AR8XXX_CAP_MIB_COUNTERS
,
2585 .config_at_probe
= true,
2586 .mii_lo_first
= true,
2588 .name
= "Atheros AR8327",
2589 .ports
= AR8327_NUM_PORTS
,
2590 .vlans
= AR8X16_MAX_VLANS
,
2591 .swops
= &ar8327_sw_ops
,
2593 .reg_port_stats_start
= 0x1000,
2594 .reg_port_stats_length
= 0x100,
2596 .hw_init
= ar8327_hw_init
,
2597 .cleanup
= ar8327_cleanup
,
2598 .init_globals
= ar8327_init_globals
,
2599 .init_port
= ar8327_init_port
,
2600 .setup_port
= ar8327_setup_port
,
2601 .read_port_status
= ar8327_read_port_status
,
2602 .atu_flush
= ar8327_atu_flush
,
2603 .vtu_flush
= ar8327_vtu_flush
,
2604 .vtu_load_vlan
= ar8327_vtu_load_vlan
,
2605 .phy_fixup
= ar8327_phy_fixup
,
2606 .set_mirror_regs
= ar8327_set_mirror_regs
,
2608 .num_mibs
= ARRAY_SIZE(ar8236_mibs
),
2609 .mib_decs
= ar8236_mibs
,
2610 .mib_func
= AR8327_REG_MIB_FUNC
2613 static const struct ar8xxx_chip ar8337_chip
= {
2614 .caps
= AR8XXX_CAP_GIGE
| AR8XXX_CAP_MIB_COUNTERS
,
2615 .config_at_probe
= true,
2616 .mii_lo_first
= true,
2618 .name
= "Atheros AR8337",
2619 .ports
= AR8327_NUM_PORTS
,
2620 .vlans
= AR8X16_MAX_VLANS
,
2621 .swops
= &ar8327_sw_ops
,
2623 .reg_port_stats_start
= 0x1000,
2624 .reg_port_stats_length
= 0x100,
2626 .hw_init
= ar8327_hw_init
,
2627 .cleanup
= ar8327_cleanup
,
2628 .init_globals
= ar8327_init_globals
,
2629 .init_port
= ar8327_init_port
,
2630 .setup_port
= ar8327_setup_port
,
2631 .read_port_status
= ar8327_read_port_status
,
2632 .atu_flush
= ar8327_atu_flush
,
2633 .vtu_flush
= ar8327_vtu_flush
,
2634 .vtu_load_vlan
= ar8327_vtu_load_vlan
,
2635 .phy_fixup
= ar8327_phy_fixup
,
2636 .set_mirror_regs
= ar8327_set_mirror_regs
,
2638 .num_mibs
= ARRAY_SIZE(ar8236_mibs
),
2639 .mib_decs
= ar8236_mibs
,
2640 .mib_func
= AR8327_REG_MIB_FUNC
2644 ar8xxx_id_chip(struct ar8xxx_priv
*priv
)
2650 val
= priv
->read(priv
, AR8216_REG_CTRL
);
2654 id
= val
& (AR8216_CTRL_REVISION
| AR8216_CTRL_VERSION
);
2655 for (i
= 0; i
< AR8X16_PROBE_RETRIES
; i
++) {
2658 val
= priv
->read(priv
, AR8216_REG_CTRL
);
2662 t
= val
& (AR8216_CTRL_REVISION
| AR8216_CTRL_VERSION
);
2667 priv
->chip_ver
= (id
& AR8216_CTRL_VERSION
) >> AR8216_CTRL_VERSION_S
;
2668 priv
->chip_rev
= (id
& AR8216_CTRL_REVISION
);
2670 switch (priv
->chip_ver
) {
2671 case AR8XXX_VER_AR8216
:
2672 priv
->chip
= &ar8216_chip
;
2674 case AR8XXX_VER_AR8236
:
2675 priv
->chip
= &ar8236_chip
;
2677 case AR8XXX_VER_AR8316
:
2678 priv
->chip
= &ar8316_chip
;
2680 case AR8XXX_VER_AR8327
:
2681 priv
->chip
= &ar8327_chip
;
2683 case AR8XXX_VER_AR8337
:
2684 priv
->chip
= &ar8337_chip
;
2687 pr_err("ar8216: Unknown Atheros device [ver=%d, rev=%d]\n",
2688 priv
->chip_ver
, priv
->chip_rev
);
2697 ar8xxx_mib_work_func(struct work_struct
*work
)
2699 struct ar8xxx_priv
*priv
;
2702 priv
= container_of(work
, struct ar8xxx_priv
, mib_work
.work
);
2704 mutex_lock(&priv
->mib_lock
);
2706 err
= ar8xxx_mib_capture(priv
);
2710 ar8xxx_mib_fetch_port_stat(priv
, priv
->mib_next_port
, false);
2713 priv
->mib_next_port
++;
2714 if (priv
->mib_next_port
>= priv
->dev
.ports
)
2715 priv
->mib_next_port
= 0;
2717 mutex_unlock(&priv
->mib_lock
);
2718 schedule_delayed_work(&priv
->mib_work
,
2719 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY
));
2723 ar8xxx_mib_init(struct ar8xxx_priv
*priv
)
2727 if (!ar8xxx_has_mib_counters(priv
))
2730 BUG_ON(!priv
->chip
->mib_decs
|| !priv
->chip
->num_mibs
);
2732 len
= priv
->dev
.ports
* priv
->chip
->num_mibs
*
2733 sizeof(*priv
->mib_stats
);
2734 priv
->mib_stats
= kzalloc(len
, GFP_KERNEL
);
2736 if (!priv
->mib_stats
)
2743 ar8xxx_mib_start(struct ar8xxx_priv
*priv
)
2745 if (!ar8xxx_has_mib_counters(priv
))
2748 schedule_delayed_work(&priv
->mib_work
,
2749 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY
));
2753 ar8xxx_mib_stop(struct ar8xxx_priv
*priv
)
2755 if (!ar8xxx_has_mib_counters(priv
))
2758 cancel_delayed_work(&priv
->mib_work
);
2761 static struct ar8xxx_priv
*
2764 struct ar8xxx_priv
*priv
;
2766 priv
= kzalloc(sizeof(struct ar8xxx_priv
), GFP_KERNEL
);
2770 mutex_init(&priv
->reg_mutex
);
2771 mutex_init(&priv
->mib_lock
);
2772 INIT_DELAYED_WORK(&priv
->mib_work
, ar8xxx_mib_work_func
);
2778 ar8xxx_free(struct ar8xxx_priv
*priv
)
2780 if (priv
->chip
&& priv
->chip
->cleanup
)
2781 priv
->chip
->cleanup(priv
);
2783 kfree(priv
->chip_data
);
2784 kfree(priv
->mib_stats
);
2788 static struct ar8xxx_priv
*
2789 ar8xxx_create_mii(struct mii_bus
*bus
)
2791 struct ar8xxx_priv
*priv
;
2793 priv
= ar8xxx_create();
2795 priv
->mii_bus
= bus
;
2796 priv
->read
= ar8xxx_mii_read
;
2797 priv
->write
= ar8xxx_mii_write
;
2798 priv
->rmw
= ar8xxx_mii_rmw
;
2805 ar8xxx_probe_switch(struct ar8xxx_priv
*priv
)
2807 const struct ar8xxx_chip
*chip
;
2808 struct switch_dev
*swdev
;
2811 ret
= ar8xxx_id_chip(priv
);
2818 swdev
->cpu_port
= AR8216_PORT_CPU
;
2819 swdev
->name
= chip
->name
;
2820 swdev
->vlans
= chip
->vlans
;
2821 swdev
->ports
= chip
->ports
;
2822 swdev
->ops
= chip
->swops
;
2824 ret
= ar8xxx_mib_init(priv
);
2832 ar8xxx_start(struct ar8xxx_priv
*priv
)
2838 ret
= priv
->chip
->hw_init(priv
);
2842 ret
= ar8xxx_sw_reset_switch(&priv
->dev
);
2848 ar8xxx_mib_start(priv
);
2854 ar8xxx_phy_config_init(struct phy_device
*phydev
)
2856 struct ar8xxx_priv
*priv
= phydev
->priv
;
2857 struct net_device
*dev
= phydev
->attached_dev
;
2863 if (priv
->chip
->config_at_probe
)
2864 return ar8xxx_phy_check_aneg(phydev
);
2868 if (phydev
->addr
!= 0) {
2869 if (chip_is_ar8316(priv
)) {
2870 /* switch device has been initialized, reinit */
2871 priv
->dev
.ports
= (AR8216_NUM_PORTS
- 1);
2872 priv
->initialized
= false;
2873 priv
->port4_phy
= true;
2874 ar8316_hw_init(priv
);
2881 ret
= ar8xxx_start(priv
);
2885 /* VID fixup only needed on ar8216 */
2886 if (chip_is_ar8216(priv
)) {
2887 dev
->phy_ptr
= priv
;
2888 dev
->priv_flags
|= IFF_NO_IP_ALIGN
;
2889 dev
->eth_mangle_rx
= ar8216_mangle_rx
;
2890 dev
->eth_mangle_tx
= ar8216_mangle_tx
;
2897 ar8xxx_phy_read_status(struct phy_device
*phydev
)
2899 struct ar8xxx_priv
*priv
= phydev
->priv
;
2900 struct switch_port_link link
;
2903 if (phydev
->addr
!= 0)
2904 return genphy_read_status(phydev
);
2906 ar8216_read_port_link(priv
, phydev
->addr
, &link
);
2907 phydev
->link
= !!link
.link
;
2911 switch (link
.speed
) {
2912 case SWITCH_PORT_SPEED_10
:
2913 phydev
->speed
= SPEED_10
;
2915 case SWITCH_PORT_SPEED_100
:
2916 phydev
->speed
= SPEED_100
;
2918 case SWITCH_PORT_SPEED_1000
:
2919 phydev
->speed
= SPEED_1000
;
2924 phydev
->duplex
= link
.duplex
? DUPLEX_FULL
: DUPLEX_HALF
;
2926 /* flush the address translation unit */
2927 mutex_lock(&priv
->reg_mutex
);
2928 ret
= priv
->chip
->atu_flush(priv
);
2929 mutex_unlock(&priv
->reg_mutex
);
2931 phydev
->state
= PHY_RUNNING
;
2932 netif_carrier_on(phydev
->attached_dev
);
2933 phydev
->adjust_link(phydev
->attached_dev
);
2939 ar8xxx_phy_config_aneg(struct phy_device
*phydev
)
2941 if (phydev
->addr
== 0)
2944 return genphy_config_aneg(phydev
);
2947 static const u32 ar8xxx_phy_ids
[] = {
2949 0x004dd034, /* AR8327 */
2950 0x004dd036, /* AR8337 */
2953 0x004dd043, /* AR8236 */
2957 ar8xxx_phy_match(u32 phy_id
)
2961 for (i
= 0; i
< ARRAY_SIZE(ar8xxx_phy_ids
); i
++)
2962 if (phy_id
== ar8xxx_phy_ids
[i
])
2969 ar8xxx_is_possible(struct mii_bus
*bus
)
2973 for (i
= 0; i
< 4; i
++) {
2976 phy_id
= mdiobus_read(bus
, i
, MII_PHYSID1
) << 16;
2977 phy_id
|= mdiobus_read(bus
, i
, MII_PHYSID2
);
2978 if (!ar8xxx_phy_match(phy_id
)) {
2979 pr_debug("ar8xxx: unknown PHY at %s:%02x id:%08x\n",
2980 dev_name(&bus
->dev
), i
, phy_id
);
2989 ar8xxx_phy_probe(struct phy_device
*phydev
)
2991 struct ar8xxx_priv
*priv
;
2992 struct switch_dev
*swdev
;
2995 /* skip PHYs at unused adresses */
2996 if (phydev
->addr
!= 0 && phydev
->addr
!= 4)
2999 if (!ar8xxx_is_possible(phydev
->bus
))
3002 mutex_lock(&ar8xxx_dev_list_lock
);
3003 list_for_each_entry(priv
, &ar8xxx_dev_list
, list
)
3004 if (priv
->mii_bus
== phydev
->bus
)
3007 priv
= ar8xxx_create_mii(phydev
->bus
);
3013 ret
= ar8xxx_probe_switch(priv
);
3018 swdev
->alias
= dev_name(&priv
->mii_bus
->dev
);
3019 ret
= register_switch(swdev
, NULL
);
3023 pr_info("%s: %s rev. %u switch registered on %s\n",
3024 swdev
->devname
, swdev
->name
, priv
->chip_rev
,
3025 dev_name(&priv
->mii_bus
->dev
));
3030 if (phydev
->addr
== 0) {
3031 if (ar8xxx_has_gige(priv
)) {
3032 phydev
->supported
= SUPPORTED_1000baseT_Full
;
3033 phydev
->advertising
= ADVERTISED_1000baseT_Full
;
3035 phydev
->supported
= SUPPORTED_100baseT_Full
;
3036 phydev
->advertising
= ADVERTISED_100baseT_Full
;
3039 if (priv
->chip
->config_at_probe
) {
3042 ret
= ar8xxx_start(priv
);
3044 goto err_unregister_switch
;
3047 if (ar8xxx_has_gige(priv
)) {
3048 phydev
->supported
|= SUPPORTED_1000baseT_Full
;
3049 phydev
->advertising
|= ADVERTISED_1000baseT_Full
;
3053 phydev
->priv
= priv
;
3055 list_add(&priv
->list
, &ar8xxx_dev_list
);
3057 mutex_unlock(&ar8xxx_dev_list_lock
);
3061 err_unregister_switch
:
3062 if (--priv
->use_count
)
3065 unregister_switch(&priv
->dev
);
3070 mutex_unlock(&ar8xxx_dev_list_lock
);
3075 ar8xxx_phy_detach(struct phy_device
*phydev
)
3077 struct net_device
*dev
= phydev
->attached_dev
;
3082 dev
->phy_ptr
= NULL
;
3083 dev
->priv_flags
&= ~IFF_NO_IP_ALIGN
;
3084 dev
->eth_mangle_rx
= NULL
;
3085 dev
->eth_mangle_tx
= NULL
;
3089 ar8xxx_phy_remove(struct phy_device
*phydev
)
3091 struct ar8xxx_priv
*priv
= phydev
->priv
;
3096 phydev
->priv
= NULL
;
3097 if (--priv
->use_count
> 0)
3100 mutex_lock(&ar8xxx_dev_list_lock
);
3101 list_del(&priv
->list
);
3102 mutex_unlock(&ar8xxx_dev_list_lock
);
3104 unregister_switch(&priv
->dev
);
3105 ar8xxx_mib_stop(priv
);
3109 #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)
3111 ar8xxx_phy_soft_reset(struct phy_device
*phydev
)
3113 /* we don't need an extra reset */
3118 static struct phy_driver ar8xxx_phy_driver
= {
3119 .phy_id
= 0x004d0000,
3120 .name
= "Atheros AR8216/AR8236/AR8316",
3121 .phy_id_mask
= 0xffff0000,
3122 .features
= PHY_BASIC_FEATURES
,
3123 .probe
= ar8xxx_phy_probe
,
3124 .remove
= ar8xxx_phy_remove
,
3125 .detach
= ar8xxx_phy_detach
,
3126 .config_init
= ar8xxx_phy_config_init
,
3127 .config_aneg
= ar8xxx_phy_config_aneg
,
3128 .read_status
= ar8xxx_phy_read_status
,
3129 #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)
3130 .soft_reset
= ar8xxx_phy_soft_reset
,
3132 .driver
= { .owner
= THIS_MODULE
},
3138 return phy_driver_register(&ar8xxx_phy_driver
);
3144 phy_driver_unregister(&ar8xxx_phy_driver
);
3147 module_init(ar8xxx_init
);
3148 module_exit(ar8xxx_exit
);
3149 MODULE_LICENSE("GPL");