2 * ar8216.c: AR8216 switch driver
4 * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>
5 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/list.h>
22 #include <linux/if_ether.h>
23 #include <linux/skbuff.h>
24 #include <linux/netdevice.h>
25 #include <linux/netlink.h>
26 #include <linux/of_device.h>
27 #include <linux/of_mdio.h>
28 #include <linux/of_net.h>
29 #include <linux/bitops.h>
30 #include <net/genetlink.h>
31 #include <linux/switch.h>
32 #include <linux/delay.h>
33 #include <linux/phy.h>
34 #include <linux/etherdevice.h>
35 #include <linux/lockdep.h>
36 #include <linux/ar8216_platform.h>
37 #include <linux/workqueue.h>
38 #include <linux/version.h>
42 extern const struct ar8xxx_chip ar8327_chip
;
43 extern const struct ar8xxx_chip ar8337_chip
;
45 #define MIB_DESC_BASIC(_s , _o, _n) \
50 .type = AR8XXX_MIB_BASIC, \
53 #define MIB_DESC_EXT(_s , _o, _n) \
58 .type = AR8XXX_MIB_EXTENDED, \
61 static const struct ar8xxx_mib_desc ar8216_mibs
[] = {
62 MIB_DESC_EXT(1, AR8216_STATS_RXBROAD
, "RxBroad"),
63 MIB_DESC_EXT(1, AR8216_STATS_RXPAUSE
, "RxPause"),
64 MIB_DESC_EXT(1, AR8216_STATS_RXMULTI
, "RxMulti"),
65 MIB_DESC_EXT(1, AR8216_STATS_RXFCSERR
, "RxFcsErr"),
66 MIB_DESC_EXT(1, AR8216_STATS_RXALIGNERR
, "RxAlignErr"),
67 MIB_DESC_EXT(1, AR8216_STATS_RXRUNT
, "RxRunt"),
68 MIB_DESC_EXT(1, AR8216_STATS_RXFRAGMENT
, "RxFragment"),
69 MIB_DESC_EXT(1, AR8216_STATS_RX64BYTE
, "Rx64Byte"),
70 MIB_DESC_EXT(1, AR8216_STATS_RX128BYTE
, "Rx128Byte"),
71 MIB_DESC_EXT(1, AR8216_STATS_RX256BYTE
, "Rx256Byte"),
72 MIB_DESC_EXT(1, AR8216_STATS_RX512BYTE
, "Rx512Byte"),
73 MIB_DESC_EXT(1, AR8216_STATS_RX1024BYTE
, "Rx1024Byte"),
74 MIB_DESC_EXT(1, AR8216_STATS_RXMAXBYTE
, "RxMaxByte"),
75 MIB_DESC_EXT(1, AR8216_STATS_RXTOOLONG
, "RxTooLong"),
76 MIB_DESC_BASIC(2, AR8216_STATS_RXGOODBYTE
, "RxGoodByte"),
77 MIB_DESC_EXT(2, AR8216_STATS_RXBADBYTE
, "RxBadByte"),
78 MIB_DESC_EXT(1, AR8216_STATS_RXOVERFLOW
, "RxOverFlow"),
79 MIB_DESC_EXT(1, AR8216_STATS_FILTERED
, "Filtered"),
80 MIB_DESC_EXT(1, AR8216_STATS_TXBROAD
, "TxBroad"),
81 MIB_DESC_EXT(1, AR8216_STATS_TXPAUSE
, "TxPause"),
82 MIB_DESC_EXT(1, AR8216_STATS_TXMULTI
, "TxMulti"),
83 MIB_DESC_EXT(1, AR8216_STATS_TXUNDERRUN
, "TxUnderRun"),
84 MIB_DESC_EXT(1, AR8216_STATS_TX64BYTE
, "Tx64Byte"),
85 MIB_DESC_EXT(1, AR8216_STATS_TX128BYTE
, "Tx128Byte"),
86 MIB_DESC_EXT(1, AR8216_STATS_TX256BYTE
, "Tx256Byte"),
87 MIB_DESC_EXT(1, AR8216_STATS_TX512BYTE
, "Tx512Byte"),
88 MIB_DESC_EXT(1, AR8216_STATS_TX1024BYTE
, "Tx1024Byte"),
89 MIB_DESC_EXT(1, AR8216_STATS_TXMAXBYTE
, "TxMaxByte"),
90 MIB_DESC_EXT(1, AR8216_STATS_TXOVERSIZE
, "TxOverSize"),
91 MIB_DESC_BASIC(2, AR8216_STATS_TXBYTE
, "TxByte"),
92 MIB_DESC_EXT(1, AR8216_STATS_TXCOLLISION
, "TxCollision"),
93 MIB_DESC_EXT(1, AR8216_STATS_TXABORTCOL
, "TxAbortCol"),
94 MIB_DESC_EXT(1, AR8216_STATS_TXMULTICOL
, "TxMultiCol"),
95 MIB_DESC_EXT(1, AR8216_STATS_TXSINGLECOL
, "TxSingleCol"),
96 MIB_DESC_EXT(1, AR8216_STATS_TXEXCDEFER
, "TxExcDefer"),
97 MIB_DESC_EXT(1, AR8216_STATS_TXDEFER
, "TxDefer"),
98 MIB_DESC_EXT(1, AR8216_STATS_TXLATECOL
, "TxLateCol"),
101 const struct ar8xxx_mib_desc ar8236_mibs
[39] = {
102 MIB_DESC_EXT(1, AR8236_STATS_RXBROAD
, "RxBroad"),
103 MIB_DESC_EXT(1, AR8236_STATS_RXPAUSE
, "RxPause"),
104 MIB_DESC_EXT(1, AR8236_STATS_RXMULTI
, "RxMulti"),
105 MIB_DESC_EXT(1, AR8236_STATS_RXFCSERR
, "RxFcsErr"),
106 MIB_DESC_EXT(1, AR8236_STATS_RXALIGNERR
, "RxAlignErr"),
107 MIB_DESC_EXT(1, AR8236_STATS_RXRUNT
, "RxRunt"),
108 MIB_DESC_EXT(1, AR8236_STATS_RXFRAGMENT
, "RxFragment"),
109 MIB_DESC_EXT(1, AR8236_STATS_RX64BYTE
, "Rx64Byte"),
110 MIB_DESC_EXT(1, AR8236_STATS_RX128BYTE
, "Rx128Byte"),
111 MIB_DESC_EXT(1, AR8236_STATS_RX256BYTE
, "Rx256Byte"),
112 MIB_DESC_EXT(1, AR8236_STATS_RX512BYTE
, "Rx512Byte"),
113 MIB_DESC_EXT(1, AR8236_STATS_RX1024BYTE
, "Rx1024Byte"),
114 MIB_DESC_EXT(1, AR8236_STATS_RX1518BYTE
, "Rx1518Byte"),
115 MIB_DESC_EXT(1, AR8236_STATS_RXMAXBYTE
, "RxMaxByte"),
116 MIB_DESC_EXT(1, AR8236_STATS_RXTOOLONG
, "RxTooLong"),
117 MIB_DESC_BASIC(2, AR8236_STATS_RXGOODBYTE
, "RxGoodByte"),
118 MIB_DESC_EXT(2, AR8236_STATS_RXBADBYTE
, "RxBadByte"),
119 MIB_DESC_EXT(1, AR8236_STATS_RXOVERFLOW
, "RxOverFlow"),
120 MIB_DESC_EXT(1, AR8236_STATS_FILTERED
, "Filtered"),
121 MIB_DESC_EXT(1, AR8236_STATS_TXBROAD
, "TxBroad"),
122 MIB_DESC_EXT(1, AR8236_STATS_TXPAUSE
, "TxPause"),
123 MIB_DESC_EXT(1, AR8236_STATS_TXMULTI
, "TxMulti"),
124 MIB_DESC_EXT(1, AR8236_STATS_TXUNDERRUN
, "TxUnderRun"),
125 MIB_DESC_EXT(1, AR8236_STATS_TX64BYTE
, "Tx64Byte"),
126 MIB_DESC_EXT(1, AR8236_STATS_TX128BYTE
, "Tx128Byte"),
127 MIB_DESC_EXT(1, AR8236_STATS_TX256BYTE
, "Tx256Byte"),
128 MIB_DESC_EXT(1, AR8236_STATS_TX512BYTE
, "Tx512Byte"),
129 MIB_DESC_EXT(1, AR8236_STATS_TX1024BYTE
, "Tx1024Byte"),
130 MIB_DESC_EXT(1, AR8236_STATS_TX1518BYTE
, "Tx1518Byte"),
131 MIB_DESC_EXT(1, AR8236_STATS_TXMAXBYTE
, "TxMaxByte"),
132 MIB_DESC_EXT(1, AR8236_STATS_TXOVERSIZE
, "TxOverSize"),
133 MIB_DESC_BASIC(2, AR8236_STATS_TXBYTE
, "TxByte"),
134 MIB_DESC_EXT(1, AR8236_STATS_TXCOLLISION
, "TxCollision"),
135 MIB_DESC_EXT(1, AR8236_STATS_TXABORTCOL
, "TxAbortCol"),
136 MIB_DESC_EXT(1, AR8236_STATS_TXMULTICOL
, "TxMultiCol"),
137 MIB_DESC_EXT(1, AR8236_STATS_TXSINGLECOL
, "TxSingleCol"),
138 MIB_DESC_EXT(1, AR8236_STATS_TXEXCDEFER
, "TxExcDefer"),
139 MIB_DESC_EXT(1, AR8236_STATS_TXDEFER
, "TxDefer"),
140 MIB_DESC_EXT(1, AR8236_STATS_TXLATECOL
, "TxLateCol"),
143 static DEFINE_MUTEX(ar8xxx_dev_list_lock
);
144 static LIST_HEAD(ar8xxx_dev_list
);
147 ar8xxx_mib_start(struct ar8xxx_priv
*priv
);
149 ar8xxx_mib_stop(struct ar8xxx_priv
*priv
);
151 /* inspired by phy_poll_reset in drivers/net/phy/phy_device.c */
153 ar8xxx_phy_poll_reset(struct mii_bus
*bus
)
155 unsigned int sleep_msecs
= 20;
158 for (elapsed
= sleep_msecs
; elapsed
<= 600;
159 elapsed
+= sleep_msecs
) {
161 for (i
= 0; i
< AR8XXX_NUM_PHYS
; i
++) {
162 ret
= mdiobus_read(bus
, i
, MII_BMCR
);
165 if (ret
& BMCR_RESET
)
167 if (i
== AR8XXX_NUM_PHYS
- 1) {
168 usleep_range(1000, 2000);
177 ar8xxx_phy_check_aneg(struct phy_device
*phydev
)
181 if (phydev
->autoneg
!= AUTONEG_ENABLE
)
184 * BMCR_ANENABLE might have been cleared
185 * by phy_init_hw in certain kernel versions
186 * therefore check for it
188 ret
= phy_read(phydev
, MII_BMCR
);
191 if (ret
& BMCR_ANENABLE
)
194 dev_info(&phydev
->mdio
.dev
, "ANEG disabled, re-enabling ...\n");
195 ret
|= BMCR_ANENABLE
| BMCR_ANRESTART
;
196 return phy_write(phydev
, MII_BMCR
, ret
);
200 ar8xxx_phy_init(struct ar8xxx_priv
*priv
)
205 bus
= priv
->sw_mii_bus
?: priv
->mii_bus
;
206 for (i
= 0; i
< AR8XXX_NUM_PHYS
; i
++) {
207 if (priv
->chip
->phy_fixup
)
208 priv
->chip
->phy_fixup(priv
, i
);
210 /* initialize the port itself */
211 mdiobus_write(bus
, i
, MII_ADVERTISE
,
212 ADVERTISE_ALL
| ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
);
213 if (ar8xxx_has_gige(priv
))
214 mdiobus_write(bus
, i
, MII_CTRL1000
, ADVERTISE_1000FULL
);
215 mdiobus_write(bus
, i
, MII_BMCR
, BMCR_RESET
| BMCR_ANENABLE
);
218 ar8xxx_phy_poll_reset(bus
);
222 ar8xxx_mii_read32(struct ar8xxx_priv
*priv
, int phy_id
, int regnum
)
224 struct mii_bus
*bus
= priv
->mii_bus
;
227 lo
= bus
->read(bus
, phy_id
, regnum
);
228 hi
= bus
->read(bus
, phy_id
, regnum
+ 1);
230 return (hi
<< 16) | lo
;
234 ar8xxx_mii_write32(struct ar8xxx_priv
*priv
, int phy_id
, int regnum
, u32 val
)
236 struct mii_bus
*bus
= priv
->mii_bus
;
240 hi
= (u16
) (val
>> 16);
242 if (priv
->chip
->mii_lo_first
)
244 bus
->write(bus
, phy_id
, regnum
, lo
);
245 bus
->write(bus
, phy_id
, regnum
+ 1, hi
);
247 bus
->write(bus
, phy_id
, regnum
+ 1, hi
);
248 bus
->write(bus
, phy_id
, regnum
, lo
);
253 ar8xxx_read(struct ar8xxx_priv
*priv
, int reg
)
255 struct mii_bus
*bus
= priv
->mii_bus
;
259 split_addr((u32
) reg
, &r1
, &r2
, &page
);
261 mutex_lock(&bus
->mdio_lock
);
263 bus
->write(bus
, 0x18, 0, page
);
264 wait_for_page_switch();
265 val
= ar8xxx_mii_read32(priv
, 0x10 | r2
, r1
);
267 mutex_unlock(&bus
->mdio_lock
);
273 ar8xxx_write(struct ar8xxx_priv
*priv
, int reg
, u32 val
)
275 struct mii_bus
*bus
= priv
->mii_bus
;
278 split_addr((u32
) reg
, &r1
, &r2
, &page
);
280 mutex_lock(&bus
->mdio_lock
);
282 bus
->write(bus
, 0x18, 0, page
);
283 wait_for_page_switch();
284 ar8xxx_mii_write32(priv
, 0x10 | r2
, r1
, val
);
286 mutex_unlock(&bus
->mdio_lock
);
290 ar8xxx_rmw(struct ar8xxx_priv
*priv
, int reg
, u32 mask
, u32 val
)
292 struct mii_bus
*bus
= priv
->mii_bus
;
296 split_addr((u32
) reg
, &r1
, &r2
, &page
);
298 mutex_lock(&bus
->mdio_lock
);
300 bus
->write(bus
, 0x18, 0, page
);
301 wait_for_page_switch();
303 ret
= ar8xxx_mii_read32(priv
, 0x10 | r2
, r1
);
306 ar8xxx_mii_write32(priv
, 0x10 | r2
, r1
, ret
);
308 mutex_unlock(&bus
->mdio_lock
);
313 ar8xxx_phy_dbg_read(struct ar8xxx_priv
*priv
, int phy_addr
,
314 u16 dbg_addr
, u16
*dbg_data
)
316 struct mii_bus
*bus
= priv
->mii_bus
;
318 mutex_lock(&bus
->mdio_lock
);
319 bus
->write(bus
, phy_addr
, MII_ATH_DBG_ADDR
, dbg_addr
);
320 *dbg_data
= bus
->read(bus
, phy_addr
, MII_ATH_DBG_DATA
);
321 mutex_unlock(&bus
->mdio_lock
);
325 ar8xxx_phy_dbg_write(struct ar8xxx_priv
*priv
, int phy_addr
,
326 u16 dbg_addr
, u16 dbg_data
)
328 struct mii_bus
*bus
= priv
->mii_bus
;
330 mutex_lock(&bus
->mdio_lock
);
331 bus
->write(bus
, phy_addr
, MII_ATH_DBG_ADDR
, dbg_addr
);
332 bus
->write(bus
, phy_addr
, MII_ATH_DBG_DATA
, dbg_data
);
333 mutex_unlock(&bus
->mdio_lock
);
337 ar8xxx_phy_mmd_prep(struct mii_bus
*bus
, int phy_addr
, u16 addr
, u16 reg
)
339 bus
->write(bus
, phy_addr
, MII_ATH_MMD_ADDR
, addr
);
340 bus
->write(bus
, phy_addr
, MII_ATH_MMD_DATA
, reg
);
341 bus
->write(bus
, phy_addr
, MII_ATH_MMD_ADDR
, addr
| 0x4000);
345 ar8xxx_phy_mmd_write(struct ar8xxx_priv
*priv
, int phy_addr
, u16 addr
, u16 reg
, u16 data
)
347 struct mii_bus
*bus
= priv
->mii_bus
;
349 mutex_lock(&bus
->mdio_lock
);
350 ar8xxx_phy_mmd_prep(bus
, phy_addr
, addr
, reg
);
351 bus
->write(bus
, phy_addr
, MII_ATH_MMD_DATA
, data
);
352 mutex_unlock(&bus
->mdio_lock
);
356 ar8xxx_phy_mmd_read(struct ar8xxx_priv
*priv
, int phy_addr
, u16 addr
, u16 reg
)
358 struct mii_bus
*bus
= priv
->mii_bus
;
361 mutex_lock(&bus
->mdio_lock
);
362 ar8xxx_phy_mmd_prep(bus
, phy_addr
, addr
, reg
);
363 data
= bus
->read(bus
, phy_addr
, MII_ATH_MMD_DATA
);
364 mutex_unlock(&bus
->mdio_lock
);
370 ar8xxx_reg_wait(struct ar8xxx_priv
*priv
, u32 reg
, u32 mask
, u32 val
,
375 for (i
= 0; i
< timeout
; i
++) {
378 t
= ar8xxx_read(priv
, reg
);
379 if ((t
& mask
) == val
)
382 usleep_range(1000, 2000);
390 ar8xxx_mib_op(struct ar8xxx_priv
*priv
, u32 op
)
392 unsigned mib_func
= priv
->chip
->mib_func
;
395 lockdep_assert_held(&priv
->mib_lock
);
397 /* Capture the hardware statistics for all ports */
398 ar8xxx_rmw(priv
, mib_func
, AR8216_MIB_FUNC
, (op
<< AR8216_MIB_FUNC_S
));
400 /* Wait for the capturing to complete. */
401 ret
= ar8xxx_reg_wait(priv
, mib_func
, AR8216_MIB_BUSY
, 0, 10);
412 ar8xxx_mib_capture(struct ar8xxx_priv
*priv
)
414 return ar8xxx_mib_op(priv
, AR8216_MIB_FUNC_CAPTURE
);
418 ar8xxx_mib_flush(struct ar8xxx_priv
*priv
)
420 return ar8xxx_mib_op(priv
, AR8216_MIB_FUNC_FLUSH
);
424 ar8xxx_mib_fetch_port_stat(struct ar8xxx_priv
*priv
, int port
, bool flush
)
430 WARN_ON(port
>= priv
->dev
.ports
);
432 lockdep_assert_held(&priv
->mib_lock
);
434 base
= priv
->chip
->reg_port_stats_start
+
435 priv
->chip
->reg_port_stats_length
* port
;
437 mib_stats
= &priv
->mib_stats
[port
* priv
->chip
->num_mibs
];
438 for (i
= 0; i
< priv
->chip
->num_mibs
; i
++) {
439 const struct ar8xxx_mib_desc
*mib
;
442 mib
= &priv
->chip
->mib_decs
[i
];
443 if (mib
->type
> priv
->mib_type
)
445 t
= ar8xxx_read(priv
, base
+ mib
->offset
);
446 if (mib
->size
== 2) {
449 hi
= ar8xxx_read(priv
, base
+ mib
->offset
+ 4);
462 ar8216_read_port_link(struct ar8xxx_priv
*priv
, int port
,
463 struct switch_port_link
*link
)
468 memset(link
, '\0', sizeof(*link
));
470 status
= priv
->chip
->read_port_status(priv
, port
);
472 link
->aneg
= !!(status
& AR8216_PORT_STATUS_LINK_AUTO
);
474 link
->link
= !!(status
& AR8216_PORT_STATUS_LINK_UP
);
478 if (priv
->get_port_link
) {
481 err
= priv
->get_port_link(port
);
490 link
->duplex
= !!(status
& AR8216_PORT_STATUS_DUPLEX
);
491 link
->tx_flow
= !!(status
& AR8216_PORT_STATUS_TXFLOW
);
492 link
->rx_flow
= !!(status
& AR8216_PORT_STATUS_RXFLOW
);
494 if (link
->aneg
&& link
->duplex
&& priv
->chip
->read_port_eee_status
)
495 link
->eee
= priv
->chip
->read_port_eee_status(priv
, port
);
497 speed
= (status
& AR8216_PORT_STATUS_SPEED
) >>
498 AR8216_PORT_STATUS_SPEED_S
;
501 case AR8216_PORT_SPEED_10M
:
502 link
->speed
= SWITCH_PORT_SPEED_10
;
504 case AR8216_PORT_SPEED_100M
:
505 link
->speed
= SWITCH_PORT_SPEED_100
;
507 case AR8216_PORT_SPEED_1000M
:
508 link
->speed
= SWITCH_PORT_SPEED_1000
;
511 link
->speed
= SWITCH_PORT_SPEED_UNKNOWN
;
516 static struct sk_buff
*
517 ar8216_mangle_tx(struct net_device
*dev
, struct sk_buff
*skb
)
519 struct ar8xxx_priv
*priv
= dev
->phy_ptr
;
528 if (unlikely(skb_headroom(skb
) < 2)) {
529 if (pskb_expand_head(skb
, 2, 0, GFP_ATOMIC
) < 0)
533 buf
= skb_push(skb
, 2);
541 dev_kfree_skb_any(skb
);
546 ar8216_mangle_rx(struct net_device
*dev
, struct sk_buff
*skb
)
548 struct ar8xxx_priv
*priv
;
556 /* don't strip the header if vlan mode is disabled */
560 /* strip header, get vlan id */
564 /* check for vlan header presence */
565 if ((buf
[12 + 2] != 0x81) || (buf
[13 + 2] != 0x00))
570 /* no need to fix up packets coming from a tagged source */
571 if (priv
->vlan_tagged
& (1 << port
))
574 /* lookup port vid from local table, the switch passes an invalid vlan id */
575 vlan
= priv
->vlan_id
[priv
->pvid
[port
]];
578 buf
[14 + 2] |= vlan
>> 8;
579 buf
[15 + 2] = vlan
& 0xff;
583 ar8216_wait_bit(struct ar8xxx_priv
*priv
, int reg
, u32 mask
, u32 val
)
589 t
= ar8xxx_read(priv
, reg
);
590 if ((t
& mask
) == val
)
600 pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
601 (unsigned int) reg
, t
, mask
, val
);
606 ar8216_vtu_op(struct ar8xxx_priv
*priv
, u32 op
, u32 val
)
608 if (ar8216_wait_bit(priv
, AR8216_REG_VTU
, AR8216_VTU_ACTIVE
, 0))
610 if ((op
& AR8216_VTU_OP
) == AR8216_VTU_OP_LOAD
) {
611 val
&= AR8216_VTUDATA_MEMBER
;
612 val
|= AR8216_VTUDATA_VALID
;
613 ar8xxx_write(priv
, AR8216_REG_VTU_DATA
, val
);
615 op
|= AR8216_VTU_ACTIVE
;
616 ar8xxx_write(priv
, AR8216_REG_VTU
, op
);
620 ar8216_vtu_flush(struct ar8xxx_priv
*priv
)
622 ar8216_vtu_op(priv
, AR8216_VTU_OP_FLUSH
, 0);
626 ar8216_vtu_load_vlan(struct ar8xxx_priv
*priv
, u32 vid
, u32 port_mask
)
630 op
= AR8216_VTU_OP_LOAD
| (vid
<< AR8216_VTU_VID_S
);
631 ar8216_vtu_op(priv
, op
, port_mask
);
635 ar8216_atu_flush(struct ar8xxx_priv
*priv
)
639 ret
= ar8216_wait_bit(priv
, AR8216_REG_ATU_FUNC0
, AR8216_ATU_ACTIVE
, 0);
641 ar8xxx_write(priv
, AR8216_REG_ATU_FUNC0
, AR8216_ATU_OP_FLUSH
|
648 ar8216_atu_flush_port(struct ar8xxx_priv
*priv
, int port
)
653 ret
= ar8216_wait_bit(priv
, AR8216_REG_ATU_FUNC0
, AR8216_ATU_ACTIVE
, 0);
655 t
= (port
<< AR8216_ATU_PORT_NUM_S
) | AR8216_ATU_OP_FLUSH_PORT
;
656 t
|= AR8216_ATU_ACTIVE
;
657 ar8xxx_write(priv
, AR8216_REG_ATU_FUNC0
, t
);
664 ar8216_read_port_status(struct ar8xxx_priv
*priv
, int port
)
666 return ar8xxx_read(priv
, AR8216_REG_PORT_STATUS(port
));
670 __ar8216_setup_port(struct ar8xxx_priv
*priv
, int port
, u32 members
,
678 pvid
= priv
->vlan_id
[priv
->pvid
[port
]];
679 if (priv
->vlan_tagged
& (1 << port
))
680 egress
= AR8216_OUT_ADD_VLAN
;
682 egress
= AR8216_OUT_STRIP_VLAN
;
683 ingress
= AR8216_IN_SECURE
;
686 egress
= AR8216_OUT_KEEP
;
687 ingress
= AR8216_IN_PORT_ONLY
;
690 header
= ath_hdr_en
? AR8216_PORT_CTRL_HEADER
: 0;
692 ar8xxx_rmw(priv
, AR8216_REG_PORT_CTRL(port
),
693 AR8216_PORT_CTRL_LEARN
| AR8216_PORT_CTRL_VLAN_MODE
|
694 AR8216_PORT_CTRL_SINGLE_VLAN
| AR8216_PORT_CTRL_STATE
|
695 AR8216_PORT_CTRL_HEADER
| AR8216_PORT_CTRL_LEARN_LOCK
,
696 AR8216_PORT_CTRL_LEARN
| header
|
697 (egress
<< AR8216_PORT_CTRL_VLAN_MODE_S
) |
698 (AR8216_PORT_STATE_FORWARD
<< AR8216_PORT_CTRL_STATE_S
));
700 ar8xxx_rmw(priv
, AR8216_REG_PORT_VLAN(port
),
701 AR8216_PORT_VLAN_DEST_PORTS
| AR8216_PORT_VLAN_MODE
|
702 AR8216_PORT_VLAN_DEFAULT_ID
,
703 (members
<< AR8216_PORT_VLAN_DEST_PORTS_S
) |
704 (ingress
<< AR8216_PORT_VLAN_MODE_S
) |
705 (pvid
<< AR8216_PORT_VLAN_DEFAULT_ID_S
));
709 ar8216_setup_port(struct ar8xxx_priv
*priv
, int port
, u32 members
)
711 return __ar8216_setup_port(priv
, port
, members
,
712 chip_is_ar8216(priv
) && priv
->vlan
&&
713 port
== AR8216_PORT_CPU
);
717 ar8216_hw_init(struct ar8xxx_priv
*priv
)
719 if (priv
->initialized
)
722 ar8xxx_write(priv
, AR8216_REG_CTRL
, AR8216_CTRL_RESET
);
723 ar8xxx_reg_wait(priv
, AR8216_REG_CTRL
, AR8216_CTRL_RESET
, 0, 1000);
725 ar8xxx_phy_init(priv
);
727 priv
->initialized
= true;
732 ar8216_init_globals(struct ar8xxx_priv
*priv
)
734 /* standard atheros magic */
735 ar8xxx_write(priv
, 0x38, 0xc000050e);
737 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
738 AR8216_GCTRL_MTU
, 1518 + 8 + 2);
742 __ar8216_init_port(struct ar8xxx_priv
*priv
, int port
,
743 bool cpu_ge
, bool flow_en
)
745 /* Enable port learning and tx */
746 ar8xxx_write(priv
, AR8216_REG_PORT_CTRL(port
),
747 AR8216_PORT_CTRL_LEARN
|
748 (4 << AR8216_PORT_CTRL_STATE_S
));
750 ar8xxx_write(priv
, AR8216_REG_PORT_VLAN(port
), 0);
752 if (port
== AR8216_PORT_CPU
) {
753 ar8xxx_write(priv
, AR8216_REG_PORT_STATUS(port
),
754 AR8216_PORT_STATUS_LINK_UP
|
755 (cpu_ge
? AR8216_PORT_SPEED_1000M
: AR8216_PORT_SPEED_100M
) |
756 AR8216_PORT_STATUS_TXMAC
|
757 AR8216_PORT_STATUS_RXMAC
|
758 (flow_en
? AR8216_PORT_STATUS_RXFLOW
: 0) |
759 (flow_en
? AR8216_PORT_STATUS_TXFLOW
: 0) |
760 AR8216_PORT_STATUS_DUPLEX
);
762 ar8xxx_write(priv
, AR8216_REG_PORT_STATUS(port
),
763 AR8216_PORT_STATUS_LINK_AUTO
);
768 ar8216_init_port(struct ar8xxx_priv
*priv
, int port
)
770 __ar8216_init_port(priv
, port
, ar8xxx_has_gige(priv
),
771 chip_is_ar8316(priv
));
775 ar8216_wait_atu_ready(struct ar8xxx_priv
*priv
, u16 r2
, u16 r1
)
779 while (ar8xxx_mii_read32(priv
, r2
, r1
) & AR8216_ATU_ACTIVE
&& --timeout
) {
785 pr_err("ar8216: timeout waiting for atu to become ready\n");
788 static void ar8216_get_arl_entry(struct ar8xxx_priv
*priv
,
789 struct arl_entry
*a
, u32
*status
, enum arl_op op
)
791 struct mii_bus
*bus
= priv
->mii_bus
;
793 u16 r1_func0
, r1_func1
, r1_func2
;
794 u32 t
, val0
, val1
, val2
;
796 split_addr(AR8216_REG_ATU_FUNC0
, &r1_func0
, &r2
, &page
);
799 r1_func1
= (AR8216_REG_ATU_FUNC1
>> 1) & 0x1e;
800 r1_func2
= (AR8216_REG_ATU_FUNC2
>> 1) & 0x1e;
803 case AR8XXX_ARL_INITIALIZE
:
804 /* all ATU registers are on the same page
805 * therefore set page only once
807 bus
->write(bus
, 0x18, 0, page
);
808 wait_for_page_switch();
810 ar8216_wait_atu_ready(priv
, r2
, r1_func0
);
812 ar8xxx_mii_write32(priv
, r2
, r1_func0
, AR8216_ATU_OP_GET_NEXT
);
813 ar8xxx_mii_write32(priv
, r2
, r1_func1
, 0);
814 ar8xxx_mii_write32(priv
, r2
, r1_func2
, 0);
816 case AR8XXX_ARL_GET_NEXT
:
817 t
= ar8xxx_mii_read32(priv
, r2
, r1_func0
);
818 t
|= AR8216_ATU_ACTIVE
;
819 ar8xxx_mii_write32(priv
, r2
, r1_func0
, t
);
820 ar8216_wait_atu_ready(priv
, r2
, r1_func0
);
822 val0
= ar8xxx_mii_read32(priv
, r2
, r1_func0
);
823 val1
= ar8xxx_mii_read32(priv
, r2
, r1_func1
);
824 val2
= ar8xxx_mii_read32(priv
, r2
, r1_func2
);
826 *status
= (val2
& AR8216_ATU_STATUS
) >> AR8216_ATU_STATUS_S
;
830 a
->portmap
= (val2
& AR8216_ATU_PORTS
) >> AR8216_ATU_PORTS_S
;
831 a
->mac
[0] = (val0
& AR8216_ATU_ADDR5
) >> AR8216_ATU_ADDR5_S
;
832 a
->mac
[1] = (val0
& AR8216_ATU_ADDR4
) >> AR8216_ATU_ADDR4_S
;
833 a
->mac
[2] = (val1
& AR8216_ATU_ADDR3
) >> AR8216_ATU_ADDR3_S
;
834 a
->mac
[3] = (val1
& AR8216_ATU_ADDR2
) >> AR8216_ATU_ADDR2_S
;
835 a
->mac
[4] = (val1
& AR8216_ATU_ADDR1
) >> AR8216_ATU_ADDR1_S
;
836 a
->mac
[5] = (val1
& AR8216_ATU_ADDR0
) >> AR8216_ATU_ADDR0_S
;
842 ar8216_phy_read(struct ar8xxx_priv
*priv
, int addr
, int regnum
)
847 if (addr
>= AR8216_NUM_PORTS
)
849 t
= (regnum
<< AR8216_MDIO_CTRL_REG_ADDR_S
) |
850 (addr
<< AR8216_MDIO_CTRL_PHY_ADDR_S
) |
851 AR8216_MDIO_CTRL_MASTER_EN
|
852 AR8216_MDIO_CTRL_BUSY
|
853 AR8216_MDIO_CTRL_CMD_READ
;
855 ar8xxx_write(priv
, AR8216_REG_MDIO_CTRL
, t
);
856 err
= ar8xxx_reg_wait(priv
, AR8216_REG_MDIO_CTRL
,
857 AR8216_MDIO_CTRL_BUSY
, 0, 5);
859 val
= ar8xxx_read(priv
, AR8216_REG_MDIO_CTRL
);
861 return val
& AR8216_MDIO_CTRL_DATA_M
;
865 ar8216_phy_write(struct ar8xxx_priv
*priv
, int addr
, int regnum
, u16 val
)
870 if (addr
>= AR8216_NUM_PORTS
)
873 t
= (addr
<< AR8216_MDIO_CTRL_PHY_ADDR_S
) |
874 (regnum
<< AR8216_MDIO_CTRL_REG_ADDR_S
) |
875 AR8216_MDIO_CTRL_MASTER_EN
|
876 AR8216_MDIO_CTRL_BUSY
|
877 AR8216_MDIO_CTRL_CMD_WRITE
|
880 ar8xxx_write(priv
, AR8216_REG_MDIO_CTRL
, t
);
881 ret
= ar8xxx_reg_wait(priv
, AR8216_REG_MDIO_CTRL
,
882 AR8216_MDIO_CTRL_BUSY
, 0, 5);
888 ar8229_hw_init(struct ar8xxx_priv
*priv
)
892 if (priv
->initialized
)
895 ar8xxx_write(priv
, AR8216_REG_CTRL
, AR8216_CTRL_RESET
);
896 ar8xxx_reg_wait(priv
, AR8216_REG_CTRL
, AR8216_CTRL_RESET
, 0, 1000);
898 phy_if_mode
= of_get_phy_mode(priv
->pdev
->of_node
);
900 if (phy_if_mode
== PHY_INTERFACE_MODE_GMII
) {
901 ar8xxx_write(priv
, AR8229_REG_OPER_MODE0
,
902 AR8229_OPER_MODE0_MAC_GMII_EN
);
903 } else if (phy_if_mode
== PHY_INTERFACE_MODE_MII
) {
904 ar8xxx_write(priv
, AR8229_REG_OPER_MODE0
,
905 AR8229_OPER_MODE0_PHY_MII_EN
);
907 pr_err("ar8229: unsupported mii mode\n");
911 if (priv
->port4_phy
) {
912 ar8xxx_write(priv
, AR8229_REG_OPER_MODE1
,
913 AR8229_REG_OPER_MODE1_PHY4_MII_EN
);
914 /* disable port5 to prevent mii conflict */
915 ar8xxx_write(priv
, AR8216_REG_PORT_STATUS(5), 0);
918 ar8xxx_phy_init(priv
);
920 priv
->initialized
= true;
925 ar8229_init_globals(struct ar8xxx_priv
*priv
)
928 /* Enable CPU port, and disable mirror port */
929 ar8xxx_write(priv
, AR8216_REG_GLOBAL_CPUPORT
,
930 AR8216_GLOBAL_CPUPORT_EN
|
931 (15 << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S
));
933 /* Setup TAG priority mapping */
934 ar8xxx_write(priv
, AR8216_REG_TAG_PRIORITY
, 0xfa50);
936 /* Enable aging, MAC replacing */
937 ar8xxx_write(priv
, AR8216_REG_ATU_CTRL
,
938 0x2b /* 5 min age time */ |
939 AR8216_ATU_CTRL_AGE_EN
|
940 AR8216_ATU_CTRL_LEARN_CHANGE
);
942 /* Enable ARP frame acknowledge */
943 ar8xxx_reg_set(priv
, AR8229_REG_QM_CTRL
,
944 AR8229_QM_CTRL_ARP_EN
);
946 /* Enable Broadcast/Multicast frames transmitted to the CPU */
947 ar8xxx_reg_set(priv
, AR8216_REG_FLOOD_MASK
,
948 AR8229_FLOOD_MASK_BC_DP(0) |
949 AR8229_FLOOD_MASK_MC_DP(0));
952 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
953 AR8236_GCTRL_MTU
, AR8236_GCTRL_MTU
);
955 /* Enable MIB counters */
956 ar8xxx_reg_set(priv
, AR8216_REG_MIB_FUNC
,
959 /* setup Service TAG */
960 ar8xxx_rmw(priv
, AR8216_REG_SERVICE_TAG
, AR8216_SERVICE_TAG_M
, 0);
964 ar8229_init_port(struct ar8xxx_priv
*priv
, int port
)
966 __ar8216_init_port(priv
, port
, true, true);
971 ar7240sw_hw_init(struct ar8xxx_priv
*priv
)
973 if (priv
->initialized
)
976 ar8xxx_write(priv
, AR8216_REG_CTRL
, AR8216_CTRL_RESET
);
977 ar8xxx_reg_wait(priv
, AR8216_REG_CTRL
, AR8216_CTRL_RESET
, 0, 1000);
980 /* disable port5 to prevent mii conflict */
981 ar8xxx_write(priv
, AR8216_REG_PORT_STATUS(5), 0);
983 ar8xxx_phy_init(priv
);
985 priv
->initialized
= true;
990 ar7240sw_init_globals(struct ar8xxx_priv
*priv
)
993 /* Enable CPU port, and disable mirror port */
994 ar8xxx_write(priv
, AR8216_REG_GLOBAL_CPUPORT
,
995 AR8216_GLOBAL_CPUPORT_EN
|
996 (15 << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S
));
998 /* Setup TAG priority mapping */
999 ar8xxx_write(priv
, AR8216_REG_TAG_PRIORITY
, 0xfa50);
1001 /* Enable ARP frame acknowledge, aging, MAC replacing */
1002 ar8xxx_write(priv
, AR8216_REG_ATU_CTRL
,
1003 AR8216_ATU_CTRL_RESERVED
|
1004 0x2b /* 5 min age time */ |
1005 AR8216_ATU_CTRL_AGE_EN
|
1006 AR8216_ATU_CTRL_ARP_EN
|
1007 AR8216_ATU_CTRL_LEARN_CHANGE
);
1009 /* Enable Broadcast frames transmitted to the CPU */
1010 ar8xxx_reg_set(priv
, AR8216_REG_FLOOD_MASK
,
1011 AR8236_FM_CPU_BROADCAST_EN
);
1014 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
1018 /* setup Service TAG */
1019 ar8xxx_rmw(priv
, AR8216_REG_SERVICE_TAG
, AR8216_SERVICE_TAG_M
, 0);
1023 ar7240sw_setup_port(struct ar8xxx_priv
*priv
, int port
, u32 members
)
1025 return __ar8216_setup_port(priv
, port
, members
, false);
1029 ar8236_setup_port(struct ar8xxx_priv
*priv
, int port
, u32 members
)
1031 u32 egress
, ingress
;
1035 pvid
= priv
->vlan_id
[priv
->pvid
[port
]];
1036 if (priv
->vlan_tagged
& (1 << port
))
1037 egress
= AR8216_OUT_ADD_VLAN
;
1039 egress
= AR8216_OUT_STRIP_VLAN
;
1040 ingress
= AR8216_IN_SECURE
;
1043 egress
= AR8216_OUT_KEEP
;
1044 ingress
= AR8216_IN_PORT_ONLY
;
1047 ar8xxx_rmw(priv
, AR8216_REG_PORT_CTRL(port
),
1048 AR8216_PORT_CTRL_LEARN
| AR8216_PORT_CTRL_VLAN_MODE
|
1049 AR8216_PORT_CTRL_SINGLE_VLAN
| AR8216_PORT_CTRL_STATE
|
1050 AR8216_PORT_CTRL_HEADER
| AR8216_PORT_CTRL_LEARN_LOCK
,
1051 AR8216_PORT_CTRL_LEARN
|
1052 (egress
<< AR8216_PORT_CTRL_VLAN_MODE_S
) |
1053 (AR8216_PORT_STATE_FORWARD
<< AR8216_PORT_CTRL_STATE_S
));
1055 ar8xxx_rmw(priv
, AR8236_REG_PORT_VLAN(port
),
1056 AR8236_PORT_VLAN_DEFAULT_ID
,
1057 (pvid
<< AR8236_PORT_VLAN_DEFAULT_ID_S
));
1059 ar8xxx_rmw(priv
, AR8236_REG_PORT_VLAN2(port
),
1060 AR8236_PORT_VLAN2_VLAN_MODE
|
1061 AR8236_PORT_VLAN2_MEMBER
,
1062 (ingress
<< AR8236_PORT_VLAN2_VLAN_MODE_S
) |
1063 (members
<< AR8236_PORT_VLAN2_MEMBER_S
));
1067 ar8236_init_globals(struct ar8xxx_priv
*priv
)
1069 /* enable jumbo frames */
1070 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
1071 AR8316_GCTRL_MTU
, 9018 + 8 + 2);
1073 /* enable cpu port to receive arp frames */
1074 ar8xxx_reg_set(priv
, AR8216_REG_ATU_CTRL
,
1075 AR8236_ATU_CTRL_RES
);
1077 /* enable cpu port to receive multicast and broadcast frames */
1078 ar8xxx_reg_set(priv
, AR8216_REG_FLOOD_MASK
,
1079 AR8236_FM_CPU_BROADCAST_EN
| AR8236_FM_CPU_BCAST_FWD_EN
);
1081 /* Enable MIB counters */
1082 ar8xxx_rmw(priv
, AR8216_REG_MIB_FUNC
, AR8216_MIB_FUNC
| AR8236_MIB_EN
,
1083 (AR8216_MIB_FUNC_NO_OP
<< AR8216_MIB_FUNC_S
) |
1088 ar8316_hw_init(struct ar8xxx_priv
*priv
)
1092 val
= ar8xxx_read(priv
, AR8316_REG_POSTRIP
);
1094 if (priv
->phy
->interface
== PHY_INTERFACE_MODE_RGMII
) {
1095 if (priv
->port4_phy
) {
1096 /* value taken from Ubiquiti RouterStation Pro */
1097 newval
= 0x81461bea;
1098 pr_info("ar8316: Using port 4 as PHY\n");
1100 newval
= 0x01261be2;
1101 pr_info("ar8316: Using port 4 as switch port\n");
1103 } else if (priv
->phy
->interface
== PHY_INTERFACE_MODE_GMII
) {
1104 /* value taken from AVM Fritz!Box 7390 sources */
1105 newval
= 0x010e5b71;
1107 /* no known value for phy interface */
1108 pr_err("ar8316: unsupported mii mode: %d.\n",
1109 priv
->phy
->interface
);
1116 ar8xxx_write(priv
, AR8316_REG_POSTRIP
, newval
);
1118 if (priv
->port4_phy
&&
1119 priv
->phy
->interface
== PHY_INTERFACE_MODE_RGMII
) {
1120 /* work around for phy4 rgmii mode */
1121 ar8xxx_phy_dbg_write(priv
, 4, 0x12, 0x480c);
1123 ar8xxx_phy_dbg_write(priv
, 4, 0x0, 0x824e);
1125 ar8xxx_phy_dbg_write(priv
, 4, 0x5, 0x3d47);
1129 ar8xxx_phy_init(priv
);
1132 priv
->initialized
= true;
1137 ar8316_init_globals(struct ar8xxx_priv
*priv
)
1139 /* standard atheros magic */
1140 ar8xxx_write(priv
, 0x38, 0xc000050e);
1142 /* enable cpu port to receive multicast and broadcast frames */
1143 ar8xxx_write(priv
, AR8216_REG_FLOOD_MASK
, 0x003f003f);
1145 /* enable jumbo frames */
1146 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
1147 AR8316_GCTRL_MTU
, 9018 + 8 + 2);
1149 /* Enable MIB counters */
1150 ar8xxx_rmw(priv
, AR8216_REG_MIB_FUNC
, AR8216_MIB_FUNC
| AR8236_MIB_EN
,
1151 (AR8216_MIB_FUNC_NO_OP
<< AR8216_MIB_FUNC_S
) |
1156 ar8xxx_sw_set_vlan(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1157 struct switch_val
*val
)
1159 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1160 priv
->vlan
= !!val
->value
.i
;
1165 ar8xxx_sw_get_vlan(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1166 struct switch_val
*val
)
1168 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1169 val
->value
.i
= priv
->vlan
;
1175 ar8xxx_sw_set_pvid(struct switch_dev
*dev
, int port
, int vlan
)
1177 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1179 /* make sure no invalid PVIDs get set */
1181 if (vlan
< 0 || vlan
>= dev
->vlans
||
1182 port
< 0 || port
>= AR8X16_MAX_PORTS
)
1185 priv
->pvid
[port
] = vlan
;
1190 ar8xxx_sw_get_pvid(struct switch_dev
*dev
, int port
, int *vlan
)
1192 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1194 if (port
< 0 || port
>= AR8X16_MAX_PORTS
)
1197 *vlan
= priv
->pvid
[port
];
1202 ar8xxx_sw_set_vid(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1203 struct switch_val
*val
)
1205 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1207 if (val
->port_vlan
>= AR8X16_MAX_VLANS
)
1210 priv
->vlan_id
[val
->port_vlan
] = val
->value
.i
;
1215 ar8xxx_sw_get_vid(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1216 struct switch_val
*val
)
1218 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1219 val
->value
.i
= priv
->vlan_id
[val
->port_vlan
];
1224 ar8xxx_sw_get_port_link(struct switch_dev
*dev
, int port
,
1225 struct switch_port_link
*link
)
1227 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1229 ar8216_read_port_link(priv
, port
, link
);
1234 ar8xxx_sw_get_ports(struct switch_dev
*dev
, struct switch_val
*val
)
1236 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1240 if (val
->port_vlan
>= AR8X16_MAX_VLANS
)
1243 ports
= priv
->vlan_table
[val
->port_vlan
];
1245 for (i
= 0; i
< dev
->ports
; i
++) {
1246 struct switch_port
*p
;
1248 if (!(ports
& (1 << i
)))
1251 p
= &val
->value
.ports
[val
->len
++];
1253 if (priv
->vlan_tagged
& (1 << i
))
1254 p
->flags
= (1 << SWITCH_PORT_FLAG_TAGGED
);
1262 ar8xxx_sw_set_ports(struct switch_dev
*dev
, struct switch_val
*val
)
1264 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1265 u8
*vt
= &priv
->vlan_table
[val
->port_vlan
];
1269 for (i
= 0; i
< val
->len
; i
++) {
1270 struct switch_port
*p
= &val
->value
.ports
[i
];
1272 if (p
->flags
& (1 << SWITCH_PORT_FLAG_TAGGED
)) {
1273 priv
->vlan_tagged
|= (1 << p
->id
);
1275 priv
->vlan_tagged
&= ~(1 << p
->id
);
1276 priv
->pvid
[p
->id
] = val
->port_vlan
;
1278 /* make sure that an untagged port does not
1279 * appear in other vlans */
1280 for (j
= 0; j
< AR8X16_MAX_VLANS
; j
++) {
1281 if (j
== val
->port_vlan
)
1283 priv
->vlan_table
[j
] &= ~(1 << p
->id
);
1293 ar8216_set_mirror_regs(struct ar8xxx_priv
*priv
)
1297 /* reset all mirror registers */
1298 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CPUPORT
,
1299 AR8216_GLOBAL_CPUPORT_MIRROR_PORT
,
1300 (0xF << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S
));
1301 for (port
= 0; port
< AR8216_NUM_PORTS
; port
++) {
1302 ar8xxx_reg_clear(priv
, AR8216_REG_PORT_CTRL(port
),
1303 AR8216_PORT_CTRL_MIRROR_RX
);
1305 ar8xxx_reg_clear(priv
, AR8216_REG_PORT_CTRL(port
),
1306 AR8216_PORT_CTRL_MIRROR_TX
);
1309 /* now enable mirroring if necessary */
1310 if (priv
->source_port
>= AR8216_NUM_PORTS
||
1311 priv
->monitor_port
>= AR8216_NUM_PORTS
||
1312 priv
->source_port
== priv
->monitor_port
) {
1316 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CPUPORT
,
1317 AR8216_GLOBAL_CPUPORT_MIRROR_PORT
,
1318 (priv
->monitor_port
<< AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S
));
1320 if (priv
->mirror_rx
)
1321 ar8xxx_reg_set(priv
, AR8216_REG_PORT_CTRL(priv
->source_port
),
1322 AR8216_PORT_CTRL_MIRROR_RX
);
1324 if (priv
->mirror_tx
)
1325 ar8xxx_reg_set(priv
, AR8216_REG_PORT_CTRL(priv
->source_port
),
1326 AR8216_PORT_CTRL_MIRROR_TX
);
1330 ar8xxx_age_time_val(int age_time
)
1332 return (age_time
+ AR8XXX_REG_ARL_CTRL_AGE_TIME_SECS
/ 2) /
1333 AR8XXX_REG_ARL_CTRL_AGE_TIME_SECS
;
1337 ar8xxx_set_age_time(struct ar8xxx_priv
*priv
, int reg
)
1339 u32 age_time
= ar8xxx_age_time_val(priv
->arl_age_time
);
1340 ar8xxx_rmw(priv
, reg
, AR8216_ATU_CTRL_AGE_TIME
, age_time
<< AR8216_ATU_CTRL_AGE_TIME_S
);
1344 ar8xxx_sw_hw_apply(struct switch_dev
*dev
)
1346 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1347 const struct ar8xxx_chip
*chip
= priv
->chip
;
1348 u8 portmask
[AR8X16_MAX_PORTS
];
1351 mutex_lock(&priv
->reg_mutex
);
1352 /* flush all vlan translation unit entries */
1353 priv
->chip
->vtu_flush(priv
);
1355 memset(portmask
, 0, sizeof(portmask
));
1357 /* calculate the port destination masks and load vlans
1358 * into the vlan translation unit */
1359 for (j
= 0; j
< AR8X16_MAX_VLANS
; j
++) {
1360 u8 vp
= priv
->vlan_table
[j
];
1365 for (i
= 0; i
< dev
->ports
; i
++) {
1368 portmask
[i
] |= vp
& ~mask
;
1371 chip
->vtu_load_vlan(priv
, priv
->vlan_id
[j
],
1372 priv
->vlan_table
[j
]);
1376 * isolate all ports, but connect them to the cpu port */
1377 for (i
= 0; i
< dev
->ports
; i
++) {
1378 if (i
== AR8216_PORT_CPU
)
1381 portmask
[i
] = 1 << AR8216_PORT_CPU
;
1382 portmask
[AR8216_PORT_CPU
] |= (1 << i
);
1386 /* update the port destination mask registers and tag settings */
1387 for (i
= 0; i
< dev
->ports
; i
++) {
1388 chip
->setup_port(priv
, i
, portmask
[i
]);
1391 chip
->set_mirror_regs(priv
);
1394 if (chip
->reg_arl_ctrl
)
1395 ar8xxx_set_age_time(priv
, chip
->reg_arl_ctrl
);
1397 mutex_unlock(&priv
->reg_mutex
);
1402 ar8xxx_sw_reset_switch(struct switch_dev
*dev
)
1404 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1405 const struct ar8xxx_chip
*chip
= priv
->chip
;
1408 mutex_lock(&priv
->reg_mutex
);
1409 memset(&priv
->vlan
, 0, sizeof(struct ar8xxx_priv
) -
1410 offsetof(struct ar8xxx_priv
, vlan
));
1412 for (i
= 0; i
< AR8X16_MAX_VLANS
; i
++)
1413 priv
->vlan_id
[i
] = i
;
1415 /* Configure all ports */
1416 for (i
= 0; i
< dev
->ports
; i
++)
1417 chip
->init_port(priv
, i
);
1419 priv
->mirror_rx
= false;
1420 priv
->mirror_tx
= false;
1421 priv
->source_port
= 0;
1422 priv
->monitor_port
= 0;
1423 priv
->arl_age_time
= AR8XXX_DEFAULT_ARL_AGE_TIME
;
1425 chip
->init_globals(priv
);
1426 chip
->atu_flush(priv
);
1428 mutex_unlock(&priv
->reg_mutex
);
1430 return chip
->sw_hw_apply(dev
);
1434 ar8xxx_sw_set_reset_mibs(struct switch_dev
*dev
,
1435 const struct switch_attr
*attr
,
1436 struct switch_val
*val
)
1438 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1442 if (!ar8xxx_has_mib_counters(priv
))
1445 mutex_lock(&priv
->mib_lock
);
1447 len
= priv
->dev
.ports
* priv
->chip
->num_mibs
*
1448 sizeof(*priv
->mib_stats
);
1449 memset(priv
->mib_stats
, '\0', len
);
1450 ret
= ar8xxx_mib_flush(priv
);
1457 mutex_unlock(&priv
->mib_lock
);
1462 ar8xxx_sw_set_mib_poll_interval(struct switch_dev
*dev
,
1463 const struct switch_attr
*attr
,
1464 struct switch_val
*val
)
1466 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1468 if (!ar8xxx_has_mib_counters(priv
))
1471 ar8xxx_mib_stop(priv
);
1472 priv
->mib_poll_interval
= val
->value
.i
;
1473 ar8xxx_mib_start(priv
);
1479 ar8xxx_sw_get_mib_poll_interval(struct switch_dev
*dev
,
1480 const struct switch_attr
*attr
,
1481 struct switch_val
*val
)
1483 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1485 if (!ar8xxx_has_mib_counters(priv
))
1487 val
->value
.i
= priv
->mib_poll_interval
;
1492 ar8xxx_sw_set_mib_type(struct switch_dev
*dev
,
1493 const struct switch_attr
*attr
,
1494 struct switch_val
*val
)
1496 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1498 if (!ar8xxx_has_mib_counters(priv
))
1500 priv
->mib_type
= val
->value
.i
;
1505 ar8xxx_sw_get_mib_type(struct switch_dev
*dev
,
1506 const struct switch_attr
*attr
,
1507 struct switch_val
*val
)
1509 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1511 if (!ar8xxx_has_mib_counters(priv
))
1513 val
->value
.i
= priv
->mib_type
;
1518 ar8xxx_sw_set_mirror_rx_enable(struct switch_dev
*dev
,
1519 const struct switch_attr
*attr
,
1520 struct switch_val
*val
)
1522 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1524 mutex_lock(&priv
->reg_mutex
);
1525 priv
->mirror_rx
= !!val
->value
.i
;
1526 priv
->chip
->set_mirror_regs(priv
);
1527 mutex_unlock(&priv
->reg_mutex
);
1533 ar8xxx_sw_get_mirror_rx_enable(struct switch_dev
*dev
,
1534 const struct switch_attr
*attr
,
1535 struct switch_val
*val
)
1537 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1538 val
->value
.i
= priv
->mirror_rx
;
1543 ar8xxx_sw_set_mirror_tx_enable(struct switch_dev
*dev
,
1544 const struct switch_attr
*attr
,
1545 struct switch_val
*val
)
1547 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1549 mutex_lock(&priv
->reg_mutex
);
1550 priv
->mirror_tx
= !!val
->value
.i
;
1551 priv
->chip
->set_mirror_regs(priv
);
1552 mutex_unlock(&priv
->reg_mutex
);
1558 ar8xxx_sw_get_mirror_tx_enable(struct switch_dev
*dev
,
1559 const struct switch_attr
*attr
,
1560 struct switch_val
*val
)
1562 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1563 val
->value
.i
= priv
->mirror_tx
;
1568 ar8xxx_sw_set_mirror_monitor_port(struct switch_dev
*dev
,
1569 const struct switch_attr
*attr
,
1570 struct switch_val
*val
)
1572 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1574 mutex_lock(&priv
->reg_mutex
);
1575 priv
->monitor_port
= val
->value
.i
;
1576 priv
->chip
->set_mirror_regs(priv
);
1577 mutex_unlock(&priv
->reg_mutex
);
1583 ar8xxx_sw_get_mirror_monitor_port(struct switch_dev
*dev
,
1584 const struct switch_attr
*attr
,
1585 struct switch_val
*val
)
1587 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1588 val
->value
.i
= priv
->monitor_port
;
1593 ar8xxx_sw_set_mirror_source_port(struct switch_dev
*dev
,
1594 const struct switch_attr
*attr
,
1595 struct switch_val
*val
)
1597 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1599 mutex_lock(&priv
->reg_mutex
);
1600 priv
->source_port
= val
->value
.i
;
1601 priv
->chip
->set_mirror_regs(priv
);
1602 mutex_unlock(&priv
->reg_mutex
);
1608 ar8xxx_sw_get_mirror_source_port(struct switch_dev
*dev
,
1609 const struct switch_attr
*attr
,
1610 struct switch_val
*val
)
1612 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1613 val
->value
.i
= priv
->source_port
;
1618 ar8xxx_sw_set_port_reset_mib(struct switch_dev
*dev
,
1619 const struct switch_attr
*attr
,
1620 struct switch_val
*val
)
1622 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1626 if (!ar8xxx_has_mib_counters(priv
))
1629 port
= val
->port_vlan
;
1630 if (port
>= dev
->ports
)
1633 mutex_lock(&priv
->mib_lock
);
1634 ret
= ar8xxx_mib_capture(priv
);
1638 ar8xxx_mib_fetch_port_stat(priv
, port
, true);
1643 mutex_unlock(&priv
->mib_lock
);
1648 ar8xxx_byte_to_str(char *buf
, int len
, u64 byte
)
1653 if (byte
>= 0x40000000) { /* 1 GiB */
1654 b
= byte
* 10 / 0x40000000;
1656 } else if (byte
>= 0x100000) { /* 1 MiB */
1657 b
= byte
* 10 / 0x100000;
1659 } else if (byte
>= 0x400) { /* 1 KiB */
1660 b
= byte
* 10 / 0x400;
1666 if (strcmp(unit
, "Byte"))
1667 snprintf(buf
, len
, "%lu.%lu %s", b
/ 10, b
% 10, unit
);
1669 snprintf(buf
, len
, "%lu %s", b
, unit
);
1673 ar8xxx_sw_get_port_mib(struct switch_dev
*dev
,
1674 const struct switch_attr
*attr
,
1675 struct switch_val
*val
)
1677 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1678 const struct ar8xxx_chip
*chip
= priv
->chip
;
1679 u64
*mib_stats
, mib_data
;
1682 char *buf
= priv
->buf
;
1684 const char *mib_name
;
1686 bool mib_stats_empty
= true;
1688 if (!ar8xxx_has_mib_counters(priv
) || !priv
->mib_poll_interval
)
1691 port
= val
->port_vlan
;
1692 if (port
>= dev
->ports
)
1695 mutex_lock(&priv
->mib_lock
);
1696 ret
= ar8xxx_mib_capture(priv
);
1700 ar8xxx_mib_fetch_port_stat(priv
, port
, false);
1702 len
+= snprintf(buf
+ len
, sizeof(priv
->buf
) - len
,
1705 mib_stats
= &priv
->mib_stats
[port
* chip
->num_mibs
];
1706 for (i
= 0; i
< chip
->num_mibs
; i
++) {
1707 if (chip
->mib_decs
[i
].type
> priv
->mib_type
)
1709 mib_name
= chip
->mib_decs
[i
].name
;
1710 mib_data
= mib_stats
[i
];
1711 len
+= snprintf(buf
+ len
, sizeof(priv
->buf
) - len
,
1712 "%-12s: %llu\n", mib_name
, mib_data
);
1713 if ((!strcmp(mib_name
, "TxByte") ||
1714 !strcmp(mib_name
, "RxGoodByte")) &&
1716 ar8xxx_byte_to_str(buf1
, sizeof(buf1
), mib_data
);
1717 --len
; /* discard newline at the end of buf */
1718 len
+= snprintf(buf
+ len
, sizeof(priv
->buf
) - len
,
1721 if (mib_stats_empty
&& mib_data
)
1722 mib_stats_empty
= false;
1725 if (mib_stats_empty
)
1726 len
= snprintf(buf
, sizeof(priv
->buf
), "No MIB data");
1734 mutex_unlock(&priv
->mib_lock
);
1739 ar8xxx_sw_set_arl_age_time(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1740 struct switch_val
*val
)
1742 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1743 int age_time
= val
->value
.i
;
1749 age_time_val
= ar8xxx_age_time_val(age_time
);
1750 if (age_time_val
== 0 || age_time_val
> 0xffff)
1753 priv
->arl_age_time
= age_time
;
1758 ar8xxx_sw_get_arl_age_time(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1759 struct switch_val
*val
)
1761 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1762 val
->value
.i
= priv
->arl_age_time
;
1767 ar8xxx_sw_get_arl_table(struct switch_dev
*dev
,
1768 const struct switch_attr
*attr
,
1769 struct switch_val
*val
)
1771 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1772 struct mii_bus
*bus
= priv
->mii_bus
;
1773 const struct ar8xxx_chip
*chip
= priv
->chip
;
1774 char *buf
= priv
->arl_buf
;
1775 int i
, j
, k
, len
= 0;
1776 struct arl_entry
*a
, *a1
;
1779 if (!chip
->get_arl_entry
)
1782 mutex_lock(&priv
->reg_mutex
);
1783 mutex_lock(&bus
->mdio_lock
);
1785 chip
->get_arl_entry(priv
, NULL
, NULL
, AR8XXX_ARL_INITIALIZE
);
1787 for(i
= 0; i
< AR8XXX_NUM_ARL_RECORDS
; ++i
) {
1788 a
= &priv
->arl_table
[i
];
1790 chip
->get_arl_entry(priv
, a
, &status
, AR8XXX_ARL_GET_NEXT
);
1796 * ARL table can include multiple valid entries
1797 * per MAC, just with differing status codes
1799 for (j
= 0; j
< i
; ++j
) {
1800 a1
= &priv
->arl_table
[j
];
1801 if (!memcmp(a
->mac
, a1
->mac
, sizeof(a
->mac
))) {
1802 /* ignore ports already seen in former entry */
1803 a
->portmap
&= ~a1
->portmap
;
1810 mutex_unlock(&bus
->mdio_lock
);
1812 len
+= snprintf(buf
+ len
, sizeof(priv
->arl_buf
) - len
,
1813 "address resolution table\n");
1815 if (i
== AR8XXX_NUM_ARL_RECORDS
)
1816 len
+= snprintf(buf
+ len
, sizeof(priv
->arl_buf
) - len
,
1817 "Too many entries found, displaying the first %d only!\n",
1818 AR8XXX_NUM_ARL_RECORDS
);
1820 for (j
= 0; j
< priv
->dev
.ports
; ++j
) {
1821 for (k
= 0; k
< i
; ++k
) {
1822 a
= &priv
->arl_table
[k
];
1823 if (!(a
->portmap
& BIT(j
)))
1825 len
+= snprintf(buf
+ len
, sizeof(priv
->arl_buf
) - len
,
1826 "Port %d: MAC %02x:%02x:%02x:%02x:%02x:%02x\n",
1828 a
->mac
[5], a
->mac
[4], a
->mac
[3],
1829 a
->mac
[2], a
->mac
[1], a
->mac
[0]);
1836 mutex_unlock(&priv
->reg_mutex
);
1842 ar8xxx_sw_set_flush_arl_table(struct switch_dev
*dev
,
1843 const struct switch_attr
*attr
,
1844 struct switch_val
*val
)
1846 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1849 mutex_lock(&priv
->reg_mutex
);
1850 ret
= priv
->chip
->atu_flush(priv
);
1851 mutex_unlock(&priv
->reg_mutex
);
1857 ar8xxx_sw_set_flush_port_arl_table(struct switch_dev
*dev
,
1858 const struct switch_attr
*attr
,
1859 struct switch_val
*val
)
1861 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1864 port
= val
->port_vlan
;
1865 if (port
>= dev
->ports
)
1868 mutex_lock(&priv
->reg_mutex
);
1869 ret
= priv
->chip
->atu_flush_port(priv
, port
);
1870 mutex_unlock(&priv
->reg_mutex
);
1876 ar8xxx_sw_get_port_stats(struct switch_dev
*dev
, int port
,
1877 struct switch_port_stats
*stats
)
1879 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1882 if (!ar8xxx_has_mib_counters(priv
) || !priv
->mib_poll_interval
)
1885 if (!(priv
->chip
->mib_rxb_id
|| priv
->chip
->mib_txb_id
))
1888 if (port
>= dev
->ports
)
1891 mutex_lock(&priv
->mib_lock
);
1893 mib_stats
= &priv
->mib_stats
[port
* priv
->chip
->num_mibs
];
1895 stats
->tx_bytes
= mib_stats
[priv
->chip
->mib_txb_id
];
1896 stats
->rx_bytes
= mib_stats
[priv
->chip
->mib_rxb_id
];
1898 mutex_unlock(&priv
->mib_lock
);
1903 ar8xxx_phy_read(struct mii_bus
*bus
, int phy_addr
, int reg_addr
)
1905 struct ar8xxx_priv
*priv
= bus
->priv
;
1906 return priv
->chip
->phy_read(priv
, phy_addr
, reg_addr
);
1910 ar8xxx_phy_write(struct mii_bus
*bus
, int phy_addr
, int reg_addr
,
1913 struct ar8xxx_priv
*priv
= bus
->priv
;
1914 return priv
->chip
->phy_write(priv
, phy_addr
, reg_addr
, reg_val
);
1917 static const struct switch_attr ar8xxx_sw_attr_globals
[] = {
1919 .type
= SWITCH_TYPE_INT
,
1920 .name
= "enable_vlan",
1921 .description
= "Enable VLAN mode",
1922 .set
= ar8xxx_sw_set_vlan
,
1923 .get
= ar8xxx_sw_get_vlan
,
1927 .type
= SWITCH_TYPE_NOVAL
,
1928 .name
= "reset_mibs",
1929 .description
= "Reset all MIB counters",
1930 .set
= ar8xxx_sw_set_reset_mibs
,
1933 .type
= SWITCH_TYPE_INT
,
1934 .name
= "ar8xxx_mib_poll_interval",
1935 .description
= "MIB polling interval in msecs (0 to disable)",
1936 .set
= ar8xxx_sw_set_mib_poll_interval
,
1937 .get
= ar8xxx_sw_get_mib_poll_interval
1940 .type
= SWITCH_TYPE_INT
,
1941 .name
= "ar8xxx_mib_type",
1942 .description
= "MIB type (0=basic 1=extended)",
1943 .set
= ar8xxx_sw_set_mib_type
,
1944 .get
= ar8xxx_sw_get_mib_type
1947 .type
= SWITCH_TYPE_INT
,
1948 .name
= "enable_mirror_rx",
1949 .description
= "Enable mirroring of RX packets",
1950 .set
= ar8xxx_sw_set_mirror_rx_enable
,
1951 .get
= ar8xxx_sw_get_mirror_rx_enable
,
1955 .type
= SWITCH_TYPE_INT
,
1956 .name
= "enable_mirror_tx",
1957 .description
= "Enable mirroring of TX packets",
1958 .set
= ar8xxx_sw_set_mirror_tx_enable
,
1959 .get
= ar8xxx_sw_get_mirror_tx_enable
,
1963 .type
= SWITCH_TYPE_INT
,
1964 .name
= "mirror_monitor_port",
1965 .description
= "Mirror monitor port",
1966 .set
= ar8xxx_sw_set_mirror_monitor_port
,
1967 .get
= ar8xxx_sw_get_mirror_monitor_port
,
1968 .max
= AR8216_NUM_PORTS
- 1
1971 .type
= SWITCH_TYPE_INT
,
1972 .name
= "mirror_source_port",
1973 .description
= "Mirror source port",
1974 .set
= ar8xxx_sw_set_mirror_source_port
,
1975 .get
= ar8xxx_sw_get_mirror_source_port
,
1976 .max
= AR8216_NUM_PORTS
- 1
1979 .type
= SWITCH_TYPE_STRING
,
1980 .name
= "arl_table",
1981 .description
= "Get ARL table",
1983 .get
= ar8xxx_sw_get_arl_table
,
1986 .type
= SWITCH_TYPE_NOVAL
,
1987 .name
= "flush_arl_table",
1988 .description
= "Flush ARL table",
1989 .set
= ar8xxx_sw_set_flush_arl_table
,
1993 const struct switch_attr ar8xxx_sw_attr_port
[] = {
1995 .type
= SWITCH_TYPE_NOVAL
,
1996 .name
= "reset_mib",
1997 .description
= "Reset single port MIB counters",
1998 .set
= ar8xxx_sw_set_port_reset_mib
,
2001 .type
= SWITCH_TYPE_STRING
,
2003 .description
= "Get port's MIB counters",
2005 .get
= ar8xxx_sw_get_port_mib
,
2008 .type
= SWITCH_TYPE_NOVAL
,
2009 .name
= "flush_arl_table",
2010 .description
= "Flush port's ARL table entries",
2011 .set
= ar8xxx_sw_set_flush_port_arl_table
,
2015 const struct switch_attr ar8xxx_sw_attr_vlan
[1] = {
2017 .type
= SWITCH_TYPE_INT
,
2019 .description
= "VLAN ID (0-4094)",
2020 .set
= ar8xxx_sw_set_vid
,
2021 .get
= ar8xxx_sw_get_vid
,
2026 static const struct switch_dev_ops ar8xxx_sw_ops
= {
2028 .attr
= ar8xxx_sw_attr_globals
,
2029 .n_attr
= ARRAY_SIZE(ar8xxx_sw_attr_globals
),
2032 .attr
= ar8xxx_sw_attr_port
,
2033 .n_attr
= ARRAY_SIZE(ar8xxx_sw_attr_port
),
2036 .attr
= ar8xxx_sw_attr_vlan
,
2037 .n_attr
= ARRAY_SIZE(ar8xxx_sw_attr_vlan
),
2039 .get_port_pvid
= ar8xxx_sw_get_pvid
,
2040 .set_port_pvid
= ar8xxx_sw_set_pvid
,
2041 .get_vlan_ports
= ar8xxx_sw_get_ports
,
2042 .set_vlan_ports
= ar8xxx_sw_set_ports
,
2043 .apply_config
= ar8xxx_sw_hw_apply
,
2044 .reset_switch
= ar8xxx_sw_reset_switch
,
2045 .get_port_link
= ar8xxx_sw_get_port_link
,
2046 .get_port_stats
= ar8xxx_sw_get_port_stats
,
2049 static const struct ar8xxx_chip ar7240sw_chip
= {
2050 .caps
= AR8XXX_CAP_MIB_COUNTERS
,
2052 .reg_port_stats_start
= 0x20000,
2053 .reg_port_stats_length
= 0x100,
2054 .reg_arl_ctrl
= AR8216_REG_ATU_CTRL
,
2056 .name
= "Atheros AR724X/AR933X built-in",
2057 .ports
= AR7240SW_NUM_PORTS
,
2058 .vlans
= AR8216_NUM_VLANS
,
2059 .swops
= &ar8xxx_sw_ops
,
2061 .hw_init
= ar7240sw_hw_init
,
2062 .init_globals
= ar7240sw_init_globals
,
2063 .init_port
= ar8229_init_port
,
2064 .phy_read
= ar8216_phy_read
,
2065 .phy_write
= ar8216_phy_write
,
2066 .setup_port
= ar7240sw_setup_port
,
2067 .read_port_status
= ar8216_read_port_status
,
2068 .atu_flush
= ar8216_atu_flush
,
2069 .atu_flush_port
= ar8216_atu_flush_port
,
2070 .vtu_flush
= ar8216_vtu_flush
,
2071 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
2072 .set_mirror_regs
= ar8216_set_mirror_regs
,
2073 .get_arl_entry
= ar8216_get_arl_entry
,
2074 .sw_hw_apply
= ar8xxx_sw_hw_apply
,
2076 .num_mibs
= ARRAY_SIZE(ar8236_mibs
),
2077 .mib_decs
= ar8236_mibs
,
2078 .mib_func
= AR8216_REG_MIB_FUNC
,
2079 .mib_rxb_id
= AR8236_MIB_RXB_ID
,
2080 .mib_txb_id
= AR8236_MIB_TXB_ID
,
2083 static const struct ar8xxx_chip ar8216_chip
= {
2084 .caps
= AR8XXX_CAP_MIB_COUNTERS
,
2086 .reg_port_stats_start
= 0x19000,
2087 .reg_port_stats_length
= 0xa0,
2088 .reg_arl_ctrl
= AR8216_REG_ATU_CTRL
,
2090 .name
= "Atheros AR8216",
2091 .ports
= AR8216_NUM_PORTS
,
2092 .vlans
= AR8216_NUM_VLANS
,
2093 .swops
= &ar8xxx_sw_ops
,
2095 .hw_init
= ar8216_hw_init
,
2096 .init_globals
= ar8216_init_globals
,
2097 .init_port
= ar8216_init_port
,
2098 .setup_port
= ar8216_setup_port
,
2099 .read_port_status
= ar8216_read_port_status
,
2100 .atu_flush
= ar8216_atu_flush
,
2101 .atu_flush_port
= ar8216_atu_flush_port
,
2102 .vtu_flush
= ar8216_vtu_flush
,
2103 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
2104 .set_mirror_regs
= ar8216_set_mirror_regs
,
2105 .get_arl_entry
= ar8216_get_arl_entry
,
2106 .sw_hw_apply
= ar8xxx_sw_hw_apply
,
2108 .num_mibs
= ARRAY_SIZE(ar8216_mibs
),
2109 .mib_decs
= ar8216_mibs
,
2110 .mib_func
= AR8216_REG_MIB_FUNC
,
2111 .mib_rxb_id
= AR8216_MIB_RXB_ID
,
2112 .mib_txb_id
= AR8216_MIB_TXB_ID
,
2115 static const struct ar8xxx_chip ar8229_chip
= {
2116 .caps
= AR8XXX_CAP_MIB_COUNTERS
,
2118 .reg_port_stats_start
= 0x20000,
2119 .reg_port_stats_length
= 0x100,
2120 .reg_arl_ctrl
= AR8216_REG_ATU_CTRL
,
2122 .name
= "Atheros AR8229",
2123 .ports
= AR8216_NUM_PORTS
,
2124 .vlans
= AR8216_NUM_VLANS
,
2125 .swops
= &ar8xxx_sw_ops
,
2127 .hw_init
= ar8229_hw_init
,
2128 .init_globals
= ar8229_init_globals
,
2129 .init_port
= ar8229_init_port
,
2130 .phy_read
= ar8216_phy_read
,
2131 .phy_write
= ar8216_phy_write
,
2132 .setup_port
= ar8236_setup_port
,
2133 .read_port_status
= ar8216_read_port_status
,
2134 .atu_flush
= ar8216_atu_flush
,
2135 .atu_flush_port
= ar8216_atu_flush_port
,
2136 .vtu_flush
= ar8216_vtu_flush
,
2137 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
2138 .set_mirror_regs
= ar8216_set_mirror_regs
,
2139 .get_arl_entry
= ar8216_get_arl_entry
,
2140 .sw_hw_apply
= ar8xxx_sw_hw_apply
,
2142 .num_mibs
= ARRAY_SIZE(ar8236_mibs
),
2143 .mib_decs
= ar8236_mibs
,
2144 .mib_func
= AR8216_REG_MIB_FUNC
,
2145 .mib_rxb_id
= AR8236_MIB_RXB_ID
,
2146 .mib_txb_id
= AR8236_MIB_TXB_ID
,
2149 static const struct ar8xxx_chip ar8236_chip
= {
2150 .caps
= AR8XXX_CAP_MIB_COUNTERS
,
2152 .reg_port_stats_start
= 0x20000,
2153 .reg_port_stats_length
= 0x100,
2154 .reg_arl_ctrl
= AR8216_REG_ATU_CTRL
,
2156 .name
= "Atheros AR8236",
2157 .ports
= AR8216_NUM_PORTS
,
2158 .vlans
= AR8216_NUM_VLANS
,
2159 .swops
= &ar8xxx_sw_ops
,
2161 .hw_init
= ar8216_hw_init
,
2162 .init_globals
= ar8236_init_globals
,
2163 .init_port
= ar8216_init_port
,
2164 .setup_port
= ar8236_setup_port
,
2165 .read_port_status
= ar8216_read_port_status
,
2166 .atu_flush
= ar8216_atu_flush
,
2167 .atu_flush_port
= ar8216_atu_flush_port
,
2168 .vtu_flush
= ar8216_vtu_flush
,
2169 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
2170 .set_mirror_regs
= ar8216_set_mirror_regs
,
2171 .get_arl_entry
= ar8216_get_arl_entry
,
2172 .sw_hw_apply
= ar8xxx_sw_hw_apply
,
2174 .num_mibs
= ARRAY_SIZE(ar8236_mibs
),
2175 .mib_decs
= ar8236_mibs
,
2176 .mib_func
= AR8216_REG_MIB_FUNC
,
2177 .mib_rxb_id
= AR8236_MIB_RXB_ID
,
2178 .mib_txb_id
= AR8236_MIB_TXB_ID
,
2181 static const struct ar8xxx_chip ar8316_chip
= {
2182 .caps
= AR8XXX_CAP_GIGE
| AR8XXX_CAP_MIB_COUNTERS
,
2184 .reg_port_stats_start
= 0x20000,
2185 .reg_port_stats_length
= 0x100,
2186 .reg_arl_ctrl
= AR8216_REG_ATU_CTRL
,
2188 .name
= "Atheros AR8316",
2189 .ports
= AR8216_NUM_PORTS
,
2190 .vlans
= AR8X16_MAX_VLANS
,
2191 .swops
= &ar8xxx_sw_ops
,
2193 .hw_init
= ar8316_hw_init
,
2194 .init_globals
= ar8316_init_globals
,
2195 .init_port
= ar8216_init_port
,
2196 .setup_port
= ar8216_setup_port
,
2197 .read_port_status
= ar8216_read_port_status
,
2198 .atu_flush
= ar8216_atu_flush
,
2199 .atu_flush_port
= ar8216_atu_flush_port
,
2200 .vtu_flush
= ar8216_vtu_flush
,
2201 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
2202 .set_mirror_regs
= ar8216_set_mirror_regs
,
2203 .get_arl_entry
= ar8216_get_arl_entry
,
2204 .sw_hw_apply
= ar8xxx_sw_hw_apply
,
2206 .num_mibs
= ARRAY_SIZE(ar8236_mibs
),
2207 .mib_decs
= ar8236_mibs
,
2208 .mib_func
= AR8216_REG_MIB_FUNC
,
2209 .mib_rxb_id
= AR8236_MIB_RXB_ID
,
2210 .mib_txb_id
= AR8236_MIB_TXB_ID
,
2214 ar8xxx_read_id(struct ar8xxx_priv
*priv
)
2220 val
= ar8xxx_read(priv
, AR8216_REG_CTRL
);
2224 id
= val
& (AR8216_CTRL_REVISION
| AR8216_CTRL_VERSION
);
2225 for (i
= 0; i
< AR8X16_PROBE_RETRIES
; i
++) {
2228 val
= ar8xxx_read(priv
, AR8216_REG_CTRL
);
2232 t
= val
& (AR8216_CTRL_REVISION
| AR8216_CTRL_VERSION
);
2237 priv
->chip_ver
= (id
& AR8216_CTRL_VERSION
) >> AR8216_CTRL_VERSION_S
;
2238 priv
->chip_rev
= (id
& AR8216_CTRL_REVISION
);
2243 ar8xxx_id_chip(struct ar8xxx_priv
*priv
)
2247 ret
= ar8xxx_read_id(priv
);
2251 switch (priv
->chip_ver
) {
2252 case AR8XXX_VER_AR8216
:
2253 priv
->chip
= &ar8216_chip
;
2255 case AR8XXX_VER_AR8236
:
2256 priv
->chip
= &ar8236_chip
;
2258 case AR8XXX_VER_AR8316
:
2259 priv
->chip
= &ar8316_chip
;
2261 case AR8XXX_VER_AR8327
:
2262 priv
->chip
= &ar8327_chip
;
2264 case AR8XXX_VER_AR8337
:
2265 priv
->chip
= &ar8337_chip
;
2268 pr_err("ar8216: Unknown Atheros device [ver=%d, rev=%d]\n",
2269 priv
->chip_ver
, priv
->chip_rev
);
2278 ar8xxx_mib_work_func(struct work_struct
*work
)
2280 struct ar8xxx_priv
*priv
;
2283 priv
= container_of(work
, struct ar8xxx_priv
, mib_work
.work
);
2285 mutex_lock(&priv
->mib_lock
);
2287 err
= ar8xxx_mib_capture(priv
);
2291 for (i
= 0; i
< priv
->dev
.ports
; i
++)
2292 ar8xxx_mib_fetch_port_stat(priv
, i
, false);
2295 mutex_unlock(&priv
->mib_lock
);
2296 schedule_delayed_work(&priv
->mib_work
,
2297 msecs_to_jiffies(priv
->mib_poll_interval
));
2301 ar8xxx_mib_init(struct ar8xxx_priv
*priv
)
2305 if (!ar8xxx_has_mib_counters(priv
))
2308 BUG_ON(!priv
->chip
->mib_decs
|| !priv
->chip
->num_mibs
);
2310 len
= priv
->dev
.ports
* priv
->chip
->num_mibs
*
2311 sizeof(*priv
->mib_stats
);
2312 priv
->mib_stats
= kzalloc(len
, GFP_KERNEL
);
2314 if (!priv
->mib_stats
)
2321 ar8xxx_mib_start(struct ar8xxx_priv
*priv
)
2323 if (!ar8xxx_has_mib_counters(priv
) || !priv
->mib_poll_interval
)
2326 schedule_delayed_work(&priv
->mib_work
,
2327 msecs_to_jiffies(priv
->mib_poll_interval
));
2331 ar8xxx_mib_stop(struct ar8xxx_priv
*priv
)
2333 if (!ar8xxx_has_mib_counters(priv
) || !priv
->mib_poll_interval
)
2336 cancel_delayed_work_sync(&priv
->mib_work
);
2339 static struct ar8xxx_priv
*
2342 struct ar8xxx_priv
*priv
;
2344 priv
= kzalloc(sizeof(struct ar8xxx_priv
), GFP_KERNEL
);
2348 mutex_init(&priv
->reg_mutex
);
2349 mutex_init(&priv
->mib_lock
);
2350 INIT_DELAYED_WORK(&priv
->mib_work
, ar8xxx_mib_work_func
);
2356 ar8xxx_free(struct ar8xxx_priv
*priv
)
2358 if (priv
->chip
&& priv
->chip
->cleanup
)
2359 priv
->chip
->cleanup(priv
);
2361 kfree(priv
->chip_data
);
2362 kfree(priv
->mib_stats
);
2367 ar8xxx_probe_switch(struct ar8xxx_priv
*priv
)
2369 const struct ar8xxx_chip
*chip
;
2370 struct switch_dev
*swdev
;
2376 swdev
->cpu_port
= AR8216_PORT_CPU
;
2377 swdev
->name
= chip
->name
;
2378 swdev
->vlans
= chip
->vlans
;
2379 swdev
->ports
= chip
->ports
;
2380 swdev
->ops
= chip
->swops
;
2382 ret
= ar8xxx_mib_init(priv
);
2390 ar8xxx_start(struct ar8xxx_priv
*priv
)
2396 ret
= priv
->chip
->hw_init(priv
);
2400 ret
= ar8xxx_sw_reset_switch(&priv
->dev
);
2406 ar8xxx_mib_start(priv
);
2412 ar8xxx_phy_config_init(struct phy_device
*phydev
)
2414 struct ar8xxx_priv
*priv
= phydev
->priv
;
2415 struct net_device
*dev
= phydev
->attached_dev
;
2421 if (priv
->chip
->config_at_probe
)
2422 return ar8xxx_phy_check_aneg(phydev
);
2426 if (phydev
->mdio
.addr
!= 0) {
2427 if (chip_is_ar8316(priv
)) {
2428 /* switch device has been initialized, reinit */
2429 priv
->dev
.ports
= (AR8216_NUM_PORTS
- 1);
2430 priv
->initialized
= false;
2431 priv
->port4_phy
= true;
2432 ar8316_hw_init(priv
);
2439 ret
= ar8xxx_start(priv
);
2443 /* VID fixup only needed on ar8216 */
2444 if (chip_is_ar8216(priv
)) {
2445 dev
->phy_ptr
= priv
;
2446 dev
->priv_flags
|= IFF_NO_IP_ALIGN
;
2447 dev
->eth_mangle_rx
= ar8216_mangle_rx
;
2448 dev
->eth_mangle_tx
= ar8216_mangle_tx
;
2455 ar8xxx_check_link_states(struct ar8xxx_priv
*priv
)
2457 bool link_new
, changed
= false;
2461 mutex_lock(&priv
->reg_mutex
);
2463 for (i
= 0; i
< priv
->dev
.ports
; i
++) {
2464 status
= priv
->chip
->read_port_status(priv
, i
);
2465 link_new
= !!(status
& AR8216_PORT_STATUS_LINK_UP
);
2466 if (link_new
== priv
->link_up
[i
])
2469 priv
->link_up
[i
] = link_new
;
2471 /* flush ARL entries for this port if it went down*/
2473 priv
->chip
->atu_flush_port(priv
, i
);
2474 dev_info(&priv
->phy
->mdio
.dev
, "Port %d is %s\n",
2475 i
, link_new
? "up" : "down");
2478 mutex_unlock(&priv
->reg_mutex
);
2484 ar8xxx_phy_read_status(struct phy_device
*phydev
)
2486 struct ar8xxx_priv
*priv
= phydev
->priv
;
2487 struct switch_port_link link
;
2489 /* check for switch port link changes */
2490 if (phydev
->state
== PHY_CHANGELINK
)
2491 ar8xxx_check_link_states(priv
);
2493 if (phydev
->mdio
.addr
!= 0)
2494 return genphy_read_status(phydev
);
2496 ar8216_read_port_link(priv
, phydev
->mdio
.addr
, &link
);
2497 phydev
->link
= !!link
.link
;
2501 switch (link
.speed
) {
2502 case SWITCH_PORT_SPEED_10
:
2503 phydev
->speed
= SPEED_10
;
2505 case SWITCH_PORT_SPEED_100
:
2506 phydev
->speed
= SPEED_100
;
2508 case SWITCH_PORT_SPEED_1000
:
2509 phydev
->speed
= SPEED_1000
;
2514 phydev
->duplex
= link
.duplex
? DUPLEX_FULL
: DUPLEX_HALF
;
2516 phydev
->state
= PHY_RUNNING
;
2517 netif_carrier_on(phydev
->attached_dev
);
2518 if (phydev
->adjust_link
)
2519 phydev
->adjust_link(phydev
->attached_dev
);
2525 ar8xxx_phy_config_aneg(struct phy_device
*phydev
)
2527 if (phydev
->mdio
.addr
== 0)
2530 return genphy_config_aneg(phydev
);
2533 static const u32 ar8xxx_phy_ids
[] = {
2535 0x004dd034, /* AR8327 */
2536 0x004dd036, /* AR8337 */
2539 0x004dd043, /* AR8236 */
2543 ar8xxx_phy_match(u32 phy_id
)
2547 for (i
= 0; i
< ARRAY_SIZE(ar8xxx_phy_ids
); i
++)
2548 if (phy_id
== ar8xxx_phy_ids
[i
])
2555 ar8xxx_is_possible(struct mii_bus
*bus
)
2557 unsigned int i
, found_phys
= 0;
2559 for (i
= 0; i
< 5; i
++) {
2562 phy_id
= mdiobus_read(bus
, i
, MII_PHYSID1
) << 16;
2563 phy_id
|= mdiobus_read(bus
, i
, MII_PHYSID2
);
2564 if (ar8xxx_phy_match(phy_id
)) {
2566 } else if (phy_id
) {
2567 pr_debug("ar8xxx: unknown PHY at %s:%02x id:%08x\n",
2568 dev_name(&bus
->dev
), i
, phy_id
);
2571 return !!found_phys
;
2575 ar8xxx_phy_probe(struct phy_device
*phydev
)
2577 struct ar8xxx_priv
*priv
;
2578 struct switch_dev
*swdev
;
2581 /* skip PHYs at unused adresses */
2582 if (phydev
->mdio
.addr
!= 0 && phydev
->mdio
.addr
!= 3 && phydev
->mdio
.addr
!= 4)
2585 if (!ar8xxx_is_possible(phydev
->mdio
.bus
))
2588 mutex_lock(&ar8xxx_dev_list_lock
);
2589 list_for_each_entry(priv
, &ar8xxx_dev_list
, list
)
2590 if (priv
->mii_bus
== phydev
->mdio
.bus
)
2593 priv
= ar8xxx_create();
2599 priv
->mii_bus
= phydev
->mdio
.bus
;
2600 priv
->pdev
= &phydev
->mdio
.dev
;
2602 ret
= of_property_read_u32(priv
->pdev
->of_node
, "qca,mib-poll-interval",
2603 &priv
->mib_poll_interval
);
2605 priv
->mib_poll_interval
= 0;
2607 ret
= ar8xxx_id_chip(priv
);
2611 ret
= ar8xxx_probe_switch(priv
);
2616 swdev
->alias
= dev_name(&priv
->mii_bus
->dev
);
2617 ret
= register_switch(swdev
, NULL
);
2621 pr_info("%s: %s rev. %u switch registered on %s\n",
2622 swdev
->devname
, swdev
->name
, priv
->chip_rev
,
2623 dev_name(&priv
->mii_bus
->dev
));
2625 list_add(&priv
->list
, &ar8xxx_dev_list
);
2630 if (phydev
->mdio
.addr
== 0) {
2631 if (ar8xxx_has_gige(priv
)) {
2632 phydev
->supported
= SUPPORTED_1000baseT_Full
;
2633 phydev
->advertising
= ADVERTISED_1000baseT_Full
;
2635 phydev
->supported
= SUPPORTED_100baseT_Full
;
2636 phydev
->advertising
= ADVERTISED_100baseT_Full
;
2639 if (priv
->chip
->config_at_probe
) {
2642 ret
= ar8xxx_start(priv
);
2644 goto err_unregister_switch
;
2647 if (ar8xxx_has_gige(priv
)) {
2648 phydev
->supported
|= SUPPORTED_1000baseT_Full
;
2649 phydev
->advertising
|= ADVERTISED_1000baseT_Full
;
2651 if (priv
->chip
->phy_rgmii_set
)
2652 priv
->chip
->phy_rgmii_set(priv
, phydev
);
2655 phydev
->priv
= priv
;
2657 mutex_unlock(&ar8xxx_dev_list_lock
);
2661 err_unregister_switch
:
2662 if (--priv
->use_count
)
2665 unregister_switch(&priv
->dev
);
2670 mutex_unlock(&ar8xxx_dev_list_lock
);
2675 ar8xxx_phy_detach(struct phy_device
*phydev
)
2677 struct net_device
*dev
= phydev
->attached_dev
;
2682 dev
->phy_ptr
= NULL
;
2683 dev
->priv_flags
&= ~IFF_NO_IP_ALIGN
;
2684 dev
->eth_mangle_rx
= NULL
;
2685 dev
->eth_mangle_tx
= NULL
;
2689 ar8xxx_phy_remove(struct phy_device
*phydev
)
2691 struct ar8xxx_priv
*priv
= phydev
->priv
;
2696 phydev
->priv
= NULL
;
2698 mutex_lock(&ar8xxx_dev_list_lock
);
2700 if (--priv
->use_count
> 0) {
2701 mutex_unlock(&ar8xxx_dev_list_lock
);
2705 list_del(&priv
->list
);
2706 mutex_unlock(&ar8xxx_dev_list_lock
);
2708 unregister_switch(&priv
->dev
);
2709 ar8xxx_mib_stop(priv
);
2714 ar8xxx_phy_soft_reset(struct phy_device
*phydev
)
2716 /* we don't need an extra reset */
2720 static struct phy_driver ar8xxx_phy_driver
[] = {
2722 .phy_id
= 0x004d0000,
2723 .name
= "Atheros AR8216/AR8236/AR8316",
2724 .phy_id_mask
= 0xffff0000,
2725 .features
= PHY_BASIC_FEATURES
,
2726 .probe
= ar8xxx_phy_probe
,
2727 .remove
= ar8xxx_phy_remove
,
2728 .detach
= ar8xxx_phy_detach
,
2729 .config_init
= ar8xxx_phy_config_init
,
2730 .config_aneg
= ar8xxx_phy_config_aneg
,
2731 .read_status
= ar8xxx_phy_read_status
,
2732 .soft_reset
= ar8xxx_phy_soft_reset
,
2736 static const struct of_device_id ar8xxx_mdiodev_of_match
[] = {
2738 .compatible
= "qca,ar7240sw",
2739 .data
= &ar7240sw_chip
,
2741 .compatible
= "qca,ar8229",
2742 .data
= &ar8229_chip
,
2744 .compatible
= "qca,ar8236",
2745 .data
= &ar8236_chip
,
2747 .compatible
= "qca,ar8327",
2748 .data
= &ar8327_chip
,
2754 ar8xxx_mdiodev_probe(struct mdio_device
*mdiodev
)
2756 const struct of_device_id
*match
;
2757 struct ar8xxx_priv
*priv
;
2758 struct switch_dev
*swdev
;
2759 struct device_node
*mdio_node
;
2762 match
= of_match_device(ar8xxx_mdiodev_of_match
, &mdiodev
->dev
);
2766 priv
= ar8xxx_create();
2770 priv
->mii_bus
= mdiodev
->bus
;
2771 priv
->pdev
= &mdiodev
->dev
;
2772 priv
->chip
= (const struct ar8xxx_chip
*) match
->data
;
2774 ret
= of_property_read_u32(priv
->pdev
->of_node
, "qca,mib-poll-interval",
2775 &priv
->mib_poll_interval
);
2777 priv
->mib_poll_interval
= 0;
2779 ret
= ar8xxx_read_id(priv
);
2783 ret
= ar8xxx_probe_switch(priv
);
2787 if (priv
->chip
->phy_read
&& priv
->chip
->phy_write
) {
2788 priv
->sw_mii_bus
= devm_mdiobus_alloc(&mdiodev
->dev
);
2789 priv
->sw_mii_bus
->name
= "ar8xxx-mdio";
2790 priv
->sw_mii_bus
->read
= ar8xxx_phy_read
;
2791 priv
->sw_mii_bus
->write
= ar8xxx_phy_write
;
2792 priv
->sw_mii_bus
->priv
= priv
;
2793 priv
->sw_mii_bus
->parent
= &mdiodev
->dev
;
2794 snprintf(priv
->sw_mii_bus
->id
, MII_BUS_ID_SIZE
, "%s",
2795 dev_name(&mdiodev
->dev
));
2796 mdio_node
= of_get_child_by_name(priv
->pdev
->of_node
, "mdio-bus");
2797 ret
= of_mdiobus_register(priv
->sw_mii_bus
, mdio_node
);
2803 swdev
->alias
= dev_name(&mdiodev
->dev
);
2805 if (of_property_read_bool(priv
->pdev
->of_node
, "qca,phy4-mii-enable")) {
2806 priv
->port4_phy
= true;
2810 ret
= register_switch(swdev
, NULL
);
2814 pr_info("%s: %s rev. %u switch registered on %s\n",
2815 swdev
->devname
, swdev
->name
, priv
->chip_rev
,
2816 dev_name(&priv
->mii_bus
->dev
));
2818 mutex_lock(&ar8xxx_dev_list_lock
);
2819 list_add(&priv
->list
, &ar8xxx_dev_list
);
2820 mutex_unlock(&ar8xxx_dev_list_lock
);
2824 ret
= ar8xxx_start(priv
);
2826 goto err_unregister_switch
;
2828 dev_set_drvdata(&mdiodev
->dev
, priv
);
2832 err_unregister_switch
:
2833 if (--priv
->use_count
)
2836 unregister_switch(&priv
->dev
);
2844 ar8xxx_mdiodev_remove(struct mdio_device
*mdiodev
)
2846 struct ar8xxx_priv
*priv
= dev_get_drvdata(&mdiodev
->dev
);
2851 mutex_lock(&ar8xxx_dev_list_lock
);
2853 if (--priv
->use_count
> 0) {
2854 mutex_unlock(&ar8xxx_dev_list_lock
);
2858 list_del(&priv
->list
);
2859 mutex_unlock(&ar8xxx_dev_list_lock
);
2861 unregister_switch(&priv
->dev
);
2862 ar8xxx_mib_stop(priv
);
2863 if(priv
->sw_mii_bus
)
2864 mdiobus_unregister(priv
->sw_mii_bus
);
2868 static struct mdio_driver ar8xxx_mdio_driver
= {
2869 .probe
= ar8xxx_mdiodev_probe
,
2870 .remove
= ar8xxx_mdiodev_remove
,
2872 .name
= "ar8xxx-switch",
2873 .of_match_table
= ar8xxx_mdiodev_of_match
,
2877 static int __init
ar8216_init(void)
2881 ret
= phy_drivers_register(ar8xxx_phy_driver
,
2882 ARRAY_SIZE(ar8xxx_phy_driver
),
2887 ret
= mdio_driver_register(&ar8xxx_mdio_driver
);
2889 phy_drivers_unregister(ar8xxx_phy_driver
,
2890 ARRAY_SIZE(ar8xxx_phy_driver
));
2894 module_init(ar8216_init
);
2896 static void __exit
ar8216_exit(void)
2898 mdio_driver_unregister(&ar8xxx_mdio_driver
);
2899 phy_drivers_unregister(ar8xxx_phy_driver
,
2900 ARRAY_SIZE(ar8xxx_phy_driver
));
2902 module_exit(ar8216_exit
);
2904 MODULE_LICENSE("GPL");