2 * ar8216.c: AR8216 switch driver
4 * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>
5 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/list.h>
22 #include <linux/if_ether.h>
23 #include <linux/skbuff.h>
24 #include <linux/netdevice.h>
25 #include <linux/netlink.h>
26 #include <linux/bitops.h>
27 #include <net/genetlink.h>
28 #include <linux/switch.h>
29 #include <linux/delay.h>
30 #include <linux/phy.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/lockdep.h>
34 #include <linux/ar8216_platform.h>
35 #include <linux/workqueue.h>
36 #include <linux/version.h>
40 extern const struct ar8xxx_chip ar8327_chip
;
41 extern const struct ar8xxx_chip ar8337_chip
;
43 #define AR8XXX_MIB_WORK_DELAY 2000 /* msecs */
45 #define MIB_DESC(_s , _o, _n) \
52 static const struct ar8xxx_mib_desc ar8216_mibs
[] = {
53 MIB_DESC(1, AR8216_STATS_RXBROAD
, "RxBroad"),
54 MIB_DESC(1, AR8216_STATS_RXPAUSE
, "RxPause"),
55 MIB_DESC(1, AR8216_STATS_RXMULTI
, "RxMulti"),
56 MIB_DESC(1, AR8216_STATS_RXFCSERR
, "RxFcsErr"),
57 MIB_DESC(1, AR8216_STATS_RXALIGNERR
, "RxAlignErr"),
58 MIB_DESC(1, AR8216_STATS_RXRUNT
, "RxRunt"),
59 MIB_DESC(1, AR8216_STATS_RXFRAGMENT
, "RxFragment"),
60 MIB_DESC(1, AR8216_STATS_RX64BYTE
, "Rx64Byte"),
61 MIB_DESC(1, AR8216_STATS_RX128BYTE
, "Rx128Byte"),
62 MIB_DESC(1, AR8216_STATS_RX256BYTE
, "Rx256Byte"),
63 MIB_DESC(1, AR8216_STATS_RX512BYTE
, "Rx512Byte"),
64 MIB_DESC(1, AR8216_STATS_RX1024BYTE
, "Rx1024Byte"),
65 MIB_DESC(1, AR8216_STATS_RXMAXBYTE
, "RxMaxByte"),
66 MIB_DESC(1, AR8216_STATS_RXTOOLONG
, "RxTooLong"),
67 MIB_DESC(2, AR8216_STATS_RXGOODBYTE
, "RxGoodByte"),
68 MIB_DESC(2, AR8216_STATS_RXBADBYTE
, "RxBadByte"),
69 MIB_DESC(1, AR8216_STATS_RXOVERFLOW
, "RxOverFlow"),
70 MIB_DESC(1, AR8216_STATS_FILTERED
, "Filtered"),
71 MIB_DESC(1, AR8216_STATS_TXBROAD
, "TxBroad"),
72 MIB_DESC(1, AR8216_STATS_TXPAUSE
, "TxPause"),
73 MIB_DESC(1, AR8216_STATS_TXMULTI
, "TxMulti"),
74 MIB_DESC(1, AR8216_STATS_TXUNDERRUN
, "TxUnderRun"),
75 MIB_DESC(1, AR8216_STATS_TX64BYTE
, "Tx64Byte"),
76 MIB_DESC(1, AR8216_STATS_TX128BYTE
, "Tx128Byte"),
77 MIB_DESC(1, AR8216_STATS_TX256BYTE
, "Tx256Byte"),
78 MIB_DESC(1, AR8216_STATS_TX512BYTE
, "Tx512Byte"),
79 MIB_DESC(1, AR8216_STATS_TX1024BYTE
, "Tx1024Byte"),
80 MIB_DESC(1, AR8216_STATS_TXMAXBYTE
, "TxMaxByte"),
81 MIB_DESC(1, AR8216_STATS_TXOVERSIZE
, "TxOverSize"),
82 MIB_DESC(2, AR8216_STATS_TXBYTE
, "TxByte"),
83 MIB_DESC(1, AR8216_STATS_TXCOLLISION
, "TxCollision"),
84 MIB_DESC(1, AR8216_STATS_TXABORTCOL
, "TxAbortCol"),
85 MIB_DESC(1, AR8216_STATS_TXMULTICOL
, "TxMultiCol"),
86 MIB_DESC(1, AR8216_STATS_TXSINGLECOL
, "TxSingleCol"),
87 MIB_DESC(1, AR8216_STATS_TXEXCDEFER
, "TxExcDefer"),
88 MIB_DESC(1, AR8216_STATS_TXDEFER
, "TxDefer"),
89 MIB_DESC(1, AR8216_STATS_TXLATECOL
, "TxLateCol"),
92 const struct ar8xxx_mib_desc ar8236_mibs
[39] = {
93 MIB_DESC(1, AR8236_STATS_RXBROAD
, "RxBroad"),
94 MIB_DESC(1, AR8236_STATS_RXPAUSE
, "RxPause"),
95 MIB_DESC(1, AR8236_STATS_RXMULTI
, "RxMulti"),
96 MIB_DESC(1, AR8236_STATS_RXFCSERR
, "RxFcsErr"),
97 MIB_DESC(1, AR8236_STATS_RXALIGNERR
, "RxAlignErr"),
98 MIB_DESC(1, AR8236_STATS_RXRUNT
, "RxRunt"),
99 MIB_DESC(1, AR8236_STATS_RXFRAGMENT
, "RxFragment"),
100 MIB_DESC(1, AR8236_STATS_RX64BYTE
, "Rx64Byte"),
101 MIB_DESC(1, AR8236_STATS_RX128BYTE
, "Rx128Byte"),
102 MIB_DESC(1, AR8236_STATS_RX256BYTE
, "Rx256Byte"),
103 MIB_DESC(1, AR8236_STATS_RX512BYTE
, "Rx512Byte"),
104 MIB_DESC(1, AR8236_STATS_RX1024BYTE
, "Rx1024Byte"),
105 MIB_DESC(1, AR8236_STATS_RX1518BYTE
, "Rx1518Byte"),
106 MIB_DESC(1, AR8236_STATS_RXMAXBYTE
, "RxMaxByte"),
107 MIB_DESC(1, AR8236_STATS_RXTOOLONG
, "RxTooLong"),
108 MIB_DESC(2, AR8236_STATS_RXGOODBYTE
, "RxGoodByte"),
109 MIB_DESC(2, AR8236_STATS_RXBADBYTE
, "RxBadByte"),
110 MIB_DESC(1, AR8236_STATS_RXOVERFLOW
, "RxOverFlow"),
111 MIB_DESC(1, AR8236_STATS_FILTERED
, "Filtered"),
112 MIB_DESC(1, AR8236_STATS_TXBROAD
, "TxBroad"),
113 MIB_DESC(1, AR8236_STATS_TXPAUSE
, "TxPause"),
114 MIB_DESC(1, AR8236_STATS_TXMULTI
, "TxMulti"),
115 MIB_DESC(1, AR8236_STATS_TXUNDERRUN
, "TxUnderRun"),
116 MIB_DESC(1, AR8236_STATS_TX64BYTE
, "Tx64Byte"),
117 MIB_DESC(1, AR8236_STATS_TX128BYTE
, "Tx128Byte"),
118 MIB_DESC(1, AR8236_STATS_TX256BYTE
, "Tx256Byte"),
119 MIB_DESC(1, AR8236_STATS_TX512BYTE
, "Tx512Byte"),
120 MIB_DESC(1, AR8236_STATS_TX1024BYTE
, "Tx1024Byte"),
121 MIB_DESC(1, AR8236_STATS_TX1518BYTE
, "Tx1518Byte"),
122 MIB_DESC(1, AR8236_STATS_TXMAXBYTE
, "TxMaxByte"),
123 MIB_DESC(1, AR8236_STATS_TXOVERSIZE
, "TxOverSize"),
124 MIB_DESC(2, AR8236_STATS_TXBYTE
, "TxByte"),
125 MIB_DESC(1, AR8236_STATS_TXCOLLISION
, "TxCollision"),
126 MIB_DESC(1, AR8236_STATS_TXABORTCOL
, "TxAbortCol"),
127 MIB_DESC(1, AR8236_STATS_TXMULTICOL
, "TxMultiCol"),
128 MIB_DESC(1, AR8236_STATS_TXSINGLECOL
, "TxSingleCol"),
129 MIB_DESC(1, AR8236_STATS_TXEXCDEFER
, "TxExcDefer"),
130 MIB_DESC(1, AR8236_STATS_TXDEFER
, "TxDefer"),
131 MIB_DESC(1, AR8236_STATS_TXLATECOL
, "TxLateCol"),
134 static DEFINE_MUTEX(ar8xxx_dev_list_lock
);
135 static LIST_HEAD(ar8xxx_dev_list
);
137 /* inspired by phy_poll_reset in drivers/net/phy/phy_device.c */
139 ar8xxx_phy_poll_reset(struct mii_bus
*bus
)
141 unsigned int sleep_msecs
= 20;
144 for (elapsed
= sleep_msecs
; elapsed
<= 600;
145 elapsed
+= sleep_msecs
) {
147 for (i
= 0; i
< AR8XXX_NUM_PHYS
; i
++) {
148 ret
= mdiobus_read(bus
, i
, MII_BMCR
);
151 if (ret
& BMCR_RESET
)
153 if (i
== AR8XXX_NUM_PHYS
- 1) {
154 usleep_range(1000, 2000);
163 ar8xxx_phy_check_aneg(struct phy_device
*phydev
)
167 if (phydev
->autoneg
!= AUTONEG_ENABLE
)
170 * BMCR_ANENABLE might have been cleared
171 * by phy_init_hw in certain kernel versions
172 * therefore check for it
174 ret
= phy_read(phydev
, MII_BMCR
);
177 if (ret
& BMCR_ANENABLE
)
180 dev_info(&phydev
->dev
, "ANEG disabled, re-enabling ...\n");
181 ret
|= BMCR_ANENABLE
| BMCR_ANRESTART
;
182 return phy_write(phydev
, MII_BMCR
, ret
);
186 ar8xxx_phy_init(struct ar8xxx_priv
*priv
)
192 for (i
= 0; i
< AR8XXX_NUM_PHYS
; i
++) {
193 if (priv
->chip
->phy_fixup
)
194 priv
->chip
->phy_fixup(priv
, i
);
196 /* initialize the port itself */
197 mdiobus_write(bus
, i
, MII_ADVERTISE
,
198 ADVERTISE_ALL
| ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
);
199 if (ar8xxx_has_gige(priv
))
200 mdiobus_write(bus
, i
, MII_CTRL1000
, ADVERTISE_1000FULL
);
201 mdiobus_write(bus
, i
, MII_BMCR
, BMCR_RESET
| BMCR_ANENABLE
);
204 ar8xxx_phy_poll_reset(bus
);
208 ar8xxx_mii_read32(struct ar8xxx_priv
*priv
, int phy_id
, int regnum
)
210 struct mii_bus
*bus
= priv
->mii_bus
;
213 lo
= bus
->read(bus
, phy_id
, regnum
);
214 hi
= bus
->read(bus
, phy_id
, regnum
+ 1);
216 return (hi
<< 16) | lo
;
220 ar8xxx_mii_write32(struct ar8xxx_priv
*priv
, int phy_id
, int regnum
, u32 val
)
222 struct mii_bus
*bus
= priv
->mii_bus
;
226 hi
= (u16
) (val
>> 16);
228 if (priv
->chip
->mii_lo_first
)
230 bus
->write(bus
, phy_id
, regnum
, lo
);
231 bus
->write(bus
, phy_id
, regnum
+ 1, hi
);
233 bus
->write(bus
, phy_id
, regnum
+ 1, hi
);
234 bus
->write(bus
, phy_id
, regnum
, lo
);
239 ar8xxx_read(struct ar8xxx_priv
*priv
, int reg
)
241 struct mii_bus
*bus
= priv
->mii_bus
;
245 split_addr((u32
) reg
, &r1
, &r2
, &page
);
247 mutex_lock(&bus
->mdio_lock
);
249 bus
->write(bus
, 0x18, 0, page
);
250 wait_for_page_switch();
251 val
= ar8xxx_mii_read32(priv
, 0x10 | r2
, r1
);
253 mutex_unlock(&bus
->mdio_lock
);
259 ar8xxx_write(struct ar8xxx_priv
*priv
, int reg
, u32 val
)
261 struct mii_bus
*bus
= priv
->mii_bus
;
264 split_addr((u32
) reg
, &r1
, &r2
, &page
);
266 mutex_lock(&bus
->mdio_lock
);
268 bus
->write(bus
, 0x18, 0, page
);
269 wait_for_page_switch();
270 ar8xxx_mii_write32(priv
, 0x10 | r2
, r1
, val
);
272 mutex_unlock(&bus
->mdio_lock
);
276 ar8xxx_rmw(struct ar8xxx_priv
*priv
, int reg
, u32 mask
, u32 val
)
278 struct mii_bus
*bus
= priv
->mii_bus
;
282 split_addr((u32
) reg
, &r1
, &r2
, &page
);
284 mutex_lock(&bus
->mdio_lock
);
286 bus
->write(bus
, 0x18, 0, page
);
287 wait_for_page_switch();
289 ret
= ar8xxx_mii_read32(priv
, 0x10 | r2
, r1
);
292 ar8xxx_mii_write32(priv
, 0x10 | r2
, r1
, ret
);
294 mutex_unlock(&bus
->mdio_lock
);
300 ar8xxx_phy_dbg_write(struct ar8xxx_priv
*priv
, int phy_addr
,
301 u16 dbg_addr
, u16 dbg_data
)
303 struct mii_bus
*bus
= priv
->mii_bus
;
305 mutex_lock(&bus
->mdio_lock
);
306 bus
->write(bus
, phy_addr
, MII_ATH_DBG_ADDR
, dbg_addr
);
307 bus
->write(bus
, phy_addr
, MII_ATH_DBG_DATA
, dbg_data
);
308 mutex_unlock(&bus
->mdio_lock
);
312 ar8xxx_phy_mmd_prep(struct mii_bus
*bus
, int phy_addr
, u16 addr
, u16 reg
)
314 bus
->write(bus
, phy_addr
, MII_ATH_MMD_ADDR
, addr
);
315 bus
->write(bus
, phy_addr
, MII_ATH_MMD_DATA
, reg
);
316 bus
->write(bus
, phy_addr
, MII_ATH_MMD_ADDR
, addr
| 0x4000);
320 ar8xxx_phy_mmd_write(struct ar8xxx_priv
*priv
, int phy_addr
, u16 addr
, u16 reg
, u16 data
)
322 struct mii_bus
*bus
= priv
->mii_bus
;
324 mutex_lock(&bus
->mdio_lock
);
325 ar8xxx_phy_mmd_prep(bus
, phy_addr
, addr
, reg
);
326 bus
->write(bus
, phy_addr
, MII_ATH_MMD_DATA
, data
);
327 mutex_unlock(&bus
->mdio_lock
);
331 ar8xxx_phy_mmd_read(struct ar8xxx_priv
*priv
, int phy_addr
, u16 addr
, u16 reg
)
333 struct mii_bus
*bus
= priv
->mii_bus
;
336 mutex_lock(&bus
->mdio_lock
);
337 ar8xxx_phy_mmd_prep(bus
, phy_addr
, addr
, reg
);
338 data
= bus
->read(bus
, phy_addr
, MII_ATH_MMD_DATA
);
339 mutex_unlock(&bus
->mdio_lock
);
345 ar8xxx_reg_wait(struct ar8xxx_priv
*priv
, u32 reg
, u32 mask
, u32 val
,
350 for (i
= 0; i
< timeout
; i
++) {
353 t
= ar8xxx_read(priv
, reg
);
354 if ((t
& mask
) == val
)
357 usleep_range(1000, 2000);
364 ar8xxx_mib_op(struct ar8xxx_priv
*priv
, u32 op
)
366 unsigned mib_func
= priv
->chip
->mib_func
;
369 lockdep_assert_held(&priv
->mib_lock
);
371 /* Capture the hardware statistics for all ports */
372 ar8xxx_rmw(priv
, mib_func
, AR8216_MIB_FUNC
, (op
<< AR8216_MIB_FUNC_S
));
374 /* Wait for the capturing to complete. */
375 ret
= ar8xxx_reg_wait(priv
, mib_func
, AR8216_MIB_BUSY
, 0, 10);
386 ar8xxx_mib_capture(struct ar8xxx_priv
*priv
)
388 return ar8xxx_mib_op(priv
, AR8216_MIB_FUNC_CAPTURE
);
392 ar8xxx_mib_flush(struct ar8xxx_priv
*priv
)
394 return ar8xxx_mib_op(priv
, AR8216_MIB_FUNC_FLUSH
);
398 ar8xxx_mib_fetch_port_stat(struct ar8xxx_priv
*priv
, int port
, bool flush
)
404 WARN_ON(port
>= priv
->dev
.ports
);
406 lockdep_assert_held(&priv
->mib_lock
);
408 base
= priv
->chip
->reg_port_stats_start
+
409 priv
->chip
->reg_port_stats_length
* port
;
411 mib_stats
= &priv
->mib_stats
[port
* priv
->chip
->num_mibs
];
412 for (i
= 0; i
< priv
->chip
->num_mibs
; i
++) {
413 const struct ar8xxx_mib_desc
*mib
;
416 mib
= &priv
->chip
->mib_decs
[i
];
417 t
= ar8xxx_read(priv
, base
+ mib
->offset
);
418 if (mib
->size
== 2) {
421 hi
= ar8xxx_read(priv
, base
+ mib
->offset
+ 4);
433 ar8216_read_port_link(struct ar8xxx_priv
*priv
, int port
,
434 struct switch_port_link
*link
)
439 memset(link
, '\0', sizeof(*link
));
441 status
= priv
->chip
->read_port_status(priv
, port
);
443 link
->aneg
= !!(status
& AR8216_PORT_STATUS_LINK_AUTO
);
445 link
->link
= !!(status
& AR8216_PORT_STATUS_LINK_UP
);
449 if (priv
->get_port_link
) {
452 err
= priv
->get_port_link(port
);
461 link
->duplex
= !!(status
& AR8216_PORT_STATUS_DUPLEX
);
462 link
->tx_flow
= !!(status
& AR8216_PORT_STATUS_TXFLOW
);
463 link
->rx_flow
= !!(status
& AR8216_PORT_STATUS_RXFLOW
);
465 if (link
->aneg
&& link
->duplex
&& priv
->chip
->read_port_eee_status
)
466 link
->eee
= priv
->chip
->read_port_eee_status(priv
, port
);
468 speed
= (status
& AR8216_PORT_STATUS_SPEED
) >>
469 AR8216_PORT_STATUS_SPEED_S
;
472 case AR8216_PORT_SPEED_10M
:
473 link
->speed
= SWITCH_PORT_SPEED_10
;
475 case AR8216_PORT_SPEED_100M
:
476 link
->speed
= SWITCH_PORT_SPEED_100
;
478 case AR8216_PORT_SPEED_1000M
:
479 link
->speed
= SWITCH_PORT_SPEED_1000
;
482 link
->speed
= SWITCH_PORT_SPEED_UNKNOWN
;
487 static struct sk_buff
*
488 ar8216_mangle_tx(struct net_device
*dev
, struct sk_buff
*skb
)
490 struct ar8xxx_priv
*priv
= dev
->phy_ptr
;
499 if (unlikely(skb_headroom(skb
) < 2)) {
500 if (pskb_expand_head(skb
, 2, 0, GFP_ATOMIC
) < 0)
504 buf
= skb_push(skb
, 2);
512 dev_kfree_skb_any(skb
);
517 ar8216_mangle_rx(struct net_device
*dev
, struct sk_buff
*skb
)
519 struct ar8xxx_priv
*priv
;
527 /* don't strip the header if vlan mode is disabled */
531 /* strip header, get vlan id */
535 /* check for vlan header presence */
536 if ((buf
[12 + 2] != 0x81) || (buf
[13 + 2] != 0x00))
541 /* no need to fix up packets coming from a tagged source */
542 if (priv
->vlan_tagged
& (1 << port
))
545 /* lookup port vid from local table, the switch passes an invalid vlan id */
546 vlan
= priv
->vlan_id
[priv
->pvid
[port
]];
549 buf
[14 + 2] |= vlan
>> 8;
550 buf
[15 + 2] = vlan
& 0xff;
554 ar8216_wait_bit(struct ar8xxx_priv
*priv
, int reg
, u32 mask
, u32 val
)
560 t
= ar8xxx_read(priv
, reg
);
561 if ((t
& mask
) == val
)
570 pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
571 (unsigned int) reg
, t
, mask
, val
);
576 ar8216_vtu_op(struct ar8xxx_priv
*priv
, u32 op
, u32 val
)
578 if (ar8216_wait_bit(priv
, AR8216_REG_VTU
, AR8216_VTU_ACTIVE
, 0))
580 if ((op
& AR8216_VTU_OP
) == AR8216_VTU_OP_LOAD
) {
581 val
&= AR8216_VTUDATA_MEMBER
;
582 val
|= AR8216_VTUDATA_VALID
;
583 ar8xxx_write(priv
, AR8216_REG_VTU_DATA
, val
);
585 op
|= AR8216_VTU_ACTIVE
;
586 ar8xxx_write(priv
, AR8216_REG_VTU
, op
);
590 ar8216_vtu_flush(struct ar8xxx_priv
*priv
)
592 ar8216_vtu_op(priv
, AR8216_VTU_OP_FLUSH
, 0);
596 ar8216_vtu_load_vlan(struct ar8xxx_priv
*priv
, u32 vid
, u32 port_mask
)
600 op
= AR8216_VTU_OP_LOAD
| (vid
<< AR8216_VTU_VID_S
);
601 ar8216_vtu_op(priv
, op
, port_mask
);
605 ar8216_atu_flush(struct ar8xxx_priv
*priv
)
609 ret
= ar8216_wait_bit(priv
, AR8216_REG_ATU_FUNC0
, AR8216_ATU_ACTIVE
, 0);
611 ar8xxx_write(priv
, AR8216_REG_ATU_FUNC0
, AR8216_ATU_OP_FLUSH
|
618 ar8216_atu_flush_port(struct ar8xxx_priv
*priv
, int port
)
623 ret
= ar8216_wait_bit(priv
, AR8216_REG_ATU_FUNC0
, AR8216_ATU_ACTIVE
, 0);
625 t
= (port
<< AR8216_ATU_PORT_NUM_S
) | AR8216_ATU_OP_FLUSH_PORT
;
626 t
|= AR8216_ATU_ACTIVE
;
627 ar8xxx_write(priv
, AR8216_REG_ATU_FUNC0
, t
);
634 ar8216_read_port_status(struct ar8xxx_priv
*priv
, int port
)
636 return ar8xxx_read(priv
, AR8216_REG_PORT_STATUS(port
));
640 ar8216_setup_port(struct ar8xxx_priv
*priv
, int port
, u32 members
)
647 pvid
= priv
->vlan_id
[priv
->pvid
[port
]];
648 if (priv
->vlan_tagged
& (1 << port
))
649 egress
= AR8216_OUT_ADD_VLAN
;
651 egress
= AR8216_OUT_STRIP_VLAN
;
652 ingress
= AR8216_IN_SECURE
;
655 egress
= AR8216_OUT_KEEP
;
656 ingress
= AR8216_IN_PORT_ONLY
;
659 if (chip_is_ar8216(priv
) && priv
->vlan
&& port
== AR8216_PORT_CPU
)
660 header
= AR8216_PORT_CTRL_HEADER
;
664 ar8xxx_rmw(priv
, AR8216_REG_PORT_CTRL(port
),
665 AR8216_PORT_CTRL_LEARN
| AR8216_PORT_CTRL_VLAN_MODE
|
666 AR8216_PORT_CTRL_SINGLE_VLAN
| AR8216_PORT_CTRL_STATE
|
667 AR8216_PORT_CTRL_HEADER
| AR8216_PORT_CTRL_LEARN_LOCK
,
668 AR8216_PORT_CTRL_LEARN
| header
|
669 (egress
<< AR8216_PORT_CTRL_VLAN_MODE_S
) |
670 (AR8216_PORT_STATE_FORWARD
<< AR8216_PORT_CTRL_STATE_S
));
672 ar8xxx_rmw(priv
, AR8216_REG_PORT_VLAN(port
),
673 AR8216_PORT_VLAN_DEST_PORTS
| AR8216_PORT_VLAN_MODE
|
674 AR8216_PORT_VLAN_DEFAULT_ID
,
675 (members
<< AR8216_PORT_VLAN_DEST_PORTS_S
) |
676 (ingress
<< AR8216_PORT_VLAN_MODE_S
) |
677 (pvid
<< AR8216_PORT_VLAN_DEFAULT_ID_S
));
681 ar8216_hw_init(struct ar8xxx_priv
*priv
)
683 if (priv
->initialized
)
686 ar8xxx_phy_init(priv
);
688 priv
->initialized
= true;
693 ar8216_init_globals(struct ar8xxx_priv
*priv
)
695 /* standard atheros magic */
696 ar8xxx_write(priv
, 0x38, 0xc000050e);
698 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
699 AR8216_GCTRL_MTU
, 1518 + 8 + 2);
703 ar8216_init_port(struct ar8xxx_priv
*priv
, int port
)
705 /* Enable port learning and tx */
706 ar8xxx_write(priv
, AR8216_REG_PORT_CTRL(port
),
707 AR8216_PORT_CTRL_LEARN
|
708 (4 << AR8216_PORT_CTRL_STATE_S
));
710 ar8xxx_write(priv
, AR8216_REG_PORT_VLAN(port
), 0);
712 if (port
== AR8216_PORT_CPU
) {
713 ar8xxx_write(priv
, AR8216_REG_PORT_STATUS(port
),
714 AR8216_PORT_STATUS_LINK_UP
|
715 (ar8xxx_has_gige(priv
) ?
716 AR8216_PORT_SPEED_1000M
: AR8216_PORT_SPEED_100M
) |
717 AR8216_PORT_STATUS_TXMAC
|
718 AR8216_PORT_STATUS_RXMAC
|
719 (chip_is_ar8316(priv
) ? AR8216_PORT_STATUS_RXFLOW
: 0) |
720 (chip_is_ar8316(priv
) ? AR8216_PORT_STATUS_TXFLOW
: 0) |
721 AR8216_PORT_STATUS_DUPLEX
);
723 ar8xxx_write(priv
, AR8216_REG_PORT_STATUS(port
),
724 AR8216_PORT_STATUS_LINK_AUTO
);
729 ar8216_wait_atu_ready(struct ar8xxx_priv
*priv
, u16 r2
, u16 r1
)
733 while (ar8xxx_mii_read32(priv
, r2
, r1
) & AR8216_ATU_ACTIVE
&& --timeout
)
737 pr_err("ar8216: timeout waiting for atu to become ready\n");
740 static void ar8216_get_arl_entry(struct ar8xxx_priv
*priv
,
741 struct arl_entry
*a
, u32
*status
, enum arl_op op
)
743 struct mii_bus
*bus
= priv
->mii_bus
;
745 u16 r1_func0
, r1_func1
, r1_func2
;
746 u32 t
, val0
, val1
, val2
;
749 split_addr(AR8216_REG_ATU_FUNC0
, &r1_func0
, &r2
, &page
);
752 r1_func1
= (AR8216_REG_ATU_FUNC1
>> 1) & 0x1e;
753 r1_func2
= (AR8216_REG_ATU_FUNC2
>> 1) & 0x1e;
756 case AR8XXX_ARL_INITIALIZE
:
757 /* all ATU registers are on the same page
758 * therefore set page only once
760 bus
->write(bus
, 0x18, 0, page
);
761 wait_for_page_switch();
763 ar8216_wait_atu_ready(priv
, r2
, r1_func0
);
765 ar8xxx_mii_write32(priv
, r2
, r1_func0
, AR8216_ATU_OP_GET_NEXT
);
766 ar8xxx_mii_write32(priv
, r2
, r1_func1
, 0);
767 ar8xxx_mii_write32(priv
, r2
, r1_func2
, 0);
769 case AR8XXX_ARL_GET_NEXT
:
770 t
= ar8xxx_mii_read32(priv
, r2
, r1_func0
);
771 t
|= AR8216_ATU_ACTIVE
;
772 ar8xxx_mii_write32(priv
, r2
, r1_func0
, t
);
773 ar8216_wait_atu_ready(priv
, r2
, r1_func0
);
775 val0
= ar8xxx_mii_read32(priv
, r2
, r1_func0
);
776 val1
= ar8xxx_mii_read32(priv
, r2
, r1_func1
);
777 val2
= ar8xxx_mii_read32(priv
, r2
, r1_func2
);
779 *status
= (val2
& AR8216_ATU_STATUS
) >> AR8216_ATU_STATUS_S
;
784 t
= AR8216_ATU_PORT0
;
785 while (!(val2
& t
) && ++i
< priv
->dev
.ports
)
789 a
->mac
[0] = (val0
& AR8216_ATU_ADDR5
) >> AR8216_ATU_ADDR5_S
;
790 a
->mac
[1] = (val0
& AR8216_ATU_ADDR4
) >> AR8216_ATU_ADDR4_S
;
791 a
->mac
[2] = (val1
& AR8216_ATU_ADDR3
) >> AR8216_ATU_ADDR3_S
;
792 a
->mac
[3] = (val1
& AR8216_ATU_ADDR2
) >> AR8216_ATU_ADDR2_S
;
793 a
->mac
[4] = (val1
& AR8216_ATU_ADDR1
) >> AR8216_ATU_ADDR1_S
;
794 a
->mac
[5] = (val1
& AR8216_ATU_ADDR0
) >> AR8216_ATU_ADDR0_S
;
800 ar8236_setup_port(struct ar8xxx_priv
*priv
, int port
, u32 members
)
806 pvid
= priv
->vlan_id
[priv
->pvid
[port
]];
807 if (priv
->vlan_tagged
& (1 << port
))
808 egress
= AR8216_OUT_ADD_VLAN
;
810 egress
= AR8216_OUT_STRIP_VLAN
;
811 ingress
= AR8216_IN_SECURE
;
814 egress
= AR8216_OUT_KEEP
;
815 ingress
= AR8216_IN_PORT_ONLY
;
818 ar8xxx_rmw(priv
, AR8216_REG_PORT_CTRL(port
),
819 AR8216_PORT_CTRL_LEARN
| AR8216_PORT_CTRL_VLAN_MODE
|
820 AR8216_PORT_CTRL_SINGLE_VLAN
| AR8216_PORT_CTRL_STATE
|
821 AR8216_PORT_CTRL_HEADER
| AR8216_PORT_CTRL_LEARN_LOCK
,
822 AR8216_PORT_CTRL_LEARN
|
823 (egress
<< AR8216_PORT_CTRL_VLAN_MODE_S
) |
824 (AR8216_PORT_STATE_FORWARD
<< AR8216_PORT_CTRL_STATE_S
));
826 ar8xxx_rmw(priv
, AR8236_REG_PORT_VLAN(port
),
827 AR8236_PORT_VLAN_DEFAULT_ID
,
828 (pvid
<< AR8236_PORT_VLAN_DEFAULT_ID_S
));
830 ar8xxx_rmw(priv
, AR8236_REG_PORT_VLAN2(port
),
831 AR8236_PORT_VLAN2_VLAN_MODE
|
832 AR8236_PORT_VLAN2_MEMBER
,
833 (ingress
<< AR8236_PORT_VLAN2_VLAN_MODE_S
) |
834 (members
<< AR8236_PORT_VLAN2_MEMBER_S
));
838 ar8236_init_globals(struct ar8xxx_priv
*priv
)
840 /* enable jumbo frames */
841 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
842 AR8316_GCTRL_MTU
, 9018 + 8 + 2);
844 /* enable cpu port to receive arp frames */
845 ar8xxx_reg_set(priv
, AR8216_REG_ATU_CTRL
,
846 AR8236_ATU_CTRL_RES
);
848 /* enable cpu port to receive multicast and broadcast frames */
849 ar8xxx_reg_set(priv
, AR8216_REG_FLOOD_MASK
,
850 AR8236_FM_CPU_BROADCAST_EN
| AR8236_FM_CPU_BCAST_FWD_EN
);
852 /* Enable MIB counters */
853 ar8xxx_rmw(priv
, AR8216_REG_MIB_FUNC
, AR8216_MIB_FUNC
| AR8236_MIB_EN
,
854 (AR8216_MIB_FUNC_NO_OP
<< AR8216_MIB_FUNC_S
) |
859 ar8316_hw_init(struct ar8xxx_priv
*priv
)
863 val
= ar8xxx_read(priv
, AR8316_REG_POSTRIP
);
865 if (priv
->phy
->interface
== PHY_INTERFACE_MODE_RGMII
) {
866 if (priv
->port4_phy
) {
867 /* value taken from Ubiquiti RouterStation Pro */
869 pr_info("ar8316: Using port 4 as PHY\n");
872 pr_info("ar8316: Using port 4 as switch port\n");
874 } else if (priv
->phy
->interface
== PHY_INTERFACE_MODE_GMII
) {
875 /* value taken from AVM Fritz!Box 7390 sources */
878 /* no known value for phy interface */
879 pr_err("ar8316: unsupported mii mode: %d.\n",
880 priv
->phy
->interface
);
887 ar8xxx_write(priv
, AR8316_REG_POSTRIP
, newval
);
889 if (priv
->port4_phy
&&
890 priv
->phy
->interface
== PHY_INTERFACE_MODE_RGMII
) {
891 /* work around for phy4 rgmii mode */
892 ar8xxx_phy_dbg_write(priv
, 4, 0x12, 0x480c);
894 ar8xxx_phy_dbg_write(priv
, 4, 0x0, 0x824e);
896 ar8xxx_phy_dbg_write(priv
, 4, 0x5, 0x3d47);
900 ar8xxx_phy_init(priv
);
903 priv
->initialized
= true;
908 ar8316_init_globals(struct ar8xxx_priv
*priv
)
910 /* standard atheros magic */
911 ar8xxx_write(priv
, 0x38, 0xc000050e);
913 /* enable cpu port to receive multicast and broadcast frames */
914 ar8xxx_write(priv
, AR8216_REG_FLOOD_MASK
, 0x003f003f);
916 /* enable jumbo frames */
917 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
918 AR8316_GCTRL_MTU
, 9018 + 8 + 2);
920 /* Enable MIB counters */
921 ar8xxx_rmw(priv
, AR8216_REG_MIB_FUNC
, AR8216_MIB_FUNC
| AR8236_MIB_EN
,
922 (AR8216_MIB_FUNC_NO_OP
<< AR8216_MIB_FUNC_S
) |
927 ar8xxx_sw_set_vlan(struct switch_dev
*dev
, const struct switch_attr
*attr
,
928 struct switch_val
*val
)
930 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
931 priv
->vlan
= !!val
->value
.i
;
936 ar8xxx_sw_get_vlan(struct switch_dev
*dev
, const struct switch_attr
*attr
,
937 struct switch_val
*val
)
939 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
940 val
->value
.i
= priv
->vlan
;
946 ar8xxx_sw_set_pvid(struct switch_dev
*dev
, int port
, int vlan
)
948 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
950 /* make sure no invalid PVIDs get set */
952 if (vlan
< 0 || vlan
>= dev
->vlans
||
953 port
< 0 || port
>= AR8X16_MAX_PORTS
)
956 priv
->pvid
[port
] = vlan
;
961 ar8xxx_sw_get_pvid(struct switch_dev
*dev
, int port
, int *vlan
)
963 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
965 if (port
< 0 || port
>= AR8X16_MAX_PORTS
)
968 *vlan
= priv
->pvid
[port
];
973 ar8xxx_sw_set_vid(struct switch_dev
*dev
, const struct switch_attr
*attr
,
974 struct switch_val
*val
)
976 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
978 if (val
->port_vlan
>= AR8X16_MAX_PORTS
)
981 priv
->vlan_id
[val
->port_vlan
] = val
->value
.i
;
986 ar8xxx_sw_get_vid(struct switch_dev
*dev
, const struct switch_attr
*attr
,
987 struct switch_val
*val
)
989 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
990 val
->value
.i
= priv
->vlan_id
[val
->port_vlan
];
995 ar8xxx_sw_get_port_link(struct switch_dev
*dev
, int port
,
996 struct switch_port_link
*link
)
998 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1000 ar8216_read_port_link(priv
, port
, link
);
1005 ar8xxx_sw_get_ports(struct switch_dev
*dev
, struct switch_val
*val
)
1007 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1011 if (val
->port_vlan
>= AR8X16_MAX_VLANS
)
1014 ports
= priv
->vlan_table
[val
->port_vlan
];
1016 for (i
= 0; i
< dev
->ports
; i
++) {
1017 struct switch_port
*p
;
1019 if (!(ports
& (1 << i
)))
1022 p
= &val
->value
.ports
[val
->len
++];
1024 if (priv
->vlan_tagged
& (1 << i
))
1025 p
->flags
= (1 << SWITCH_PORT_FLAG_TAGGED
);
1033 ar8xxx_sw_set_ports(struct switch_dev
*dev
, struct switch_val
*val
)
1035 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1036 u8
*vt
= &priv
->vlan_table
[val
->port_vlan
];
1040 for (i
= 0; i
< val
->len
; i
++) {
1041 struct switch_port
*p
= &val
->value
.ports
[i
];
1043 if (p
->flags
& (1 << SWITCH_PORT_FLAG_TAGGED
)) {
1044 priv
->vlan_tagged
|= (1 << p
->id
);
1046 priv
->vlan_tagged
&= ~(1 << p
->id
);
1047 priv
->pvid
[p
->id
] = val
->port_vlan
;
1049 /* make sure that an untagged port does not
1050 * appear in other vlans */
1051 for (j
= 0; j
< AR8X16_MAX_VLANS
; j
++) {
1052 if (j
== val
->port_vlan
)
1054 priv
->vlan_table
[j
] &= ~(1 << p
->id
);
1064 ar8216_set_mirror_regs(struct ar8xxx_priv
*priv
)
1068 /* reset all mirror registers */
1069 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CPUPORT
,
1070 AR8216_GLOBAL_CPUPORT_MIRROR_PORT
,
1071 (0xF << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S
));
1072 for (port
= 0; port
< AR8216_NUM_PORTS
; port
++) {
1073 ar8xxx_reg_clear(priv
, AR8216_REG_PORT_CTRL(port
),
1074 AR8216_PORT_CTRL_MIRROR_RX
);
1076 ar8xxx_reg_clear(priv
, AR8216_REG_PORT_CTRL(port
),
1077 AR8216_PORT_CTRL_MIRROR_TX
);
1080 /* now enable mirroring if necessary */
1081 if (priv
->source_port
>= AR8216_NUM_PORTS
||
1082 priv
->monitor_port
>= AR8216_NUM_PORTS
||
1083 priv
->source_port
== priv
->monitor_port
) {
1087 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CPUPORT
,
1088 AR8216_GLOBAL_CPUPORT_MIRROR_PORT
,
1089 (priv
->monitor_port
<< AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S
));
1091 if (priv
->mirror_rx
)
1092 ar8xxx_reg_set(priv
, AR8216_REG_PORT_CTRL(priv
->source_port
),
1093 AR8216_PORT_CTRL_MIRROR_RX
);
1095 if (priv
->mirror_tx
)
1096 ar8xxx_reg_set(priv
, AR8216_REG_PORT_CTRL(priv
->source_port
),
1097 AR8216_PORT_CTRL_MIRROR_TX
);
1101 ar8xxx_age_time_val(int age_time
)
1103 return (age_time
+ AR8XXX_REG_ARL_CTRL_AGE_TIME_SECS
/ 2) /
1104 AR8XXX_REG_ARL_CTRL_AGE_TIME_SECS
;
1108 ar8xxx_set_age_time(struct ar8xxx_priv
*priv
, int reg
)
1110 u32 age_time
= ar8xxx_age_time_val(priv
->arl_age_time
);
1111 ar8xxx_rmw(priv
, reg
, AR8216_ATU_CTRL_AGE_TIME
, age_time
<< AR8216_ATU_CTRL_AGE_TIME_S
);
1115 ar8xxx_sw_hw_apply(struct switch_dev
*dev
)
1117 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1118 const struct ar8xxx_chip
*chip
= priv
->chip
;
1119 u8 portmask
[AR8X16_MAX_PORTS
];
1122 mutex_lock(&priv
->reg_mutex
);
1123 /* flush all vlan translation unit entries */
1124 priv
->chip
->vtu_flush(priv
);
1126 memset(portmask
, 0, sizeof(portmask
));
1128 /* calculate the port destination masks and load vlans
1129 * into the vlan translation unit */
1130 for (j
= 0; j
< AR8X16_MAX_VLANS
; j
++) {
1131 u8 vp
= priv
->vlan_table
[j
];
1136 for (i
= 0; i
< dev
->ports
; i
++) {
1139 portmask
[i
] |= vp
& ~mask
;
1142 chip
->vtu_load_vlan(priv
, priv
->vlan_id
[j
],
1143 priv
->vlan_table
[j
]);
1147 * isolate all ports, but connect them to the cpu port */
1148 for (i
= 0; i
< dev
->ports
; i
++) {
1149 if (i
== AR8216_PORT_CPU
)
1152 portmask
[i
] = 1 << AR8216_PORT_CPU
;
1153 portmask
[AR8216_PORT_CPU
] |= (1 << i
);
1157 /* update the port destination mask registers and tag settings */
1158 for (i
= 0; i
< dev
->ports
; i
++) {
1159 chip
->setup_port(priv
, i
, portmask
[i
]);
1162 chip
->set_mirror_regs(priv
);
1165 if (chip
->reg_arl_ctrl
)
1166 ar8xxx_set_age_time(priv
, chip
->reg_arl_ctrl
);
1168 mutex_unlock(&priv
->reg_mutex
);
1173 ar8xxx_sw_reset_switch(struct switch_dev
*dev
)
1175 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1176 const struct ar8xxx_chip
*chip
= priv
->chip
;
1179 mutex_lock(&priv
->reg_mutex
);
1180 memset(&priv
->vlan
, 0, sizeof(struct ar8xxx_priv
) -
1181 offsetof(struct ar8xxx_priv
, vlan
));
1183 for (i
= 0; i
< AR8X16_MAX_VLANS
; i
++)
1184 priv
->vlan_id
[i
] = i
;
1186 /* Configure all ports */
1187 for (i
= 0; i
< dev
->ports
; i
++)
1188 chip
->init_port(priv
, i
);
1190 priv
->mirror_rx
= false;
1191 priv
->mirror_tx
= false;
1192 priv
->source_port
= 0;
1193 priv
->monitor_port
= 0;
1194 priv
->arl_age_time
= AR8XXX_DEFAULT_ARL_AGE_TIME
;
1196 chip
->init_globals(priv
);
1198 mutex_unlock(&priv
->reg_mutex
);
1200 return chip
->sw_hw_apply(dev
);
1204 ar8xxx_sw_set_reset_mibs(struct switch_dev
*dev
,
1205 const struct switch_attr
*attr
,
1206 struct switch_val
*val
)
1208 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1212 if (!ar8xxx_has_mib_counters(priv
))
1215 mutex_lock(&priv
->mib_lock
);
1217 len
= priv
->dev
.ports
* priv
->chip
->num_mibs
*
1218 sizeof(*priv
->mib_stats
);
1219 memset(priv
->mib_stats
, '\0', len
);
1220 ret
= ar8xxx_mib_flush(priv
);
1227 mutex_unlock(&priv
->mib_lock
);
1232 ar8xxx_sw_set_mirror_rx_enable(struct switch_dev
*dev
,
1233 const struct switch_attr
*attr
,
1234 struct switch_val
*val
)
1236 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1238 mutex_lock(&priv
->reg_mutex
);
1239 priv
->mirror_rx
= !!val
->value
.i
;
1240 priv
->chip
->set_mirror_regs(priv
);
1241 mutex_unlock(&priv
->reg_mutex
);
1247 ar8xxx_sw_get_mirror_rx_enable(struct switch_dev
*dev
,
1248 const struct switch_attr
*attr
,
1249 struct switch_val
*val
)
1251 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1252 val
->value
.i
= priv
->mirror_rx
;
1257 ar8xxx_sw_set_mirror_tx_enable(struct switch_dev
*dev
,
1258 const struct switch_attr
*attr
,
1259 struct switch_val
*val
)
1261 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1263 mutex_lock(&priv
->reg_mutex
);
1264 priv
->mirror_tx
= !!val
->value
.i
;
1265 priv
->chip
->set_mirror_regs(priv
);
1266 mutex_unlock(&priv
->reg_mutex
);
1272 ar8xxx_sw_get_mirror_tx_enable(struct switch_dev
*dev
,
1273 const struct switch_attr
*attr
,
1274 struct switch_val
*val
)
1276 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1277 val
->value
.i
= priv
->mirror_tx
;
1282 ar8xxx_sw_set_mirror_monitor_port(struct switch_dev
*dev
,
1283 const struct switch_attr
*attr
,
1284 struct switch_val
*val
)
1286 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1288 mutex_lock(&priv
->reg_mutex
);
1289 priv
->monitor_port
= val
->value
.i
;
1290 priv
->chip
->set_mirror_regs(priv
);
1291 mutex_unlock(&priv
->reg_mutex
);
1297 ar8xxx_sw_get_mirror_monitor_port(struct switch_dev
*dev
,
1298 const struct switch_attr
*attr
,
1299 struct switch_val
*val
)
1301 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1302 val
->value
.i
= priv
->monitor_port
;
1307 ar8xxx_sw_set_mirror_source_port(struct switch_dev
*dev
,
1308 const struct switch_attr
*attr
,
1309 struct switch_val
*val
)
1311 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1313 mutex_lock(&priv
->reg_mutex
);
1314 priv
->source_port
= val
->value
.i
;
1315 priv
->chip
->set_mirror_regs(priv
);
1316 mutex_unlock(&priv
->reg_mutex
);
1322 ar8xxx_sw_get_mirror_source_port(struct switch_dev
*dev
,
1323 const struct switch_attr
*attr
,
1324 struct switch_val
*val
)
1326 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1327 val
->value
.i
= priv
->source_port
;
1332 ar8xxx_sw_set_port_reset_mib(struct switch_dev
*dev
,
1333 const struct switch_attr
*attr
,
1334 struct switch_val
*val
)
1336 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1340 if (!ar8xxx_has_mib_counters(priv
))
1343 port
= val
->port_vlan
;
1344 if (port
>= dev
->ports
)
1347 mutex_lock(&priv
->mib_lock
);
1348 ret
= ar8xxx_mib_capture(priv
);
1352 ar8xxx_mib_fetch_port_stat(priv
, port
, true);
1357 mutex_unlock(&priv
->mib_lock
);
1362 ar8xxx_byte_to_str(char *buf
, int len
, u64 byte
)
1367 if (byte
>= 0x40000000) { /* 1 GiB */
1368 b
= byte
* 10 / 0x40000000;
1370 } else if (byte
>= 0x100000) { /* 1 MiB */
1371 b
= byte
* 10 / 0x100000;
1373 } else if (byte
>= 0x400) { /* 1 KiB */
1374 b
= byte
* 10 / 0x400;
1380 if (strcmp(unit
, "Byte"))
1381 snprintf(buf
, len
, "%lu.%lu %s", b
/ 10, b
% 10, unit
);
1383 snprintf(buf
, len
, "%lu %s", b
, unit
);
1387 ar8xxx_sw_get_port_mib(struct switch_dev
*dev
,
1388 const struct switch_attr
*attr
,
1389 struct switch_val
*val
)
1391 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1392 const struct ar8xxx_chip
*chip
= priv
->chip
;
1393 u64
*mib_stats
, mib_data
;
1396 char *buf
= priv
->buf
;
1398 const char *mib_name
;
1400 bool mib_stats_empty
= true;
1402 if (!ar8xxx_has_mib_counters(priv
))
1405 port
= val
->port_vlan
;
1406 if (port
>= dev
->ports
)
1409 mutex_lock(&priv
->mib_lock
);
1410 ret
= ar8xxx_mib_capture(priv
);
1414 ar8xxx_mib_fetch_port_stat(priv
, port
, false);
1416 len
+= snprintf(buf
+ len
, sizeof(priv
->buf
) - len
,
1419 mib_stats
= &priv
->mib_stats
[port
* chip
->num_mibs
];
1420 for (i
= 0; i
< chip
->num_mibs
; i
++) {
1421 mib_name
= chip
->mib_decs
[i
].name
;
1422 mib_data
= mib_stats
[i
];
1423 len
+= snprintf(buf
+ len
, sizeof(priv
->buf
) - len
,
1424 "%-12s: %llu\n", mib_name
, mib_data
);
1425 if ((!strcmp(mib_name
, "TxByte") ||
1426 !strcmp(mib_name
, "RxGoodByte")) &&
1428 ar8xxx_byte_to_str(buf1
, sizeof(buf1
), mib_data
);
1429 --len
; /* discard newline at the end of buf */
1430 len
+= snprintf(buf
+ len
, sizeof(priv
->buf
) - len
,
1433 if (mib_stats_empty
&& mib_data
)
1434 mib_stats_empty
= false;
1437 if (mib_stats_empty
)
1438 len
= snprintf(buf
, sizeof(priv
->buf
), "No MIB data");
1446 mutex_unlock(&priv
->mib_lock
);
1451 ar8xxx_sw_set_arl_age_time(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1452 struct switch_val
*val
)
1454 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1455 int age_time
= val
->value
.i
;
1461 age_time_val
= ar8xxx_age_time_val(age_time
);
1462 if (age_time_val
== 0 || age_time_val
> 0xffff)
1465 priv
->arl_age_time
= age_time
;
1470 ar8xxx_sw_get_arl_age_time(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1471 struct switch_val
*val
)
1473 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1474 val
->value
.i
= priv
->arl_age_time
;
1479 ar8xxx_sw_get_arl_table(struct switch_dev
*dev
,
1480 const struct switch_attr
*attr
,
1481 struct switch_val
*val
)
1483 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1484 struct mii_bus
*bus
= priv
->mii_bus
;
1485 const struct ar8xxx_chip
*chip
= priv
->chip
;
1486 char *buf
= priv
->arl_buf
;
1487 int i
, j
, k
, len
= 0;
1488 struct arl_entry
*a
, *a1
;
1491 if (!chip
->get_arl_entry
)
1494 mutex_lock(&priv
->reg_mutex
);
1495 mutex_lock(&bus
->mdio_lock
);
1497 chip
->get_arl_entry(priv
, NULL
, NULL
, AR8XXX_ARL_INITIALIZE
);
1499 for(i
= 0; i
< AR8XXX_NUM_ARL_RECORDS
; ++i
) {
1500 a
= &priv
->arl_table
[i
];
1502 chip
->get_arl_entry(priv
, a
, &status
, AR8XXX_ARL_GET_NEXT
);
1508 * ARL table can include multiple valid entries
1509 * per MAC, just with differing status codes
1511 for (j
= 0; j
< i
; ++j
) {
1512 a1
= &priv
->arl_table
[j
];
1513 if (a
->port
== a1
->port
&& !memcmp(a
->mac
, a1
->mac
, sizeof(a
->mac
)))
1518 mutex_unlock(&bus
->mdio_lock
);
1520 len
+= snprintf(buf
+ len
, sizeof(priv
->arl_buf
) - len
,
1521 "address resolution table\n");
1523 if (i
== AR8XXX_NUM_ARL_RECORDS
)
1524 len
+= snprintf(buf
+ len
, sizeof(priv
->arl_buf
) - len
,
1525 "Too many entries found, displaying the first %d only!\n",
1526 AR8XXX_NUM_ARL_RECORDS
);
1528 for (j
= 0; j
< priv
->dev
.ports
; ++j
) {
1529 for (k
= 0; k
< i
; ++k
) {
1530 a
= &priv
->arl_table
[k
];
1533 len
+= snprintf(buf
+ len
, sizeof(priv
->arl_buf
) - len
,
1534 "Port %d: MAC %02x:%02x:%02x:%02x:%02x:%02x\n",
1536 a
->mac
[5], a
->mac
[4], a
->mac
[3],
1537 a
->mac
[2], a
->mac
[1], a
->mac
[0]);
1544 mutex_unlock(&priv
->reg_mutex
);
1550 ar8xxx_sw_set_flush_arl_table(struct switch_dev
*dev
,
1551 const struct switch_attr
*attr
,
1552 struct switch_val
*val
)
1554 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1557 mutex_lock(&priv
->reg_mutex
);
1558 ret
= priv
->chip
->atu_flush(priv
);
1559 mutex_unlock(&priv
->reg_mutex
);
1565 ar8xxx_sw_set_flush_port_arl_table(struct switch_dev
*dev
,
1566 const struct switch_attr
*attr
,
1567 struct switch_val
*val
)
1569 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1572 port
= val
->port_vlan
;
1573 if (port
>= dev
->ports
)
1576 mutex_lock(&priv
->reg_mutex
);
1577 ret
= priv
->chip
->atu_flush_port(priv
, port
);
1578 mutex_unlock(&priv
->reg_mutex
);
1583 static const struct switch_attr ar8xxx_sw_attr_globals
[] = {
1585 .type
= SWITCH_TYPE_INT
,
1586 .name
= "enable_vlan",
1587 .description
= "Enable VLAN mode",
1588 .set
= ar8xxx_sw_set_vlan
,
1589 .get
= ar8xxx_sw_get_vlan
,
1593 .type
= SWITCH_TYPE_NOVAL
,
1594 .name
= "reset_mibs",
1595 .description
= "Reset all MIB counters",
1596 .set
= ar8xxx_sw_set_reset_mibs
,
1599 .type
= SWITCH_TYPE_INT
,
1600 .name
= "enable_mirror_rx",
1601 .description
= "Enable mirroring of RX packets",
1602 .set
= ar8xxx_sw_set_mirror_rx_enable
,
1603 .get
= ar8xxx_sw_get_mirror_rx_enable
,
1607 .type
= SWITCH_TYPE_INT
,
1608 .name
= "enable_mirror_tx",
1609 .description
= "Enable mirroring of TX packets",
1610 .set
= ar8xxx_sw_set_mirror_tx_enable
,
1611 .get
= ar8xxx_sw_get_mirror_tx_enable
,
1615 .type
= SWITCH_TYPE_INT
,
1616 .name
= "mirror_monitor_port",
1617 .description
= "Mirror monitor port",
1618 .set
= ar8xxx_sw_set_mirror_monitor_port
,
1619 .get
= ar8xxx_sw_get_mirror_monitor_port
,
1620 .max
= AR8216_NUM_PORTS
- 1
1623 .type
= SWITCH_TYPE_INT
,
1624 .name
= "mirror_source_port",
1625 .description
= "Mirror source port",
1626 .set
= ar8xxx_sw_set_mirror_source_port
,
1627 .get
= ar8xxx_sw_get_mirror_source_port
,
1628 .max
= AR8216_NUM_PORTS
- 1
1631 .type
= SWITCH_TYPE_STRING
,
1632 .name
= "arl_table",
1633 .description
= "Get ARL table",
1635 .get
= ar8xxx_sw_get_arl_table
,
1638 .type
= SWITCH_TYPE_NOVAL
,
1639 .name
= "flush_arl_table",
1640 .description
= "Flush ARL table",
1641 .set
= ar8xxx_sw_set_flush_arl_table
,
1645 const struct switch_attr ar8xxx_sw_attr_port
[] = {
1647 .type
= SWITCH_TYPE_NOVAL
,
1648 .name
= "reset_mib",
1649 .description
= "Reset single port MIB counters",
1650 .set
= ar8xxx_sw_set_port_reset_mib
,
1653 .type
= SWITCH_TYPE_STRING
,
1655 .description
= "Get port's MIB counters",
1657 .get
= ar8xxx_sw_get_port_mib
,
1660 .type
= SWITCH_TYPE_NOVAL
,
1661 .name
= "flush_arl_table",
1662 .description
= "Flush port's ARL table entries",
1663 .set
= ar8xxx_sw_set_flush_port_arl_table
,
1667 const struct switch_attr ar8xxx_sw_attr_vlan
[1] = {
1669 .type
= SWITCH_TYPE_INT
,
1671 .description
= "VLAN ID (0-4094)",
1672 .set
= ar8xxx_sw_set_vid
,
1673 .get
= ar8xxx_sw_get_vid
,
1678 static const struct switch_dev_ops ar8xxx_sw_ops
= {
1680 .attr
= ar8xxx_sw_attr_globals
,
1681 .n_attr
= ARRAY_SIZE(ar8xxx_sw_attr_globals
),
1684 .attr
= ar8xxx_sw_attr_port
,
1685 .n_attr
= ARRAY_SIZE(ar8xxx_sw_attr_port
),
1688 .attr
= ar8xxx_sw_attr_vlan
,
1689 .n_attr
= ARRAY_SIZE(ar8xxx_sw_attr_vlan
),
1691 .get_port_pvid
= ar8xxx_sw_get_pvid
,
1692 .set_port_pvid
= ar8xxx_sw_set_pvid
,
1693 .get_vlan_ports
= ar8xxx_sw_get_ports
,
1694 .set_vlan_ports
= ar8xxx_sw_set_ports
,
1695 .apply_config
= ar8xxx_sw_hw_apply
,
1696 .reset_switch
= ar8xxx_sw_reset_switch
,
1697 .get_port_link
= ar8xxx_sw_get_port_link
,
1700 static const struct ar8xxx_chip ar8216_chip
= {
1701 .caps
= AR8XXX_CAP_MIB_COUNTERS
,
1703 .reg_port_stats_start
= 0x19000,
1704 .reg_port_stats_length
= 0xa0,
1705 .reg_arl_ctrl
= AR8216_REG_ATU_CTRL
,
1707 .name
= "Atheros AR8216",
1708 .ports
= AR8216_NUM_PORTS
,
1709 .vlans
= AR8216_NUM_VLANS
,
1710 .swops
= &ar8xxx_sw_ops
,
1712 .hw_init
= ar8216_hw_init
,
1713 .init_globals
= ar8216_init_globals
,
1714 .init_port
= ar8216_init_port
,
1715 .setup_port
= ar8216_setup_port
,
1716 .read_port_status
= ar8216_read_port_status
,
1717 .atu_flush
= ar8216_atu_flush
,
1718 .atu_flush_port
= ar8216_atu_flush_port
,
1719 .vtu_flush
= ar8216_vtu_flush
,
1720 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
1721 .set_mirror_regs
= ar8216_set_mirror_regs
,
1722 .get_arl_entry
= ar8216_get_arl_entry
,
1723 .sw_hw_apply
= ar8xxx_sw_hw_apply
,
1725 .num_mibs
= ARRAY_SIZE(ar8216_mibs
),
1726 .mib_decs
= ar8216_mibs
,
1727 .mib_func
= AR8216_REG_MIB_FUNC
1730 static const struct ar8xxx_chip ar8236_chip
= {
1731 .caps
= AR8XXX_CAP_MIB_COUNTERS
,
1733 .reg_port_stats_start
= 0x20000,
1734 .reg_port_stats_length
= 0x100,
1735 .reg_arl_ctrl
= AR8216_REG_ATU_CTRL
,
1737 .name
= "Atheros AR8236",
1738 .ports
= AR8216_NUM_PORTS
,
1739 .vlans
= AR8216_NUM_VLANS
,
1740 .swops
= &ar8xxx_sw_ops
,
1742 .hw_init
= ar8216_hw_init
,
1743 .init_globals
= ar8236_init_globals
,
1744 .init_port
= ar8216_init_port
,
1745 .setup_port
= ar8236_setup_port
,
1746 .read_port_status
= ar8216_read_port_status
,
1747 .atu_flush
= ar8216_atu_flush
,
1748 .atu_flush_port
= ar8216_atu_flush_port
,
1749 .vtu_flush
= ar8216_vtu_flush
,
1750 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
1751 .set_mirror_regs
= ar8216_set_mirror_regs
,
1752 .get_arl_entry
= ar8216_get_arl_entry
,
1753 .sw_hw_apply
= ar8xxx_sw_hw_apply
,
1755 .num_mibs
= ARRAY_SIZE(ar8236_mibs
),
1756 .mib_decs
= ar8236_mibs
,
1757 .mib_func
= AR8216_REG_MIB_FUNC
1760 static const struct ar8xxx_chip ar8316_chip
= {
1761 .caps
= AR8XXX_CAP_GIGE
| AR8XXX_CAP_MIB_COUNTERS
,
1763 .reg_port_stats_start
= 0x20000,
1764 .reg_port_stats_length
= 0x100,
1765 .reg_arl_ctrl
= AR8216_REG_ATU_CTRL
,
1767 .name
= "Atheros AR8316",
1768 .ports
= AR8216_NUM_PORTS
,
1769 .vlans
= AR8X16_MAX_VLANS
,
1770 .swops
= &ar8xxx_sw_ops
,
1772 .hw_init
= ar8316_hw_init
,
1773 .init_globals
= ar8316_init_globals
,
1774 .init_port
= ar8216_init_port
,
1775 .setup_port
= ar8216_setup_port
,
1776 .read_port_status
= ar8216_read_port_status
,
1777 .atu_flush
= ar8216_atu_flush
,
1778 .atu_flush_port
= ar8216_atu_flush_port
,
1779 .vtu_flush
= ar8216_vtu_flush
,
1780 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
1781 .set_mirror_regs
= ar8216_set_mirror_regs
,
1782 .get_arl_entry
= ar8216_get_arl_entry
,
1783 .sw_hw_apply
= ar8xxx_sw_hw_apply
,
1785 .num_mibs
= ARRAY_SIZE(ar8236_mibs
),
1786 .mib_decs
= ar8236_mibs
,
1787 .mib_func
= AR8216_REG_MIB_FUNC
1791 ar8xxx_id_chip(struct ar8xxx_priv
*priv
)
1797 val
= ar8xxx_read(priv
, AR8216_REG_CTRL
);
1801 id
= val
& (AR8216_CTRL_REVISION
| AR8216_CTRL_VERSION
);
1802 for (i
= 0; i
< AR8X16_PROBE_RETRIES
; i
++) {
1805 val
= ar8xxx_read(priv
, AR8216_REG_CTRL
);
1809 t
= val
& (AR8216_CTRL_REVISION
| AR8216_CTRL_VERSION
);
1814 priv
->chip_ver
= (id
& AR8216_CTRL_VERSION
) >> AR8216_CTRL_VERSION_S
;
1815 priv
->chip_rev
= (id
& AR8216_CTRL_REVISION
);
1817 switch (priv
->chip_ver
) {
1818 case AR8XXX_VER_AR8216
:
1819 priv
->chip
= &ar8216_chip
;
1821 case AR8XXX_VER_AR8236
:
1822 priv
->chip
= &ar8236_chip
;
1824 case AR8XXX_VER_AR8316
:
1825 priv
->chip
= &ar8316_chip
;
1827 case AR8XXX_VER_AR8327
:
1828 priv
->chip
= &ar8327_chip
;
1830 case AR8XXX_VER_AR8337
:
1831 priv
->chip
= &ar8337_chip
;
1834 pr_err("ar8216: Unknown Atheros device [ver=%d, rev=%d]\n",
1835 priv
->chip_ver
, priv
->chip_rev
);
1844 ar8xxx_mib_work_func(struct work_struct
*work
)
1846 struct ar8xxx_priv
*priv
;
1849 priv
= container_of(work
, struct ar8xxx_priv
, mib_work
.work
);
1851 mutex_lock(&priv
->mib_lock
);
1853 err
= ar8xxx_mib_capture(priv
);
1857 ar8xxx_mib_fetch_port_stat(priv
, priv
->mib_next_port
, false);
1860 priv
->mib_next_port
++;
1861 if (priv
->mib_next_port
>= priv
->dev
.ports
)
1862 priv
->mib_next_port
= 0;
1864 mutex_unlock(&priv
->mib_lock
);
1865 schedule_delayed_work(&priv
->mib_work
,
1866 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY
));
1870 ar8xxx_mib_init(struct ar8xxx_priv
*priv
)
1874 if (!ar8xxx_has_mib_counters(priv
))
1877 BUG_ON(!priv
->chip
->mib_decs
|| !priv
->chip
->num_mibs
);
1879 len
= priv
->dev
.ports
* priv
->chip
->num_mibs
*
1880 sizeof(*priv
->mib_stats
);
1881 priv
->mib_stats
= kzalloc(len
, GFP_KERNEL
);
1883 if (!priv
->mib_stats
)
1890 ar8xxx_mib_start(struct ar8xxx_priv
*priv
)
1892 if (!ar8xxx_has_mib_counters(priv
))
1895 schedule_delayed_work(&priv
->mib_work
,
1896 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY
));
1900 ar8xxx_mib_stop(struct ar8xxx_priv
*priv
)
1902 if (!ar8xxx_has_mib_counters(priv
))
1905 cancel_delayed_work_sync(&priv
->mib_work
);
1908 static struct ar8xxx_priv
*
1911 struct ar8xxx_priv
*priv
;
1913 priv
= kzalloc(sizeof(struct ar8xxx_priv
), GFP_KERNEL
);
1917 mutex_init(&priv
->reg_mutex
);
1918 mutex_init(&priv
->mib_lock
);
1919 INIT_DELAYED_WORK(&priv
->mib_work
, ar8xxx_mib_work_func
);
1925 ar8xxx_free(struct ar8xxx_priv
*priv
)
1927 if (priv
->chip
&& priv
->chip
->cleanup
)
1928 priv
->chip
->cleanup(priv
);
1930 kfree(priv
->chip_data
);
1931 kfree(priv
->mib_stats
);
1936 ar8xxx_probe_switch(struct ar8xxx_priv
*priv
)
1938 const struct ar8xxx_chip
*chip
;
1939 struct switch_dev
*swdev
;
1942 ret
= ar8xxx_id_chip(priv
);
1949 swdev
->cpu_port
= AR8216_PORT_CPU
;
1950 swdev
->name
= chip
->name
;
1951 swdev
->vlans
= chip
->vlans
;
1952 swdev
->ports
= chip
->ports
;
1953 swdev
->ops
= chip
->swops
;
1955 ret
= ar8xxx_mib_init(priv
);
1963 ar8xxx_start(struct ar8xxx_priv
*priv
)
1969 ret
= priv
->chip
->hw_init(priv
);
1973 ret
= ar8xxx_sw_reset_switch(&priv
->dev
);
1979 ar8xxx_mib_start(priv
);
1985 ar8xxx_phy_config_init(struct phy_device
*phydev
)
1987 struct ar8xxx_priv
*priv
= phydev
->priv
;
1988 struct net_device
*dev
= phydev
->attached_dev
;
1994 if (priv
->chip
->config_at_probe
)
1995 return ar8xxx_phy_check_aneg(phydev
);
1999 if (phydev
->addr
!= 0) {
2000 if (chip_is_ar8316(priv
)) {
2001 /* switch device has been initialized, reinit */
2002 priv
->dev
.ports
= (AR8216_NUM_PORTS
- 1);
2003 priv
->initialized
= false;
2004 priv
->port4_phy
= true;
2005 ar8316_hw_init(priv
);
2012 ret
= ar8xxx_start(priv
);
2016 /* VID fixup only needed on ar8216 */
2017 if (chip_is_ar8216(priv
)) {
2018 dev
->phy_ptr
= priv
;
2019 dev
->priv_flags
|= IFF_NO_IP_ALIGN
;
2020 dev
->eth_mangle_rx
= ar8216_mangle_rx
;
2021 dev
->eth_mangle_tx
= ar8216_mangle_tx
;
2028 ar8xxx_check_link_states(struct ar8xxx_priv
*priv
)
2030 bool link_new
, changed
= false;
2034 mutex_lock(&priv
->reg_mutex
);
2036 for (i
= 0; i
< priv
->dev
.ports
; i
++) {
2037 status
= priv
->chip
->read_port_status(priv
, i
);
2038 link_new
= !!(status
& AR8216_PORT_STATUS_LINK_UP
);
2039 if (link_new
== priv
->link_up
[i
])
2042 priv
->link_up
[i
] = link_new
;
2044 /* flush ARL entries for this port if it went down*/
2046 priv
->chip
->atu_flush_port(priv
, i
);
2047 dev_info(&priv
->phy
->dev
, "Port %d is %s\n",
2048 i
, link_new
? "up" : "down");
2051 mutex_unlock(&priv
->reg_mutex
);
2057 ar8xxx_phy_read_status(struct phy_device
*phydev
)
2059 struct ar8xxx_priv
*priv
= phydev
->priv
;
2060 struct switch_port_link link
;
2062 /* check for switch port link changes */
2063 if (phydev
->state
== PHY_CHANGELINK
)
2064 ar8xxx_check_link_states(priv
);
2066 if (phydev
->addr
!= 0)
2067 return genphy_read_status(phydev
);
2069 ar8216_read_port_link(priv
, phydev
->addr
, &link
);
2070 phydev
->link
= !!link
.link
;
2074 switch (link
.speed
) {
2075 case SWITCH_PORT_SPEED_10
:
2076 phydev
->speed
= SPEED_10
;
2078 case SWITCH_PORT_SPEED_100
:
2079 phydev
->speed
= SPEED_100
;
2081 case SWITCH_PORT_SPEED_1000
:
2082 phydev
->speed
= SPEED_1000
;
2087 phydev
->duplex
= link
.duplex
? DUPLEX_FULL
: DUPLEX_HALF
;
2089 phydev
->state
= PHY_RUNNING
;
2090 netif_carrier_on(phydev
->attached_dev
);
2091 phydev
->adjust_link(phydev
->attached_dev
);
2097 ar8xxx_phy_config_aneg(struct phy_device
*phydev
)
2099 if (phydev
->addr
== 0)
2102 return genphy_config_aneg(phydev
);
2105 static const u32 ar8xxx_phy_ids
[] = {
2107 0x004dd034, /* AR8327 */
2108 0x004dd036, /* AR8337 */
2111 0x004dd043, /* AR8236 */
2115 ar8xxx_phy_match(u32 phy_id
)
2119 for (i
= 0; i
< ARRAY_SIZE(ar8xxx_phy_ids
); i
++)
2120 if (phy_id
== ar8xxx_phy_ids
[i
])
2127 ar8xxx_is_possible(struct mii_bus
*bus
)
2129 unsigned int i
, found_phys
= 0;
2131 for (i
= 0; i
< 5; i
++) {
2134 phy_id
= mdiobus_read(bus
, i
, MII_PHYSID1
) << 16;
2135 phy_id
|= mdiobus_read(bus
, i
, MII_PHYSID2
);
2136 if (ar8xxx_phy_match(phy_id
)) {
2138 } else if (phy_id
) {
2139 pr_debug("ar8xxx: unknown PHY at %s:%02x id:%08x\n",
2140 dev_name(&bus
->dev
), i
, phy_id
);
2143 return !!found_phys
;
2147 ar8xxx_phy_probe(struct phy_device
*phydev
)
2149 struct ar8xxx_priv
*priv
;
2150 struct switch_dev
*swdev
;
2153 /* skip PHYs at unused adresses */
2154 if (phydev
->addr
!= 0 && phydev
->addr
!= 4)
2157 if (!ar8xxx_is_possible(phydev
->bus
))
2160 mutex_lock(&ar8xxx_dev_list_lock
);
2161 list_for_each_entry(priv
, &ar8xxx_dev_list
, list
)
2162 if (priv
->mii_bus
== phydev
->bus
)
2165 priv
= ar8xxx_create();
2171 priv
->mii_bus
= phydev
->bus
;
2173 ret
= ar8xxx_probe_switch(priv
);
2178 swdev
->alias
= dev_name(&priv
->mii_bus
->dev
);
2179 ret
= register_switch(swdev
, NULL
);
2183 pr_info("%s: %s rev. %u switch registered on %s\n",
2184 swdev
->devname
, swdev
->name
, priv
->chip_rev
,
2185 dev_name(&priv
->mii_bus
->dev
));
2187 list_add(&priv
->list
, &ar8xxx_dev_list
);
2192 if (phydev
->addr
== 0) {
2193 if (ar8xxx_has_gige(priv
)) {
2194 phydev
->supported
= SUPPORTED_1000baseT_Full
;
2195 phydev
->advertising
= ADVERTISED_1000baseT_Full
;
2197 phydev
->supported
= SUPPORTED_100baseT_Full
;
2198 phydev
->advertising
= ADVERTISED_100baseT_Full
;
2201 if (priv
->chip
->config_at_probe
) {
2204 ret
= ar8xxx_start(priv
);
2206 goto err_unregister_switch
;
2209 if (ar8xxx_has_gige(priv
)) {
2210 phydev
->supported
|= SUPPORTED_1000baseT_Full
;
2211 phydev
->advertising
|= ADVERTISED_1000baseT_Full
;
2215 phydev
->priv
= priv
;
2217 mutex_unlock(&ar8xxx_dev_list_lock
);
2221 err_unregister_switch
:
2222 if (--priv
->use_count
)
2225 unregister_switch(&priv
->dev
);
2230 mutex_unlock(&ar8xxx_dev_list_lock
);
2235 ar8xxx_phy_detach(struct phy_device
*phydev
)
2237 struct net_device
*dev
= phydev
->attached_dev
;
2242 dev
->phy_ptr
= NULL
;
2243 dev
->priv_flags
&= ~IFF_NO_IP_ALIGN
;
2244 dev
->eth_mangle_rx
= NULL
;
2245 dev
->eth_mangle_tx
= NULL
;
2249 ar8xxx_phy_remove(struct phy_device
*phydev
)
2251 struct ar8xxx_priv
*priv
= phydev
->priv
;
2256 phydev
->priv
= NULL
;
2258 mutex_lock(&ar8xxx_dev_list_lock
);
2260 if (--priv
->use_count
> 0) {
2261 mutex_unlock(&ar8xxx_dev_list_lock
);
2265 list_del(&priv
->list
);
2266 mutex_unlock(&ar8xxx_dev_list_lock
);
2268 unregister_switch(&priv
->dev
);
2269 ar8xxx_mib_stop(priv
);
2273 #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)
2275 ar8xxx_phy_soft_reset(struct phy_device
*phydev
)
2277 /* we don't need an extra reset */
2282 static struct phy_driver ar8xxx_phy_driver
= {
2283 .phy_id
= 0x004d0000,
2284 .name
= "Atheros AR8216/AR8236/AR8316",
2285 .phy_id_mask
= 0xffff0000,
2286 .features
= PHY_BASIC_FEATURES
,
2287 .probe
= ar8xxx_phy_probe
,
2288 .remove
= ar8xxx_phy_remove
,
2289 .detach
= ar8xxx_phy_detach
,
2290 .config_init
= ar8xxx_phy_config_init
,
2291 .config_aneg
= ar8xxx_phy_config_aneg
,
2292 .read_status
= ar8xxx_phy_read_status
,
2293 #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)
2294 .soft_reset
= ar8xxx_phy_soft_reset
,
2296 .driver
= { .owner
= THIS_MODULE
},
2302 return phy_driver_register(&ar8xxx_phy_driver
);
2308 phy_driver_unregister(&ar8xxx_phy_driver
);
2311 module_init(ar8xxx_init
);
2312 module_exit(ar8xxx_exit
);
2313 MODULE_LICENSE("GPL");