2 * ar8216.c: AR8216 switch driver
4 * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/list.h>
22 #include <linux/if_ether.h>
23 #include <linux/skbuff.h>
24 #include <linux/netdevice.h>
25 #include <linux/netlink.h>
26 #include <linux/bitops.h>
27 #include <net/genetlink.h>
28 #include <linux/switch.h>
29 #include <linux/delay.h>
30 #include <linux/phy.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/lockdep.h>
34 #include <linux/ar8216_platform.h>
35 #include <linux/workqueue.h>
38 /* size of the vlan table */
39 #define AR8X16_MAX_VLANS 128
40 #define AR8X16_PROBE_RETRIES 10
41 #define AR8X16_MAX_PORTS 8
43 #define AR8XXX_MIB_WORK_DELAY 2000 /* msecs */
47 #define AR8XXX_CAP_GIGE BIT(0)
48 #define AR8XXX_CAP_MIB_COUNTERS BIT(1)
51 AR8XXX_VER_AR8216
= 0x01,
52 AR8XXX_VER_AR8236
= 0x03,
53 AR8XXX_VER_AR8316
= 0x10,
54 AR8XXX_VER_AR8327
= 0x12,
57 struct ar8xxx_mib_desc
{
66 int (*hw_init
)(struct ar8xxx_priv
*priv
);
67 void (*init_globals
)(struct ar8xxx_priv
*priv
);
68 void (*init_port
)(struct ar8xxx_priv
*priv
, int port
);
69 void (*setup_port
)(struct ar8xxx_priv
*priv
, int port
, u32 egress
,
70 u32 ingress
, u32 members
, u32 pvid
);
71 u32 (*read_port_status
)(struct ar8xxx_priv
*priv
, int port
);
72 int (*atu_flush
)(struct ar8xxx_priv
*priv
);
73 void (*vtu_flush
)(struct ar8xxx_priv
*priv
);
74 void (*vtu_load_vlan
)(struct ar8xxx_priv
*priv
, u32 vid
, u32 port_mask
);
76 const struct ar8xxx_mib_desc
*mib_decs
;
86 struct switch_dev dev
;
87 struct mii_bus
*mii_bus
;
88 struct phy_device
*phy
;
89 u32 (*read
)(struct ar8xxx_priv
*priv
, int reg
);
90 void (*write
)(struct ar8xxx_priv
*priv
, int reg
, u32 val
);
91 const struct net_device_ops
*ndo_old
;
92 struct net_device_ops ndo
;
93 struct mutex reg_mutex
;
96 const struct ar8xxx_chip
*chip
;
98 struct ar8327_data ar8327
;
107 struct mutex mib_lock
;
108 struct delayed_work mib_work
;
112 struct list_head list
;
113 unsigned int use_count
;
115 /* all fields below are cleared on reset */
117 u16 vlan_id
[AR8X16_MAX_VLANS
];
118 u8 vlan_table
[AR8X16_MAX_VLANS
];
120 u16 pvid
[AR8X16_MAX_PORTS
];
123 #define MIB_DESC(_s , _o, _n) \
130 static const struct ar8xxx_mib_desc ar8216_mibs
[] = {
131 MIB_DESC(1, AR8216_STATS_RXBROAD
, "RxBroad"),
132 MIB_DESC(1, AR8216_STATS_RXPAUSE
, "RxPause"),
133 MIB_DESC(1, AR8216_STATS_RXMULTI
, "RxMulti"),
134 MIB_DESC(1, AR8216_STATS_RXFCSERR
, "RxFcsErr"),
135 MIB_DESC(1, AR8216_STATS_RXALIGNERR
, "RxAlignErr"),
136 MIB_DESC(1, AR8216_STATS_RXRUNT
, "RxRunt"),
137 MIB_DESC(1, AR8216_STATS_RXFRAGMENT
, "RxFragment"),
138 MIB_DESC(1, AR8216_STATS_RX64BYTE
, "Rx64Byte"),
139 MIB_DESC(1, AR8216_STATS_RX128BYTE
, "Rx128Byte"),
140 MIB_DESC(1, AR8216_STATS_RX256BYTE
, "Rx256Byte"),
141 MIB_DESC(1, AR8216_STATS_RX512BYTE
, "Rx512Byte"),
142 MIB_DESC(1, AR8216_STATS_RX1024BYTE
, "Rx1024Byte"),
143 MIB_DESC(1, AR8216_STATS_RXMAXBYTE
, "RxMaxByte"),
144 MIB_DESC(1, AR8216_STATS_RXTOOLONG
, "RxTooLong"),
145 MIB_DESC(2, AR8216_STATS_RXGOODBYTE
, "RxGoodByte"),
146 MIB_DESC(2, AR8216_STATS_RXBADBYTE
, "RxBadByte"),
147 MIB_DESC(1, AR8216_STATS_RXOVERFLOW
, "RxOverFlow"),
148 MIB_DESC(1, AR8216_STATS_FILTERED
, "Filtered"),
149 MIB_DESC(1, AR8216_STATS_TXBROAD
, "TxBroad"),
150 MIB_DESC(1, AR8216_STATS_TXPAUSE
, "TxPause"),
151 MIB_DESC(1, AR8216_STATS_TXMULTI
, "TxMulti"),
152 MIB_DESC(1, AR8216_STATS_TXUNDERRUN
, "TxUnderRun"),
153 MIB_DESC(1, AR8216_STATS_TX64BYTE
, "Tx64Byte"),
154 MIB_DESC(1, AR8216_STATS_TX128BYTE
, "Tx128Byte"),
155 MIB_DESC(1, AR8216_STATS_TX256BYTE
, "Tx256Byte"),
156 MIB_DESC(1, AR8216_STATS_TX512BYTE
, "Tx512Byte"),
157 MIB_DESC(1, AR8216_STATS_TX1024BYTE
, "Tx1024Byte"),
158 MIB_DESC(1, AR8216_STATS_TXMAXBYTE
, "TxMaxByte"),
159 MIB_DESC(1, AR8216_STATS_TXOVERSIZE
, "TxOverSize"),
160 MIB_DESC(2, AR8216_STATS_TXBYTE
, "TxByte"),
161 MIB_DESC(1, AR8216_STATS_TXCOLLISION
, "TxCollision"),
162 MIB_DESC(1, AR8216_STATS_TXABORTCOL
, "TxAbortCol"),
163 MIB_DESC(1, AR8216_STATS_TXMULTICOL
, "TxMultiCol"),
164 MIB_DESC(1, AR8216_STATS_TXSINGLECOL
, "TxSingleCol"),
165 MIB_DESC(1, AR8216_STATS_TXEXCDEFER
, "TxExcDefer"),
166 MIB_DESC(1, AR8216_STATS_TXDEFER
, "TxDefer"),
167 MIB_DESC(1, AR8216_STATS_TXLATECOL
, "TxLateCol"),
170 static const struct ar8xxx_mib_desc ar8236_mibs
[] = {
171 MIB_DESC(1, AR8236_STATS_RXBROAD
, "RxBroad"),
172 MIB_DESC(1, AR8236_STATS_RXPAUSE
, "RxPause"),
173 MIB_DESC(1, AR8236_STATS_RXMULTI
, "RxMulti"),
174 MIB_DESC(1, AR8236_STATS_RXFCSERR
, "RxFcsErr"),
175 MIB_DESC(1, AR8236_STATS_RXALIGNERR
, "RxAlignErr"),
176 MIB_DESC(1, AR8236_STATS_RXRUNT
, "RxRunt"),
177 MIB_DESC(1, AR8236_STATS_RXFRAGMENT
, "RxFragment"),
178 MIB_DESC(1, AR8236_STATS_RX64BYTE
, "Rx64Byte"),
179 MIB_DESC(1, AR8236_STATS_RX128BYTE
, "Rx128Byte"),
180 MIB_DESC(1, AR8236_STATS_RX256BYTE
, "Rx256Byte"),
181 MIB_DESC(1, AR8236_STATS_RX512BYTE
, "Rx512Byte"),
182 MIB_DESC(1, AR8236_STATS_RX1024BYTE
, "Rx1024Byte"),
183 MIB_DESC(1, AR8236_STATS_RX1518BYTE
, "Rx1518Byte"),
184 MIB_DESC(1, AR8236_STATS_RXMAXBYTE
, "RxMaxByte"),
185 MIB_DESC(1, AR8236_STATS_RXTOOLONG
, "RxTooLong"),
186 MIB_DESC(2, AR8236_STATS_RXGOODBYTE
, "RxGoodByte"),
187 MIB_DESC(2, AR8236_STATS_RXBADBYTE
, "RxBadByte"),
188 MIB_DESC(1, AR8236_STATS_RXOVERFLOW
, "RxOverFlow"),
189 MIB_DESC(1, AR8236_STATS_FILTERED
, "Filtered"),
190 MIB_DESC(1, AR8236_STATS_TXBROAD
, "TxBroad"),
191 MIB_DESC(1, AR8236_STATS_TXPAUSE
, "TxPause"),
192 MIB_DESC(1, AR8236_STATS_TXMULTI
, "TxMulti"),
193 MIB_DESC(1, AR8236_STATS_TXUNDERRUN
, "TxUnderRun"),
194 MIB_DESC(1, AR8236_STATS_TX64BYTE
, "Tx64Byte"),
195 MIB_DESC(1, AR8236_STATS_TX128BYTE
, "Tx128Byte"),
196 MIB_DESC(1, AR8236_STATS_TX256BYTE
, "Tx256Byte"),
197 MIB_DESC(1, AR8236_STATS_TX512BYTE
, "Tx512Byte"),
198 MIB_DESC(1, AR8236_STATS_TX1024BYTE
, "Tx1024Byte"),
199 MIB_DESC(1, AR8236_STATS_TX1518BYTE
, "Tx1518Byte"),
200 MIB_DESC(1, AR8236_STATS_TXMAXBYTE
, "TxMaxByte"),
201 MIB_DESC(1, AR8236_STATS_TXOVERSIZE
, "TxOverSize"),
202 MIB_DESC(2, AR8236_STATS_TXBYTE
, "TxByte"),
203 MIB_DESC(1, AR8236_STATS_TXCOLLISION
, "TxCollision"),
204 MIB_DESC(1, AR8236_STATS_TXABORTCOL
, "TxAbortCol"),
205 MIB_DESC(1, AR8236_STATS_TXMULTICOL
, "TxMultiCol"),
206 MIB_DESC(1, AR8236_STATS_TXSINGLECOL
, "TxSingleCol"),
207 MIB_DESC(1, AR8236_STATS_TXEXCDEFER
, "TxExcDefer"),
208 MIB_DESC(1, AR8236_STATS_TXDEFER
, "TxDefer"),
209 MIB_DESC(1, AR8236_STATS_TXLATECOL
, "TxLateCol"),
212 static DEFINE_MUTEX(ar8xxx_dev_list_lock
);
213 static LIST_HEAD(ar8xxx_dev_list
);
215 static inline struct ar8xxx_priv
*
216 swdev_to_ar8xxx(struct switch_dev
*swdev
)
218 return container_of(swdev
, struct ar8xxx_priv
, dev
);
221 static inline bool ar8xxx_has_gige(struct ar8xxx_priv
*priv
)
223 return priv
->chip
->caps
& AR8XXX_CAP_GIGE
;
226 static inline bool ar8xxx_has_mib_counters(struct ar8xxx_priv
*priv
)
228 return priv
->chip
->caps
& AR8XXX_CAP_MIB_COUNTERS
;
231 static inline bool chip_is_ar8216(struct ar8xxx_priv
*priv
)
233 return priv
->chip_ver
== AR8XXX_VER_AR8216
;
236 static inline bool chip_is_ar8236(struct ar8xxx_priv
*priv
)
238 return priv
->chip_ver
== AR8XXX_VER_AR8236
;
241 static inline bool chip_is_ar8316(struct ar8xxx_priv
*priv
)
243 return priv
->chip_ver
== AR8XXX_VER_AR8316
;
246 static inline bool chip_is_ar8327(struct ar8xxx_priv
*priv
)
248 return priv
->chip_ver
== AR8XXX_VER_AR8327
;
252 split_addr(u32 regaddr
, u16
*r1
, u16
*r2
, u16
*page
)
255 *r1
= regaddr
& 0x1e;
261 *page
= regaddr
& 0x1ff;
265 ar8xxx_mii_read(struct ar8xxx_priv
*priv
, int reg
)
267 struct mii_bus
*bus
= priv
->mii_bus
;
271 split_addr((u32
) reg
, &r1
, &r2
, &page
);
273 mutex_lock(&bus
->mdio_lock
);
275 bus
->write(bus
, 0x18, 0, page
);
276 usleep_range(1000, 2000); /* wait for the page switch to propagate */
277 lo
= bus
->read(bus
, 0x10 | r2
, r1
);
278 hi
= bus
->read(bus
, 0x10 | r2
, r1
+ 1);
280 mutex_unlock(&bus
->mdio_lock
);
282 return (hi
<< 16) | lo
;
286 ar8xxx_mii_write(struct ar8xxx_priv
*priv
, int reg
, u32 val
)
288 struct mii_bus
*bus
= priv
->mii_bus
;
292 split_addr((u32
) reg
, &r1
, &r2
, &r3
);
294 hi
= (u16
) (val
>> 16);
296 mutex_lock(&bus
->mdio_lock
);
298 bus
->write(bus
, 0x18, 0, r3
);
299 usleep_range(1000, 2000); /* wait for the page switch to propagate */
300 if (priv
->mii_lo_first
) {
301 bus
->write(bus
, 0x10 | r2
, r1
, lo
);
302 bus
->write(bus
, 0x10 | r2
, r1
+ 1, hi
);
304 bus
->write(bus
, 0x10 | r2
, r1
+ 1, hi
);
305 bus
->write(bus
, 0x10 | r2
, r1
, lo
);
308 mutex_unlock(&bus
->mdio_lock
);
312 ar8xxx_phy_dbg_write(struct ar8xxx_priv
*priv
, int phy_addr
,
313 u16 dbg_addr
, u16 dbg_data
)
315 struct mii_bus
*bus
= priv
->mii_bus
;
317 mutex_lock(&bus
->mdio_lock
);
318 bus
->write(bus
, phy_addr
, MII_ATH_DBG_ADDR
, dbg_addr
);
319 bus
->write(bus
, phy_addr
, MII_ATH_DBG_DATA
, dbg_data
);
320 mutex_unlock(&bus
->mdio_lock
);
324 ar8xxx_phy_mmd_write(struct ar8xxx_priv
*priv
, int phy_addr
, u16 addr
, u16 data
)
326 struct mii_bus
*bus
= priv
->mii_bus
;
328 mutex_lock(&bus
->mdio_lock
);
329 bus
->write(bus
, phy_addr
, MII_ATH_MMD_ADDR
, addr
);
330 bus
->write(bus
, phy_addr
, MII_ATH_MMD_DATA
, data
);
331 mutex_unlock(&bus
->mdio_lock
);
335 ar8xxx_rmw(struct ar8xxx_priv
*priv
, int reg
, u32 mask
, u32 val
)
339 lockdep_assert_held(&priv
->reg_mutex
);
341 v
= priv
->read(priv
, reg
);
344 priv
->write(priv
, reg
, v
);
350 ar8xxx_reg_set(struct ar8xxx_priv
*priv
, int reg
, u32 val
)
354 lockdep_assert_held(&priv
->reg_mutex
);
356 v
= priv
->read(priv
, reg
);
358 priv
->write(priv
, reg
, v
);
362 ar8xxx_reg_wait(struct ar8xxx_priv
*priv
, u32 reg
, u32 mask
, u32 val
,
367 for (i
= 0; i
< timeout
; i
++) {
370 t
= priv
->read(priv
, reg
);
371 if ((t
& mask
) == val
)
374 usleep_range(1000, 2000);
381 ar8xxx_mib_op(struct ar8xxx_priv
*priv
, u32 op
)
386 lockdep_assert_held(&priv
->mib_lock
);
388 if (chip_is_ar8327(priv
))
389 mib_func
= AR8327_REG_MIB_FUNC
;
391 mib_func
= AR8216_REG_MIB_FUNC
;
393 mutex_lock(&priv
->reg_mutex
);
394 /* Capture the hardware statistics for all ports */
395 ar8xxx_rmw(priv
, mib_func
, AR8216_MIB_FUNC
, (op
<< AR8216_MIB_FUNC_S
));
396 mutex_unlock(&priv
->reg_mutex
);
398 /* Wait for the capturing to complete. */
399 ret
= ar8xxx_reg_wait(priv
, mib_func
, AR8216_MIB_BUSY
, 0, 10);
410 ar8xxx_mib_capture(struct ar8xxx_priv
*priv
)
412 return ar8xxx_mib_op(priv
, AR8216_MIB_FUNC_CAPTURE
);
416 ar8xxx_mib_flush(struct ar8xxx_priv
*priv
)
418 return ar8xxx_mib_op(priv
, AR8216_MIB_FUNC_FLUSH
);
422 ar8xxx_mib_fetch_port_stat(struct ar8xxx_priv
*priv
, int port
, bool flush
)
428 WARN_ON(port
>= priv
->dev
.ports
);
430 lockdep_assert_held(&priv
->mib_lock
);
432 if (chip_is_ar8327(priv
))
433 base
= AR8327_REG_PORT_STATS_BASE(port
);
434 else if (chip_is_ar8236(priv
) ||
435 chip_is_ar8316(priv
))
436 base
= AR8236_REG_PORT_STATS_BASE(port
);
438 base
= AR8216_REG_PORT_STATS_BASE(port
);
440 mib_stats
= &priv
->mib_stats
[port
* priv
->chip
->num_mibs
];
441 for (i
= 0; i
< priv
->chip
->num_mibs
; i
++) {
442 const struct ar8xxx_mib_desc
*mib
;
445 mib
= &priv
->chip
->mib_decs
[i
];
446 t
= priv
->read(priv
, base
+ mib
->offset
);
447 if (mib
->size
== 2) {
450 hi
= priv
->read(priv
, base
+ mib
->offset
+ 4);
462 ar8216_read_port_link(struct ar8xxx_priv
*priv
, int port
,
463 struct switch_port_link
*link
)
468 memset(link
, '\0', sizeof(*link
));
470 status
= priv
->chip
->read_port_status(priv
, port
);
472 link
->aneg
= !!(status
& AR8216_PORT_STATUS_LINK_AUTO
);
474 link
->link
= !!(status
& AR8216_PORT_STATUS_LINK_UP
);
481 link
->duplex
= !!(status
& AR8216_PORT_STATUS_DUPLEX
);
482 link
->tx_flow
= !!(status
& AR8216_PORT_STATUS_TXFLOW
);
483 link
->rx_flow
= !!(status
& AR8216_PORT_STATUS_RXFLOW
);
485 speed
= (status
& AR8216_PORT_STATUS_SPEED
) >>
486 AR8216_PORT_STATUS_SPEED_S
;
489 case AR8216_PORT_SPEED_10M
:
490 link
->speed
= SWITCH_PORT_SPEED_10
;
492 case AR8216_PORT_SPEED_100M
:
493 link
->speed
= SWITCH_PORT_SPEED_100
;
495 case AR8216_PORT_SPEED_1000M
:
496 link
->speed
= SWITCH_PORT_SPEED_1000
;
499 link
->speed
= SWITCH_PORT_SPEED_UNKNOWN
;
504 static struct sk_buff
*
505 ar8216_mangle_tx(struct net_device
*dev
, struct sk_buff
*skb
)
507 struct ar8xxx_priv
*priv
= dev
->phy_ptr
;
516 if (unlikely(skb_headroom(skb
) < 2)) {
517 if (pskb_expand_head(skb
, 2, 0, GFP_ATOMIC
) < 0)
521 buf
= skb_push(skb
, 2);
529 dev_kfree_skb_any(skb
);
534 ar8216_mangle_rx(struct net_device
*dev
, struct sk_buff
*skb
)
536 struct ar8xxx_priv
*priv
;
544 /* don't strip the header if vlan mode is disabled */
548 /* strip header, get vlan id */
552 /* check for vlan header presence */
553 if ((buf
[12 + 2] != 0x81) || (buf
[13 + 2] != 0x00))
558 /* no need to fix up packets coming from a tagged source */
559 if (priv
->vlan_tagged
& (1 << port
))
562 /* lookup port vid from local table, the switch passes an invalid vlan id */
563 vlan
= priv
->vlan_id
[priv
->pvid
[port
]];
566 buf
[14 + 2] |= vlan
>> 8;
567 buf
[15 + 2] = vlan
& 0xff;
571 ar8216_wait_bit(struct ar8xxx_priv
*priv
, int reg
, u32 mask
, u32 val
)
577 t
= priv
->read(priv
, reg
);
578 if ((t
& mask
) == val
)
587 pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
588 (unsigned int) reg
, t
, mask
, val
);
593 ar8216_vtu_op(struct ar8xxx_priv
*priv
, u32 op
, u32 val
)
595 if (ar8216_wait_bit(priv
, AR8216_REG_VTU
, AR8216_VTU_ACTIVE
, 0))
597 if ((op
& AR8216_VTU_OP
) == AR8216_VTU_OP_LOAD
) {
598 val
&= AR8216_VTUDATA_MEMBER
;
599 val
|= AR8216_VTUDATA_VALID
;
600 priv
->write(priv
, AR8216_REG_VTU_DATA
, val
);
602 op
|= AR8216_VTU_ACTIVE
;
603 priv
->write(priv
, AR8216_REG_VTU
, op
);
607 ar8216_vtu_flush(struct ar8xxx_priv
*priv
)
609 ar8216_vtu_op(priv
, AR8216_VTU_OP_FLUSH
, 0);
613 ar8216_vtu_load_vlan(struct ar8xxx_priv
*priv
, u32 vid
, u32 port_mask
)
617 op
= AR8216_VTU_OP_LOAD
| (vid
<< AR8216_VTU_VID_S
);
618 ar8216_vtu_op(priv
, op
, port_mask
);
622 ar8216_atu_flush(struct ar8xxx_priv
*priv
)
626 ret
= ar8216_wait_bit(priv
, AR8216_REG_ATU
, AR8216_ATU_ACTIVE
, 0);
628 priv
->write(priv
, AR8216_REG_ATU
, AR8216_ATU_OP_FLUSH
);
634 ar8216_read_port_status(struct ar8xxx_priv
*priv
, int port
)
636 return priv
->read(priv
, AR8216_REG_PORT_STATUS(port
));
640 ar8216_setup_port(struct ar8xxx_priv
*priv
, int port
, u32 egress
, u32 ingress
,
641 u32 members
, u32 pvid
)
645 if (chip_is_ar8216(priv
) && priv
->vlan
&& port
== AR8216_PORT_CPU
)
646 header
= AR8216_PORT_CTRL_HEADER
;
650 ar8xxx_rmw(priv
, AR8216_REG_PORT_CTRL(port
),
651 AR8216_PORT_CTRL_LEARN
| AR8216_PORT_CTRL_VLAN_MODE
|
652 AR8216_PORT_CTRL_SINGLE_VLAN
| AR8216_PORT_CTRL_STATE
|
653 AR8216_PORT_CTRL_HEADER
| AR8216_PORT_CTRL_LEARN_LOCK
,
654 AR8216_PORT_CTRL_LEARN
| header
|
655 (egress
<< AR8216_PORT_CTRL_VLAN_MODE_S
) |
656 (AR8216_PORT_STATE_FORWARD
<< AR8216_PORT_CTRL_STATE_S
));
658 ar8xxx_rmw(priv
, AR8216_REG_PORT_VLAN(port
),
659 AR8216_PORT_VLAN_DEST_PORTS
| AR8216_PORT_VLAN_MODE
|
660 AR8216_PORT_VLAN_DEFAULT_ID
,
661 (members
<< AR8216_PORT_VLAN_DEST_PORTS_S
) |
662 (ingress
<< AR8216_PORT_VLAN_MODE_S
) |
663 (pvid
<< AR8216_PORT_VLAN_DEFAULT_ID_S
));
667 ar8216_hw_init(struct ar8xxx_priv
*priv
)
673 ar8216_init_globals(struct ar8xxx_priv
*priv
)
675 /* standard atheros magic */
676 priv
->write(priv
, 0x38, 0xc000050e);
678 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
679 AR8216_GCTRL_MTU
, 1518 + 8 + 2);
683 ar8216_init_port(struct ar8xxx_priv
*priv
, int port
)
685 /* Enable port learning and tx */
686 priv
->write(priv
, AR8216_REG_PORT_CTRL(port
),
687 AR8216_PORT_CTRL_LEARN
|
688 (4 << AR8216_PORT_CTRL_STATE_S
));
690 priv
->write(priv
, AR8216_REG_PORT_VLAN(port
), 0);
692 if (port
== AR8216_PORT_CPU
) {
693 priv
->write(priv
, AR8216_REG_PORT_STATUS(port
),
694 AR8216_PORT_STATUS_LINK_UP
|
695 (ar8xxx_has_gige(priv
) ?
696 AR8216_PORT_SPEED_1000M
: AR8216_PORT_SPEED_100M
) |
697 AR8216_PORT_STATUS_TXMAC
|
698 AR8216_PORT_STATUS_RXMAC
|
699 (chip_is_ar8316(priv
) ? AR8216_PORT_STATUS_RXFLOW
: 0) |
700 (chip_is_ar8316(priv
) ? AR8216_PORT_STATUS_TXFLOW
: 0) |
701 AR8216_PORT_STATUS_DUPLEX
);
703 priv
->write(priv
, AR8216_REG_PORT_STATUS(port
),
704 AR8216_PORT_STATUS_LINK_AUTO
);
708 static const struct ar8xxx_chip ar8216_chip
= {
709 .caps
= AR8XXX_CAP_MIB_COUNTERS
,
711 .hw_init
= ar8216_hw_init
,
712 .init_globals
= ar8216_init_globals
,
713 .init_port
= ar8216_init_port
,
714 .setup_port
= ar8216_setup_port
,
715 .read_port_status
= ar8216_read_port_status
,
716 .atu_flush
= ar8216_atu_flush
,
717 .vtu_flush
= ar8216_vtu_flush
,
718 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
720 .num_mibs
= ARRAY_SIZE(ar8216_mibs
),
721 .mib_decs
= ar8216_mibs
,
725 ar8236_setup_port(struct ar8xxx_priv
*priv
, int port
, u32 egress
, u32 ingress
,
726 u32 members
, u32 pvid
)
728 ar8xxx_rmw(priv
, AR8216_REG_PORT_CTRL(port
),
729 AR8216_PORT_CTRL_LEARN
| AR8216_PORT_CTRL_VLAN_MODE
|
730 AR8216_PORT_CTRL_SINGLE_VLAN
| AR8216_PORT_CTRL_STATE
|
731 AR8216_PORT_CTRL_HEADER
| AR8216_PORT_CTRL_LEARN_LOCK
,
732 AR8216_PORT_CTRL_LEARN
|
733 (egress
<< AR8216_PORT_CTRL_VLAN_MODE_S
) |
734 (AR8216_PORT_STATE_FORWARD
<< AR8216_PORT_CTRL_STATE_S
));
736 ar8xxx_rmw(priv
, AR8236_REG_PORT_VLAN(port
),
737 AR8236_PORT_VLAN_DEFAULT_ID
,
738 (pvid
<< AR8236_PORT_VLAN_DEFAULT_ID_S
));
740 ar8xxx_rmw(priv
, AR8236_REG_PORT_VLAN2(port
),
741 AR8236_PORT_VLAN2_VLAN_MODE
|
742 AR8236_PORT_VLAN2_MEMBER
,
743 (ingress
<< AR8236_PORT_VLAN2_VLAN_MODE_S
) |
744 (members
<< AR8236_PORT_VLAN2_MEMBER_S
));
748 ar8236_hw_init(struct ar8xxx_priv
*priv
)
753 if (priv
->initialized
)
756 /* Initialize the PHYs */
758 for (i
= 0; i
< 5; i
++) {
759 mdiobus_write(bus
, i
, MII_ADVERTISE
,
760 ADVERTISE_ALL
| ADVERTISE_PAUSE_CAP
|
761 ADVERTISE_PAUSE_ASYM
);
762 mdiobus_write(bus
, i
, MII_BMCR
, BMCR_RESET
| BMCR_ANENABLE
);
766 priv
->initialized
= true;
771 ar8236_init_globals(struct ar8xxx_priv
*priv
)
773 /* enable jumbo frames */
774 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
775 AR8316_GCTRL_MTU
, 9018 + 8 + 2);
777 /* Enable MIB counters */
778 ar8xxx_rmw(priv
, AR8216_REG_MIB_FUNC
, AR8216_MIB_FUNC
| AR8236_MIB_EN
,
779 (AR8216_MIB_FUNC_NO_OP
<< AR8216_MIB_FUNC_S
) |
783 static const struct ar8xxx_chip ar8236_chip
= {
784 .caps
= AR8XXX_CAP_MIB_COUNTERS
,
785 .hw_init
= ar8236_hw_init
,
786 .init_globals
= ar8236_init_globals
,
787 .init_port
= ar8216_init_port
,
788 .setup_port
= ar8236_setup_port
,
789 .read_port_status
= ar8216_read_port_status
,
790 .atu_flush
= ar8216_atu_flush
,
791 .vtu_flush
= ar8216_vtu_flush
,
792 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
794 .num_mibs
= ARRAY_SIZE(ar8236_mibs
),
795 .mib_decs
= ar8236_mibs
,
799 ar8316_hw_init(struct ar8xxx_priv
*priv
)
805 val
= priv
->read(priv
, AR8316_REG_POSTRIP
);
807 if (priv
->phy
->interface
== PHY_INTERFACE_MODE_RGMII
) {
808 if (priv
->port4_phy
) {
809 /* value taken from Ubiquiti RouterStation Pro */
811 pr_info("ar8316: Using port 4 as PHY\n");
814 pr_info("ar8316: Using port 4 as switch port\n");
816 } else if (priv
->phy
->interface
== PHY_INTERFACE_MODE_GMII
) {
817 /* value taken from AVM Fritz!Box 7390 sources */
820 /* no known value for phy interface */
821 pr_err("ar8316: unsupported mii mode: %d.\n",
822 priv
->phy
->interface
);
829 priv
->write(priv
, AR8316_REG_POSTRIP
, newval
);
831 if (priv
->port4_phy
&&
832 priv
->phy
->interface
== PHY_INTERFACE_MODE_RGMII
) {
833 /* work around for phy4 rgmii mode */
834 ar8xxx_phy_dbg_write(priv
, 4, 0x12, 0x480c);
836 ar8xxx_phy_dbg_write(priv
, 4, 0x0, 0x824e);
838 ar8xxx_phy_dbg_write(priv
, 4, 0x5, 0x3d47);
842 /* Initialize the ports */
844 for (i
= 0; i
< 5; i
++) {
845 /* initialize the port itself */
846 mdiobus_write(bus
, i
, MII_ADVERTISE
,
847 ADVERTISE_ALL
| ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
);
848 mdiobus_write(bus
, i
, MII_CTRL1000
, ADVERTISE_1000FULL
);
849 mdiobus_write(bus
, i
, MII_BMCR
, BMCR_RESET
| BMCR_ANENABLE
);
855 priv
->initialized
= true;
860 ar8316_init_globals(struct ar8xxx_priv
*priv
)
862 /* standard atheros magic */
863 priv
->write(priv
, 0x38, 0xc000050e);
865 /* enable cpu port to receive multicast and broadcast frames */
866 priv
->write(priv
, AR8216_REG_FLOOD_MASK
, 0x003f003f);
868 /* enable jumbo frames */
869 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
870 AR8316_GCTRL_MTU
, 9018 + 8 + 2);
872 /* Enable MIB counters */
873 ar8xxx_rmw(priv
, AR8216_REG_MIB_FUNC
, AR8216_MIB_FUNC
| AR8236_MIB_EN
,
874 (AR8216_MIB_FUNC_NO_OP
<< AR8216_MIB_FUNC_S
) |
878 static const struct ar8xxx_chip ar8316_chip
= {
879 .caps
= AR8XXX_CAP_GIGE
| AR8XXX_CAP_MIB_COUNTERS
,
880 .hw_init
= ar8316_hw_init
,
881 .init_globals
= ar8316_init_globals
,
882 .init_port
= ar8216_init_port
,
883 .setup_port
= ar8216_setup_port
,
884 .read_port_status
= ar8216_read_port_status
,
885 .atu_flush
= ar8216_atu_flush
,
886 .vtu_flush
= ar8216_vtu_flush
,
887 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
889 .num_mibs
= ARRAY_SIZE(ar8236_mibs
),
890 .mib_decs
= ar8236_mibs
,
894 ar8327_get_pad_cfg(struct ar8327_pad_cfg
*cfg
)
906 case AR8327_PAD_MAC2MAC_MII
:
907 t
= AR8327_PAD_MAC_MII_EN
;
909 t
|= AR8327_PAD_MAC_MII_RXCLK_SEL
;
911 t
|= AR8327_PAD_MAC_MII_TXCLK_SEL
;
914 case AR8327_PAD_MAC2MAC_GMII
:
915 t
= AR8327_PAD_MAC_GMII_EN
;
917 t
|= AR8327_PAD_MAC_GMII_RXCLK_SEL
;
919 t
|= AR8327_PAD_MAC_GMII_TXCLK_SEL
;
922 case AR8327_PAD_MAC_SGMII
:
923 t
= AR8327_PAD_SGMII_EN
;
926 * WAR for the QUalcomm Atheros AP136 board.
927 * It seems that RGMII TX/RX delay settings needs to be
928 * applied for SGMII mode as well, The ethernet is not
929 * reliable without this.
931 t
|= cfg
->txclk_delay_sel
<< AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S
;
932 t
|= cfg
->rxclk_delay_sel
<< AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S
;
933 if (cfg
->rxclk_delay_en
)
934 t
|= AR8327_PAD_RGMII_RXCLK_DELAY_EN
;
935 if (cfg
->txclk_delay_en
)
936 t
|= AR8327_PAD_RGMII_TXCLK_DELAY_EN
;
938 if (cfg
->sgmii_delay_en
)
939 t
|= AR8327_PAD_SGMII_DELAY_EN
;
943 case AR8327_PAD_MAC2PHY_MII
:
944 t
= AR8327_PAD_PHY_MII_EN
;
946 t
|= AR8327_PAD_PHY_MII_RXCLK_SEL
;
948 t
|= AR8327_PAD_PHY_MII_TXCLK_SEL
;
951 case AR8327_PAD_MAC2PHY_GMII
:
952 t
= AR8327_PAD_PHY_GMII_EN
;
953 if (cfg
->pipe_rxclk_sel
)
954 t
|= AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL
;
956 t
|= AR8327_PAD_PHY_GMII_RXCLK_SEL
;
958 t
|= AR8327_PAD_PHY_GMII_TXCLK_SEL
;
961 case AR8327_PAD_MAC_RGMII
:
962 t
= AR8327_PAD_RGMII_EN
;
963 t
|= cfg
->txclk_delay_sel
<< AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S
;
964 t
|= cfg
->rxclk_delay_sel
<< AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S
;
965 if (cfg
->rxclk_delay_en
)
966 t
|= AR8327_PAD_RGMII_RXCLK_DELAY_EN
;
967 if (cfg
->txclk_delay_en
)
968 t
|= AR8327_PAD_RGMII_TXCLK_DELAY_EN
;
971 case AR8327_PAD_PHY_GMII
:
972 t
= AR8327_PAD_PHYX_GMII_EN
;
975 case AR8327_PAD_PHY_RGMII
:
976 t
= AR8327_PAD_PHYX_RGMII_EN
;
979 case AR8327_PAD_PHY_MII
:
980 t
= AR8327_PAD_PHYX_MII_EN
;
988 ar8327_phy_fixup(struct ar8xxx_priv
*priv
, int phy
)
990 switch (priv
->chip_rev
) {
992 /* For 100M waveform */
993 ar8xxx_phy_dbg_write(priv
, phy
, 0, 0x02ea);
994 /* Turn on Gigabit clock */
995 ar8xxx_phy_dbg_write(priv
, phy
, 0x3d, 0x68a0);
999 ar8xxx_phy_mmd_write(priv
, phy
, 0x7, 0x3c);
1000 ar8xxx_phy_mmd_write(priv
, phy
, 0x4007, 0x0);
1003 ar8xxx_phy_mmd_write(priv
, phy
, 0x3, 0x800d);
1004 ar8xxx_phy_mmd_write(priv
, phy
, 0x4003, 0x803f);
1006 ar8xxx_phy_dbg_write(priv
, phy
, 0x3d, 0x6860);
1007 ar8xxx_phy_dbg_write(priv
, phy
, 0x5, 0x2c46);
1008 ar8xxx_phy_dbg_write(priv
, phy
, 0x3c, 0x6000);
1014 ar8327_get_port_init_status(struct ar8327_port_cfg
*cfg
)
1018 if (!cfg
->force_link
)
1019 return AR8216_PORT_STATUS_LINK_AUTO
;
1021 t
= AR8216_PORT_STATUS_TXMAC
| AR8216_PORT_STATUS_RXMAC
;
1022 t
|= cfg
->duplex
? AR8216_PORT_STATUS_DUPLEX
: 0;
1023 t
|= cfg
->rxpause
? AR8216_PORT_STATUS_RXFLOW
: 0;
1024 t
|= cfg
->txpause
? AR8216_PORT_STATUS_TXFLOW
: 0;
1026 switch (cfg
->speed
) {
1027 case AR8327_PORT_SPEED_10
:
1028 t
|= AR8216_PORT_SPEED_10M
;
1030 case AR8327_PORT_SPEED_100
:
1031 t
|= AR8216_PORT_SPEED_100M
;
1033 case AR8327_PORT_SPEED_1000
:
1034 t
|= AR8216_PORT_SPEED_1000M
;
1042 ar8327_hw_init(struct ar8xxx_priv
*priv
)
1044 struct ar8327_platform_data
*pdata
;
1045 struct ar8327_led_cfg
*led_cfg
;
1046 struct ar8327_data
*data
;
1047 struct mii_bus
*bus
;
1052 pdata
= priv
->phy
->dev
.platform_data
;
1056 data
= &priv
->chip_data
.ar8327
;
1058 data
->port0_status
= ar8327_get_port_init_status(&pdata
->port0_cfg
);
1059 data
->port6_status
= ar8327_get_port_init_status(&pdata
->port6_cfg
);
1061 t
= ar8327_get_pad_cfg(pdata
->pad0_cfg
);
1062 priv
->write(priv
, AR8327_REG_PAD0_MODE
, t
);
1063 t
= ar8327_get_pad_cfg(pdata
->pad5_cfg
);
1064 priv
->write(priv
, AR8327_REG_PAD5_MODE
, t
);
1065 t
= ar8327_get_pad_cfg(pdata
->pad6_cfg
);
1066 priv
->write(priv
, AR8327_REG_PAD6_MODE
, t
);
1068 pos
= priv
->read(priv
, AR8327_REG_POWER_ON_STRIP
);
1071 led_cfg
= pdata
->led_cfg
;
1073 if (led_cfg
->open_drain
)
1074 new_pos
|= AR8327_POWER_ON_STRIP_LED_OPEN_EN
;
1076 new_pos
&= ~AR8327_POWER_ON_STRIP_LED_OPEN_EN
;
1078 priv
->write(priv
, AR8327_REG_LED_CTRL0
, led_cfg
->led_ctrl0
);
1079 priv
->write(priv
, AR8327_REG_LED_CTRL1
, led_cfg
->led_ctrl1
);
1080 priv
->write(priv
, AR8327_REG_LED_CTRL2
, led_cfg
->led_ctrl2
);
1081 priv
->write(priv
, AR8327_REG_LED_CTRL3
, led_cfg
->led_ctrl3
);
1084 if (new_pos
!= pos
) {
1085 new_pos
|= AR8327_POWER_ON_STRIP_POWER_ON_SEL
;
1086 priv
->write(priv
, AR8327_REG_POWER_ON_STRIP
, new_pos
);
1089 bus
= priv
->mii_bus
;
1090 for (i
= 0; i
< AR8327_NUM_PHYS
; i
++) {
1091 ar8327_phy_fixup(priv
, i
);
1093 /* start aneg on the PHY */
1094 mdiobus_write(bus
, i
, MII_ADVERTISE
, ADVERTISE_ALL
|
1095 ADVERTISE_PAUSE_CAP
|
1096 ADVERTISE_PAUSE_ASYM
);
1097 mdiobus_write(bus
, i
, MII_CTRL1000
, ADVERTISE_1000FULL
);
1098 mdiobus_write(bus
, i
, MII_BMCR
, BMCR_RESET
| BMCR_ANENABLE
);
1107 ar8327_init_globals(struct ar8xxx_priv
*priv
)
1111 /* enable CPU port and disable mirror port */
1112 t
= AR8327_FWD_CTRL0_CPU_PORT_EN
|
1113 AR8327_FWD_CTRL0_MIRROR_PORT
;
1114 priv
->write(priv
, AR8327_REG_FWD_CTRL0
, t
);
1116 /* forward multicast and broadcast frames to CPU */
1117 t
= (AR8327_PORTS_ALL
<< AR8327_FWD_CTRL1_UC_FLOOD_S
) |
1118 (AR8327_PORTS_ALL
<< AR8327_FWD_CTRL1_MC_FLOOD_S
) |
1119 (AR8327_PORTS_ALL
<< AR8327_FWD_CTRL1_BC_FLOOD_S
);
1120 priv
->write(priv
, AR8327_REG_FWD_CTRL1
, t
);
1123 ar8xxx_rmw(priv
, AR8327_REG_MAX_FRAME_SIZE
,
1124 AR8327_MAX_FRAME_SIZE_MTU
, 1518 + 8 + 2);
1126 /* Enable MIB counters */
1127 ar8xxx_reg_set(priv
, AR8327_REG_MODULE_EN
,
1128 AR8327_MODULE_EN_MIB
);
1132 ar8327_init_port(struct ar8xxx_priv
*priv
, int port
)
1136 if (port
== AR8216_PORT_CPU
)
1137 t
= priv
->chip_data
.ar8327
.port0_status
;
1139 t
= priv
->chip_data
.ar8327
.port6_status
;
1141 t
= AR8216_PORT_STATUS_LINK_AUTO
;
1143 priv
->write(priv
, AR8327_REG_PORT_STATUS(port
), t
);
1144 priv
->write(priv
, AR8327_REG_PORT_HEADER(port
), 0);
1146 t
= 1 << AR8327_PORT_VLAN0_DEF_SVID_S
;
1147 t
|= 1 << AR8327_PORT_VLAN0_DEF_CVID_S
;
1148 priv
->write(priv
, AR8327_REG_PORT_VLAN0(port
), t
);
1150 t
= AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH
<< AR8327_PORT_VLAN1_OUT_MODE_S
;
1151 priv
->write(priv
, AR8327_REG_PORT_VLAN1(port
), t
);
1153 t
= AR8327_PORT_LOOKUP_LEARN
;
1154 t
|= AR8216_PORT_STATE_FORWARD
<< AR8327_PORT_LOOKUP_STATE_S
;
1155 priv
->write(priv
, AR8327_REG_PORT_LOOKUP(port
), t
);
1159 ar8327_read_port_status(struct ar8xxx_priv
*priv
, int port
)
1161 return priv
->read(priv
, AR8327_REG_PORT_STATUS(port
));
1165 ar8327_atu_flush(struct ar8xxx_priv
*priv
)
1169 ret
= ar8216_wait_bit(priv
, AR8327_REG_ATU_FUNC
,
1170 AR8327_ATU_FUNC_BUSY
, 0);
1172 priv
->write(priv
, AR8327_REG_ATU_FUNC
,
1173 AR8327_ATU_FUNC_OP_FLUSH
);
1179 ar8327_vtu_op(struct ar8xxx_priv
*priv
, u32 op
, u32 val
)
1181 if (ar8216_wait_bit(priv
, AR8327_REG_VTU_FUNC1
,
1182 AR8327_VTU_FUNC1_BUSY
, 0))
1185 if ((op
& AR8327_VTU_FUNC1_OP
) == AR8327_VTU_FUNC1_OP_LOAD
)
1186 priv
->write(priv
, AR8327_REG_VTU_FUNC0
, val
);
1188 op
|= AR8327_VTU_FUNC1_BUSY
;
1189 priv
->write(priv
, AR8327_REG_VTU_FUNC1
, op
);
1193 ar8327_vtu_flush(struct ar8xxx_priv
*priv
)
1195 ar8327_vtu_op(priv
, AR8327_VTU_FUNC1_OP_FLUSH
, 0);
1199 ar8327_vtu_load_vlan(struct ar8xxx_priv
*priv
, u32 vid
, u32 port_mask
)
1205 op
= AR8327_VTU_FUNC1_OP_LOAD
| (vid
<< AR8327_VTU_FUNC1_VID_S
);
1206 val
= AR8327_VTU_FUNC0_VALID
| AR8327_VTU_FUNC0_IVL
;
1207 for (i
= 0; i
< AR8327_NUM_PORTS
; i
++) {
1210 if ((port_mask
& BIT(i
)) == 0)
1211 mode
= AR8327_VTU_FUNC0_EG_MODE_NOT
;
1212 else if (priv
->vlan
== 0)
1213 mode
= AR8327_VTU_FUNC0_EG_MODE_KEEP
;
1214 else if (priv
->vlan_tagged
& BIT(i
))
1215 mode
= AR8327_VTU_FUNC0_EG_MODE_TAG
;
1217 mode
= AR8327_VTU_FUNC0_EG_MODE_UNTAG
;
1219 val
|= mode
<< AR8327_VTU_FUNC0_EG_MODE_S(i
);
1221 ar8327_vtu_op(priv
, op
, val
);
1225 ar8327_setup_port(struct ar8xxx_priv
*priv
, int port
, u32 egress
, u32 ingress
,
1226 u32 members
, u32 pvid
)
1231 t
= pvid
<< AR8327_PORT_VLAN0_DEF_SVID_S
;
1232 t
|= pvid
<< AR8327_PORT_VLAN0_DEF_CVID_S
;
1233 priv
->write(priv
, AR8327_REG_PORT_VLAN0(port
), t
);
1235 mode
= AR8327_PORT_VLAN1_OUT_MODE_UNMOD
;
1237 case AR8216_OUT_KEEP
:
1238 mode
= AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH
;
1240 case AR8216_OUT_STRIP_VLAN
:
1241 mode
= AR8327_PORT_VLAN1_OUT_MODE_UNTAG
;
1243 case AR8216_OUT_ADD_VLAN
:
1244 mode
= AR8327_PORT_VLAN1_OUT_MODE_TAG
;
1248 t
= AR8327_PORT_VLAN1_PORT_VLAN_PROP
;
1249 t
|= mode
<< AR8327_PORT_VLAN1_OUT_MODE_S
;
1250 priv
->write(priv
, AR8327_REG_PORT_VLAN1(port
), t
);
1253 t
|= AR8327_PORT_LOOKUP_LEARN
;
1254 t
|= ingress
<< AR8327_PORT_LOOKUP_IN_MODE_S
;
1255 t
|= AR8216_PORT_STATE_FORWARD
<< AR8327_PORT_LOOKUP_STATE_S
;
1256 priv
->write(priv
, AR8327_REG_PORT_LOOKUP(port
), t
);
1259 static const struct ar8xxx_chip ar8327_chip
= {
1260 .caps
= AR8XXX_CAP_GIGE
| AR8XXX_CAP_MIB_COUNTERS
,
1261 .hw_init
= ar8327_hw_init
,
1262 .init_globals
= ar8327_init_globals
,
1263 .init_port
= ar8327_init_port
,
1264 .setup_port
= ar8327_setup_port
,
1265 .read_port_status
= ar8327_read_port_status
,
1266 .atu_flush
= ar8327_atu_flush
,
1267 .vtu_flush
= ar8327_vtu_flush
,
1268 .vtu_load_vlan
= ar8327_vtu_load_vlan
,
1270 .num_mibs
= ARRAY_SIZE(ar8236_mibs
),
1271 .mib_decs
= ar8236_mibs
,
1275 ar8xxx_sw_set_vlan(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1276 struct switch_val
*val
)
1278 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1279 priv
->vlan
= !!val
->value
.i
;
1284 ar8xxx_sw_get_vlan(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1285 struct switch_val
*val
)
1287 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1288 val
->value
.i
= priv
->vlan
;
1294 ar8xxx_sw_set_pvid(struct switch_dev
*dev
, int port
, int vlan
)
1296 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1298 /* make sure no invalid PVIDs get set */
1300 if (vlan
>= dev
->vlans
)
1303 priv
->pvid
[port
] = vlan
;
1308 ar8xxx_sw_get_pvid(struct switch_dev
*dev
, int port
, int *vlan
)
1310 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1311 *vlan
= priv
->pvid
[port
];
1316 ar8xxx_sw_set_vid(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1317 struct switch_val
*val
)
1319 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1320 priv
->vlan_id
[val
->port_vlan
] = val
->value
.i
;
1325 ar8xxx_sw_get_vid(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1326 struct switch_val
*val
)
1328 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1329 val
->value
.i
= priv
->vlan_id
[val
->port_vlan
];
1334 ar8xxx_sw_get_port_link(struct switch_dev
*dev
, int port
,
1335 struct switch_port_link
*link
)
1337 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1339 ar8216_read_port_link(priv
, port
, link
);
1344 ar8xxx_sw_get_ports(struct switch_dev
*dev
, struct switch_val
*val
)
1346 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1347 u8 ports
= priv
->vlan_table
[val
->port_vlan
];
1351 for (i
= 0; i
< dev
->ports
; i
++) {
1352 struct switch_port
*p
;
1354 if (!(ports
& (1 << i
)))
1357 p
= &val
->value
.ports
[val
->len
++];
1359 if (priv
->vlan_tagged
& (1 << i
))
1360 p
->flags
= (1 << SWITCH_PORT_FLAG_TAGGED
);
1368 ar8xxx_sw_set_ports(struct switch_dev
*dev
, struct switch_val
*val
)
1370 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1371 u8
*vt
= &priv
->vlan_table
[val
->port_vlan
];
1375 for (i
= 0; i
< val
->len
; i
++) {
1376 struct switch_port
*p
= &val
->value
.ports
[i
];
1378 if (p
->flags
& (1 << SWITCH_PORT_FLAG_TAGGED
)) {
1379 priv
->vlan_tagged
|= (1 << p
->id
);
1381 priv
->vlan_tagged
&= ~(1 << p
->id
);
1382 priv
->pvid
[p
->id
] = val
->port_vlan
;
1384 /* make sure that an untagged port does not
1385 * appear in other vlans */
1386 for (j
= 0; j
< AR8X16_MAX_VLANS
; j
++) {
1387 if (j
== val
->port_vlan
)
1389 priv
->vlan_table
[j
] &= ~(1 << p
->id
);
1399 ar8xxx_sw_hw_apply(struct switch_dev
*dev
)
1401 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1402 u8 portmask
[AR8X16_MAX_PORTS
];
1405 mutex_lock(&priv
->reg_mutex
);
1406 /* flush all vlan translation unit entries */
1407 priv
->chip
->vtu_flush(priv
);
1409 memset(portmask
, 0, sizeof(portmask
));
1411 /* calculate the port destination masks and load vlans
1412 * into the vlan translation unit */
1413 for (j
= 0; j
< AR8X16_MAX_VLANS
; j
++) {
1414 u8 vp
= priv
->vlan_table
[j
];
1419 for (i
= 0; i
< dev
->ports
; i
++) {
1422 portmask
[i
] |= vp
& ~mask
;
1425 priv
->chip
->vtu_load_vlan(priv
, priv
->vlan_id
[j
],
1426 priv
->vlan_table
[j
]);
1430 * isolate all ports, but connect them to the cpu port */
1431 for (i
= 0; i
< dev
->ports
; i
++) {
1432 if (i
== AR8216_PORT_CPU
)
1435 portmask
[i
] = 1 << AR8216_PORT_CPU
;
1436 portmask
[AR8216_PORT_CPU
] |= (1 << i
);
1440 /* update the port destination mask registers and tag settings */
1441 for (i
= 0; i
< dev
->ports
; i
++) {
1442 int egress
, ingress
;
1446 pvid
= priv
->vlan_id
[priv
->pvid
[i
]];
1447 if (priv
->vlan_tagged
& (1 << i
))
1448 egress
= AR8216_OUT_ADD_VLAN
;
1450 egress
= AR8216_OUT_STRIP_VLAN
;
1451 ingress
= AR8216_IN_SECURE
;
1454 egress
= AR8216_OUT_KEEP
;
1455 ingress
= AR8216_IN_PORT_ONLY
;
1458 priv
->chip
->setup_port(priv
, i
, egress
, ingress
, portmask
[i
],
1461 mutex_unlock(&priv
->reg_mutex
);
1466 ar8xxx_sw_reset_switch(struct switch_dev
*dev
)
1468 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1471 mutex_lock(&priv
->reg_mutex
);
1472 memset(&priv
->vlan
, 0, sizeof(struct ar8xxx_priv
) -
1473 offsetof(struct ar8xxx_priv
, vlan
));
1475 for (i
= 0; i
< AR8X16_MAX_VLANS
; i
++)
1476 priv
->vlan_id
[i
] = i
;
1478 /* Configure all ports */
1479 for (i
= 0; i
< dev
->ports
; i
++)
1480 priv
->chip
->init_port(priv
, i
);
1482 priv
->chip
->init_globals(priv
);
1483 mutex_unlock(&priv
->reg_mutex
);
1485 return ar8xxx_sw_hw_apply(dev
);
1489 ar8xxx_sw_set_reset_mibs(struct switch_dev
*dev
,
1490 const struct switch_attr
*attr
,
1491 struct switch_val
*val
)
1493 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1497 if (!ar8xxx_has_mib_counters(priv
))
1500 mutex_lock(&priv
->mib_lock
);
1502 len
= priv
->dev
.ports
* priv
->chip
->num_mibs
*
1503 sizeof(*priv
->mib_stats
);
1504 memset(priv
->mib_stats
, '\0', len
);
1505 ret
= ar8xxx_mib_flush(priv
);
1512 mutex_unlock(&priv
->mib_lock
);
1517 ar8xxx_sw_set_port_reset_mib(struct switch_dev
*dev
,
1518 const struct switch_attr
*attr
,
1519 struct switch_val
*val
)
1521 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1525 if (!ar8xxx_has_mib_counters(priv
))
1528 port
= val
->port_vlan
;
1529 if (port
>= dev
->ports
)
1532 mutex_lock(&priv
->mib_lock
);
1533 ret
= ar8xxx_mib_capture(priv
);
1537 ar8xxx_mib_fetch_port_stat(priv
, port
, true);
1542 mutex_unlock(&priv
->mib_lock
);
1547 ar8xxx_sw_get_port_mib(struct switch_dev
*dev
,
1548 const struct switch_attr
*attr
,
1549 struct switch_val
*val
)
1551 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1552 const struct ar8xxx_chip
*chip
= priv
->chip
;
1556 char *buf
= priv
->buf
;
1559 if (!ar8xxx_has_mib_counters(priv
))
1562 port
= val
->port_vlan
;
1563 if (port
>= dev
->ports
)
1566 mutex_lock(&priv
->mib_lock
);
1567 ret
= ar8xxx_mib_capture(priv
);
1571 ar8xxx_mib_fetch_port_stat(priv
, port
, false);
1573 len
+= snprintf(buf
+ len
, sizeof(priv
->buf
) - len
,
1574 "Port %d MIB counters\n",
1577 mib_stats
= &priv
->mib_stats
[port
* chip
->num_mibs
];
1578 for (i
= 0; i
< chip
->num_mibs
; i
++)
1579 len
+= snprintf(buf
+ len
, sizeof(priv
->buf
) - len
,
1581 chip
->mib_decs
[i
].name
,
1590 mutex_unlock(&priv
->mib_lock
);
1594 static struct switch_attr ar8xxx_sw_attr_globals
[] = {
1596 .type
= SWITCH_TYPE_INT
,
1597 .name
= "enable_vlan",
1598 .description
= "Enable VLAN mode",
1599 .set
= ar8xxx_sw_set_vlan
,
1600 .get
= ar8xxx_sw_get_vlan
,
1604 .type
= SWITCH_TYPE_NOVAL
,
1605 .name
= "reset_mibs",
1606 .description
= "Reset all MIB counters",
1607 .set
= ar8xxx_sw_set_reset_mibs
,
1612 static struct switch_attr ar8xxx_sw_attr_port
[] = {
1614 .type
= SWITCH_TYPE_NOVAL
,
1615 .name
= "reset_mib",
1616 .description
= "Reset single port MIB counters",
1617 .set
= ar8xxx_sw_set_port_reset_mib
,
1620 .type
= SWITCH_TYPE_STRING
,
1622 .description
= "Get port's MIB counters",
1624 .get
= ar8xxx_sw_get_port_mib
,
1628 static struct switch_attr ar8xxx_sw_attr_vlan
[] = {
1630 .type
= SWITCH_TYPE_INT
,
1632 .description
= "VLAN ID (0-4094)",
1633 .set
= ar8xxx_sw_set_vid
,
1634 .get
= ar8xxx_sw_get_vid
,
1639 static const struct switch_dev_ops ar8xxx_sw_ops
= {
1641 .attr
= ar8xxx_sw_attr_globals
,
1642 .n_attr
= ARRAY_SIZE(ar8xxx_sw_attr_globals
),
1645 .attr
= ar8xxx_sw_attr_port
,
1646 .n_attr
= ARRAY_SIZE(ar8xxx_sw_attr_port
),
1649 .attr
= ar8xxx_sw_attr_vlan
,
1650 .n_attr
= ARRAY_SIZE(ar8xxx_sw_attr_vlan
),
1652 .get_port_pvid
= ar8xxx_sw_get_pvid
,
1653 .set_port_pvid
= ar8xxx_sw_set_pvid
,
1654 .get_vlan_ports
= ar8xxx_sw_get_ports
,
1655 .set_vlan_ports
= ar8xxx_sw_set_ports
,
1656 .apply_config
= ar8xxx_sw_hw_apply
,
1657 .reset_switch
= ar8xxx_sw_reset_switch
,
1658 .get_port_link
= ar8xxx_sw_get_port_link
,
1662 ar8xxx_id_chip(struct ar8xxx_priv
*priv
)
1668 val
= priv
->read(priv
, AR8216_REG_CTRL
);
1672 id
= val
& (AR8216_CTRL_REVISION
| AR8216_CTRL_VERSION
);
1673 for (i
= 0; i
< AR8X16_PROBE_RETRIES
; i
++) {
1676 val
= priv
->read(priv
, AR8216_REG_CTRL
);
1680 t
= val
& (AR8216_CTRL_REVISION
| AR8216_CTRL_VERSION
);
1685 priv
->chip_ver
= (id
& AR8216_CTRL_VERSION
) >> AR8216_CTRL_VERSION_S
;
1686 priv
->chip_rev
= (id
& AR8216_CTRL_REVISION
);
1688 switch (priv
->chip_ver
) {
1689 case AR8XXX_VER_AR8216
:
1690 priv
->chip
= &ar8216_chip
;
1692 case AR8XXX_VER_AR8236
:
1693 priv
->chip
= &ar8236_chip
;
1695 case AR8XXX_VER_AR8316
:
1696 priv
->chip
= &ar8316_chip
;
1698 case AR8XXX_VER_AR8327
:
1699 priv
->mii_lo_first
= true;
1700 priv
->chip
= &ar8327_chip
;
1703 pr_err("ar8216: Unknown Atheros device [ver=%d, rev=%d]\n",
1704 priv
->chip_ver
, priv
->chip_rev
);
1713 ar8xxx_mib_work_func(struct work_struct
*work
)
1715 struct ar8xxx_priv
*priv
;
1718 priv
= container_of(work
, struct ar8xxx_priv
, mib_work
.work
);
1720 mutex_lock(&priv
->mib_lock
);
1722 err
= ar8xxx_mib_capture(priv
);
1726 ar8xxx_mib_fetch_port_stat(priv
, priv
->mib_next_port
, false);
1729 priv
->mib_next_port
++;
1730 if (priv
->mib_next_port
>= priv
->dev
.ports
)
1731 priv
->mib_next_port
= 0;
1733 mutex_unlock(&priv
->mib_lock
);
1734 schedule_delayed_work(&priv
->mib_work
,
1735 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY
));
1739 ar8xxx_mib_init(struct ar8xxx_priv
*priv
)
1743 if (!ar8xxx_has_mib_counters(priv
))
1746 BUG_ON(!priv
->chip
->mib_decs
|| !priv
->chip
->num_mibs
);
1748 len
= priv
->dev
.ports
* priv
->chip
->num_mibs
*
1749 sizeof(*priv
->mib_stats
);
1750 priv
->mib_stats
= kzalloc(len
, GFP_KERNEL
);
1752 if (!priv
->mib_stats
)
1759 ar8xxx_mib_start(struct ar8xxx_priv
*priv
)
1761 if (!ar8xxx_has_mib_counters(priv
))
1764 schedule_delayed_work(&priv
->mib_work
,
1765 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY
));
1769 ar8xxx_mib_stop(struct ar8xxx_priv
*priv
)
1771 if (!ar8xxx_has_mib_counters(priv
))
1774 cancel_delayed_work(&priv
->mib_work
);
1777 static struct ar8xxx_priv
*
1780 struct ar8xxx_priv
*priv
;
1782 priv
= kzalloc(sizeof(struct ar8xxx_priv
), GFP_KERNEL
);
1786 mutex_init(&priv
->reg_mutex
);
1787 mutex_init(&priv
->mib_lock
);
1788 INIT_DELAYED_WORK(&priv
->mib_work
, ar8xxx_mib_work_func
);
1794 ar8xxx_free(struct ar8xxx_priv
*priv
)
1796 kfree(priv
->mib_stats
);
1800 static struct ar8xxx_priv
*
1801 ar8xxx_create_mii(struct mii_bus
*bus
)
1803 struct ar8xxx_priv
*priv
;
1805 priv
= ar8xxx_create();
1807 priv
->mii_bus
= bus
;
1808 priv
->read
= ar8xxx_mii_read
;
1809 priv
->write
= ar8xxx_mii_write
;
1816 ar8xxx_probe_switch(struct ar8xxx_priv
*priv
)
1818 struct switch_dev
*swdev
;
1821 ret
= ar8xxx_id_chip(priv
);
1826 swdev
->cpu_port
= AR8216_PORT_CPU
;
1827 swdev
->ops
= &ar8xxx_sw_ops
;
1829 if (chip_is_ar8316(priv
)) {
1830 swdev
->name
= "Atheros AR8316";
1831 swdev
->vlans
= AR8X16_MAX_VLANS
;
1832 swdev
->ports
= AR8216_NUM_PORTS
;
1833 } else if (chip_is_ar8236(priv
)) {
1834 swdev
->name
= "Atheros AR8236";
1835 swdev
->vlans
= AR8216_NUM_VLANS
;
1836 swdev
->ports
= AR8216_NUM_PORTS
;
1837 } else if (chip_is_ar8327(priv
)) {
1838 swdev
->name
= "Atheros AR8327";
1839 swdev
->vlans
= AR8X16_MAX_VLANS
;
1840 swdev
->ports
= AR8327_NUM_PORTS
;
1842 swdev
->name
= "Atheros AR8216";
1843 swdev
->vlans
= AR8216_NUM_VLANS
;
1844 swdev
->ports
= AR8216_NUM_PORTS
;
1847 ret
= ar8xxx_mib_init(priv
);
1855 ar8xxx_phy_config_init(struct phy_device
*phydev
)
1857 struct ar8xxx_priv
*priv
= phydev
->priv
;
1858 struct net_device
*dev
= phydev
->attached_dev
;
1866 if (phydev
->addr
!= 0) {
1867 if (chip_is_ar8316(priv
)) {
1868 /* switch device has been initialized, reinit */
1869 priv
->dev
.ports
= (AR8216_NUM_PORTS
- 1);
1870 priv
->initialized
= false;
1871 priv
->port4_phy
= true;
1872 ar8316_hw_init(priv
);
1881 ret
= priv
->chip
->hw_init(priv
);
1885 ret
= ar8xxx_sw_reset_switch(&priv
->dev
);
1889 /* VID fixup only needed on ar8216 */
1890 if (chip_is_ar8216(priv
)) {
1891 dev
->phy_ptr
= priv
;
1892 dev
->priv_flags
|= IFF_NO_IP_ALIGN
;
1893 dev
->eth_mangle_rx
= ar8216_mangle_rx
;
1894 dev
->eth_mangle_tx
= ar8216_mangle_tx
;
1899 ar8xxx_mib_start(priv
);
1905 ar8xxx_phy_read_status(struct phy_device
*phydev
)
1907 struct ar8xxx_priv
*priv
= phydev
->priv
;
1908 struct switch_port_link link
;
1911 if (phydev
->addr
!= 0)
1912 return genphy_read_status(phydev
);
1914 ar8216_read_port_link(priv
, phydev
->addr
, &link
);
1915 phydev
->link
= !!link
.link
;
1919 switch (link
.speed
) {
1920 case SWITCH_PORT_SPEED_10
:
1921 phydev
->speed
= SPEED_10
;
1923 case SWITCH_PORT_SPEED_100
:
1924 phydev
->speed
= SPEED_100
;
1926 case SWITCH_PORT_SPEED_1000
:
1927 phydev
->speed
= SPEED_1000
;
1932 phydev
->duplex
= link
.duplex
? DUPLEX_FULL
: DUPLEX_HALF
;
1934 /* flush the address translation unit */
1935 mutex_lock(&priv
->reg_mutex
);
1936 ret
= priv
->chip
->atu_flush(priv
);
1937 mutex_unlock(&priv
->reg_mutex
);
1939 phydev
->state
= PHY_RUNNING
;
1940 netif_carrier_on(phydev
->attached_dev
);
1941 phydev
->adjust_link(phydev
->attached_dev
);
1947 ar8xxx_phy_config_aneg(struct phy_device
*phydev
)
1949 if (phydev
->addr
== 0)
1952 return genphy_config_aneg(phydev
);
1955 static const u32 ar8xxx_phy_ids
[] = {
1962 ar8xxx_phy_match(u32 phy_id
)
1966 for (i
= 0; i
< ARRAY_SIZE(ar8xxx_phy_ids
); i
++)
1967 if (phy_id
== ar8xxx_phy_ids
[i
])
1974 ar8xxx_is_possible(struct mii_bus
*bus
)
1978 for (i
= 0; i
< 4; i
++) {
1981 phy_id
= mdiobus_read(bus
, i
, MII_PHYSID1
) << 16;
1982 phy_id
|= mdiobus_read(bus
, i
, MII_PHYSID2
);
1983 if (!ar8xxx_phy_match(phy_id
)) {
1984 pr_debug("ar8xxx: unknown PHY at %s:%02x id:%08x\n",
1985 dev_name(&bus
->dev
), i
, phy_id
);
1994 ar8xxx_phy_probe(struct phy_device
*phydev
)
1996 struct ar8xxx_priv
*priv
;
1997 struct switch_dev
*swdev
;
2000 /* skip PHYs at unused adresses */
2001 if (phydev
->addr
!= 0 && phydev
->addr
!= 4)
2004 if (!ar8xxx_is_possible(phydev
->bus
))
2007 mutex_lock(&ar8xxx_dev_list_lock
);
2008 list_for_each_entry(priv
, &ar8xxx_dev_list
, list
)
2009 if (priv
->mii_bus
== phydev
->bus
)
2012 priv
= ar8xxx_create_mii(phydev
->bus
);
2018 ret
= ar8xxx_probe_switch(priv
);
2023 swdev
->alias
= dev_name(&priv
->mii_bus
->dev
);
2024 ret
= register_switch(swdev
, NULL
);
2028 pr_info("%s: %s switch registered on %s\n",
2029 swdev
->devname
, swdev
->name
, dev_name(&priv
->mii_bus
->dev
));
2032 if (phydev
->addr
== 0) {
2033 if (ar8xxx_has_gige(priv
)) {
2034 phydev
->supported
= SUPPORTED_1000baseT_Full
;
2035 phydev
->advertising
= ADVERTISED_1000baseT_Full
;
2037 phydev
->supported
= SUPPORTED_100baseT_Full
;
2038 phydev
->advertising
= ADVERTISED_100baseT_Full
;
2041 if (ar8xxx_has_gige(priv
)) {
2042 phydev
->supported
|= SUPPORTED_1000baseT_Full
;
2043 phydev
->advertising
|= ADVERTISED_1000baseT_Full
;
2047 phydev
->priv
= priv
;
2050 list_add(&priv
->list
, &ar8xxx_dev_list
);
2052 mutex_unlock(&ar8xxx_dev_list_lock
);
2059 mutex_unlock(&ar8xxx_dev_list_lock
);
2064 ar8xxx_phy_detach(struct phy_device
*phydev
)
2066 struct net_device
*dev
= phydev
->attached_dev
;
2071 dev
->phy_ptr
= NULL
;
2072 dev
->priv_flags
&= ~IFF_NO_IP_ALIGN
;
2073 dev
->eth_mangle_rx
= NULL
;
2074 dev
->eth_mangle_tx
= NULL
;
2078 ar8xxx_phy_remove(struct phy_device
*phydev
)
2080 struct ar8xxx_priv
*priv
= phydev
->priv
;
2085 phydev
->priv
= NULL
;
2086 if (--priv
->use_count
> 0)
2089 mutex_lock(&ar8xxx_dev_list_lock
);
2090 list_del(&priv
->list
);
2091 mutex_unlock(&ar8xxx_dev_list_lock
);
2093 unregister_switch(&priv
->dev
);
2094 ar8xxx_mib_stop(priv
);
2098 static struct phy_driver ar8xxx_phy_driver
= {
2099 .phy_id
= 0x004d0000,
2100 .name
= "Atheros AR8216/AR8236/AR8316",
2101 .phy_id_mask
= 0xffff0000,
2102 .features
= PHY_BASIC_FEATURES
,
2103 .probe
= ar8xxx_phy_probe
,
2104 .remove
= ar8xxx_phy_remove
,
2105 .detach
= ar8xxx_phy_detach
,
2106 .config_init
= ar8xxx_phy_config_init
,
2107 .config_aneg
= ar8xxx_phy_config_aneg
,
2108 .read_status
= ar8xxx_phy_read_status
,
2109 .driver
= { .owner
= THIS_MODULE
},
2115 return phy_driver_register(&ar8xxx_phy_driver
);
2121 phy_driver_unregister(&ar8xxx_phy_driver
);
2124 module_init(ar8xxx_init
);
2125 module_exit(ar8xxx_exit
);
2126 MODULE_LICENSE("GPL");