2 * ar8216.c: AR8216 switch driver
4 * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>
5 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/list.h>
22 #include <linux/if_ether.h>
23 #include <linux/skbuff.h>
24 #include <linux/netdevice.h>
25 #include <linux/netlink.h>
26 #include <linux/of_device.h>
27 #include <linux/of_mdio.h>
28 #include <linux/of_net.h>
29 #include <linux/bitops.h>
30 #include <net/genetlink.h>
31 #include <linux/switch.h>
32 #include <linux/delay.h>
33 #include <linux/phy.h>
34 #include <linux/etherdevice.h>
35 #include <linux/lockdep.h>
36 #include <linux/ar8216_platform.h>
37 #include <linux/workqueue.h>
38 #include <linux/version.h>
42 extern const struct ar8xxx_chip ar8327_chip
;
43 extern const struct ar8xxx_chip ar8337_chip
;
45 #define MIB_DESC_BASIC(_s , _o, _n) \
50 .type = AR8XXX_MIB_BASIC, \
53 #define MIB_DESC_EXT(_s , _o, _n) \
58 .type = AR8XXX_MIB_EXTENDED, \
61 static const struct ar8xxx_mib_desc ar8216_mibs
[] = {
62 MIB_DESC_EXT(1, AR8216_STATS_RXBROAD
, "RxBroad"),
63 MIB_DESC_EXT(1, AR8216_STATS_RXPAUSE
, "RxPause"),
64 MIB_DESC_EXT(1, AR8216_STATS_RXMULTI
, "RxMulti"),
65 MIB_DESC_EXT(1, AR8216_STATS_RXFCSERR
, "RxFcsErr"),
66 MIB_DESC_EXT(1, AR8216_STATS_RXALIGNERR
, "RxAlignErr"),
67 MIB_DESC_EXT(1, AR8216_STATS_RXRUNT
, "RxRunt"),
68 MIB_DESC_EXT(1, AR8216_STATS_RXFRAGMENT
, "RxFragment"),
69 MIB_DESC_EXT(1, AR8216_STATS_RX64BYTE
, "Rx64Byte"),
70 MIB_DESC_EXT(1, AR8216_STATS_RX128BYTE
, "Rx128Byte"),
71 MIB_DESC_EXT(1, AR8216_STATS_RX256BYTE
, "Rx256Byte"),
72 MIB_DESC_EXT(1, AR8216_STATS_RX512BYTE
, "Rx512Byte"),
73 MIB_DESC_EXT(1, AR8216_STATS_RX1024BYTE
, "Rx1024Byte"),
74 MIB_DESC_EXT(1, AR8216_STATS_RXMAXBYTE
, "RxMaxByte"),
75 MIB_DESC_EXT(1, AR8216_STATS_RXTOOLONG
, "RxTooLong"),
76 MIB_DESC_BASIC(2, AR8216_STATS_RXGOODBYTE
, "RxGoodByte"),
77 MIB_DESC_EXT(2, AR8216_STATS_RXBADBYTE
, "RxBadByte"),
78 MIB_DESC_EXT(1, AR8216_STATS_RXOVERFLOW
, "RxOverFlow"),
79 MIB_DESC_EXT(1, AR8216_STATS_FILTERED
, "Filtered"),
80 MIB_DESC_EXT(1, AR8216_STATS_TXBROAD
, "TxBroad"),
81 MIB_DESC_EXT(1, AR8216_STATS_TXPAUSE
, "TxPause"),
82 MIB_DESC_EXT(1, AR8216_STATS_TXMULTI
, "TxMulti"),
83 MIB_DESC_EXT(1, AR8216_STATS_TXUNDERRUN
, "TxUnderRun"),
84 MIB_DESC_EXT(1, AR8216_STATS_TX64BYTE
, "Tx64Byte"),
85 MIB_DESC_EXT(1, AR8216_STATS_TX128BYTE
, "Tx128Byte"),
86 MIB_DESC_EXT(1, AR8216_STATS_TX256BYTE
, "Tx256Byte"),
87 MIB_DESC_EXT(1, AR8216_STATS_TX512BYTE
, "Tx512Byte"),
88 MIB_DESC_EXT(1, AR8216_STATS_TX1024BYTE
, "Tx1024Byte"),
89 MIB_DESC_EXT(1, AR8216_STATS_TXMAXBYTE
, "TxMaxByte"),
90 MIB_DESC_EXT(1, AR8216_STATS_TXOVERSIZE
, "TxOverSize"),
91 MIB_DESC_BASIC(2, AR8216_STATS_TXBYTE
, "TxByte"),
92 MIB_DESC_EXT(1, AR8216_STATS_TXCOLLISION
, "TxCollision"),
93 MIB_DESC_EXT(1, AR8216_STATS_TXABORTCOL
, "TxAbortCol"),
94 MIB_DESC_EXT(1, AR8216_STATS_TXMULTICOL
, "TxMultiCol"),
95 MIB_DESC_EXT(1, AR8216_STATS_TXSINGLECOL
, "TxSingleCol"),
96 MIB_DESC_EXT(1, AR8216_STATS_TXEXCDEFER
, "TxExcDefer"),
97 MIB_DESC_EXT(1, AR8216_STATS_TXDEFER
, "TxDefer"),
98 MIB_DESC_EXT(1, AR8216_STATS_TXLATECOL
, "TxLateCol"),
101 const struct ar8xxx_mib_desc ar8236_mibs
[39] = {
102 MIB_DESC_EXT(1, AR8236_STATS_RXBROAD
, "RxBroad"),
103 MIB_DESC_EXT(1, AR8236_STATS_RXPAUSE
, "RxPause"),
104 MIB_DESC_EXT(1, AR8236_STATS_RXMULTI
, "RxMulti"),
105 MIB_DESC_EXT(1, AR8236_STATS_RXFCSERR
, "RxFcsErr"),
106 MIB_DESC_EXT(1, AR8236_STATS_RXALIGNERR
, "RxAlignErr"),
107 MIB_DESC_EXT(1, AR8236_STATS_RXRUNT
, "RxRunt"),
108 MIB_DESC_EXT(1, AR8236_STATS_RXFRAGMENT
, "RxFragment"),
109 MIB_DESC_EXT(1, AR8236_STATS_RX64BYTE
, "Rx64Byte"),
110 MIB_DESC_EXT(1, AR8236_STATS_RX128BYTE
, "Rx128Byte"),
111 MIB_DESC_EXT(1, AR8236_STATS_RX256BYTE
, "Rx256Byte"),
112 MIB_DESC_EXT(1, AR8236_STATS_RX512BYTE
, "Rx512Byte"),
113 MIB_DESC_EXT(1, AR8236_STATS_RX1024BYTE
, "Rx1024Byte"),
114 MIB_DESC_EXT(1, AR8236_STATS_RX1518BYTE
, "Rx1518Byte"),
115 MIB_DESC_EXT(1, AR8236_STATS_RXMAXBYTE
, "RxMaxByte"),
116 MIB_DESC_EXT(1, AR8236_STATS_RXTOOLONG
, "RxTooLong"),
117 MIB_DESC_BASIC(2, AR8236_STATS_RXGOODBYTE
, "RxGoodByte"),
118 MIB_DESC_EXT(2, AR8236_STATS_RXBADBYTE
, "RxBadByte"),
119 MIB_DESC_EXT(1, AR8236_STATS_RXOVERFLOW
, "RxOverFlow"),
120 MIB_DESC_EXT(1, AR8236_STATS_FILTERED
, "Filtered"),
121 MIB_DESC_EXT(1, AR8236_STATS_TXBROAD
, "TxBroad"),
122 MIB_DESC_EXT(1, AR8236_STATS_TXPAUSE
, "TxPause"),
123 MIB_DESC_EXT(1, AR8236_STATS_TXMULTI
, "TxMulti"),
124 MIB_DESC_EXT(1, AR8236_STATS_TXUNDERRUN
, "TxUnderRun"),
125 MIB_DESC_EXT(1, AR8236_STATS_TX64BYTE
, "Tx64Byte"),
126 MIB_DESC_EXT(1, AR8236_STATS_TX128BYTE
, "Tx128Byte"),
127 MIB_DESC_EXT(1, AR8236_STATS_TX256BYTE
, "Tx256Byte"),
128 MIB_DESC_EXT(1, AR8236_STATS_TX512BYTE
, "Tx512Byte"),
129 MIB_DESC_EXT(1, AR8236_STATS_TX1024BYTE
, "Tx1024Byte"),
130 MIB_DESC_EXT(1, AR8236_STATS_TX1518BYTE
, "Tx1518Byte"),
131 MIB_DESC_EXT(1, AR8236_STATS_TXMAXBYTE
, "TxMaxByte"),
132 MIB_DESC_EXT(1, AR8236_STATS_TXOVERSIZE
, "TxOverSize"),
133 MIB_DESC_BASIC(2, AR8236_STATS_TXBYTE
, "TxByte"),
134 MIB_DESC_EXT(1, AR8236_STATS_TXCOLLISION
, "TxCollision"),
135 MIB_DESC_EXT(1, AR8236_STATS_TXABORTCOL
, "TxAbortCol"),
136 MIB_DESC_EXT(1, AR8236_STATS_TXMULTICOL
, "TxMultiCol"),
137 MIB_DESC_EXT(1, AR8236_STATS_TXSINGLECOL
, "TxSingleCol"),
138 MIB_DESC_EXT(1, AR8236_STATS_TXEXCDEFER
, "TxExcDefer"),
139 MIB_DESC_EXT(1, AR8236_STATS_TXDEFER
, "TxDefer"),
140 MIB_DESC_EXT(1, AR8236_STATS_TXLATECOL
, "TxLateCol"),
143 static DEFINE_MUTEX(ar8xxx_dev_list_lock
);
144 static LIST_HEAD(ar8xxx_dev_list
);
147 ar8xxx_mib_start(struct ar8xxx_priv
*priv
);
149 ar8xxx_mib_stop(struct ar8xxx_priv
*priv
);
151 /* inspired by phy_poll_reset in drivers/net/phy/phy_device.c */
153 ar8xxx_phy_poll_reset(struct mii_bus
*bus
)
155 unsigned int sleep_msecs
= 20;
158 for (elapsed
= sleep_msecs
; elapsed
<= 600;
159 elapsed
+= sleep_msecs
) {
161 for (i
= 0; i
< AR8XXX_NUM_PHYS
; i
++) {
162 ret
= mdiobus_read(bus
, i
, MII_BMCR
);
165 if (ret
& BMCR_RESET
)
167 if (i
== AR8XXX_NUM_PHYS
- 1) {
168 usleep_range(1000, 2000);
177 ar8xxx_phy_check_aneg(struct phy_device
*phydev
)
181 if (phydev
->autoneg
!= AUTONEG_ENABLE
)
184 * BMCR_ANENABLE might have been cleared
185 * by phy_init_hw in certain kernel versions
186 * therefore check for it
188 ret
= phy_read(phydev
, MII_BMCR
);
191 if (ret
& BMCR_ANENABLE
)
194 dev_info(&phydev
->mdio
.dev
, "ANEG disabled, re-enabling ...\n");
195 ret
|= BMCR_ANENABLE
| BMCR_ANRESTART
;
196 return phy_write(phydev
, MII_BMCR
, ret
);
200 ar8xxx_phy_init(struct ar8xxx_priv
*priv
)
205 bus
= priv
->sw_mii_bus
?: priv
->mii_bus
;
206 for (i
= 0; i
< AR8XXX_NUM_PHYS
; i
++) {
207 if (priv
->chip
->phy_fixup
)
208 priv
->chip
->phy_fixup(priv
, i
);
210 /* initialize the port itself */
211 mdiobus_write(bus
, i
, MII_ADVERTISE
,
212 ADVERTISE_ALL
| ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
);
213 if (ar8xxx_has_gige(priv
))
214 mdiobus_write(bus
, i
, MII_CTRL1000
, ADVERTISE_1000FULL
);
215 mdiobus_write(bus
, i
, MII_BMCR
, BMCR_RESET
| BMCR_ANENABLE
);
218 ar8xxx_phy_poll_reset(bus
);
222 ar8xxx_mii_read32(struct ar8xxx_priv
*priv
, int phy_id
, int regnum
)
224 struct mii_bus
*bus
= priv
->mii_bus
;
227 lo
= bus
->read(bus
, phy_id
, regnum
);
228 hi
= bus
->read(bus
, phy_id
, regnum
+ 1);
230 return (hi
<< 16) | lo
;
234 ar8xxx_mii_write32(struct ar8xxx_priv
*priv
, int phy_id
, int regnum
, u32 val
)
236 struct mii_bus
*bus
= priv
->mii_bus
;
240 hi
= (u16
) (val
>> 16);
242 if (priv
->chip
->mii_lo_first
)
244 bus
->write(bus
, phy_id
, regnum
, lo
);
245 bus
->write(bus
, phy_id
, regnum
+ 1, hi
);
247 bus
->write(bus
, phy_id
, regnum
+ 1, hi
);
248 bus
->write(bus
, phy_id
, regnum
, lo
);
253 ar8xxx_read(struct ar8xxx_priv
*priv
, int reg
)
255 struct mii_bus
*bus
= priv
->mii_bus
;
259 split_addr((u32
) reg
, &r1
, &r2
, &page
);
261 mutex_lock(&bus
->mdio_lock
);
263 bus
->write(bus
, 0x18, 0, page
);
264 wait_for_page_switch();
265 val
= ar8xxx_mii_read32(priv
, 0x10 | r2
, r1
);
267 mutex_unlock(&bus
->mdio_lock
);
273 ar8xxx_write(struct ar8xxx_priv
*priv
, int reg
, u32 val
)
275 struct mii_bus
*bus
= priv
->mii_bus
;
278 split_addr((u32
) reg
, &r1
, &r2
, &page
);
280 mutex_lock(&bus
->mdio_lock
);
282 bus
->write(bus
, 0x18, 0, page
);
283 wait_for_page_switch();
284 ar8xxx_mii_write32(priv
, 0x10 | r2
, r1
, val
);
286 mutex_unlock(&bus
->mdio_lock
);
290 ar8xxx_rmw(struct ar8xxx_priv
*priv
, int reg
, u32 mask
, u32 val
)
292 struct mii_bus
*bus
= priv
->mii_bus
;
296 split_addr((u32
) reg
, &r1
, &r2
, &page
);
298 mutex_lock(&bus
->mdio_lock
);
300 bus
->write(bus
, 0x18, 0, page
);
301 wait_for_page_switch();
303 ret
= ar8xxx_mii_read32(priv
, 0x10 | r2
, r1
);
306 ar8xxx_mii_write32(priv
, 0x10 | r2
, r1
, ret
);
308 mutex_unlock(&bus
->mdio_lock
);
313 ar8xxx_phy_dbg_read(struct ar8xxx_priv
*priv
, int phy_addr
,
314 u16 dbg_addr
, u16
*dbg_data
)
316 struct mii_bus
*bus
= priv
->mii_bus
;
318 mutex_lock(&bus
->mdio_lock
);
319 bus
->write(bus
, phy_addr
, MII_ATH_DBG_ADDR
, dbg_addr
);
320 *dbg_data
= bus
->read(bus
, phy_addr
, MII_ATH_DBG_DATA
);
321 mutex_unlock(&bus
->mdio_lock
);
325 ar8xxx_phy_dbg_write(struct ar8xxx_priv
*priv
, int phy_addr
,
326 u16 dbg_addr
, u16 dbg_data
)
328 struct mii_bus
*bus
= priv
->mii_bus
;
330 mutex_lock(&bus
->mdio_lock
);
331 bus
->write(bus
, phy_addr
, MII_ATH_DBG_ADDR
, dbg_addr
);
332 bus
->write(bus
, phy_addr
, MII_ATH_DBG_DATA
, dbg_data
);
333 mutex_unlock(&bus
->mdio_lock
);
337 ar8xxx_phy_mmd_prep(struct mii_bus
*bus
, int phy_addr
, u16 addr
, u16 reg
)
339 bus
->write(bus
, phy_addr
, MII_ATH_MMD_ADDR
, addr
);
340 bus
->write(bus
, phy_addr
, MII_ATH_MMD_DATA
, reg
);
341 bus
->write(bus
, phy_addr
, MII_ATH_MMD_ADDR
, addr
| 0x4000);
345 ar8xxx_phy_mmd_write(struct ar8xxx_priv
*priv
, int phy_addr
, u16 addr
, u16 reg
, u16 data
)
347 struct mii_bus
*bus
= priv
->mii_bus
;
349 mutex_lock(&bus
->mdio_lock
);
350 ar8xxx_phy_mmd_prep(bus
, phy_addr
, addr
, reg
);
351 bus
->write(bus
, phy_addr
, MII_ATH_MMD_DATA
, data
);
352 mutex_unlock(&bus
->mdio_lock
);
356 ar8xxx_phy_mmd_read(struct ar8xxx_priv
*priv
, int phy_addr
, u16 addr
, u16 reg
)
358 struct mii_bus
*bus
= priv
->mii_bus
;
361 mutex_lock(&bus
->mdio_lock
);
362 ar8xxx_phy_mmd_prep(bus
, phy_addr
, addr
, reg
);
363 data
= bus
->read(bus
, phy_addr
, MII_ATH_MMD_DATA
);
364 mutex_unlock(&bus
->mdio_lock
);
370 ar8xxx_reg_wait(struct ar8xxx_priv
*priv
, u32 reg
, u32 mask
, u32 val
,
375 for (i
= 0; i
< timeout
; i
++) {
378 t
= ar8xxx_read(priv
, reg
);
379 if ((t
& mask
) == val
)
382 usleep_range(1000, 2000);
390 ar8xxx_mib_op(struct ar8xxx_priv
*priv
, u32 op
)
392 unsigned mib_func
= priv
->chip
->mib_func
;
395 lockdep_assert_held(&priv
->mib_lock
);
397 /* Capture the hardware statistics for all ports */
398 ar8xxx_rmw(priv
, mib_func
, AR8216_MIB_FUNC
, (op
<< AR8216_MIB_FUNC_S
));
400 /* Wait for the capturing to complete. */
401 ret
= ar8xxx_reg_wait(priv
, mib_func
, AR8216_MIB_BUSY
, 0, 10);
412 ar8xxx_mib_capture(struct ar8xxx_priv
*priv
)
414 return ar8xxx_mib_op(priv
, AR8216_MIB_FUNC_CAPTURE
);
418 ar8xxx_mib_flush(struct ar8xxx_priv
*priv
)
420 return ar8xxx_mib_op(priv
, AR8216_MIB_FUNC_FLUSH
);
424 ar8xxx_mib_fetch_port_stat(struct ar8xxx_priv
*priv
, int port
, bool flush
)
430 WARN_ON(port
>= priv
->dev
.ports
);
432 lockdep_assert_held(&priv
->mib_lock
);
434 base
= priv
->chip
->reg_port_stats_start
+
435 priv
->chip
->reg_port_stats_length
* port
;
437 mib_stats
= &priv
->mib_stats
[port
* priv
->chip
->num_mibs
];
438 for (i
= 0; i
< priv
->chip
->num_mibs
; i
++) {
439 const struct ar8xxx_mib_desc
*mib
;
442 mib
= &priv
->chip
->mib_decs
[i
];
443 if (mib
->type
> priv
->mib_type
)
445 t
= ar8xxx_read(priv
, base
+ mib
->offset
);
446 if (mib
->size
== 2) {
449 hi
= ar8xxx_read(priv
, base
+ mib
->offset
+ 4);
462 ar8216_read_port_link(struct ar8xxx_priv
*priv
, int port
,
463 struct switch_port_link
*link
)
468 memset(link
, '\0', sizeof(*link
));
470 status
= priv
->chip
->read_port_status(priv
, port
);
472 link
->aneg
= !!(status
& AR8216_PORT_STATUS_LINK_AUTO
);
474 link
->link
= !!(status
& AR8216_PORT_STATUS_LINK_UP
);
478 if (priv
->get_port_link
) {
481 err
= priv
->get_port_link(port
);
490 link
->duplex
= !!(status
& AR8216_PORT_STATUS_DUPLEX
);
491 link
->tx_flow
= !!(status
& AR8216_PORT_STATUS_TXFLOW
);
492 link
->rx_flow
= !!(status
& AR8216_PORT_STATUS_RXFLOW
);
494 if (link
->aneg
&& link
->duplex
&& priv
->chip
->read_port_eee_status
)
495 link
->eee
= priv
->chip
->read_port_eee_status(priv
, port
);
497 speed
= (status
& AR8216_PORT_STATUS_SPEED
) >>
498 AR8216_PORT_STATUS_SPEED_S
;
501 case AR8216_PORT_SPEED_10M
:
502 link
->speed
= SWITCH_PORT_SPEED_10
;
504 case AR8216_PORT_SPEED_100M
:
505 link
->speed
= SWITCH_PORT_SPEED_100
;
507 case AR8216_PORT_SPEED_1000M
:
508 link
->speed
= SWITCH_PORT_SPEED_1000
;
511 link
->speed
= SWITCH_PORT_SPEED_UNKNOWN
;
516 #ifdef CONFIG_ETHERNET_PACKET_MANGLE
518 static struct sk_buff
*
519 ar8216_mangle_tx(struct net_device
*dev
, struct sk_buff
*skb
)
521 struct ar8xxx_priv
*priv
= dev
->phy_ptr
;
530 if (unlikely(skb_headroom(skb
) < 2)) {
531 if (pskb_expand_head(skb
, 2, 0, GFP_ATOMIC
) < 0)
535 buf
= skb_push(skb
, 2);
543 dev_kfree_skb_any(skb
);
548 ar8216_mangle_rx(struct net_device
*dev
, struct sk_buff
*skb
)
550 struct ar8xxx_priv
*priv
;
558 /* don't strip the header if vlan mode is disabled */
562 /* strip header, get vlan id */
566 /* check for vlan header presence */
567 if ((buf
[12 + 2] != 0x81) || (buf
[13 + 2] != 0x00))
572 /* no need to fix up packets coming from a tagged source */
573 if (priv
->vlan_tagged
& (1 << port
))
576 /* lookup port vid from local table, the switch passes an invalid vlan id */
577 vlan
= priv
->vlan_id
[priv
->pvid
[port
]];
580 buf
[14 + 2] |= vlan
>> 8;
581 buf
[15 + 2] = vlan
& 0xff;
587 ar8216_wait_bit(struct ar8xxx_priv
*priv
, int reg
, u32 mask
, u32 val
)
593 t
= ar8xxx_read(priv
, reg
);
594 if ((t
& mask
) == val
)
604 pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
605 (unsigned int) reg
, t
, mask
, val
);
610 ar8216_vtu_op(struct ar8xxx_priv
*priv
, u32 op
, u32 val
)
612 if (ar8216_wait_bit(priv
, AR8216_REG_VTU
, AR8216_VTU_ACTIVE
, 0))
614 if ((op
& AR8216_VTU_OP
) == AR8216_VTU_OP_LOAD
) {
615 val
&= AR8216_VTUDATA_MEMBER
;
616 val
|= AR8216_VTUDATA_VALID
;
617 ar8xxx_write(priv
, AR8216_REG_VTU_DATA
, val
);
619 op
|= AR8216_VTU_ACTIVE
;
620 ar8xxx_write(priv
, AR8216_REG_VTU
, op
);
624 ar8216_vtu_flush(struct ar8xxx_priv
*priv
)
626 ar8216_vtu_op(priv
, AR8216_VTU_OP_FLUSH
, 0);
630 ar8216_vtu_load_vlan(struct ar8xxx_priv
*priv
, u32 vid
, u32 port_mask
)
634 op
= AR8216_VTU_OP_LOAD
| (vid
<< AR8216_VTU_VID_S
);
635 ar8216_vtu_op(priv
, op
, port_mask
);
639 ar8216_atu_flush(struct ar8xxx_priv
*priv
)
643 ret
= ar8216_wait_bit(priv
, AR8216_REG_ATU_FUNC0
, AR8216_ATU_ACTIVE
, 0);
645 ar8xxx_write(priv
, AR8216_REG_ATU_FUNC0
, AR8216_ATU_OP_FLUSH
|
652 ar8216_atu_flush_port(struct ar8xxx_priv
*priv
, int port
)
657 ret
= ar8216_wait_bit(priv
, AR8216_REG_ATU_FUNC0
, AR8216_ATU_ACTIVE
, 0);
659 t
= (port
<< AR8216_ATU_PORT_NUM_S
) | AR8216_ATU_OP_FLUSH_PORT
;
660 t
|= AR8216_ATU_ACTIVE
;
661 ar8xxx_write(priv
, AR8216_REG_ATU_FUNC0
, t
);
668 ar8216_read_port_status(struct ar8xxx_priv
*priv
, int port
)
670 return ar8xxx_read(priv
, AR8216_REG_PORT_STATUS(port
));
674 __ar8216_setup_port(struct ar8xxx_priv
*priv
, int port
, u32 members
,
682 pvid
= priv
->vlan_id
[priv
->pvid
[port
]];
683 if (priv
->vlan_tagged
& (1 << port
))
684 egress
= AR8216_OUT_ADD_VLAN
;
686 egress
= AR8216_OUT_STRIP_VLAN
;
687 ingress
= AR8216_IN_SECURE
;
690 egress
= AR8216_OUT_KEEP
;
691 ingress
= AR8216_IN_PORT_ONLY
;
694 header
= ath_hdr_en
? AR8216_PORT_CTRL_HEADER
: 0;
696 ar8xxx_rmw(priv
, AR8216_REG_PORT_CTRL(port
),
697 AR8216_PORT_CTRL_LEARN
| AR8216_PORT_CTRL_VLAN_MODE
|
698 AR8216_PORT_CTRL_SINGLE_VLAN
| AR8216_PORT_CTRL_STATE
|
699 AR8216_PORT_CTRL_HEADER
| AR8216_PORT_CTRL_LEARN_LOCK
,
700 AR8216_PORT_CTRL_LEARN
| header
|
701 (egress
<< AR8216_PORT_CTRL_VLAN_MODE_S
) |
702 (AR8216_PORT_STATE_FORWARD
<< AR8216_PORT_CTRL_STATE_S
));
704 ar8xxx_rmw(priv
, AR8216_REG_PORT_VLAN(port
),
705 AR8216_PORT_VLAN_DEST_PORTS
| AR8216_PORT_VLAN_MODE
|
706 AR8216_PORT_VLAN_DEFAULT_ID
,
707 (members
<< AR8216_PORT_VLAN_DEST_PORTS_S
) |
708 (ingress
<< AR8216_PORT_VLAN_MODE_S
) |
709 (pvid
<< AR8216_PORT_VLAN_DEFAULT_ID_S
));
713 ar8216_setup_port(struct ar8xxx_priv
*priv
, int port
, u32 members
)
715 return __ar8216_setup_port(priv
, port
, members
,
716 chip_is_ar8216(priv
) && priv
->vlan
&&
717 port
== AR8216_PORT_CPU
);
721 ar8216_hw_init(struct ar8xxx_priv
*priv
)
723 if (priv
->initialized
)
726 ar8xxx_write(priv
, AR8216_REG_CTRL
, AR8216_CTRL_RESET
);
727 ar8xxx_reg_wait(priv
, AR8216_REG_CTRL
, AR8216_CTRL_RESET
, 0, 1000);
729 ar8xxx_phy_init(priv
);
731 priv
->initialized
= true;
736 ar8216_init_globals(struct ar8xxx_priv
*priv
)
738 /* standard atheros magic */
739 ar8xxx_write(priv
, 0x38, 0xc000050e);
741 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
742 AR8216_GCTRL_MTU
, 1518 + 8 + 2);
746 __ar8216_init_port(struct ar8xxx_priv
*priv
, int port
,
747 bool cpu_ge
, bool flow_en
)
749 /* Enable port learning and tx */
750 ar8xxx_write(priv
, AR8216_REG_PORT_CTRL(port
),
751 AR8216_PORT_CTRL_LEARN
|
752 (4 << AR8216_PORT_CTRL_STATE_S
));
754 ar8xxx_write(priv
, AR8216_REG_PORT_VLAN(port
), 0);
756 if (port
== AR8216_PORT_CPU
) {
757 ar8xxx_write(priv
, AR8216_REG_PORT_STATUS(port
),
758 AR8216_PORT_STATUS_LINK_UP
|
759 (cpu_ge
? AR8216_PORT_SPEED_1000M
: AR8216_PORT_SPEED_100M
) |
760 AR8216_PORT_STATUS_TXMAC
|
761 AR8216_PORT_STATUS_RXMAC
|
762 (flow_en
? AR8216_PORT_STATUS_RXFLOW
: 0) |
763 (flow_en
? AR8216_PORT_STATUS_TXFLOW
: 0) |
764 AR8216_PORT_STATUS_DUPLEX
);
766 ar8xxx_write(priv
, AR8216_REG_PORT_STATUS(port
),
767 AR8216_PORT_STATUS_LINK_AUTO
);
772 ar8216_init_port(struct ar8xxx_priv
*priv
, int port
)
774 __ar8216_init_port(priv
, port
, ar8xxx_has_gige(priv
),
775 chip_is_ar8316(priv
));
779 ar8216_wait_atu_ready(struct ar8xxx_priv
*priv
, u16 r2
, u16 r1
)
783 while (ar8xxx_mii_read32(priv
, r2
, r1
) & AR8216_ATU_ACTIVE
&& --timeout
) {
789 pr_err("ar8216: timeout waiting for atu to become ready\n");
792 static void ar8216_get_arl_entry(struct ar8xxx_priv
*priv
,
793 struct arl_entry
*a
, u32
*status
, enum arl_op op
)
795 struct mii_bus
*bus
= priv
->mii_bus
;
797 u16 r1_func0
, r1_func1
, r1_func2
;
798 u32 t
, val0
, val1
, val2
;
800 split_addr(AR8216_REG_ATU_FUNC0
, &r1_func0
, &r2
, &page
);
803 r1_func1
= (AR8216_REG_ATU_FUNC1
>> 1) & 0x1e;
804 r1_func2
= (AR8216_REG_ATU_FUNC2
>> 1) & 0x1e;
807 case AR8XXX_ARL_INITIALIZE
:
808 /* all ATU registers are on the same page
809 * therefore set page only once
811 bus
->write(bus
, 0x18, 0, page
);
812 wait_for_page_switch();
814 ar8216_wait_atu_ready(priv
, r2
, r1_func0
);
816 ar8xxx_mii_write32(priv
, r2
, r1_func0
, AR8216_ATU_OP_GET_NEXT
);
817 ar8xxx_mii_write32(priv
, r2
, r1_func1
, 0);
818 ar8xxx_mii_write32(priv
, r2
, r1_func2
, 0);
820 case AR8XXX_ARL_GET_NEXT
:
821 t
= ar8xxx_mii_read32(priv
, r2
, r1_func0
);
822 t
|= AR8216_ATU_ACTIVE
;
823 ar8xxx_mii_write32(priv
, r2
, r1_func0
, t
);
824 ar8216_wait_atu_ready(priv
, r2
, r1_func0
);
826 val0
= ar8xxx_mii_read32(priv
, r2
, r1_func0
);
827 val1
= ar8xxx_mii_read32(priv
, r2
, r1_func1
);
828 val2
= ar8xxx_mii_read32(priv
, r2
, r1_func2
);
830 *status
= (val2
& AR8216_ATU_STATUS
) >> AR8216_ATU_STATUS_S
;
834 a
->portmap
= (val2
& AR8216_ATU_PORTS
) >> AR8216_ATU_PORTS_S
;
835 a
->mac
[0] = (val0
& AR8216_ATU_ADDR5
) >> AR8216_ATU_ADDR5_S
;
836 a
->mac
[1] = (val0
& AR8216_ATU_ADDR4
) >> AR8216_ATU_ADDR4_S
;
837 a
->mac
[2] = (val1
& AR8216_ATU_ADDR3
) >> AR8216_ATU_ADDR3_S
;
838 a
->mac
[3] = (val1
& AR8216_ATU_ADDR2
) >> AR8216_ATU_ADDR2_S
;
839 a
->mac
[4] = (val1
& AR8216_ATU_ADDR1
) >> AR8216_ATU_ADDR1_S
;
840 a
->mac
[5] = (val1
& AR8216_ATU_ADDR0
) >> AR8216_ATU_ADDR0_S
;
846 ar8216_phy_read(struct ar8xxx_priv
*priv
, int addr
, int regnum
)
851 if (addr
>= AR8216_NUM_PORTS
)
853 t
= (regnum
<< AR8216_MDIO_CTRL_REG_ADDR_S
) |
854 (addr
<< AR8216_MDIO_CTRL_PHY_ADDR_S
) |
855 AR8216_MDIO_CTRL_MASTER_EN
|
856 AR8216_MDIO_CTRL_BUSY
|
857 AR8216_MDIO_CTRL_CMD_READ
;
859 ar8xxx_write(priv
, AR8216_REG_MDIO_CTRL
, t
);
860 err
= ar8xxx_reg_wait(priv
, AR8216_REG_MDIO_CTRL
,
861 AR8216_MDIO_CTRL_BUSY
, 0, 5);
863 val
= ar8xxx_read(priv
, AR8216_REG_MDIO_CTRL
);
865 return val
& AR8216_MDIO_CTRL_DATA_M
;
869 ar8216_phy_write(struct ar8xxx_priv
*priv
, int addr
, int regnum
, u16 val
)
874 if (addr
>= AR8216_NUM_PORTS
)
877 t
= (addr
<< AR8216_MDIO_CTRL_PHY_ADDR_S
) |
878 (regnum
<< AR8216_MDIO_CTRL_REG_ADDR_S
) |
879 AR8216_MDIO_CTRL_MASTER_EN
|
880 AR8216_MDIO_CTRL_BUSY
|
881 AR8216_MDIO_CTRL_CMD_WRITE
|
884 ar8xxx_write(priv
, AR8216_REG_MDIO_CTRL
, t
);
885 ret
= ar8xxx_reg_wait(priv
, AR8216_REG_MDIO_CTRL
,
886 AR8216_MDIO_CTRL_BUSY
, 0, 5);
892 ar8229_hw_init(struct ar8xxx_priv
*priv
)
894 phy_interface_t phy_if_mode
;
896 if (priv
->initialized
)
899 ar8xxx_write(priv
, AR8216_REG_CTRL
, AR8216_CTRL_RESET
);
900 ar8xxx_reg_wait(priv
, AR8216_REG_CTRL
, AR8216_CTRL_RESET
, 0, 1000);
902 of_get_phy_mode(priv
->pdev
->of_node
, &phy_if_mode
);
904 if (phy_if_mode
== PHY_INTERFACE_MODE_GMII
) {
905 ar8xxx_write(priv
, AR8229_REG_OPER_MODE0
,
906 AR8229_OPER_MODE0_MAC_GMII_EN
);
907 } else if (phy_if_mode
== PHY_INTERFACE_MODE_MII
) {
908 ar8xxx_write(priv
, AR8229_REG_OPER_MODE0
,
909 AR8229_OPER_MODE0_PHY_MII_EN
);
911 pr_err("ar8229: unsupported mii mode\n");
915 if (priv
->port4_phy
) {
916 ar8xxx_write(priv
, AR8229_REG_OPER_MODE1
,
917 AR8229_REG_OPER_MODE1_PHY4_MII_EN
);
918 /* disable port5 to prevent mii conflict */
919 ar8xxx_write(priv
, AR8216_REG_PORT_STATUS(5), 0);
922 ar8xxx_phy_init(priv
);
924 priv
->initialized
= true;
929 ar8229_init_globals(struct ar8xxx_priv
*priv
)
932 /* Enable CPU port, and disable mirror port */
933 ar8xxx_write(priv
, AR8216_REG_GLOBAL_CPUPORT
,
934 AR8216_GLOBAL_CPUPORT_EN
|
935 (15 << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S
));
937 /* Setup TAG priority mapping */
938 ar8xxx_write(priv
, AR8216_REG_TAG_PRIORITY
, 0xfa50);
940 /* Enable aging, MAC replacing */
941 ar8xxx_write(priv
, AR8216_REG_ATU_CTRL
,
942 0x2b /* 5 min age time */ |
943 AR8216_ATU_CTRL_AGE_EN
|
944 AR8216_ATU_CTRL_LEARN_CHANGE
);
946 /* Enable ARP frame acknowledge */
947 ar8xxx_reg_set(priv
, AR8229_REG_QM_CTRL
,
948 AR8229_QM_CTRL_ARP_EN
);
951 * Enable Broadcast/unknown multicast and unicast frames
952 * transmitted to the CPU port.
954 ar8xxx_reg_set(priv
, AR8216_REG_FLOOD_MASK
,
955 AR8229_FLOOD_MASK_BC_DP(0) |
956 AR8229_FLOOD_MASK_MC_DP(0) |
957 AR8229_FLOOD_MASK_UC_DP(0));
960 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
961 AR8236_GCTRL_MTU
, AR8236_GCTRL_MTU
);
963 /* Enable MIB counters */
964 ar8xxx_reg_set(priv
, AR8216_REG_MIB_FUNC
,
967 /* setup Service TAG */
968 ar8xxx_rmw(priv
, AR8216_REG_SERVICE_TAG
, AR8216_SERVICE_TAG_M
, 0);
972 ar8229_init_port(struct ar8xxx_priv
*priv
, int port
)
974 __ar8216_init_port(priv
, port
, true, true);
979 ar7240sw_hw_init(struct ar8xxx_priv
*priv
)
981 if (priv
->initialized
)
984 ar8xxx_write(priv
, AR8216_REG_CTRL
, AR8216_CTRL_RESET
);
985 ar8xxx_reg_wait(priv
, AR8216_REG_CTRL
, AR8216_CTRL_RESET
, 0, 1000);
988 /* disable port5 to prevent mii conflict */
989 ar8xxx_write(priv
, AR8216_REG_PORT_STATUS(5), 0);
991 ar8xxx_phy_init(priv
);
993 priv
->initialized
= true;
998 ar7240sw_init_globals(struct ar8xxx_priv
*priv
)
1001 /* Enable CPU port, and disable mirror port */
1002 ar8xxx_write(priv
, AR8216_REG_GLOBAL_CPUPORT
,
1003 AR8216_GLOBAL_CPUPORT_EN
|
1004 (15 << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S
));
1006 /* Setup TAG priority mapping */
1007 ar8xxx_write(priv
, AR8216_REG_TAG_PRIORITY
, 0xfa50);
1009 /* Enable ARP frame acknowledge, aging, MAC replacing */
1010 ar8xxx_write(priv
, AR8216_REG_ATU_CTRL
,
1011 AR8216_ATU_CTRL_RESERVED
|
1012 0x2b /* 5 min age time */ |
1013 AR8216_ATU_CTRL_AGE_EN
|
1014 AR8216_ATU_CTRL_ARP_EN
|
1015 AR8216_ATU_CTRL_LEARN_CHANGE
);
1017 /* Enable Broadcast frames transmitted to the CPU */
1018 ar8xxx_reg_set(priv
, AR8216_REG_FLOOD_MASK
,
1019 AR8216_FM_CPU_BROADCAST_EN
);
1022 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
1026 /* setup Service TAG */
1027 ar8xxx_rmw(priv
, AR8216_REG_SERVICE_TAG
, AR8216_SERVICE_TAG_M
, 0);
1031 ar7240sw_setup_port(struct ar8xxx_priv
*priv
, int port
, u32 members
)
1033 return __ar8216_setup_port(priv
, port
, members
, false);
1037 ar8236_setup_port(struct ar8xxx_priv
*priv
, int port
, u32 members
)
1039 u32 egress
, ingress
;
1043 pvid
= priv
->vlan_id
[priv
->pvid
[port
]];
1044 if (priv
->vlan_tagged
& (1 << port
))
1045 egress
= AR8216_OUT_ADD_VLAN
;
1047 egress
= AR8216_OUT_STRIP_VLAN
;
1048 ingress
= AR8216_IN_SECURE
;
1051 egress
= AR8216_OUT_KEEP
;
1052 ingress
= AR8216_IN_PORT_ONLY
;
1055 ar8xxx_rmw(priv
, AR8216_REG_PORT_CTRL(port
),
1056 AR8216_PORT_CTRL_LEARN
| AR8216_PORT_CTRL_VLAN_MODE
|
1057 AR8216_PORT_CTRL_SINGLE_VLAN
| AR8216_PORT_CTRL_STATE
|
1058 AR8216_PORT_CTRL_HEADER
| AR8216_PORT_CTRL_LEARN_LOCK
,
1059 AR8216_PORT_CTRL_LEARN
|
1060 (egress
<< AR8216_PORT_CTRL_VLAN_MODE_S
) |
1061 (AR8216_PORT_STATE_FORWARD
<< AR8216_PORT_CTRL_STATE_S
));
1063 ar8xxx_rmw(priv
, AR8236_REG_PORT_VLAN(port
),
1064 AR8236_PORT_VLAN_DEFAULT_ID
,
1065 (pvid
<< AR8236_PORT_VLAN_DEFAULT_ID_S
));
1067 ar8xxx_rmw(priv
, AR8236_REG_PORT_VLAN2(port
),
1068 AR8236_PORT_VLAN2_VLAN_MODE
|
1069 AR8236_PORT_VLAN2_MEMBER
,
1070 (ingress
<< AR8236_PORT_VLAN2_VLAN_MODE_S
) |
1071 (members
<< AR8236_PORT_VLAN2_MEMBER_S
));
1075 ar8236_init_globals(struct ar8xxx_priv
*priv
)
1077 /* enable jumbo frames */
1078 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
1079 AR8316_GCTRL_MTU
, 9018 + 8 + 2);
1081 /* enable cpu port to receive arp frames */
1082 ar8xxx_reg_set(priv
, AR8216_REG_ATU_CTRL
,
1083 AR8236_ATU_CTRL_RES
);
1086 * Enable Broadcast/unknown multicast and unicast frames
1087 * transmitted to the CPU port.
1089 ar8xxx_reg_set(priv
, AR8216_REG_FLOOD_MASK
,
1090 AR8229_FLOOD_MASK_BC_DP(0) |
1091 AR8229_FLOOD_MASK_MC_DP(0) |
1092 AR8229_FLOOD_MASK_UC_DP(0));
1094 /* Enable MIB counters */
1095 ar8xxx_rmw(priv
, AR8216_REG_MIB_FUNC
, AR8216_MIB_FUNC
| AR8236_MIB_EN
,
1096 (AR8216_MIB_FUNC_NO_OP
<< AR8216_MIB_FUNC_S
) |
1101 ar8316_hw_init(struct ar8xxx_priv
*priv
)
1105 val
= ar8xxx_read(priv
, AR8316_REG_POSTRIP
);
1107 if (priv
->phy
->interface
== PHY_INTERFACE_MODE_RGMII
) {
1108 if (priv
->port4_phy
) {
1109 /* value taken from Ubiquiti RouterStation Pro */
1110 newval
= 0x81461bea;
1111 pr_info("ar8316: Using port 4 as PHY\n");
1113 newval
= 0x01261be2;
1114 pr_info("ar8316: Using port 4 as switch port\n");
1116 } else if (priv
->phy
->interface
== PHY_INTERFACE_MODE_GMII
) {
1117 /* value taken from AVM Fritz!Box 7390 sources */
1118 newval
= 0x010e5b71;
1120 /* no known value for phy interface */
1121 pr_err("ar8316: unsupported mii mode: %d.\n",
1122 priv
->phy
->interface
);
1129 ar8xxx_write(priv
, AR8316_REG_POSTRIP
, newval
);
1131 if (priv
->port4_phy
&&
1132 priv
->phy
->interface
== PHY_INTERFACE_MODE_RGMII
) {
1133 /* work around for phy4 rgmii mode */
1134 ar8xxx_phy_dbg_write(priv
, 4, 0x12, 0x480c);
1136 ar8xxx_phy_dbg_write(priv
, 4, 0x0, 0x824e);
1138 ar8xxx_phy_dbg_write(priv
, 4, 0x5, 0x3d47);
1142 ar8xxx_phy_init(priv
);
1145 priv
->initialized
= true;
1150 ar8316_init_globals(struct ar8xxx_priv
*priv
)
1152 /* standard atheros magic */
1153 ar8xxx_write(priv
, 0x38, 0xc000050e);
1155 /* enable cpu port to receive multicast and broadcast frames */
1156 ar8xxx_write(priv
, AR8216_REG_FLOOD_MASK
, 0x003f003f);
1158 /* enable jumbo frames */
1159 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
1160 AR8316_GCTRL_MTU
, 9018 + 8 + 2);
1162 /* Enable MIB counters */
1163 ar8xxx_rmw(priv
, AR8216_REG_MIB_FUNC
, AR8216_MIB_FUNC
| AR8236_MIB_EN
,
1164 (AR8216_MIB_FUNC_NO_OP
<< AR8216_MIB_FUNC_S
) |
1169 ar8xxx_sw_set_vlan(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1170 struct switch_val
*val
)
1172 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1173 priv
->vlan
= !!val
->value
.i
;
1178 ar8xxx_sw_get_vlan(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1179 struct switch_val
*val
)
1181 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1182 val
->value
.i
= priv
->vlan
;
1188 ar8xxx_sw_set_pvid(struct switch_dev
*dev
, int port
, int vlan
)
1190 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1192 /* make sure no invalid PVIDs get set */
1194 if (vlan
< 0 || vlan
>= dev
->vlans
||
1195 port
< 0 || port
>= AR8X16_MAX_PORTS
)
1198 priv
->pvid
[port
] = vlan
;
1203 ar8xxx_sw_get_pvid(struct switch_dev
*dev
, int port
, int *vlan
)
1205 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1207 if (port
< 0 || port
>= AR8X16_MAX_PORTS
)
1210 *vlan
= priv
->pvid
[port
];
1215 ar8xxx_sw_set_vid(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1216 struct switch_val
*val
)
1218 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1220 if (val
->port_vlan
>= dev
->vlans
)
1223 priv
->vlan_id
[val
->port_vlan
] = val
->value
.i
;
1228 ar8xxx_sw_get_vid(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1229 struct switch_val
*val
)
1231 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1232 val
->value
.i
= priv
->vlan_id
[val
->port_vlan
];
1237 ar8xxx_sw_get_port_link(struct switch_dev
*dev
, int port
,
1238 struct switch_port_link
*link
)
1240 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1242 ar8216_read_port_link(priv
, port
, link
);
1247 ar8xxx_sw_get_ports(struct switch_dev
*dev
, struct switch_val
*val
)
1249 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1253 if (val
->port_vlan
>= dev
->vlans
)
1256 ports
= priv
->vlan_table
[val
->port_vlan
];
1258 for (i
= 0; i
< dev
->ports
; i
++) {
1259 struct switch_port
*p
;
1261 if (!(ports
& (1 << i
)))
1264 p
= &val
->value
.ports
[val
->len
++];
1266 if (priv
->vlan_tagged
& (1 << i
))
1267 p
->flags
= (1 << SWITCH_PORT_FLAG_TAGGED
);
1275 ar8xxx_sw_set_ports(struct switch_dev
*dev
, struct switch_val
*val
)
1277 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1278 u8
*vt
= &priv
->vlan_table
[val
->port_vlan
];
1282 for (i
= 0; i
< val
->len
; i
++) {
1283 struct switch_port
*p
= &val
->value
.ports
[i
];
1285 if (p
->flags
& (1 << SWITCH_PORT_FLAG_TAGGED
)) {
1286 priv
->vlan_tagged
|= (1 << p
->id
);
1288 priv
->vlan_tagged
&= ~(1 << p
->id
);
1289 priv
->pvid
[p
->id
] = val
->port_vlan
;
1291 /* make sure that an untagged port does not
1292 * appear in other vlans */
1293 for (j
= 0; j
< dev
->vlans
; j
++) {
1294 if (j
== val
->port_vlan
)
1296 priv
->vlan_table
[j
] &= ~(1 << p
->id
);
1306 ar8216_set_mirror_regs(struct ar8xxx_priv
*priv
)
1310 /* reset all mirror registers */
1311 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CPUPORT
,
1312 AR8216_GLOBAL_CPUPORT_MIRROR_PORT
,
1313 (0xF << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S
));
1314 for (port
= 0; port
< AR8216_NUM_PORTS
; port
++) {
1315 ar8xxx_reg_clear(priv
, AR8216_REG_PORT_CTRL(port
),
1316 AR8216_PORT_CTRL_MIRROR_RX
);
1318 ar8xxx_reg_clear(priv
, AR8216_REG_PORT_CTRL(port
),
1319 AR8216_PORT_CTRL_MIRROR_TX
);
1322 /* now enable mirroring if necessary */
1323 if (priv
->source_port
>= AR8216_NUM_PORTS
||
1324 priv
->monitor_port
>= AR8216_NUM_PORTS
||
1325 priv
->source_port
== priv
->monitor_port
) {
1329 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CPUPORT
,
1330 AR8216_GLOBAL_CPUPORT_MIRROR_PORT
,
1331 (priv
->monitor_port
<< AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S
));
1333 if (priv
->mirror_rx
)
1334 ar8xxx_reg_set(priv
, AR8216_REG_PORT_CTRL(priv
->source_port
),
1335 AR8216_PORT_CTRL_MIRROR_RX
);
1337 if (priv
->mirror_tx
)
1338 ar8xxx_reg_set(priv
, AR8216_REG_PORT_CTRL(priv
->source_port
),
1339 AR8216_PORT_CTRL_MIRROR_TX
);
1343 ar8xxx_age_time_val(int age_time
)
1345 return (age_time
+ AR8XXX_REG_ARL_CTRL_AGE_TIME_SECS
/ 2) /
1346 AR8XXX_REG_ARL_CTRL_AGE_TIME_SECS
;
1350 ar8xxx_set_age_time(struct ar8xxx_priv
*priv
, int reg
)
1352 u32 age_time
= ar8xxx_age_time_val(priv
->arl_age_time
);
1353 ar8xxx_rmw(priv
, reg
, AR8216_ATU_CTRL_AGE_TIME
, age_time
<< AR8216_ATU_CTRL_AGE_TIME_S
);
1357 ar8xxx_sw_hw_apply(struct switch_dev
*dev
)
1359 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1360 const struct ar8xxx_chip
*chip
= priv
->chip
;
1361 u8 portmask
[AR8X16_MAX_PORTS
];
1364 mutex_lock(&priv
->reg_mutex
);
1365 /* flush all vlan translation unit entries */
1366 priv
->chip
->vtu_flush(priv
);
1368 memset(portmask
, 0, sizeof(portmask
));
1370 /* calculate the port destination masks and load vlans
1371 * into the vlan translation unit */
1372 for (j
= 0; j
< dev
->vlans
; j
++) {
1373 u8 vp
= priv
->vlan_table
[j
];
1378 for (i
= 0; i
< dev
->ports
; i
++) {
1381 portmask
[i
] |= vp
& ~mask
;
1384 chip
->vtu_load_vlan(priv
, priv
->vlan_id
[j
],
1385 priv
->vlan_table
[j
]);
1389 * isolate all ports, but connect them to the cpu port */
1390 for (i
= 0; i
< dev
->ports
; i
++) {
1391 if (i
== AR8216_PORT_CPU
)
1394 portmask
[i
] = 1 << AR8216_PORT_CPU
;
1395 portmask
[AR8216_PORT_CPU
] |= (1 << i
);
1399 /* update the port destination mask registers and tag settings */
1400 for (i
= 0; i
< dev
->ports
; i
++) {
1401 chip
->setup_port(priv
, i
, portmask
[i
]);
1404 chip
->set_mirror_regs(priv
);
1407 if (chip
->reg_arl_ctrl
)
1408 ar8xxx_set_age_time(priv
, chip
->reg_arl_ctrl
);
1410 mutex_unlock(&priv
->reg_mutex
);
1415 ar8xxx_sw_reset_switch(struct switch_dev
*dev
)
1417 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1418 const struct ar8xxx_chip
*chip
= priv
->chip
;
1421 mutex_lock(&priv
->reg_mutex
);
1422 memset(&priv
->vlan
, 0, sizeof(struct ar8xxx_priv
) -
1423 offsetof(struct ar8xxx_priv
, vlan
));
1425 for (i
= 0; i
< dev
->vlans
; i
++)
1426 priv
->vlan_id
[i
] = i
;
1428 /* Configure all ports */
1429 for (i
= 0; i
< dev
->ports
; i
++)
1430 chip
->init_port(priv
, i
);
1432 priv
->mirror_rx
= false;
1433 priv
->mirror_tx
= false;
1434 priv
->source_port
= 0;
1435 priv
->monitor_port
= 0;
1436 priv
->arl_age_time
= AR8XXX_DEFAULT_ARL_AGE_TIME
;
1438 chip
->init_globals(priv
);
1439 chip
->atu_flush(priv
);
1441 mutex_unlock(&priv
->reg_mutex
);
1443 return chip
->sw_hw_apply(dev
);
1447 ar8xxx_sw_set_reset_mibs(struct switch_dev
*dev
,
1448 const struct switch_attr
*attr
,
1449 struct switch_val
*val
)
1451 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1455 if (!ar8xxx_has_mib_counters(priv
))
1458 mutex_lock(&priv
->mib_lock
);
1460 len
= priv
->dev
.ports
* priv
->chip
->num_mibs
*
1461 sizeof(*priv
->mib_stats
);
1462 memset(priv
->mib_stats
, '\0', len
);
1463 ret
= ar8xxx_mib_flush(priv
);
1470 mutex_unlock(&priv
->mib_lock
);
1475 ar8xxx_sw_set_mib_poll_interval(struct switch_dev
*dev
,
1476 const struct switch_attr
*attr
,
1477 struct switch_val
*val
)
1479 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1481 if (!ar8xxx_has_mib_counters(priv
))
1484 ar8xxx_mib_stop(priv
);
1485 priv
->mib_poll_interval
= val
->value
.i
;
1486 ar8xxx_mib_start(priv
);
1492 ar8xxx_sw_get_mib_poll_interval(struct switch_dev
*dev
,
1493 const struct switch_attr
*attr
,
1494 struct switch_val
*val
)
1496 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1498 if (!ar8xxx_has_mib_counters(priv
))
1500 val
->value
.i
= priv
->mib_poll_interval
;
1505 ar8xxx_sw_set_mib_type(struct switch_dev
*dev
,
1506 const struct switch_attr
*attr
,
1507 struct switch_val
*val
)
1509 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1511 if (!ar8xxx_has_mib_counters(priv
))
1513 priv
->mib_type
= val
->value
.i
;
1518 ar8xxx_sw_get_mib_type(struct switch_dev
*dev
,
1519 const struct switch_attr
*attr
,
1520 struct switch_val
*val
)
1522 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1524 if (!ar8xxx_has_mib_counters(priv
))
1526 val
->value
.i
= priv
->mib_type
;
1531 ar8xxx_sw_set_mirror_rx_enable(struct switch_dev
*dev
,
1532 const struct switch_attr
*attr
,
1533 struct switch_val
*val
)
1535 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1537 mutex_lock(&priv
->reg_mutex
);
1538 priv
->mirror_rx
= !!val
->value
.i
;
1539 priv
->chip
->set_mirror_regs(priv
);
1540 mutex_unlock(&priv
->reg_mutex
);
1546 ar8xxx_sw_get_mirror_rx_enable(struct switch_dev
*dev
,
1547 const struct switch_attr
*attr
,
1548 struct switch_val
*val
)
1550 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1551 val
->value
.i
= priv
->mirror_rx
;
1556 ar8xxx_sw_set_mirror_tx_enable(struct switch_dev
*dev
,
1557 const struct switch_attr
*attr
,
1558 struct switch_val
*val
)
1560 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1562 mutex_lock(&priv
->reg_mutex
);
1563 priv
->mirror_tx
= !!val
->value
.i
;
1564 priv
->chip
->set_mirror_regs(priv
);
1565 mutex_unlock(&priv
->reg_mutex
);
1571 ar8xxx_sw_get_mirror_tx_enable(struct switch_dev
*dev
,
1572 const struct switch_attr
*attr
,
1573 struct switch_val
*val
)
1575 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1576 val
->value
.i
= priv
->mirror_tx
;
1581 ar8xxx_sw_set_mirror_monitor_port(struct switch_dev
*dev
,
1582 const struct switch_attr
*attr
,
1583 struct switch_val
*val
)
1585 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1587 mutex_lock(&priv
->reg_mutex
);
1588 priv
->monitor_port
= val
->value
.i
;
1589 priv
->chip
->set_mirror_regs(priv
);
1590 mutex_unlock(&priv
->reg_mutex
);
1596 ar8xxx_sw_get_mirror_monitor_port(struct switch_dev
*dev
,
1597 const struct switch_attr
*attr
,
1598 struct switch_val
*val
)
1600 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1601 val
->value
.i
= priv
->monitor_port
;
1606 ar8xxx_sw_set_mirror_source_port(struct switch_dev
*dev
,
1607 const struct switch_attr
*attr
,
1608 struct switch_val
*val
)
1610 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1612 mutex_lock(&priv
->reg_mutex
);
1613 priv
->source_port
= val
->value
.i
;
1614 priv
->chip
->set_mirror_regs(priv
);
1615 mutex_unlock(&priv
->reg_mutex
);
1621 ar8xxx_sw_get_mirror_source_port(struct switch_dev
*dev
,
1622 const struct switch_attr
*attr
,
1623 struct switch_val
*val
)
1625 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1626 val
->value
.i
= priv
->source_port
;
1631 ar8xxx_sw_set_port_reset_mib(struct switch_dev
*dev
,
1632 const struct switch_attr
*attr
,
1633 struct switch_val
*val
)
1635 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1639 if (!ar8xxx_has_mib_counters(priv
))
1642 port
= val
->port_vlan
;
1643 if (port
>= dev
->ports
)
1646 mutex_lock(&priv
->mib_lock
);
1647 ret
= ar8xxx_mib_capture(priv
);
1651 ar8xxx_mib_fetch_port_stat(priv
, port
, true);
1656 mutex_unlock(&priv
->mib_lock
);
1661 ar8xxx_byte_to_str(char *buf
, int len
, u64 byte
)
1666 if (byte
>= 0x40000000) { /* 1 GiB */
1667 b
= byte
* 10 / 0x40000000;
1669 } else if (byte
>= 0x100000) { /* 1 MiB */
1670 b
= byte
* 10 / 0x100000;
1672 } else if (byte
>= 0x400) { /* 1 KiB */
1673 b
= byte
* 10 / 0x400;
1679 if (strcmp(unit
, "Byte"))
1680 snprintf(buf
, len
, "%lu.%lu %s", b
/ 10, b
% 10, unit
);
1682 snprintf(buf
, len
, "%lu %s", b
, unit
);
1686 ar8xxx_sw_get_port_mib(struct switch_dev
*dev
,
1687 const struct switch_attr
*attr
,
1688 struct switch_val
*val
)
1690 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1691 const struct ar8xxx_chip
*chip
= priv
->chip
;
1692 u64
*mib_stats
, mib_data
;
1695 char *buf
= priv
->buf
;
1697 const char *mib_name
;
1699 bool mib_stats_empty
= true;
1701 if (!ar8xxx_has_mib_counters(priv
) || !priv
->mib_poll_interval
)
1704 port
= val
->port_vlan
;
1705 if (port
>= dev
->ports
)
1708 mutex_lock(&priv
->mib_lock
);
1709 ret
= ar8xxx_mib_capture(priv
);
1713 ar8xxx_mib_fetch_port_stat(priv
, port
, false);
1715 len
+= snprintf(buf
+ len
, sizeof(priv
->buf
) - len
,
1718 mib_stats
= &priv
->mib_stats
[port
* chip
->num_mibs
];
1719 for (i
= 0; i
< chip
->num_mibs
; i
++) {
1720 if (chip
->mib_decs
[i
].type
> priv
->mib_type
)
1722 mib_name
= chip
->mib_decs
[i
].name
;
1723 mib_data
= mib_stats
[i
];
1724 len
+= snprintf(buf
+ len
, sizeof(priv
->buf
) - len
,
1725 "%-12s: %llu\n", mib_name
, mib_data
);
1726 if ((!strcmp(mib_name
, "TxByte") ||
1727 !strcmp(mib_name
, "RxGoodByte")) &&
1729 ar8xxx_byte_to_str(buf1
, sizeof(buf1
), mib_data
);
1730 --len
; /* discard newline at the end of buf */
1731 len
+= snprintf(buf
+ len
, sizeof(priv
->buf
) - len
,
1734 if (mib_stats_empty
&& mib_data
)
1735 mib_stats_empty
= false;
1738 if (mib_stats_empty
)
1739 len
= snprintf(buf
, sizeof(priv
->buf
), "No MIB data");
1747 mutex_unlock(&priv
->mib_lock
);
1752 ar8xxx_sw_set_arl_age_time(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1753 struct switch_val
*val
)
1755 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1756 int age_time
= val
->value
.i
;
1762 age_time_val
= ar8xxx_age_time_val(age_time
);
1763 if (age_time_val
== 0 || age_time_val
> 0xffff)
1766 priv
->arl_age_time
= age_time
;
1771 ar8xxx_sw_get_arl_age_time(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1772 struct switch_val
*val
)
1774 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1775 val
->value
.i
= priv
->arl_age_time
;
1780 ar8xxx_sw_get_arl_table(struct switch_dev
*dev
,
1781 const struct switch_attr
*attr
,
1782 struct switch_val
*val
)
1784 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1785 struct mii_bus
*bus
= priv
->mii_bus
;
1786 const struct ar8xxx_chip
*chip
= priv
->chip
;
1787 char *buf
= priv
->arl_buf
;
1788 int i
, j
, k
, len
= 0;
1789 struct arl_entry
*a
, *a1
;
1792 if (!chip
->get_arl_entry
)
1795 mutex_lock(&priv
->reg_mutex
);
1796 mutex_lock(&bus
->mdio_lock
);
1798 chip
->get_arl_entry(priv
, NULL
, NULL
, AR8XXX_ARL_INITIALIZE
);
1800 for(i
= 0; i
< AR8XXX_NUM_ARL_RECORDS
; ++i
) {
1801 a
= &priv
->arl_table
[i
];
1803 chip
->get_arl_entry(priv
, a
, &status
, AR8XXX_ARL_GET_NEXT
);
1809 * ARL table can include multiple valid entries
1810 * per MAC, just with differing status codes
1812 for (j
= 0; j
< i
; ++j
) {
1813 a1
= &priv
->arl_table
[j
];
1814 if (!memcmp(a
->mac
, a1
->mac
, sizeof(a
->mac
))) {
1815 /* ignore ports already seen in former entry */
1816 a
->portmap
&= ~a1
->portmap
;
1823 mutex_unlock(&bus
->mdio_lock
);
1825 len
+= snprintf(buf
+ len
, sizeof(priv
->arl_buf
) - len
,
1826 "address resolution table\n");
1828 if (i
== AR8XXX_NUM_ARL_RECORDS
)
1829 len
+= snprintf(buf
+ len
, sizeof(priv
->arl_buf
) - len
,
1830 "Too many entries found, displaying the first %d only!\n",
1831 AR8XXX_NUM_ARL_RECORDS
);
1833 for (j
= 0; j
< priv
->dev
.ports
; ++j
) {
1834 for (k
= 0; k
< i
; ++k
) {
1835 a
= &priv
->arl_table
[k
];
1836 if (!(a
->portmap
& BIT(j
)))
1838 len
+= snprintf(buf
+ len
, sizeof(priv
->arl_buf
) - len
,
1839 "Port %d: MAC %02x:%02x:%02x:%02x:%02x:%02x\n",
1841 a
->mac
[5], a
->mac
[4], a
->mac
[3],
1842 a
->mac
[2], a
->mac
[1], a
->mac
[0]);
1849 mutex_unlock(&priv
->reg_mutex
);
1855 ar8xxx_sw_set_flush_arl_table(struct switch_dev
*dev
,
1856 const struct switch_attr
*attr
,
1857 struct switch_val
*val
)
1859 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1862 mutex_lock(&priv
->reg_mutex
);
1863 ret
= priv
->chip
->atu_flush(priv
);
1864 mutex_unlock(&priv
->reg_mutex
);
1870 ar8xxx_sw_set_flush_port_arl_table(struct switch_dev
*dev
,
1871 const struct switch_attr
*attr
,
1872 struct switch_val
*val
)
1874 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1877 port
= val
->port_vlan
;
1878 if (port
>= dev
->ports
)
1881 mutex_lock(&priv
->reg_mutex
);
1882 ret
= priv
->chip
->atu_flush_port(priv
, port
);
1883 mutex_unlock(&priv
->reg_mutex
);
1889 ar8xxx_sw_get_port_stats(struct switch_dev
*dev
, int port
,
1890 struct switch_port_stats
*stats
)
1892 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1895 if (!ar8xxx_has_mib_counters(priv
) || !priv
->mib_poll_interval
)
1898 if (!(priv
->chip
->mib_rxb_id
|| priv
->chip
->mib_txb_id
))
1901 if (port
>= dev
->ports
)
1904 mutex_lock(&priv
->mib_lock
);
1906 mib_stats
= &priv
->mib_stats
[port
* priv
->chip
->num_mibs
];
1908 stats
->tx_bytes
= mib_stats
[priv
->chip
->mib_txb_id
];
1909 stats
->rx_bytes
= mib_stats
[priv
->chip
->mib_rxb_id
];
1911 mutex_unlock(&priv
->mib_lock
);
1916 ar8xxx_phy_read(struct mii_bus
*bus
, int phy_addr
, int reg_addr
)
1918 struct ar8xxx_priv
*priv
= bus
->priv
;
1919 return priv
->chip
->phy_read(priv
, phy_addr
, reg_addr
);
1923 ar8xxx_phy_write(struct mii_bus
*bus
, int phy_addr
, int reg_addr
,
1926 struct ar8xxx_priv
*priv
= bus
->priv
;
1927 return priv
->chip
->phy_write(priv
, phy_addr
, reg_addr
, reg_val
);
1930 static const struct switch_attr ar8xxx_sw_attr_globals
[] = {
1932 .type
= SWITCH_TYPE_INT
,
1933 .name
= "enable_vlan",
1934 .description
= "Enable VLAN mode",
1935 .set
= ar8xxx_sw_set_vlan
,
1936 .get
= ar8xxx_sw_get_vlan
,
1940 .type
= SWITCH_TYPE_NOVAL
,
1941 .name
= "reset_mibs",
1942 .description
= "Reset all MIB counters",
1943 .set
= ar8xxx_sw_set_reset_mibs
,
1946 .type
= SWITCH_TYPE_INT
,
1947 .name
= "ar8xxx_mib_poll_interval",
1948 .description
= "MIB polling interval in msecs (0 to disable)",
1949 .set
= ar8xxx_sw_set_mib_poll_interval
,
1950 .get
= ar8xxx_sw_get_mib_poll_interval
1953 .type
= SWITCH_TYPE_INT
,
1954 .name
= "ar8xxx_mib_type",
1955 .description
= "MIB type (0=basic 1=extended)",
1956 .set
= ar8xxx_sw_set_mib_type
,
1957 .get
= ar8xxx_sw_get_mib_type
1960 .type
= SWITCH_TYPE_INT
,
1961 .name
= "enable_mirror_rx",
1962 .description
= "Enable mirroring of RX packets",
1963 .set
= ar8xxx_sw_set_mirror_rx_enable
,
1964 .get
= ar8xxx_sw_get_mirror_rx_enable
,
1968 .type
= SWITCH_TYPE_INT
,
1969 .name
= "enable_mirror_tx",
1970 .description
= "Enable mirroring of TX packets",
1971 .set
= ar8xxx_sw_set_mirror_tx_enable
,
1972 .get
= ar8xxx_sw_get_mirror_tx_enable
,
1976 .type
= SWITCH_TYPE_INT
,
1977 .name
= "mirror_monitor_port",
1978 .description
= "Mirror monitor port",
1979 .set
= ar8xxx_sw_set_mirror_monitor_port
,
1980 .get
= ar8xxx_sw_get_mirror_monitor_port
,
1981 .max
= AR8216_NUM_PORTS
- 1
1984 .type
= SWITCH_TYPE_INT
,
1985 .name
= "mirror_source_port",
1986 .description
= "Mirror source port",
1987 .set
= ar8xxx_sw_set_mirror_source_port
,
1988 .get
= ar8xxx_sw_get_mirror_source_port
,
1989 .max
= AR8216_NUM_PORTS
- 1
1992 .type
= SWITCH_TYPE_STRING
,
1993 .name
= "arl_table",
1994 .description
= "Get ARL table",
1996 .get
= ar8xxx_sw_get_arl_table
,
1999 .type
= SWITCH_TYPE_NOVAL
,
2000 .name
= "flush_arl_table",
2001 .description
= "Flush ARL table",
2002 .set
= ar8xxx_sw_set_flush_arl_table
,
2006 const struct switch_attr ar8xxx_sw_attr_port
[] = {
2008 .type
= SWITCH_TYPE_NOVAL
,
2009 .name
= "reset_mib",
2010 .description
= "Reset single port MIB counters",
2011 .set
= ar8xxx_sw_set_port_reset_mib
,
2014 .type
= SWITCH_TYPE_STRING
,
2016 .description
= "Get port's MIB counters",
2018 .get
= ar8xxx_sw_get_port_mib
,
2021 .type
= SWITCH_TYPE_NOVAL
,
2022 .name
= "flush_arl_table",
2023 .description
= "Flush port's ARL table entries",
2024 .set
= ar8xxx_sw_set_flush_port_arl_table
,
2028 const struct switch_attr ar8xxx_sw_attr_vlan
[1] = {
2030 .type
= SWITCH_TYPE_INT
,
2032 .description
= "VLAN ID (0-4094)",
2033 .set
= ar8xxx_sw_set_vid
,
2034 .get
= ar8xxx_sw_get_vid
,
2039 static const struct switch_dev_ops ar8xxx_sw_ops
= {
2041 .attr
= ar8xxx_sw_attr_globals
,
2042 .n_attr
= ARRAY_SIZE(ar8xxx_sw_attr_globals
),
2045 .attr
= ar8xxx_sw_attr_port
,
2046 .n_attr
= ARRAY_SIZE(ar8xxx_sw_attr_port
),
2049 .attr
= ar8xxx_sw_attr_vlan
,
2050 .n_attr
= ARRAY_SIZE(ar8xxx_sw_attr_vlan
),
2052 .get_port_pvid
= ar8xxx_sw_get_pvid
,
2053 .set_port_pvid
= ar8xxx_sw_set_pvid
,
2054 .get_vlan_ports
= ar8xxx_sw_get_ports
,
2055 .set_vlan_ports
= ar8xxx_sw_set_ports
,
2056 .apply_config
= ar8xxx_sw_hw_apply
,
2057 .reset_switch
= ar8xxx_sw_reset_switch
,
2058 .get_port_link
= ar8xxx_sw_get_port_link
,
2059 .get_port_stats
= ar8xxx_sw_get_port_stats
,
2062 static const struct ar8xxx_chip ar7240sw_chip
= {
2063 .caps
= AR8XXX_CAP_MIB_COUNTERS
,
2065 .reg_port_stats_start
= 0x20000,
2066 .reg_port_stats_length
= 0x100,
2067 .reg_arl_ctrl
= AR8216_REG_ATU_CTRL
,
2069 .name
= "Atheros AR724X/AR933X built-in",
2070 .ports
= AR7240SW_NUM_PORTS
,
2071 .vlans
= AR8216_NUM_VLANS
,
2072 .swops
= &ar8xxx_sw_ops
,
2074 .hw_init
= ar7240sw_hw_init
,
2075 .init_globals
= ar7240sw_init_globals
,
2076 .init_port
= ar8229_init_port
,
2077 .phy_read
= ar8216_phy_read
,
2078 .phy_write
= ar8216_phy_write
,
2079 .setup_port
= ar7240sw_setup_port
,
2080 .read_port_status
= ar8216_read_port_status
,
2081 .atu_flush
= ar8216_atu_flush
,
2082 .atu_flush_port
= ar8216_atu_flush_port
,
2083 .vtu_flush
= ar8216_vtu_flush
,
2084 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
2085 .set_mirror_regs
= ar8216_set_mirror_regs
,
2086 .get_arl_entry
= ar8216_get_arl_entry
,
2087 .sw_hw_apply
= ar8xxx_sw_hw_apply
,
2089 .num_mibs
= ARRAY_SIZE(ar8236_mibs
),
2090 .mib_decs
= ar8236_mibs
,
2091 .mib_func
= AR8216_REG_MIB_FUNC
,
2092 .mib_rxb_id
= AR8236_MIB_RXB_ID
,
2093 .mib_txb_id
= AR8236_MIB_TXB_ID
,
2096 static const struct ar8xxx_chip ar8216_chip
= {
2097 .caps
= AR8XXX_CAP_MIB_COUNTERS
,
2099 .reg_port_stats_start
= 0x19000,
2100 .reg_port_stats_length
= 0xa0,
2101 .reg_arl_ctrl
= AR8216_REG_ATU_CTRL
,
2103 .name
= "Atheros AR8216",
2104 .ports
= AR8216_NUM_PORTS
,
2105 .vlans
= AR8216_NUM_VLANS
,
2106 .swops
= &ar8xxx_sw_ops
,
2108 .hw_init
= ar8216_hw_init
,
2109 .init_globals
= ar8216_init_globals
,
2110 .init_port
= ar8216_init_port
,
2111 .setup_port
= ar8216_setup_port
,
2112 .read_port_status
= ar8216_read_port_status
,
2113 .atu_flush
= ar8216_atu_flush
,
2114 .atu_flush_port
= ar8216_atu_flush_port
,
2115 .vtu_flush
= ar8216_vtu_flush
,
2116 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
2117 .set_mirror_regs
= ar8216_set_mirror_regs
,
2118 .get_arl_entry
= ar8216_get_arl_entry
,
2119 .sw_hw_apply
= ar8xxx_sw_hw_apply
,
2121 .num_mibs
= ARRAY_SIZE(ar8216_mibs
),
2122 .mib_decs
= ar8216_mibs
,
2123 .mib_func
= AR8216_REG_MIB_FUNC
,
2124 .mib_rxb_id
= AR8216_MIB_RXB_ID
,
2125 .mib_txb_id
= AR8216_MIB_TXB_ID
,
2128 static const struct ar8xxx_chip ar8229_chip
= {
2129 .caps
= AR8XXX_CAP_MIB_COUNTERS
,
2131 .reg_port_stats_start
= 0x20000,
2132 .reg_port_stats_length
= 0x100,
2133 .reg_arl_ctrl
= AR8216_REG_ATU_CTRL
,
2135 .name
= "Atheros AR8229",
2136 .ports
= AR8216_NUM_PORTS
,
2137 .vlans
= AR8216_NUM_VLANS
,
2138 .swops
= &ar8xxx_sw_ops
,
2140 .hw_init
= ar8229_hw_init
,
2141 .init_globals
= ar8229_init_globals
,
2142 .init_port
= ar8229_init_port
,
2143 .phy_read
= ar8216_phy_read
,
2144 .phy_write
= ar8216_phy_write
,
2145 .setup_port
= ar8236_setup_port
,
2146 .read_port_status
= ar8216_read_port_status
,
2147 .atu_flush
= ar8216_atu_flush
,
2148 .atu_flush_port
= ar8216_atu_flush_port
,
2149 .vtu_flush
= ar8216_vtu_flush
,
2150 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
2151 .set_mirror_regs
= ar8216_set_mirror_regs
,
2152 .get_arl_entry
= ar8216_get_arl_entry
,
2153 .sw_hw_apply
= ar8xxx_sw_hw_apply
,
2155 .num_mibs
= ARRAY_SIZE(ar8236_mibs
),
2156 .mib_decs
= ar8236_mibs
,
2157 .mib_func
= AR8216_REG_MIB_FUNC
,
2158 .mib_rxb_id
= AR8236_MIB_RXB_ID
,
2159 .mib_txb_id
= AR8236_MIB_TXB_ID
,
2162 static const struct ar8xxx_chip ar8236_chip
= {
2163 .caps
= AR8XXX_CAP_MIB_COUNTERS
,
2165 .reg_port_stats_start
= 0x20000,
2166 .reg_port_stats_length
= 0x100,
2167 .reg_arl_ctrl
= AR8216_REG_ATU_CTRL
,
2169 .name
= "Atheros AR8236",
2170 .ports
= AR8216_NUM_PORTS
,
2171 .vlans
= AR8216_NUM_VLANS
,
2172 .swops
= &ar8xxx_sw_ops
,
2174 .hw_init
= ar8216_hw_init
,
2175 .init_globals
= ar8236_init_globals
,
2176 .init_port
= ar8216_init_port
,
2177 .setup_port
= ar8236_setup_port
,
2178 .read_port_status
= ar8216_read_port_status
,
2179 .atu_flush
= ar8216_atu_flush
,
2180 .atu_flush_port
= ar8216_atu_flush_port
,
2181 .vtu_flush
= ar8216_vtu_flush
,
2182 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
2183 .set_mirror_regs
= ar8216_set_mirror_regs
,
2184 .get_arl_entry
= ar8216_get_arl_entry
,
2185 .sw_hw_apply
= ar8xxx_sw_hw_apply
,
2187 .num_mibs
= ARRAY_SIZE(ar8236_mibs
),
2188 .mib_decs
= ar8236_mibs
,
2189 .mib_func
= AR8216_REG_MIB_FUNC
,
2190 .mib_rxb_id
= AR8236_MIB_RXB_ID
,
2191 .mib_txb_id
= AR8236_MIB_TXB_ID
,
2194 static const struct ar8xxx_chip ar8316_chip
= {
2195 .caps
= AR8XXX_CAP_GIGE
| AR8XXX_CAP_MIB_COUNTERS
,
2197 .reg_port_stats_start
= 0x20000,
2198 .reg_port_stats_length
= 0x100,
2199 .reg_arl_ctrl
= AR8216_REG_ATU_CTRL
,
2201 .name
= "Atheros AR8316",
2202 .ports
= AR8216_NUM_PORTS
,
2203 .vlans
= AR8X16_MAX_VLANS
,
2204 .swops
= &ar8xxx_sw_ops
,
2206 .hw_init
= ar8316_hw_init
,
2207 .init_globals
= ar8316_init_globals
,
2208 .init_port
= ar8216_init_port
,
2209 .setup_port
= ar8216_setup_port
,
2210 .read_port_status
= ar8216_read_port_status
,
2211 .atu_flush
= ar8216_atu_flush
,
2212 .atu_flush_port
= ar8216_atu_flush_port
,
2213 .vtu_flush
= ar8216_vtu_flush
,
2214 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
2215 .set_mirror_regs
= ar8216_set_mirror_regs
,
2216 .get_arl_entry
= ar8216_get_arl_entry
,
2217 .sw_hw_apply
= ar8xxx_sw_hw_apply
,
2219 .num_mibs
= ARRAY_SIZE(ar8236_mibs
),
2220 .mib_decs
= ar8236_mibs
,
2221 .mib_func
= AR8216_REG_MIB_FUNC
,
2222 .mib_rxb_id
= AR8236_MIB_RXB_ID
,
2223 .mib_txb_id
= AR8236_MIB_TXB_ID
,
2227 ar8xxx_read_id(struct ar8xxx_priv
*priv
)
2233 val
= ar8xxx_read(priv
, AR8216_REG_CTRL
);
2237 id
= val
& (AR8216_CTRL_REVISION
| AR8216_CTRL_VERSION
);
2238 for (i
= 0; i
< AR8X16_PROBE_RETRIES
; i
++) {
2241 val
= ar8xxx_read(priv
, AR8216_REG_CTRL
);
2245 t
= val
& (AR8216_CTRL_REVISION
| AR8216_CTRL_VERSION
);
2250 priv
->chip_ver
= (id
& AR8216_CTRL_VERSION
) >> AR8216_CTRL_VERSION_S
;
2251 priv
->chip_rev
= (id
& AR8216_CTRL_REVISION
);
2256 ar8xxx_id_chip(struct ar8xxx_priv
*priv
)
2260 ret
= ar8xxx_read_id(priv
);
2264 switch (priv
->chip_ver
) {
2265 case AR8XXX_VER_AR8216
:
2266 priv
->chip
= &ar8216_chip
;
2268 case AR8XXX_VER_AR8236
:
2269 priv
->chip
= &ar8236_chip
;
2271 case AR8XXX_VER_AR8316
:
2272 priv
->chip
= &ar8316_chip
;
2274 case AR8XXX_VER_AR8327
:
2275 priv
->chip
= &ar8327_chip
;
2277 case AR8XXX_VER_AR8337
:
2278 priv
->chip
= &ar8337_chip
;
2281 pr_err("ar8216: Unknown Atheros device [ver=%d, rev=%d]\n",
2282 priv
->chip_ver
, priv
->chip_rev
);
2291 ar8xxx_mib_work_func(struct work_struct
*work
)
2293 struct ar8xxx_priv
*priv
;
2296 priv
= container_of(work
, struct ar8xxx_priv
, mib_work
.work
);
2298 mutex_lock(&priv
->mib_lock
);
2300 err
= ar8xxx_mib_capture(priv
);
2304 for (i
= 0; i
< priv
->dev
.ports
; i
++)
2305 ar8xxx_mib_fetch_port_stat(priv
, i
, false);
2308 mutex_unlock(&priv
->mib_lock
);
2309 schedule_delayed_work(&priv
->mib_work
,
2310 msecs_to_jiffies(priv
->mib_poll_interval
));
2314 ar8xxx_mib_init(struct ar8xxx_priv
*priv
)
2318 if (!ar8xxx_has_mib_counters(priv
))
2321 BUG_ON(!priv
->chip
->mib_decs
|| !priv
->chip
->num_mibs
);
2323 len
= priv
->dev
.ports
* priv
->chip
->num_mibs
*
2324 sizeof(*priv
->mib_stats
);
2325 priv
->mib_stats
= kzalloc(len
, GFP_KERNEL
);
2327 if (!priv
->mib_stats
)
2334 ar8xxx_mib_start(struct ar8xxx_priv
*priv
)
2336 if (!ar8xxx_has_mib_counters(priv
) || !priv
->mib_poll_interval
)
2339 schedule_delayed_work(&priv
->mib_work
,
2340 msecs_to_jiffies(priv
->mib_poll_interval
));
2344 ar8xxx_mib_stop(struct ar8xxx_priv
*priv
)
2346 if (!ar8xxx_has_mib_counters(priv
) || !priv
->mib_poll_interval
)
2349 cancel_delayed_work_sync(&priv
->mib_work
);
2352 static struct ar8xxx_priv
*
2355 struct ar8xxx_priv
*priv
;
2357 priv
= kzalloc(sizeof(struct ar8xxx_priv
), GFP_KERNEL
);
2361 mutex_init(&priv
->reg_mutex
);
2362 mutex_init(&priv
->mib_lock
);
2363 INIT_DELAYED_WORK(&priv
->mib_work
, ar8xxx_mib_work_func
);
2369 ar8xxx_free(struct ar8xxx_priv
*priv
)
2371 if (priv
->chip
&& priv
->chip
->cleanup
)
2372 priv
->chip
->cleanup(priv
);
2374 kfree(priv
->chip_data
);
2375 kfree(priv
->mib_stats
);
2380 ar8xxx_probe_switch(struct ar8xxx_priv
*priv
)
2382 const struct ar8xxx_chip
*chip
;
2383 struct switch_dev
*swdev
;
2389 swdev
->cpu_port
= AR8216_PORT_CPU
;
2390 swdev
->name
= chip
->name
;
2391 swdev
->vlans
= chip
->vlans
;
2392 swdev
->ports
= chip
->ports
;
2393 swdev
->ops
= chip
->swops
;
2395 ret
= ar8xxx_mib_init(priv
);
2403 ar8xxx_start(struct ar8xxx_priv
*priv
)
2409 ret
= priv
->chip
->hw_init(priv
);
2413 ret
= ar8xxx_sw_reset_switch(&priv
->dev
);
2419 ar8xxx_mib_start(priv
);
2425 ar8xxx_phy_config_init(struct phy_device
*phydev
)
2427 struct ar8xxx_priv
*priv
= phydev
->priv
;
2428 #ifdef CONFIG_ETHERNET_PACKET_MANGLE
2429 struct net_device
*dev
= phydev
->attached_dev
;
2436 if (priv
->chip
->config_at_probe
)
2437 return ar8xxx_phy_check_aneg(phydev
);
2441 if (phydev
->mdio
.addr
!= 0) {
2442 if (chip_is_ar8316(priv
)) {
2443 /* switch device has been initialized, reinit */
2444 priv
->dev
.ports
= (AR8216_NUM_PORTS
- 1);
2445 priv
->initialized
= false;
2446 priv
->port4_phy
= true;
2447 ar8316_hw_init(priv
);
2454 ret
= ar8xxx_start(priv
);
2458 #ifdef CONFIG_ETHERNET_PACKET_MANGLE
2459 /* VID fixup only needed on ar8216 */
2460 if (chip_is_ar8216(priv
)) {
2461 dev
->phy_ptr
= priv
;
2462 #if LINUX_VERSION_CODE >= KERNEL_VERSION(6,1,0)
2463 dev
->priv_flags
|= IFF_NO_IP_ALIGN
;
2464 #else LINUX_VERSION_CODE >= KERNEL_VERSION(5,15,0)
2465 dev
->extra_priv_flags
|= IFF_NO_IP_ALIGN
;
2467 dev
->eth_mangle_rx
= ar8216_mangle_rx
;
2468 dev
->eth_mangle_tx
= ar8216_mangle_tx
;
2476 ar8xxx_check_link_states(struct ar8xxx_priv
*priv
)
2478 bool link_new
, changed
= false;
2482 mutex_lock(&priv
->reg_mutex
);
2484 for (i
= 0; i
< priv
->dev
.ports
; i
++) {
2485 status
= priv
->chip
->read_port_status(priv
, i
);
2486 link_new
= !!(status
& AR8216_PORT_STATUS_LINK_UP
);
2487 if (link_new
== priv
->link_up
[i
])
2490 priv
->link_up
[i
] = link_new
;
2492 /* flush ARL entries for this port if it went down*/
2494 priv
->chip
->atu_flush_port(priv
, i
);
2495 dev_info(&priv
->phy
->mdio
.dev
, "Port %d is %s\n",
2496 i
, link_new
? "up" : "down");
2499 mutex_unlock(&priv
->reg_mutex
);
2505 ar8xxx_phy_read_status(struct phy_device
*phydev
)
2507 struct ar8xxx_priv
*priv
= phydev
->priv
;
2508 struct switch_port_link link
;
2510 /* check for switch port link changes */
2511 ar8xxx_check_link_states(priv
);
2513 if (phydev
->mdio
.addr
!= 0)
2514 return genphy_read_status(phydev
);
2516 ar8216_read_port_link(priv
, phydev
->mdio
.addr
, &link
);
2517 phydev
->link
= !!link
.link
;
2521 switch (link
.speed
) {
2522 case SWITCH_PORT_SPEED_10
:
2523 phydev
->speed
= SPEED_10
;
2525 case SWITCH_PORT_SPEED_100
:
2526 phydev
->speed
= SPEED_100
;
2528 case SWITCH_PORT_SPEED_1000
:
2529 phydev
->speed
= SPEED_1000
;
2534 phydev
->duplex
= link
.duplex
? DUPLEX_FULL
: DUPLEX_HALF
;
2536 phydev
->state
= PHY_RUNNING
;
2537 netif_carrier_on(phydev
->attached_dev
);
2538 if (phydev
->adjust_link
)
2539 phydev
->adjust_link(phydev
->attached_dev
);
2545 ar8xxx_phy_config_aneg(struct phy_device
*phydev
)
2547 if (phydev
->mdio
.addr
== 0)
2550 return genphy_config_aneg(phydev
);
2554 ar8xxx_get_features(struct phy_device
*phydev
)
2556 struct ar8xxx_priv
*priv
= phydev
->priv
;
2558 linkmode_copy(phydev
->supported
, PHY_BASIC_FEATURES
);
2559 if (ar8xxx_has_gige(priv
))
2560 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT
, phydev
->supported
);
2565 static const u32 ar8xxx_phy_ids
[] = {
2567 0x004dd034, /* AR8327 */
2568 0x004dd036, /* AR8337 */
2571 0x004dd043, /* AR8236 */
2575 ar8xxx_phy_match(u32 phy_id
)
2579 for (i
= 0; i
< ARRAY_SIZE(ar8xxx_phy_ids
); i
++)
2580 if (phy_id
== ar8xxx_phy_ids
[i
])
2587 ar8xxx_is_possible(struct mii_bus
*bus
)
2589 unsigned int i
, found_phys
= 0;
2591 for (i
= 0; i
< 5; i
++) {
2594 phy_id
= mdiobus_read(bus
, i
, MII_PHYSID1
) << 16;
2595 phy_id
|= mdiobus_read(bus
, i
, MII_PHYSID2
);
2596 if (ar8xxx_phy_match(phy_id
)) {
2598 } else if (phy_id
) {
2599 pr_debug("ar8xxx: unknown PHY at %s:%02x id:%08x\n",
2600 dev_name(&bus
->dev
), i
, phy_id
);
2603 return !!found_phys
;
2607 ar8xxx_phy_probe(struct phy_device
*phydev
)
2609 struct ar8xxx_priv
*priv
;
2610 struct switch_dev
*swdev
;
2613 /* skip PHYs at unused adresses */
2614 if (phydev
->mdio
.addr
!= 0 && phydev
->mdio
.addr
!= 3 && phydev
->mdio
.addr
!= 4)
2617 if (!ar8xxx_is_possible(phydev
->mdio
.bus
))
2620 mutex_lock(&ar8xxx_dev_list_lock
);
2621 list_for_each_entry(priv
, &ar8xxx_dev_list
, list
)
2622 if (priv
->mii_bus
== phydev
->mdio
.bus
)
2625 priv
= ar8xxx_create();
2631 priv
->mii_bus
= phydev
->mdio
.bus
;
2632 priv
->pdev
= &phydev
->mdio
.dev
;
2634 ret
= of_property_read_u32(priv
->pdev
->of_node
, "qca,mib-poll-interval",
2635 &priv
->mib_poll_interval
);
2637 priv
->mib_poll_interval
= 0;
2639 ret
= ar8xxx_id_chip(priv
);
2643 ret
= ar8xxx_probe_switch(priv
);
2648 swdev
->alias
= dev_name(&priv
->mii_bus
->dev
);
2649 ret
= register_switch(swdev
, NULL
);
2653 pr_info("%s: %s rev. %u switch registered on %s\n",
2654 swdev
->devname
, swdev
->name
, priv
->chip_rev
,
2655 dev_name(&priv
->mii_bus
->dev
));
2657 list_add(&priv
->list
, &ar8xxx_dev_list
);
2662 if (phydev
->mdio
.addr
== 0 && priv
->chip
->config_at_probe
) {
2665 ret
= ar8xxx_start(priv
);
2667 goto err_unregister_switch
;
2668 } else if (priv
->chip
->phy_rgmii_set
) {
2669 priv
->chip
->phy_rgmii_set(priv
, phydev
);
2672 phydev
->priv
= priv
;
2674 mutex_unlock(&ar8xxx_dev_list_lock
);
2678 err_unregister_switch
:
2679 if (--priv
->use_count
)
2682 unregister_switch(&priv
->dev
);
2687 mutex_unlock(&ar8xxx_dev_list_lock
);
2692 ar8xxx_phy_detach(struct phy_device
*phydev
)
2694 struct net_device
*dev
= phydev
->attached_dev
;
2699 #ifdef CONFIG_ETHERNET_PACKET_MANGLE
2700 dev
->phy_ptr
= NULL
;
2701 #if LINUX_VERSION_CODE >= KERNEL_VERSION(6,1,0)
2702 dev
->priv_flags
&= ~IFF_NO_IP_ALIGN
;
2703 #else LINUX_VERSION_CODE >= KERNEL_VERSION(5,15,0)
2704 dev
->extra_priv_flags
&= ~IFF_NO_IP_ALIGN
;
2706 dev
->eth_mangle_rx
= NULL
;
2707 dev
->eth_mangle_tx
= NULL
;
2712 ar8xxx_phy_remove(struct phy_device
*phydev
)
2714 struct ar8xxx_priv
*priv
= phydev
->priv
;
2719 phydev
->priv
= NULL
;
2721 mutex_lock(&ar8xxx_dev_list_lock
);
2723 if (--priv
->use_count
> 0) {
2724 mutex_unlock(&ar8xxx_dev_list_lock
);
2728 list_del(&priv
->list
);
2729 mutex_unlock(&ar8xxx_dev_list_lock
);
2731 unregister_switch(&priv
->dev
);
2732 ar8xxx_mib_stop(priv
);
2736 static struct phy_driver ar8xxx_phy_driver
[] = {
2738 .phy_id
= 0x004d0000,
2739 .name
= "Atheros AR8216/AR8236/AR8316",
2740 .phy_id_mask
= 0xffff0000,
2741 .probe
= ar8xxx_phy_probe
,
2742 .remove
= ar8xxx_phy_remove
,
2743 .detach
= ar8xxx_phy_detach
,
2744 .config_init
= ar8xxx_phy_config_init
,
2745 .config_aneg
= ar8xxx_phy_config_aneg
,
2746 .read_status
= ar8xxx_phy_read_status
,
2747 .get_features
= ar8xxx_get_features
,
2751 static const struct of_device_id ar8xxx_mdiodev_of_match
[] = {
2753 .compatible
= "qca,ar7240sw",
2754 .data
= &ar7240sw_chip
,
2756 .compatible
= "qca,ar8229",
2757 .data
= &ar8229_chip
,
2759 .compatible
= "qca,ar8236",
2760 .data
= &ar8236_chip
,
2762 .compatible
= "qca,ar8327",
2763 .data
= &ar8327_chip
,
2769 ar8xxx_mdiodev_probe(struct mdio_device
*mdiodev
)
2771 const struct of_device_id
*match
;
2772 struct ar8xxx_priv
*priv
;
2773 struct switch_dev
*swdev
;
2774 struct device_node
*mdio_node
;
2777 match
= of_match_device(ar8xxx_mdiodev_of_match
, &mdiodev
->dev
);
2781 priv
= ar8xxx_create();
2785 priv
->mii_bus
= mdiodev
->bus
;
2786 priv
->pdev
= &mdiodev
->dev
;
2787 priv
->chip
= (const struct ar8xxx_chip
*) match
->data
;
2789 ret
= of_property_read_u32(priv
->pdev
->of_node
, "qca,mib-poll-interval",
2790 &priv
->mib_poll_interval
);
2792 priv
->mib_poll_interval
= 0;
2794 ret
= ar8xxx_read_id(priv
);
2798 ret
= ar8xxx_probe_switch(priv
);
2802 if (priv
->chip
->phy_read
&& priv
->chip
->phy_write
) {
2803 priv
->sw_mii_bus
= devm_mdiobus_alloc(&mdiodev
->dev
);
2804 priv
->sw_mii_bus
->name
= "ar8xxx-mdio";
2805 priv
->sw_mii_bus
->read
= ar8xxx_phy_read
;
2806 priv
->sw_mii_bus
->write
= ar8xxx_phy_write
;
2807 priv
->sw_mii_bus
->priv
= priv
;
2808 priv
->sw_mii_bus
->parent
= &mdiodev
->dev
;
2809 snprintf(priv
->sw_mii_bus
->id
, MII_BUS_ID_SIZE
, "%s",
2810 dev_name(&mdiodev
->dev
));
2811 mdio_node
= of_get_child_by_name(priv
->pdev
->of_node
, "mdio-bus");
2812 ret
= of_mdiobus_register(priv
->sw_mii_bus
, mdio_node
);
2818 swdev
->alias
= dev_name(&mdiodev
->dev
);
2820 if (of_property_read_bool(priv
->pdev
->of_node
, "qca,phy4-mii-enable")) {
2821 priv
->port4_phy
= true;
2825 ret
= register_switch(swdev
, NULL
);
2829 pr_info("%s: %s rev. %u switch registered on %s\n",
2830 swdev
->devname
, swdev
->name
, priv
->chip_rev
,
2831 dev_name(&priv
->mii_bus
->dev
));
2833 mutex_lock(&ar8xxx_dev_list_lock
);
2834 list_add(&priv
->list
, &ar8xxx_dev_list
);
2835 mutex_unlock(&ar8xxx_dev_list_lock
);
2839 ret
= ar8xxx_start(priv
);
2841 goto err_unregister_switch
;
2843 dev_set_drvdata(&mdiodev
->dev
, priv
);
2847 err_unregister_switch
:
2848 if (--priv
->use_count
)
2851 unregister_switch(&priv
->dev
);
2859 ar8xxx_mdiodev_remove(struct mdio_device
*mdiodev
)
2861 struct ar8xxx_priv
*priv
= dev_get_drvdata(&mdiodev
->dev
);
2866 mutex_lock(&ar8xxx_dev_list_lock
);
2868 if (--priv
->use_count
> 0) {
2869 mutex_unlock(&ar8xxx_dev_list_lock
);
2873 list_del(&priv
->list
);
2874 mutex_unlock(&ar8xxx_dev_list_lock
);
2876 unregister_switch(&priv
->dev
);
2877 ar8xxx_mib_stop(priv
);
2878 if(priv
->sw_mii_bus
)
2879 mdiobus_unregister(priv
->sw_mii_bus
);
2883 static struct mdio_driver ar8xxx_mdio_driver
= {
2884 .probe
= ar8xxx_mdiodev_probe
,
2885 .remove
= ar8xxx_mdiodev_remove
,
2887 .name
= "ar8xxx-switch",
2888 .of_match_table
= ar8xxx_mdiodev_of_match
,
2892 static int __init
ar8216_init(void)
2896 ret
= phy_drivers_register(ar8xxx_phy_driver
,
2897 ARRAY_SIZE(ar8xxx_phy_driver
),
2902 ret
= mdio_driver_register(&ar8xxx_mdio_driver
);
2904 phy_drivers_unregister(ar8xxx_phy_driver
,
2905 ARRAY_SIZE(ar8xxx_phy_driver
));
2909 module_init(ar8216_init
);
2911 static void __exit
ar8216_exit(void)
2913 mdio_driver_unregister(&ar8xxx_mdio_driver
);
2914 phy_drivers_unregister(ar8xxx_phy_driver
,
2915 ARRAY_SIZE(ar8xxx_phy_driver
));
2917 module_exit(ar8216_exit
);
2919 MODULE_LICENSE("GPL");