2 * ar8216.c: AR8216 switch driver
4 * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/list.h>
22 #include <linux/if_ether.h>
23 #include <linux/skbuff.h>
24 #include <linux/netdevice.h>
25 #include <linux/netlink.h>
26 #include <linux/bitops.h>
27 #include <net/genetlink.h>
28 #include <linux/switch.h>
29 #include <linux/delay.h>
30 #include <linux/phy.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/lockdep.h>
34 #include <linux/ar8216_platform.h>
35 #include <linux/workqueue.h>
36 #include <linux/of_device.h>
37 #include <linux/leds.h>
38 #include <linux/gpio.h>
42 /* size of the vlan table */
43 #define AR8X16_MAX_VLANS 128
44 #define AR8X16_PROBE_RETRIES 10
45 #define AR8X16_MAX_PORTS 8
47 #define AR8XXX_MIB_WORK_DELAY 2000 /* msecs */
51 #define AR8XXX_CAP_GIGE BIT(0)
52 #define AR8XXX_CAP_MIB_COUNTERS BIT(1)
55 AR8XXX_VER_AR8216
= 0x01,
56 AR8XXX_VER_AR8236
= 0x03,
57 AR8XXX_VER_AR8316
= 0x10,
58 AR8XXX_VER_AR8327
= 0x12,
59 AR8XXX_VER_AR8337
= 0x13,
62 struct ar8xxx_mib_desc
{
71 int (*hw_init
)(struct ar8xxx_priv
*priv
);
72 void (*cleanup
)(struct ar8xxx_priv
*priv
);
74 void (*init_globals
)(struct ar8xxx_priv
*priv
);
75 void (*init_port
)(struct ar8xxx_priv
*priv
, int port
);
76 void (*setup_port
)(struct ar8xxx_priv
*priv
, int port
, u32 members
);
77 u32 (*read_port_status
)(struct ar8xxx_priv
*priv
, int port
);
78 int (*atu_flush
)(struct ar8xxx_priv
*priv
);
79 void (*vtu_flush
)(struct ar8xxx_priv
*priv
);
80 void (*vtu_load_vlan
)(struct ar8xxx_priv
*priv
, u32 vlan
);
82 const struct ar8xxx_mib_desc
*mib_decs
;
86 enum ar8327_led_pattern
{
87 AR8327_LED_PATTERN_OFF
= 0,
88 AR8327_LED_PATTERN_BLINK
,
89 AR8327_LED_PATTERN_ON
,
90 AR8327_LED_PATTERN_RULE
,
93 struct ar8327_led_entry
{
99 struct led_classdev cdev
;
100 struct ar8xxx_priv
*sw_priv
;
105 enum ar8327_led_mode mode
;
109 struct work_struct led_work
;
111 enum ar8327_led_pattern pattern
;
119 u8 vlan_tagged
[AR8X16_MAX_VLANS
];
123 struct ar8327_led
**leds
;
124 unsigned int num_leds
;
128 struct switch_dev dev
;
129 struct mii_bus
*mii_bus
;
130 struct phy_device
*phy
;
132 u32 (*read
)(struct ar8xxx_priv
*priv
, int reg
);
133 void (*write
)(struct ar8xxx_priv
*priv
, int reg
, u32 val
);
134 u32 (*rmw
)(struct ar8xxx_priv
*priv
, int reg
, u32 mask
, u32 val
);
136 int (*get_port_link
)(unsigned port
);
138 const struct net_device_ops
*ndo_old
;
139 struct net_device_ops ndo
;
140 struct mutex reg_mutex
;
143 const struct ar8xxx_chip
*chip
;
145 struct ar8216_data ar8216
;
146 struct ar8327_data ar8327
;
155 struct mutex mib_lock
;
156 struct delayed_work mib_work
;
160 struct list_head list
;
161 unsigned int use_count
;
163 /* all fields below are cleared on reset */
165 u16 vlan_id
[AR8X16_MAX_VLANS
];
166 u8 vlan_table
[AR8X16_MAX_VLANS
];
167 u16 pvid
[AR8X16_MAX_PORTS
];
176 #define MIB_DESC(_s , _o, _n) \
183 static const struct ar8xxx_mib_desc ar8216_mibs
[] = {
184 MIB_DESC(1, AR8216_STATS_RXBROAD
, "RxBroad"),
185 MIB_DESC(1, AR8216_STATS_RXPAUSE
, "RxPause"),
186 MIB_DESC(1, AR8216_STATS_RXMULTI
, "RxMulti"),
187 MIB_DESC(1, AR8216_STATS_RXFCSERR
, "RxFcsErr"),
188 MIB_DESC(1, AR8216_STATS_RXALIGNERR
, "RxAlignErr"),
189 MIB_DESC(1, AR8216_STATS_RXRUNT
, "RxRunt"),
190 MIB_DESC(1, AR8216_STATS_RXFRAGMENT
, "RxFragment"),
191 MIB_DESC(1, AR8216_STATS_RX64BYTE
, "Rx64Byte"),
192 MIB_DESC(1, AR8216_STATS_RX128BYTE
, "Rx128Byte"),
193 MIB_DESC(1, AR8216_STATS_RX256BYTE
, "Rx256Byte"),
194 MIB_DESC(1, AR8216_STATS_RX512BYTE
, "Rx512Byte"),
195 MIB_DESC(1, AR8216_STATS_RX1024BYTE
, "Rx1024Byte"),
196 MIB_DESC(1, AR8216_STATS_RXMAXBYTE
, "RxMaxByte"),
197 MIB_DESC(1, AR8216_STATS_RXTOOLONG
, "RxTooLong"),
198 MIB_DESC(2, AR8216_STATS_RXGOODBYTE
, "RxGoodByte"),
199 MIB_DESC(2, AR8216_STATS_RXBADBYTE
, "RxBadByte"),
200 MIB_DESC(1, AR8216_STATS_RXOVERFLOW
, "RxOverFlow"),
201 MIB_DESC(1, AR8216_STATS_FILTERED
, "Filtered"),
202 MIB_DESC(1, AR8216_STATS_TXBROAD
, "TxBroad"),
203 MIB_DESC(1, AR8216_STATS_TXPAUSE
, "TxPause"),
204 MIB_DESC(1, AR8216_STATS_TXMULTI
, "TxMulti"),
205 MIB_DESC(1, AR8216_STATS_TXUNDERRUN
, "TxUnderRun"),
206 MIB_DESC(1, AR8216_STATS_TX64BYTE
, "Tx64Byte"),
207 MIB_DESC(1, AR8216_STATS_TX128BYTE
, "Tx128Byte"),
208 MIB_DESC(1, AR8216_STATS_TX256BYTE
, "Tx256Byte"),
209 MIB_DESC(1, AR8216_STATS_TX512BYTE
, "Tx512Byte"),
210 MIB_DESC(1, AR8216_STATS_TX1024BYTE
, "Tx1024Byte"),
211 MIB_DESC(1, AR8216_STATS_TXMAXBYTE
, "TxMaxByte"),
212 MIB_DESC(1, AR8216_STATS_TXOVERSIZE
, "TxOverSize"),
213 MIB_DESC(2, AR8216_STATS_TXBYTE
, "TxByte"),
214 MIB_DESC(1, AR8216_STATS_TXCOLLISION
, "TxCollision"),
215 MIB_DESC(1, AR8216_STATS_TXABORTCOL
, "TxAbortCol"),
216 MIB_DESC(1, AR8216_STATS_TXMULTICOL
, "TxMultiCol"),
217 MIB_DESC(1, AR8216_STATS_TXSINGLECOL
, "TxSingleCol"),
218 MIB_DESC(1, AR8216_STATS_TXEXCDEFER
, "TxExcDefer"),
219 MIB_DESC(1, AR8216_STATS_TXDEFER
, "TxDefer"),
220 MIB_DESC(1, AR8216_STATS_TXLATECOL
, "TxLateCol"),
223 static const struct ar8xxx_mib_desc ar8236_mibs
[] = {
224 MIB_DESC(1, AR8236_STATS_RXBROAD
, "RxBroad"),
225 MIB_DESC(1, AR8236_STATS_RXPAUSE
, "RxPause"),
226 MIB_DESC(1, AR8236_STATS_RXMULTI
, "RxMulti"),
227 MIB_DESC(1, AR8236_STATS_RXFCSERR
, "RxFcsErr"),
228 MIB_DESC(1, AR8236_STATS_RXALIGNERR
, "RxAlignErr"),
229 MIB_DESC(1, AR8236_STATS_RXRUNT
, "RxRunt"),
230 MIB_DESC(1, AR8236_STATS_RXFRAGMENT
, "RxFragment"),
231 MIB_DESC(1, AR8236_STATS_RX64BYTE
, "Rx64Byte"),
232 MIB_DESC(1, AR8236_STATS_RX128BYTE
, "Rx128Byte"),
233 MIB_DESC(1, AR8236_STATS_RX256BYTE
, "Rx256Byte"),
234 MIB_DESC(1, AR8236_STATS_RX512BYTE
, "Rx512Byte"),
235 MIB_DESC(1, AR8236_STATS_RX1024BYTE
, "Rx1024Byte"),
236 MIB_DESC(1, AR8236_STATS_RX1518BYTE
, "Rx1518Byte"),
237 MIB_DESC(1, AR8236_STATS_RXMAXBYTE
, "RxMaxByte"),
238 MIB_DESC(1, AR8236_STATS_RXTOOLONG
, "RxTooLong"),
239 MIB_DESC(2, AR8236_STATS_RXGOODBYTE
, "RxGoodByte"),
240 MIB_DESC(2, AR8236_STATS_RXBADBYTE
, "RxBadByte"),
241 MIB_DESC(1, AR8236_STATS_RXOVERFLOW
, "RxOverFlow"),
242 MIB_DESC(1, AR8236_STATS_FILTERED
, "Filtered"),
243 MIB_DESC(1, AR8236_STATS_TXBROAD
, "TxBroad"),
244 MIB_DESC(1, AR8236_STATS_TXPAUSE
, "TxPause"),
245 MIB_DESC(1, AR8236_STATS_TXMULTI
, "TxMulti"),
246 MIB_DESC(1, AR8236_STATS_TXUNDERRUN
, "TxUnderRun"),
247 MIB_DESC(1, AR8236_STATS_TX64BYTE
, "Tx64Byte"),
248 MIB_DESC(1, AR8236_STATS_TX128BYTE
, "Tx128Byte"),
249 MIB_DESC(1, AR8236_STATS_TX256BYTE
, "Tx256Byte"),
250 MIB_DESC(1, AR8236_STATS_TX512BYTE
, "Tx512Byte"),
251 MIB_DESC(1, AR8236_STATS_TX1024BYTE
, "Tx1024Byte"),
252 MIB_DESC(1, AR8236_STATS_TX1518BYTE
, "Tx1518Byte"),
253 MIB_DESC(1, AR8236_STATS_TXMAXBYTE
, "TxMaxByte"),
254 MIB_DESC(1, AR8236_STATS_TXOVERSIZE
, "TxOverSize"),
255 MIB_DESC(2, AR8236_STATS_TXBYTE
, "TxByte"),
256 MIB_DESC(1, AR8236_STATS_TXCOLLISION
, "TxCollision"),
257 MIB_DESC(1, AR8236_STATS_TXABORTCOL
, "TxAbortCol"),
258 MIB_DESC(1, AR8236_STATS_TXMULTICOL
, "TxMultiCol"),
259 MIB_DESC(1, AR8236_STATS_TXSINGLECOL
, "TxSingleCol"),
260 MIB_DESC(1, AR8236_STATS_TXEXCDEFER
, "TxExcDefer"),
261 MIB_DESC(1, AR8236_STATS_TXDEFER
, "TxDefer"),
262 MIB_DESC(1, AR8236_STATS_TXLATECOL
, "TxLateCol"),
265 static DEFINE_MUTEX(ar8xxx_dev_list_lock
);
266 static LIST_HEAD(ar8xxx_dev_list
);
268 static inline struct ar8xxx_priv
*
269 swdev_to_ar8xxx(struct switch_dev
*swdev
)
271 return container_of(swdev
, struct ar8xxx_priv
, dev
);
274 static inline bool ar8xxx_has_gige(struct ar8xxx_priv
*priv
)
276 return priv
->chip
->caps
& AR8XXX_CAP_GIGE
;
279 static inline bool ar8xxx_has_mib_counters(struct ar8xxx_priv
*priv
)
281 return priv
->chip
->caps
& AR8XXX_CAP_MIB_COUNTERS
;
284 static inline bool chip_is_ar8216(struct ar8xxx_priv
*priv
)
286 return priv
->chip_ver
== AR8XXX_VER_AR8216
;
289 static inline bool chip_is_ar8236(struct ar8xxx_priv
*priv
)
291 return priv
->chip_ver
== AR8XXX_VER_AR8236
;
294 static inline bool chip_is_ar8316(struct ar8xxx_priv
*priv
)
296 return priv
->chip_ver
== AR8XXX_VER_AR8316
;
299 static inline bool chip_is_ar8327(struct ar8xxx_priv
*priv
)
301 return priv
->chip_ver
== AR8XXX_VER_AR8327
;
304 static inline bool chip_is_ar8337(struct ar8xxx_priv
*priv
)
306 return priv
->chip_ver
== AR8XXX_VER_AR8337
;
310 split_addr(u32 regaddr
, u16
*r1
, u16
*r2
, u16
*page
)
313 *r1
= regaddr
& 0x1e;
319 *page
= regaddr
& 0x1ff;
323 ar8xxx_mii_read(struct ar8xxx_priv
*priv
, int reg
)
325 struct mii_bus
*bus
= priv
->mii_bus
;
329 split_addr((u32
) reg
, &r1
, &r2
, &page
);
331 mutex_lock(&bus
->mdio_lock
);
333 bus
->write(bus
, 0x18, 0, page
);
334 usleep_range(1000, 2000); /* wait for the page switch to propagate */
335 lo
= bus
->read(bus
, 0x10 | r2
, r1
);
336 hi
= bus
->read(bus
, 0x10 | r2
, r1
+ 1);
338 mutex_unlock(&bus
->mdio_lock
);
340 return (hi
<< 16) | lo
;
344 ar8xxx_mii_write(struct ar8xxx_priv
*priv
, int reg
, u32 val
)
346 struct mii_bus
*bus
= priv
->mii_bus
;
350 split_addr((u32
) reg
, &r1
, &r2
, &r3
);
352 hi
= (u16
) (val
>> 16);
354 mutex_lock(&bus
->mdio_lock
);
356 bus
->write(bus
, 0x18, 0, r3
);
357 usleep_range(1000, 2000); /* wait for the page switch to propagate */
358 if (priv
->mii_lo_first
) {
359 bus
->write(bus
, 0x10 | r2
, r1
, lo
);
360 bus
->write(bus
, 0x10 | r2
, r1
+ 1, hi
);
362 bus
->write(bus
, 0x10 | r2
, r1
+ 1, hi
);
363 bus
->write(bus
, 0x10 | r2
, r1
, lo
);
366 mutex_unlock(&bus
->mdio_lock
);
370 ar8xxx_mii_rmw(struct ar8xxx_priv
*priv
, int reg
, u32 mask
, u32 val
)
372 struct mii_bus
*bus
= priv
->mii_bus
;
377 split_addr((u32
) reg
, &r1
, &r2
, &page
);
379 mutex_lock(&bus
->mdio_lock
);
381 bus
->write(bus
, 0x18, 0, page
);
382 usleep_range(1000, 2000); /* wait for the page switch to propagate */
384 lo
= bus
->read(bus
, 0x10 | r2
, r1
);
385 hi
= bus
->read(bus
, 0x10 | r2
, r1
+ 1);
392 hi
= (u16
) (ret
>> 16);
394 if (priv
->mii_lo_first
) {
395 bus
->write(bus
, 0x10 | r2
, r1
, lo
);
396 bus
->write(bus
, 0x10 | r2
, r1
+ 1, hi
);
398 bus
->write(bus
, 0x10 | r2
, r1
+ 1, hi
);
399 bus
->write(bus
, 0x10 | r2
, r1
, lo
);
402 mutex_unlock(&bus
->mdio_lock
);
409 ar8xxx_phy_dbg_write(struct ar8xxx_priv
*priv
, int phy_addr
,
410 u16 dbg_addr
, u16 dbg_data
)
412 struct mii_bus
*bus
= priv
->mii_bus
;
414 mutex_lock(&bus
->mdio_lock
);
415 bus
->write(bus
, phy_addr
, MII_ATH_DBG_ADDR
, dbg_addr
);
416 bus
->write(bus
, phy_addr
, MII_ATH_DBG_DATA
, dbg_data
);
417 mutex_unlock(&bus
->mdio_lock
);
421 ar8xxx_phy_mmd_write(struct ar8xxx_priv
*priv
, int phy_addr
, u16 addr
, u16 data
)
423 struct mii_bus
*bus
= priv
->mii_bus
;
425 mutex_lock(&bus
->mdio_lock
);
426 bus
->write(bus
, phy_addr
, MII_ATH_MMD_ADDR
, addr
);
427 bus
->write(bus
, phy_addr
, MII_ATH_MMD_DATA
, data
);
428 mutex_unlock(&bus
->mdio_lock
);
432 ar8xxx_rmw(struct ar8xxx_priv
*priv
, int reg
, u32 mask
, u32 val
)
434 return priv
->rmw(priv
, reg
, mask
, val
);
438 ar8xxx_reg_set(struct ar8xxx_priv
*priv
, int reg
, u32 val
)
440 priv
->rmw(priv
, reg
, 0, val
);
444 ar8xxx_reg_wait(struct ar8xxx_priv
*priv
, u32 reg
, u32 mask
, u32 val
,
449 for (i
= 0; i
< timeout
; i
++) {
452 t
= priv
->read(priv
, reg
);
453 if ((t
& mask
) == val
)
456 usleep_range(1000, 2000);
463 ar8xxx_mib_op(struct ar8xxx_priv
*priv
, u32 op
)
468 lockdep_assert_held(&priv
->mib_lock
);
470 if (chip_is_ar8327(priv
) || chip_is_ar8337(priv
))
471 mib_func
= AR8327_REG_MIB_FUNC
;
473 mib_func
= AR8216_REG_MIB_FUNC
;
475 /* Capture the hardware statistics for all ports */
476 ar8xxx_rmw(priv
, mib_func
, AR8216_MIB_FUNC
, (op
<< AR8216_MIB_FUNC_S
));
478 /* Wait for the capturing to complete. */
479 ret
= ar8xxx_reg_wait(priv
, mib_func
, AR8216_MIB_BUSY
, 0, 10);
490 ar8xxx_mib_capture(struct ar8xxx_priv
*priv
)
492 return ar8xxx_mib_op(priv
, AR8216_MIB_FUNC_CAPTURE
);
496 ar8xxx_mib_flush(struct ar8xxx_priv
*priv
)
498 return ar8xxx_mib_op(priv
, AR8216_MIB_FUNC_FLUSH
);
502 ar8xxx_mib_fetch_port_stat(struct ar8xxx_priv
*priv
, int port
, bool flush
)
508 WARN_ON(port
>= priv
->dev
.ports
);
510 lockdep_assert_held(&priv
->mib_lock
);
512 if (chip_is_ar8327(priv
) || chip_is_ar8337(priv
))
513 base
= AR8327_REG_PORT_STATS_BASE(port
);
514 else if (chip_is_ar8236(priv
) ||
515 chip_is_ar8316(priv
))
516 base
= AR8236_REG_PORT_STATS_BASE(port
);
518 base
= AR8216_REG_PORT_STATS_BASE(port
);
520 mib_stats
= &priv
->mib_stats
[port
* priv
->chip
->num_mibs
];
521 for (i
= 0; i
< priv
->chip
->num_mibs
; i
++) {
522 const struct ar8xxx_mib_desc
*mib
;
525 mib
= &priv
->chip
->mib_decs
[i
];
526 t
= priv
->read(priv
, base
+ mib
->offset
);
527 if (mib
->size
== 2) {
530 hi
= priv
->read(priv
, base
+ mib
->offset
+ 4);
542 ar8216_read_port_link(struct ar8xxx_priv
*priv
, int port
,
543 struct switch_port_link
*link
)
548 memset(link
, '\0', sizeof(*link
));
550 status
= priv
->chip
->read_port_status(priv
, port
);
552 link
->aneg
= !!(status
& AR8216_PORT_STATUS_LINK_AUTO
);
554 link
->link
= !!(status
& AR8216_PORT_STATUS_LINK_UP
);
558 if (priv
->get_port_link
) {
561 err
= priv
->get_port_link(port
);
570 link
->duplex
= !!(status
& AR8216_PORT_STATUS_DUPLEX
);
571 link
->tx_flow
= !!(status
& AR8216_PORT_STATUS_TXFLOW
);
572 link
->rx_flow
= !!(status
& AR8216_PORT_STATUS_RXFLOW
);
574 speed
= (status
& AR8216_PORT_STATUS_SPEED
) >>
575 AR8216_PORT_STATUS_SPEED_S
;
578 case AR8216_PORT_SPEED_10M
:
579 link
->speed
= SWITCH_PORT_SPEED_10
;
581 case AR8216_PORT_SPEED_100M
:
582 link
->speed
= SWITCH_PORT_SPEED_100
;
584 case AR8216_PORT_SPEED_1000M
:
585 link
->speed
= SWITCH_PORT_SPEED_1000
;
588 link
->speed
= SWITCH_PORT_SPEED_UNKNOWN
;
593 static struct sk_buff
*
594 ar8216_mangle_tx(struct net_device
*dev
, struct sk_buff
*skb
)
596 struct ar8xxx_priv
*priv
= dev
->phy_ptr
;
605 if (unlikely(skb_headroom(skb
) < 2)) {
606 if (pskb_expand_head(skb
, 2, 0, GFP_ATOMIC
) < 0)
610 buf
= skb_push(skb
, 2);
618 dev_kfree_skb_any(skb
);
623 ar8216_mangle_rx(struct net_device
*dev
, struct sk_buff
*skb
)
625 struct ar8xxx_priv
*priv
;
633 /* don't strip the header if vlan mode is disabled */
637 /* strip header, get vlan id */
641 /* check for vlan header presence */
642 if ((buf
[12 + 2] != 0x81) || (buf
[13 + 2] != 0x00))
647 /* no need to fix up packets coming from a tagged source */
648 if (priv
->chip_data
.ar8216
.vlan_tagged
& BIT(port
))
651 /* lookup port vid from local table, the switch passes an invalid vlan id */
652 vlan
= priv
->vlan_id
[priv
->pvid
[port
]];
655 buf
[14 + 2] |= vlan
>> 8;
656 buf
[15 + 2] = vlan
& 0xff;
660 ar8216_wait_bit(struct ar8xxx_priv
*priv
, int reg
, u32 mask
, u32 val
)
666 t
= priv
->read(priv
, reg
);
667 if ((t
& mask
) == val
)
676 pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
677 (unsigned int) reg
, t
, mask
, val
);
682 ar8216_vtu_op(struct ar8xxx_priv
*priv
, u32 op
, u32 val
)
684 if (ar8216_wait_bit(priv
, AR8216_REG_VTU
, AR8216_VTU_ACTIVE
, 0))
686 if ((op
& AR8216_VTU_OP
) == AR8216_VTU_OP_LOAD
) {
687 val
&= AR8216_VTUDATA_MEMBER
;
688 val
|= AR8216_VTUDATA_VALID
;
689 priv
->write(priv
, AR8216_REG_VTU_DATA
, val
);
691 op
|= AR8216_VTU_ACTIVE
;
692 priv
->write(priv
, AR8216_REG_VTU
, op
);
696 ar8216_vtu_flush(struct ar8xxx_priv
*priv
)
698 ar8216_vtu_op(priv
, AR8216_VTU_OP_FLUSH
, 0);
702 ar8216_vtu_load_vlan(struct ar8xxx_priv
*priv
, u32 vlan
)
706 u32 vid
= priv
->vlan_id
[vlan
];
707 u32 port_mask
= priv
->vlan_table
[vlan
];
709 op
= AR8216_VTU_OP_LOAD
| (vid
<< AR8216_VTU_VID_S
);
711 ar8216_vtu_op(priv
, op
, port_mask
);
715 ar8216_atu_flush(struct ar8xxx_priv
*priv
)
719 ret
= ar8216_wait_bit(priv
, AR8216_REG_ATU
, AR8216_ATU_ACTIVE
, 0);
721 priv
->write(priv
, AR8216_REG_ATU
, AR8216_ATU_OP_FLUSH
);
727 ar8216_read_port_status(struct ar8xxx_priv
*priv
, int port
)
729 return priv
->read(priv
, AR8216_REG_PORT_STATUS(port
));
733 ar8216_setup_port(struct ar8xxx_priv
*priv
, int port
, u32 members
)
740 pvid
= priv
->vlan_id
[priv
->pvid
[port
]];
741 if (priv
->chip_data
.ar8216
.vlan_tagged
& BIT(port
))
742 egress
= AR8216_OUT_ADD_VLAN
;
744 egress
= AR8216_OUT_STRIP_VLAN
;
745 ingress
= AR8216_IN_SECURE
;
748 egress
= AR8216_OUT_KEEP
;
749 ingress
= AR8216_IN_PORT_ONLY
;
754 if (chip_is_ar8216(priv
) && priv
->vlan
&& port
== AR8216_PORT_CPU
)
755 header
= AR8216_PORT_CTRL_HEADER
;
759 ar8xxx_rmw(priv
, AR8216_REG_PORT_CTRL(port
),
760 AR8216_PORT_CTRL_LEARN
| AR8216_PORT_CTRL_VLAN_MODE
|
761 AR8216_PORT_CTRL_SINGLE_VLAN
| AR8216_PORT_CTRL_STATE
|
762 AR8216_PORT_CTRL_HEADER
| AR8216_PORT_CTRL_LEARN_LOCK
,
763 AR8216_PORT_CTRL_LEARN
| header
|
764 (egress
<< AR8216_PORT_CTRL_VLAN_MODE_S
) |
765 (AR8216_PORT_STATE_FORWARD
<< AR8216_PORT_CTRL_STATE_S
));
767 ar8xxx_rmw(priv
, AR8216_REG_PORT_VLAN(port
),
768 AR8216_PORT_VLAN_DEST_PORTS
| AR8216_PORT_VLAN_MODE
|
769 AR8216_PORT_VLAN_DEFAULT_ID
,
770 (members
<< AR8216_PORT_VLAN_DEST_PORTS_S
) |
771 (ingress
<< AR8216_PORT_VLAN_MODE_S
) |
772 (pvid
<< AR8216_PORT_VLAN_DEFAULT_ID_S
));
776 ar8216_hw_init(struct ar8xxx_priv
*priv
)
782 ar8216_init_globals(struct ar8xxx_priv
*priv
)
784 /* standard atheros magic */
785 priv
->write(priv
, 0x38, 0xc000050e);
787 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
788 AR8216_GCTRL_MTU
, 1518 + 8 + 2);
792 ar8216_init_port(struct ar8xxx_priv
*priv
, int port
)
794 /* Enable port learning and tx */
795 priv
->write(priv
, AR8216_REG_PORT_CTRL(port
),
796 AR8216_PORT_CTRL_LEARN
|
797 (4 << AR8216_PORT_CTRL_STATE_S
));
799 priv
->write(priv
, AR8216_REG_PORT_VLAN(port
), 0);
801 if (port
== AR8216_PORT_CPU
) {
802 priv
->write(priv
, AR8216_REG_PORT_STATUS(port
),
803 AR8216_PORT_STATUS_LINK_UP
|
804 (ar8xxx_has_gige(priv
) ?
805 AR8216_PORT_SPEED_1000M
: AR8216_PORT_SPEED_100M
) |
806 AR8216_PORT_STATUS_TXMAC
|
807 AR8216_PORT_STATUS_RXMAC
|
808 (chip_is_ar8316(priv
) ? AR8216_PORT_STATUS_RXFLOW
: 0) |
809 (chip_is_ar8316(priv
) ? AR8216_PORT_STATUS_TXFLOW
: 0) |
810 AR8216_PORT_STATUS_DUPLEX
);
812 priv
->write(priv
, AR8216_REG_PORT_STATUS(port
),
813 AR8216_PORT_STATUS_LINK_AUTO
);
817 static const struct ar8xxx_chip ar8216_chip
= {
818 .caps
= AR8XXX_CAP_MIB_COUNTERS
,
820 .hw_init
= ar8216_hw_init
,
821 .init_globals
= ar8216_init_globals
,
822 .init_port
= ar8216_init_port
,
823 .setup_port
= ar8216_setup_port
,
824 .read_port_status
= ar8216_read_port_status
,
825 .atu_flush
= ar8216_atu_flush
,
826 .vtu_flush
= ar8216_vtu_flush
,
827 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
829 .num_mibs
= ARRAY_SIZE(ar8216_mibs
),
830 .mib_decs
= ar8216_mibs
,
834 ar8236_setup_port(struct ar8xxx_priv
*priv
, int port
, u32 members
)
840 pvid
= priv
->vlan_id
[priv
->pvid
[port
]];
841 if (priv
->chip_data
.ar8216
.vlan_tagged
& BIT(port
))
842 egress
= AR8216_OUT_ADD_VLAN
;
844 egress
= AR8216_OUT_STRIP_VLAN
;
845 ingress
= AR8216_IN_SECURE
;
848 egress
= AR8216_OUT_KEEP
;
849 ingress
= AR8216_IN_PORT_ONLY
;
852 ar8xxx_rmw(priv
, AR8216_REG_PORT_CTRL(port
),
853 AR8216_PORT_CTRL_LEARN
| AR8216_PORT_CTRL_VLAN_MODE
|
854 AR8216_PORT_CTRL_SINGLE_VLAN
| AR8216_PORT_CTRL_STATE
|
855 AR8216_PORT_CTRL_HEADER
| AR8216_PORT_CTRL_LEARN_LOCK
,
856 AR8216_PORT_CTRL_LEARN
|
857 (egress
<< AR8216_PORT_CTRL_VLAN_MODE_S
) |
858 (AR8216_PORT_STATE_FORWARD
<< AR8216_PORT_CTRL_STATE_S
));
860 ar8xxx_rmw(priv
, AR8236_REG_PORT_VLAN(port
),
861 AR8236_PORT_VLAN_DEFAULT_ID
,
862 (pvid
<< AR8236_PORT_VLAN_DEFAULT_ID_S
));
864 ar8xxx_rmw(priv
, AR8236_REG_PORT_VLAN2(port
),
865 AR8236_PORT_VLAN2_VLAN_MODE
|
866 AR8236_PORT_VLAN2_MEMBER
,
867 (ingress
<< AR8236_PORT_VLAN2_VLAN_MODE_S
) |
868 (members
<< AR8236_PORT_VLAN2_MEMBER_S
));
872 ar8236_hw_init(struct ar8xxx_priv
*priv
)
877 if (priv
->initialized
)
880 /* Initialize the PHYs */
882 for (i
= 0; i
< 5; i
++) {
883 mdiobus_write(bus
, i
, MII_ADVERTISE
,
884 ADVERTISE_ALL
| ADVERTISE_PAUSE_CAP
|
885 ADVERTISE_PAUSE_ASYM
);
886 mdiobus_write(bus
, i
, MII_BMCR
, BMCR_RESET
| BMCR_ANENABLE
);
890 priv
->initialized
= true;
895 ar8236_init_globals(struct ar8xxx_priv
*priv
)
897 /* enable jumbo frames */
898 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
899 AR8316_GCTRL_MTU
, 9018 + 8 + 2);
901 /* Enable MIB counters */
902 ar8xxx_rmw(priv
, AR8216_REG_MIB_FUNC
, AR8216_MIB_FUNC
| AR8236_MIB_EN
,
903 (AR8216_MIB_FUNC_NO_OP
<< AR8216_MIB_FUNC_S
) |
907 static const struct ar8xxx_chip ar8236_chip
= {
908 .caps
= AR8XXX_CAP_MIB_COUNTERS
,
909 .hw_init
= ar8236_hw_init
,
910 .init_globals
= ar8236_init_globals
,
911 .init_port
= ar8216_init_port
,
912 .setup_port
= ar8236_setup_port
,
913 .read_port_status
= ar8216_read_port_status
,
914 .atu_flush
= ar8216_atu_flush
,
915 .vtu_flush
= ar8216_vtu_flush
,
916 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
918 .num_mibs
= ARRAY_SIZE(ar8236_mibs
),
919 .mib_decs
= ar8236_mibs
,
923 ar8316_hw_init(struct ar8xxx_priv
*priv
)
929 val
= priv
->read(priv
, AR8316_REG_POSTRIP
);
931 if (priv
->phy
->interface
== PHY_INTERFACE_MODE_RGMII
) {
932 if (priv
->port4_phy
) {
933 /* value taken from Ubiquiti RouterStation Pro */
935 pr_info("ar8316: Using port 4 as PHY\n");
938 pr_info("ar8316: Using port 4 as switch port\n");
940 } else if (priv
->phy
->interface
== PHY_INTERFACE_MODE_GMII
) {
941 /* value taken from AVM Fritz!Box 7390 sources */
944 /* no known value for phy interface */
945 pr_err("ar8316: unsupported mii mode: %d.\n",
946 priv
->phy
->interface
);
953 priv
->write(priv
, AR8316_REG_POSTRIP
, newval
);
955 if (priv
->port4_phy
&&
956 priv
->phy
->interface
== PHY_INTERFACE_MODE_RGMII
) {
957 /* work around for phy4 rgmii mode */
958 ar8xxx_phy_dbg_write(priv
, 4, 0x12, 0x480c);
960 ar8xxx_phy_dbg_write(priv
, 4, 0x0, 0x824e);
962 ar8xxx_phy_dbg_write(priv
, 4, 0x5, 0x3d47);
966 /* Initialize the ports */
968 for (i
= 0; i
< 5; i
++) {
969 /* initialize the port itself */
970 mdiobus_write(bus
, i
, MII_ADVERTISE
,
971 ADVERTISE_ALL
| ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
);
972 mdiobus_write(bus
, i
, MII_CTRL1000
, ADVERTISE_1000FULL
);
973 mdiobus_write(bus
, i
, MII_BMCR
, BMCR_RESET
| BMCR_ANENABLE
);
979 priv
->initialized
= true;
984 ar8316_init_globals(struct ar8xxx_priv
*priv
)
986 /* standard atheros magic */
987 priv
->write(priv
, 0x38, 0xc000050e);
989 /* enable cpu port to receive multicast and broadcast frames */
990 priv
->write(priv
, AR8216_REG_FLOOD_MASK
, 0x003f003f);
992 /* enable jumbo frames */
993 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
994 AR8316_GCTRL_MTU
, 9018 + 8 + 2);
996 /* Enable MIB counters */
997 ar8xxx_rmw(priv
, AR8216_REG_MIB_FUNC
, AR8216_MIB_FUNC
| AR8236_MIB_EN
,
998 (AR8216_MIB_FUNC_NO_OP
<< AR8216_MIB_FUNC_S
) |
1002 static const struct ar8xxx_chip ar8316_chip
= {
1003 .caps
= AR8XXX_CAP_GIGE
| AR8XXX_CAP_MIB_COUNTERS
,
1004 .hw_init
= ar8316_hw_init
,
1005 .init_globals
= ar8316_init_globals
,
1006 .init_port
= ar8216_init_port
,
1007 .setup_port
= ar8216_setup_port
,
1008 .read_port_status
= ar8216_read_port_status
,
1009 .atu_flush
= ar8216_atu_flush
,
1010 .vtu_flush
= ar8216_vtu_flush
,
1011 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
1013 .num_mibs
= ARRAY_SIZE(ar8236_mibs
),
1014 .mib_decs
= ar8236_mibs
,
1018 ar8327_get_pad_cfg(struct ar8327_pad_cfg
*cfg
)
1026 switch (cfg
->mode
) {
1030 case AR8327_PAD_MAC2MAC_MII
:
1031 t
= AR8327_PAD_MAC_MII_EN
;
1033 t
|= AR8327_PAD_MAC_MII_RXCLK_SEL
;
1035 t
|= AR8327_PAD_MAC_MII_TXCLK_SEL
;
1038 case AR8327_PAD_MAC2MAC_GMII
:
1039 t
= AR8327_PAD_MAC_GMII_EN
;
1041 t
|= AR8327_PAD_MAC_GMII_RXCLK_SEL
;
1043 t
|= AR8327_PAD_MAC_GMII_TXCLK_SEL
;
1046 case AR8327_PAD_MAC_SGMII
:
1047 t
= AR8327_PAD_SGMII_EN
;
1050 * WAR for the QUalcomm Atheros AP136 board.
1051 * It seems that RGMII TX/RX delay settings needs to be
1052 * applied for SGMII mode as well, The ethernet is not
1053 * reliable without this.
1055 t
|= cfg
->txclk_delay_sel
<< AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S
;
1056 t
|= cfg
->rxclk_delay_sel
<< AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S
;
1057 if (cfg
->rxclk_delay_en
)
1058 t
|= AR8327_PAD_RGMII_RXCLK_DELAY_EN
;
1059 if (cfg
->txclk_delay_en
)
1060 t
|= AR8327_PAD_RGMII_TXCLK_DELAY_EN
;
1062 if (cfg
->sgmii_delay_en
)
1063 t
|= AR8327_PAD_SGMII_DELAY_EN
;
1067 case AR8327_PAD_MAC2PHY_MII
:
1068 t
= AR8327_PAD_PHY_MII_EN
;
1070 t
|= AR8327_PAD_PHY_MII_RXCLK_SEL
;
1072 t
|= AR8327_PAD_PHY_MII_TXCLK_SEL
;
1075 case AR8327_PAD_MAC2PHY_GMII
:
1076 t
= AR8327_PAD_PHY_GMII_EN
;
1077 if (cfg
->pipe_rxclk_sel
)
1078 t
|= AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL
;
1080 t
|= AR8327_PAD_PHY_GMII_RXCLK_SEL
;
1082 t
|= AR8327_PAD_PHY_GMII_TXCLK_SEL
;
1085 case AR8327_PAD_MAC_RGMII
:
1086 t
= AR8327_PAD_RGMII_EN
;
1087 t
|= cfg
->txclk_delay_sel
<< AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S
;
1088 t
|= cfg
->rxclk_delay_sel
<< AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S
;
1089 if (cfg
->rxclk_delay_en
)
1090 t
|= AR8327_PAD_RGMII_RXCLK_DELAY_EN
;
1091 if (cfg
->txclk_delay_en
)
1092 t
|= AR8327_PAD_RGMII_TXCLK_DELAY_EN
;
1095 case AR8327_PAD_PHY_GMII
:
1096 t
= AR8327_PAD_PHYX_GMII_EN
;
1099 case AR8327_PAD_PHY_RGMII
:
1100 t
= AR8327_PAD_PHYX_RGMII_EN
;
1103 case AR8327_PAD_PHY_MII
:
1104 t
= AR8327_PAD_PHYX_MII_EN
;
1112 ar8327_phy_fixup(struct ar8xxx_priv
*priv
, int phy
)
1114 switch (priv
->chip_rev
) {
1116 /* For 100M waveform */
1117 ar8xxx_phy_dbg_write(priv
, phy
, 0, 0x02ea);
1118 /* Turn on Gigabit clock */
1119 ar8xxx_phy_dbg_write(priv
, phy
, 0x3d, 0x68a0);
1123 ar8xxx_phy_mmd_write(priv
, phy
, 0x7, 0x3c);
1124 ar8xxx_phy_mmd_write(priv
, phy
, 0x4007, 0x0);
1127 ar8xxx_phy_mmd_write(priv
, phy
, 0x3, 0x800d);
1128 ar8xxx_phy_mmd_write(priv
, phy
, 0x4003, 0x803f);
1130 ar8xxx_phy_dbg_write(priv
, phy
, 0x3d, 0x6860);
1131 ar8xxx_phy_dbg_write(priv
, phy
, 0x5, 0x2c46);
1132 ar8xxx_phy_dbg_write(priv
, phy
, 0x3c, 0x6000);
1138 ar8327_get_port_init_status(struct ar8327_port_cfg
*cfg
)
1142 if (!cfg
->force_link
)
1143 return AR8216_PORT_STATUS_LINK_AUTO
;
1145 t
= AR8216_PORT_STATUS_TXMAC
| AR8216_PORT_STATUS_RXMAC
;
1146 t
|= cfg
->duplex
? AR8216_PORT_STATUS_DUPLEX
: 0;
1147 t
|= cfg
->rxpause
? AR8216_PORT_STATUS_RXFLOW
: 0;
1148 t
|= cfg
->txpause
? AR8216_PORT_STATUS_TXFLOW
: 0;
1150 switch (cfg
->speed
) {
1151 case AR8327_PORT_SPEED_10
:
1152 t
|= AR8216_PORT_SPEED_10M
;
1154 case AR8327_PORT_SPEED_100
:
1155 t
|= AR8216_PORT_SPEED_100M
;
1157 case AR8327_PORT_SPEED_1000
:
1158 t
|= AR8216_PORT_SPEED_1000M
;
1165 #define AR8327_LED_ENTRY(_num, _reg, _shift) \
1166 [_num] = { .reg = (_reg), .shift = (_shift) }
1168 static const struct ar8327_led_entry
1169 ar8327_led_map
[AR8327_NUM_LEDS
] = {
1170 AR8327_LED_ENTRY(AR8327_LED_PHY0_0
, 0, 14),
1171 AR8327_LED_ENTRY(AR8327_LED_PHY0_1
, 1, 14),
1172 AR8327_LED_ENTRY(AR8327_LED_PHY0_2
, 2, 14),
1174 AR8327_LED_ENTRY(AR8327_LED_PHY1_0
, 3, 8),
1175 AR8327_LED_ENTRY(AR8327_LED_PHY1_1
, 3, 10),
1176 AR8327_LED_ENTRY(AR8327_LED_PHY1_2
, 3, 12),
1178 AR8327_LED_ENTRY(AR8327_LED_PHY2_0
, 3, 14),
1179 AR8327_LED_ENTRY(AR8327_LED_PHY2_1
, 3, 16),
1180 AR8327_LED_ENTRY(AR8327_LED_PHY2_2
, 3, 18),
1182 AR8327_LED_ENTRY(AR8327_LED_PHY3_0
, 3, 20),
1183 AR8327_LED_ENTRY(AR8327_LED_PHY3_1
, 3, 22),
1184 AR8327_LED_ENTRY(AR8327_LED_PHY3_2
, 3, 24),
1186 AR8327_LED_ENTRY(AR8327_LED_PHY4_0
, 0, 30),
1187 AR8327_LED_ENTRY(AR8327_LED_PHY4_1
, 1, 30),
1188 AR8327_LED_ENTRY(AR8327_LED_PHY4_2
, 2, 30),
1192 ar8327_set_led_pattern(struct ar8xxx_priv
*priv
, unsigned int led_num
,
1193 enum ar8327_led_pattern pattern
)
1195 const struct ar8327_led_entry
*entry
;
1197 entry
= &ar8327_led_map
[led_num
];
1198 ar8xxx_rmw(priv
, AR8327_REG_LED_CTRL(entry
->reg
),
1199 (3 << entry
->shift
), pattern
<< entry
->shift
);
1203 ar8327_led_work_func(struct work_struct
*work
)
1205 struct ar8327_led
*aled
;
1208 aled
= container_of(work
, struct ar8327_led
, led_work
);
1210 spin_lock(&aled
->lock
);
1211 pattern
= aled
->pattern
;
1212 spin_unlock(&aled
->lock
);
1214 ar8327_set_led_pattern(aled
->sw_priv
, aled
->led_num
,
1219 ar8327_led_schedule_change(struct ar8327_led
*aled
, u8 pattern
)
1221 if (aled
->pattern
== pattern
)
1224 aled
->pattern
= pattern
;
1225 schedule_work(&aled
->led_work
);
1228 static inline struct ar8327_led
*
1229 led_cdev_to_ar8327_led(struct led_classdev
*led_cdev
)
1231 return container_of(led_cdev
, struct ar8327_led
, cdev
);
1235 ar8327_led_blink_set(struct led_classdev
*led_cdev
,
1236 unsigned long *delay_on
,
1237 unsigned long *delay_off
)
1239 struct ar8327_led
*aled
= led_cdev_to_ar8327_led(led_cdev
);
1241 if (*delay_on
== 0 && *delay_off
== 0) {
1246 if (*delay_on
!= 125 || *delay_off
!= 125) {
1248 * The hardware only supports blinking at 4Hz. Fall back
1249 * to software implementation in other cases.
1254 spin_lock(&aled
->lock
);
1256 aled
->enable_hw_mode
= false;
1257 ar8327_led_schedule_change(aled
, AR8327_LED_PATTERN_BLINK
);
1259 spin_unlock(&aled
->lock
);
1265 ar8327_led_set_brightness(struct led_classdev
*led_cdev
,
1266 enum led_brightness brightness
)
1268 struct ar8327_led
*aled
= led_cdev_to_ar8327_led(led_cdev
);
1272 active
= (brightness
!= LED_OFF
);
1273 active
^= aled
->active_low
;
1275 pattern
= (active
) ? AR8327_LED_PATTERN_ON
:
1276 AR8327_LED_PATTERN_OFF
;
1278 spin_lock(&aled
->lock
);
1280 aled
->enable_hw_mode
= false;
1281 ar8327_led_schedule_change(aled
, pattern
);
1283 spin_unlock(&aled
->lock
);
1287 ar8327_led_enable_hw_mode_show(struct device
*dev
,
1288 struct device_attribute
*attr
,
1291 struct led_classdev
*led_cdev
= dev_get_drvdata(dev
);
1292 struct ar8327_led
*aled
= led_cdev_to_ar8327_led(led_cdev
);
1295 spin_lock(&aled
->lock
);
1296 ret
+= sprintf(buf
, "%d\n", aled
->enable_hw_mode
);
1297 spin_unlock(&aled
->lock
);
1303 ar8327_led_enable_hw_mode_store(struct device
*dev
,
1304 struct device_attribute
*attr
,
1308 struct led_classdev
*led_cdev
= dev_get_drvdata(dev
);
1309 struct ar8327_led
*aled
= led_cdev_to_ar8327_led(led_cdev
);
1314 ret
= kstrtou8(buf
, 10, &value
);
1318 spin_lock(&aled
->lock
);
1320 aled
->enable_hw_mode
= !!value
;
1321 if (aled
->enable_hw_mode
)
1322 pattern
= AR8327_LED_PATTERN_RULE
;
1324 pattern
= AR8327_LED_PATTERN_OFF
;
1326 ar8327_led_schedule_change(aled
, pattern
);
1328 spin_unlock(&aled
->lock
);
1333 static DEVICE_ATTR(enable_hw_mode
, S_IRUGO
| S_IWUSR
,
1334 ar8327_led_enable_hw_mode_show
,
1335 ar8327_led_enable_hw_mode_store
);
1338 ar8327_led_register(struct ar8xxx_priv
*priv
, struct ar8327_led
*aled
)
1342 ret
= led_classdev_register(NULL
, &aled
->cdev
);
1346 if (aled
->mode
== AR8327_LED_MODE_HW
) {
1347 ret
= device_create_file(aled
->cdev
.dev
,
1348 &dev_attr_enable_hw_mode
);
1350 goto err_unregister
;
1356 led_classdev_unregister(&aled
->cdev
);
1361 ar8327_led_unregister(struct ar8327_led
*aled
)
1363 if (aled
->mode
== AR8327_LED_MODE_HW
)
1364 device_remove_file(aled
->cdev
.dev
, &dev_attr_enable_hw_mode
);
1366 led_classdev_unregister(&aled
->cdev
);
1367 cancel_work_sync(&aled
->led_work
);
1371 ar8327_led_create(struct ar8xxx_priv
*priv
,
1372 const struct ar8327_led_info
*led_info
)
1374 struct ar8327_data
*data
= &priv
->chip_data
.ar8327
;
1375 struct ar8327_led
*aled
;
1378 if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS
))
1381 if (!led_info
->name
)
1384 if (led_info
->led_num
>= AR8327_NUM_LEDS
)
1387 aled
= kzalloc(sizeof(*aled
) + strlen(led_info
->name
) + 1,
1392 aled
->sw_priv
= priv
;
1393 aled
->led_num
= led_info
->led_num
;
1394 aled
->active_low
= led_info
->active_low
;
1395 aled
->mode
= led_info
->mode
;
1397 if (aled
->mode
== AR8327_LED_MODE_HW
)
1398 aled
->enable_hw_mode
= true;
1400 aled
->name
= (char *)(aled
+ 1);
1401 strcpy(aled
->name
, led_info
->name
);
1403 aled
->cdev
.name
= aled
->name
;
1404 aled
->cdev
.brightness_set
= ar8327_led_set_brightness
;
1405 aled
->cdev
.blink_set
= ar8327_led_blink_set
;
1406 aled
->cdev
.default_trigger
= led_info
->default_trigger
;
1408 spin_lock_init(&aled
->lock
);
1409 mutex_init(&aled
->mutex
);
1410 INIT_WORK(&aled
->led_work
, ar8327_led_work_func
);
1412 ret
= ar8327_led_register(priv
, aled
);
1416 data
->leds
[data
->num_leds
++] = aled
;
1426 ar8327_led_destroy(struct ar8327_led
*aled
)
1428 ar8327_led_unregister(aled
);
1433 ar8327_leds_init(struct ar8xxx_priv
*priv
)
1435 struct ar8327_data
*data
;
1438 if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS
))
1441 data
= &priv
->chip_data
.ar8327
;
1443 for (i
= 0; i
< data
->num_leds
; i
++) {
1444 struct ar8327_led
*aled
;
1446 aled
= data
->leds
[i
];
1448 if (aled
->enable_hw_mode
)
1449 aled
->pattern
= AR8327_LED_PATTERN_RULE
;
1451 aled
->pattern
= AR8327_LED_PATTERN_OFF
;
1453 ar8327_set_led_pattern(priv
, aled
->led_num
, aled
->pattern
);
1458 ar8327_leds_cleanup(struct ar8xxx_priv
*priv
)
1460 struct ar8327_data
*data
= &priv
->chip_data
.ar8327
;
1463 if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS
))
1466 for (i
= 0; i
< data
->num_leds
; i
++) {
1467 struct ar8327_led
*aled
;
1469 aled
= data
->leds
[i
];
1470 ar8327_led_destroy(aled
);
1477 ar8327_hw_config_pdata(struct ar8xxx_priv
*priv
,
1478 struct ar8327_platform_data
*pdata
)
1480 struct ar8327_led_cfg
*led_cfg
;
1481 struct ar8327_data
*data
;
1488 priv
->get_port_link
= pdata
->get_port_link
;
1490 data
= &priv
->chip_data
.ar8327
;
1492 data
->port0_status
= ar8327_get_port_init_status(&pdata
->port0_cfg
);
1493 data
->port6_status
= ar8327_get_port_init_status(&pdata
->port6_cfg
);
1495 t
= ar8327_get_pad_cfg(pdata
->pad0_cfg
);
1496 if (chip_is_ar8337(priv
))
1497 t
|= AR8337_PAD_MAC06_EXCHANGE_EN
;
1499 priv
->write(priv
, AR8327_REG_PAD0_MODE
, t
);
1500 t
= ar8327_get_pad_cfg(pdata
->pad5_cfg
);
1501 priv
->write(priv
, AR8327_REG_PAD5_MODE
, t
);
1502 t
= ar8327_get_pad_cfg(pdata
->pad6_cfg
);
1503 priv
->write(priv
, AR8327_REG_PAD6_MODE
, t
);
1505 pos
= priv
->read(priv
, AR8327_REG_POWER_ON_STRIP
);
1508 led_cfg
= pdata
->led_cfg
;
1510 if (led_cfg
->open_drain
)
1511 new_pos
|= AR8327_POWER_ON_STRIP_LED_OPEN_EN
;
1513 new_pos
&= ~AR8327_POWER_ON_STRIP_LED_OPEN_EN
;
1515 priv
->write(priv
, AR8327_REG_LED_CTRL0
, led_cfg
->led_ctrl0
);
1516 priv
->write(priv
, AR8327_REG_LED_CTRL1
, led_cfg
->led_ctrl1
);
1517 priv
->write(priv
, AR8327_REG_LED_CTRL2
, led_cfg
->led_ctrl2
);
1518 priv
->write(priv
, AR8327_REG_LED_CTRL3
, led_cfg
->led_ctrl3
);
1521 new_pos
|= AR8327_POWER_ON_STRIP_POWER_ON_SEL
;
1524 if (pdata
->sgmii_cfg
) {
1525 t
= pdata
->sgmii_cfg
->sgmii_ctrl
;
1526 if (priv
->chip_rev
== 1)
1527 t
|= AR8327_SGMII_CTRL_EN_PLL
|
1528 AR8327_SGMII_CTRL_EN_RX
|
1529 AR8327_SGMII_CTRL_EN_TX
;
1531 t
&= ~(AR8327_SGMII_CTRL_EN_PLL
|
1532 AR8327_SGMII_CTRL_EN_RX
|
1533 AR8327_SGMII_CTRL_EN_TX
);
1535 priv
->write(priv
, AR8327_REG_SGMII_CTRL
, t
);
1537 if (pdata
->sgmii_cfg
->serdes_aen
)
1538 new_pos
&= ~AR8327_POWER_ON_STRIP_SERDES_AEN
;
1540 new_pos
|= AR8327_POWER_ON_STRIP_SERDES_AEN
;
1543 priv
->write(priv
, AR8327_REG_POWER_ON_STRIP
, new_pos
);
1545 if (pdata
->leds
&& pdata
->num_leds
) {
1548 data
->leds
= kzalloc(pdata
->num_leds
* sizeof(void *),
1553 for (i
= 0; i
< pdata
->num_leds
; i
++)
1554 ar8327_led_create(priv
, &pdata
->leds
[i
]);
1562 ar8327_hw_config_of(struct ar8xxx_priv
*priv
, struct device_node
*np
)
1564 const __be32
*paddr
;
1568 paddr
= of_get_property(np
, "qca,ar8327-initvals", &len
);
1569 if (!paddr
|| len
< (2 * sizeof(*paddr
)))
1572 len
/= sizeof(*paddr
);
1574 for (i
= 0; i
< len
- 1; i
+= 2) {
1578 reg
= be32_to_cpup(paddr
+ i
);
1579 val
= be32_to_cpup(paddr
+ i
+ 1);
1582 case AR8327_REG_PORT_STATUS(0):
1583 priv
->chip_data
.ar8327
.port0_status
= val
;
1585 case AR8327_REG_PORT_STATUS(6):
1586 priv
->chip_data
.ar8327
.port6_status
= val
;
1589 priv
->write(priv
, reg
, val
);
1598 ar8327_hw_config_of(struct ar8xxx_priv
*priv
, struct device_node
*np
)
1605 ar8327_hw_init(struct ar8xxx_priv
*priv
)
1607 struct mii_bus
*bus
;
1611 if (priv
->phy
->dev
.of_node
)
1612 ret
= ar8327_hw_config_of(priv
, priv
->phy
->dev
.of_node
);
1614 ret
= ar8327_hw_config_pdata(priv
,
1615 priv
->phy
->dev
.platform_data
);
1620 ar8327_leds_init(priv
);
1622 bus
= priv
->mii_bus
;
1623 for (i
= 0; i
< AR8327_NUM_PHYS
; i
++) {
1624 ar8327_phy_fixup(priv
, i
);
1626 /* start aneg on the PHY */
1627 mdiobus_write(bus
, i
, MII_ADVERTISE
, ADVERTISE_ALL
|
1628 ADVERTISE_PAUSE_CAP
|
1629 ADVERTISE_PAUSE_ASYM
);
1630 mdiobus_write(bus
, i
, MII_CTRL1000
, ADVERTISE_1000FULL
);
1631 mdiobus_write(bus
, i
, MII_BMCR
, BMCR_RESET
| BMCR_ANENABLE
);
1640 ar8327_cleanup(struct ar8xxx_priv
*priv
)
1642 ar8327_leds_cleanup(priv
);
1646 ar8327_init_globals(struct ar8xxx_priv
*priv
)
1650 /* enable CPU port and disable mirror port */
1651 t
= AR8327_FWD_CTRL0_CPU_PORT_EN
|
1652 AR8327_FWD_CTRL0_MIRROR_PORT
;
1653 priv
->write(priv
, AR8327_REG_FWD_CTRL0
, t
);
1655 /* forward multicast and broadcast frames to CPU */
1656 t
= (AR8327_PORTS_ALL
<< AR8327_FWD_CTRL1_UC_FLOOD_S
) |
1657 (AR8327_PORTS_ALL
<< AR8327_FWD_CTRL1_MC_FLOOD_S
) |
1658 (AR8327_PORTS_ALL
<< AR8327_FWD_CTRL1_BC_FLOOD_S
);
1659 priv
->write(priv
, AR8327_REG_FWD_CTRL1
, t
);
1661 /* enable jumbo frames */
1662 ar8xxx_rmw(priv
, AR8327_REG_MAX_FRAME_SIZE
,
1663 AR8327_MAX_FRAME_SIZE_MTU
, 9018 + 8 + 2);
1665 /* Enable MIB counters */
1666 ar8xxx_reg_set(priv
, AR8327_REG_MODULE_EN
,
1667 AR8327_MODULE_EN_MIB
);
1671 ar8327_init_port(struct ar8xxx_priv
*priv
, int port
)
1675 if (port
== AR8216_PORT_CPU
)
1676 t
= priv
->chip_data
.ar8327
.port0_status
;
1678 t
= priv
->chip_data
.ar8327
.port6_status
;
1680 t
= AR8216_PORT_STATUS_LINK_AUTO
;
1682 priv
->write(priv
, AR8327_REG_PORT_STATUS(port
), t
);
1683 priv
->write(priv
, AR8327_REG_PORT_HEADER(port
), 0);
1685 t
= 1 << AR8327_PORT_VLAN0_DEF_SVID_S
;
1686 t
|= 1 << AR8327_PORT_VLAN0_DEF_CVID_S
;
1687 priv
->write(priv
, AR8327_REG_PORT_VLAN0(port
), t
);
1689 t
= AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH
<< AR8327_PORT_VLAN1_OUT_MODE_S
;
1690 priv
->write(priv
, AR8327_REG_PORT_VLAN1(port
), t
);
1692 t
= AR8327_PORT_LOOKUP_LEARN
;
1693 t
|= AR8216_PORT_STATE_FORWARD
<< AR8327_PORT_LOOKUP_STATE_S
;
1694 priv
->write(priv
, AR8327_REG_PORT_LOOKUP(port
), t
);
1698 ar8327_read_port_status(struct ar8xxx_priv
*priv
, int port
)
1700 return priv
->read(priv
, AR8327_REG_PORT_STATUS(port
));
1704 ar8327_atu_flush(struct ar8xxx_priv
*priv
)
1708 ret
= ar8216_wait_bit(priv
, AR8327_REG_ATU_FUNC
,
1709 AR8327_ATU_FUNC_BUSY
, 0);
1711 priv
->write(priv
, AR8327_REG_ATU_FUNC
,
1712 AR8327_ATU_FUNC_OP_FLUSH
);
1718 ar8327_vtu_op(struct ar8xxx_priv
*priv
, u32 op
, u32 val
)
1720 if (ar8216_wait_bit(priv
, AR8327_REG_VTU_FUNC1
,
1721 AR8327_VTU_FUNC1_BUSY
, 0))
1724 if ((op
& AR8327_VTU_FUNC1_OP
) == AR8327_VTU_FUNC1_OP_LOAD
)
1725 priv
->write(priv
, AR8327_REG_VTU_FUNC0
, val
);
1727 op
|= AR8327_VTU_FUNC1_BUSY
;
1728 priv
->write(priv
, AR8327_REG_VTU_FUNC1
, op
);
1732 ar8327_vtu_flush(struct ar8xxx_priv
*priv
)
1734 ar8327_vtu_op(priv
, AR8327_VTU_FUNC1_OP_FLUSH
, 0);
1738 ar8327_vtu_load_vlan(struct ar8xxx_priv
*priv
, u32 vlan
)
1743 u32 vid
= priv
->vlan_id
[vlan
];
1744 u32 port_mask
= priv
->vlan_table
[vlan
];
1745 u32 tagged
= priv
->chip_data
.ar8327
.vlan_tagged
[vlan
];
1748 op
= AR8327_VTU_FUNC1_OP_LOAD
| (vid
<< AR8327_VTU_FUNC1_VID_S
);
1749 val
= AR8327_VTU_FUNC0_VALID
| AR8327_VTU_FUNC0_IVL
;
1750 for (i
= 0; i
< AR8327_NUM_PORTS
; i
++) {
1753 if ((port_mask
& BIT(i
)) == 0)
1754 mode
= AR8327_VTU_FUNC0_EG_MODE_NOT
;
1755 else if (priv
->vlan
== 0)
1756 mode
= AR8327_VTU_FUNC0_EG_MODE_KEEP
;
1757 else if (tagged
& BIT(i
))
1758 mode
= AR8327_VTU_FUNC0_EG_MODE_TAG
;
1760 mode
= AR8327_VTU_FUNC0_EG_MODE_UNTAG
;
1762 val
|= mode
<< AR8327_VTU_FUNC0_EG_MODE_S(i
);
1764 ar8327_vtu_op(priv
, op
, val
);
1768 ar8327_setup_port(struct ar8xxx_priv
*priv
, int port
, u32 members
)
1776 pvid
= priv
->vlan_id
[priv
->pvid
[port
]];
1777 mode
= AR8327_PORT_VLAN1_OUT_MODE_UNMOD
;
1778 ingress
= AR8216_IN_SECURE
;
1781 mode
= AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH
;
1782 ingress
= AR8216_IN_PORT_ONLY
;
1785 t
= pvid
<< AR8327_PORT_VLAN0_DEF_SVID_S
;
1786 t
|= pvid
<< AR8327_PORT_VLAN0_DEF_CVID_S
;
1787 priv
->write(priv
, AR8327_REG_PORT_VLAN0(port
), t
);
1789 t
= AR8327_PORT_VLAN1_PORT_VLAN_PROP
;
1790 t
|= mode
<< AR8327_PORT_VLAN1_OUT_MODE_S
;
1791 priv
->write(priv
, AR8327_REG_PORT_VLAN1(port
), t
);
1794 t
|= AR8327_PORT_LOOKUP_LEARN
;
1795 t
|= ingress
<< AR8327_PORT_LOOKUP_IN_MODE_S
;
1796 t
|= AR8216_PORT_STATE_FORWARD
<< AR8327_PORT_LOOKUP_STATE_S
;
1797 priv
->write(priv
, AR8327_REG_PORT_LOOKUP(port
), t
);
1800 static const struct ar8xxx_chip ar8327_chip
= {
1801 .caps
= AR8XXX_CAP_GIGE
| AR8XXX_CAP_MIB_COUNTERS
,
1802 .hw_init
= ar8327_hw_init
,
1803 .cleanup
= ar8327_cleanup
,
1804 .init_globals
= ar8327_init_globals
,
1805 .init_port
= ar8327_init_port
,
1806 .setup_port
= ar8327_setup_port
,
1807 .read_port_status
= ar8327_read_port_status
,
1808 .atu_flush
= ar8327_atu_flush
,
1809 .vtu_flush
= ar8327_vtu_flush
,
1810 .vtu_load_vlan
= ar8327_vtu_load_vlan
,
1812 .num_mibs
= ARRAY_SIZE(ar8236_mibs
),
1813 .mib_decs
= ar8236_mibs
,
1817 ar8xxx_sw_set_vlan(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1818 struct switch_val
*val
)
1820 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1821 priv
->vlan
= !!val
->value
.i
;
1826 ar8xxx_sw_get_vlan(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1827 struct switch_val
*val
)
1829 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1830 val
->value
.i
= priv
->vlan
;
1836 ar8xxx_sw_set_pvid(struct switch_dev
*dev
, int port
, int vlan
)
1838 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1840 /* make sure no invalid PVIDs get set */
1842 if (vlan
>= dev
->vlans
)
1845 priv
->pvid
[port
] = vlan
;
1850 ar8xxx_sw_get_pvid(struct switch_dev
*dev
, int port
, int *vlan
)
1852 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1853 *vlan
= priv
->pvid
[port
];
1858 ar8xxx_sw_set_vid(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1859 struct switch_val
*val
)
1861 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1862 priv
->vlan_id
[val
->port_vlan
] = val
->value
.i
;
1867 ar8xxx_sw_get_vid(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1868 struct switch_val
*val
)
1870 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1871 val
->value
.i
= priv
->vlan_id
[val
->port_vlan
];
1876 ar8xxx_sw_get_port_link(struct switch_dev
*dev
, int port
,
1877 struct switch_port_link
*link
)
1879 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1881 ar8216_read_port_link(priv
, port
, link
);
1886 ar8xxx_sw_get_ports(struct switch_val
*val
, int ports
, u8 port_mask
, u8 tagged
)
1890 for (i
= 0; i
< ports
; i
++) {
1891 struct switch_port
*p
;
1893 if (!(port_mask
& BIT(i
)))
1896 p
= &val
->value
.ports
[val
->len
++];
1898 if (tagged
& BIT(i
))
1899 p
->flags
= BIT(SWITCH_PORT_FLAG_TAGGED
);
1907 ar8216_sw_get_ports(struct switch_dev
*dev
, struct switch_val
*val
)
1909 int ports
= dev
->ports
;
1910 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1911 u8 port_mask
= priv
->vlan_table
[val
->port_vlan
];
1912 u8 tagged
= priv
->chip_data
.ar8216
.vlan_tagged
;
1914 return ar8xxx_sw_get_ports(val
, ports
, port_mask
, tagged
);
1918 ar8327_sw_get_ports(struct switch_dev
*dev
, struct switch_val
*val
)
1920 int ports
= dev
->ports
;
1921 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1922 u8 port_mask
= priv
->vlan_table
[val
->port_vlan
];
1923 u8 tagged
= priv
->chip_data
.ar8327
.vlan_tagged
[val
->port_vlan
];
1925 return ar8xxx_sw_get_ports(val
, ports
, port_mask
, tagged
);
1929 ar8216_sw_set_ports(struct switch_dev
*dev
, struct switch_val
*val
)
1931 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1932 u8
*vt
= &priv
->vlan_table
[val
->port_vlan
];
1933 u8
*tagged
= &priv
->chip_data
.ar8216
.vlan_tagged
;
1938 for (i
= 0; i
< val
->len
; i
++) {
1939 struct switch_port
*p
= &val
->value
.ports
[i
];
1941 if (p
->flags
& BIT(SWITCH_PORT_FLAG_TAGGED
)) {
1943 /* if port was untagged before then
1944 * remove him from other vlans */
1945 if(*tagged
& BIT(p
->id
)){
1946 for (j
= 0; j
< AR8X16_MAX_VLANS
; j
++) {
1947 if (j
== val
->port_vlan
)
1950 priv
->vlan_table
[j
] &= ~(BIT(p
->id
));
1954 *tagged
|= BIT(p
->id
);
1956 *tagged
&= ~(BIT(p
->id
));
1957 priv
->pvid
[p
->id
] = val
->port_vlan
;
1959 /* make sure that an untagged port does not
1960 * appear in other vlans */
1961 for (j
= 0; j
< AR8X16_MAX_VLANS
; j
++) {
1962 if (j
== val
->port_vlan
)
1965 priv
->vlan_table
[j
] &= ~(BIT(p
->id
));
1975 ar8327_sw_set_ports(struct switch_dev
*dev
, struct switch_val
*val
)
1977 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1978 u8
*vt
= &priv
->vlan_table
[val
->port_vlan
];
1979 u8
*vlan_tagged
= priv
->chip_data
.ar8327
.vlan_tagged
;
1980 u8
*tagged
= &vlan_tagged
[val
->port_vlan
];
1986 for (i
= 0; i
< val
->len
; i
++) {
1987 struct switch_port
*p
= &val
->value
.ports
[i
];
1989 if (p
->flags
& BIT(SWITCH_PORT_FLAG_TAGGED
)) {
1990 *tagged
|= BIT(p
->id
);
1992 priv
->pvid
[p
->id
] = val
->port_vlan
;
2001 ar8327_set_mirror_regs(struct ar8xxx_priv
*priv
)
2005 /* reset all mirror registers */
2006 ar8xxx_rmw(priv
, AR8327_REG_FWD_CTRL0
,
2007 AR8327_FWD_CTRL0_MIRROR_PORT
,
2008 (0xF << AR8327_FWD_CTRL0_MIRROR_PORT_S
));
2009 for (port
= 0; port
< AR8327_NUM_PORTS
; port
++) {
2010 ar8xxx_rmw(priv
, AR8327_REG_PORT_LOOKUP(port
),
2011 AR8327_PORT_LOOKUP_ING_MIRROR_EN
,
2014 ar8xxx_rmw(priv
, AR8327_REG_PORT_HOL_CTRL1(port
),
2015 AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN
,
2019 /* now enable mirroring if necessary */
2020 if (priv
->source_port
>= AR8327_NUM_PORTS
||
2021 priv
->monitor_port
>= AR8327_NUM_PORTS
||
2022 priv
->source_port
== priv
->monitor_port
) {
2026 ar8xxx_rmw(priv
, AR8327_REG_FWD_CTRL0
,
2027 AR8327_FWD_CTRL0_MIRROR_PORT
,
2028 (priv
->monitor_port
<< AR8327_FWD_CTRL0_MIRROR_PORT_S
));
2030 if (priv
->mirror_rx
)
2031 ar8xxx_rmw(priv
, AR8327_REG_PORT_LOOKUP(priv
->source_port
),
2032 AR8327_PORT_LOOKUP_ING_MIRROR_EN
,
2033 AR8327_PORT_LOOKUP_ING_MIRROR_EN
);
2035 if (priv
->mirror_tx
)
2036 ar8xxx_rmw(priv
, AR8327_REG_PORT_HOL_CTRL1(priv
->source_port
),
2037 AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN
,
2038 AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN
);
2042 ar8216_set_mirror_regs(struct ar8xxx_priv
*priv
)
2046 /* reset all mirror registers */
2047 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CPUPORT
,
2048 AR8216_GLOBAL_CPUPORT_MIRROR_PORT
,
2049 (0xF << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S
));
2050 for (port
= 0; port
< AR8216_NUM_PORTS
; port
++) {
2051 ar8xxx_rmw(priv
, AR8216_REG_PORT_CTRL(port
),
2052 AR8216_PORT_CTRL_MIRROR_RX
,
2055 ar8xxx_rmw(priv
, AR8216_REG_PORT_CTRL(port
),
2056 AR8216_PORT_CTRL_MIRROR_TX
,
2060 /* now enable mirroring if necessary */
2061 if (priv
->source_port
>= AR8216_NUM_PORTS
||
2062 priv
->monitor_port
>= AR8216_NUM_PORTS
||
2063 priv
->source_port
== priv
->monitor_port
) {
2067 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CPUPORT
,
2068 AR8216_GLOBAL_CPUPORT_MIRROR_PORT
,
2069 (priv
->monitor_port
<< AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S
));
2071 if (priv
->mirror_rx
)
2072 ar8xxx_rmw(priv
, AR8216_REG_PORT_CTRL(priv
->source_port
),
2073 AR8216_PORT_CTRL_MIRROR_RX
,
2074 AR8216_PORT_CTRL_MIRROR_RX
);
2076 if (priv
->mirror_tx
)
2077 ar8xxx_rmw(priv
, AR8216_REG_PORT_CTRL(priv
->source_port
),
2078 AR8216_PORT_CTRL_MIRROR_TX
,
2079 AR8216_PORT_CTRL_MIRROR_TX
);
2083 ar8xxx_set_mirror_regs(struct ar8xxx_priv
*priv
)
2085 if (chip_is_ar8327(priv
) || chip_is_ar8337(priv
)) {
2086 ar8327_set_mirror_regs(priv
);
2088 ar8216_set_mirror_regs(priv
);
2093 ar8xxx_sw_hw_apply(struct switch_dev
*dev
)
2095 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
2096 u8 portmask
[AR8X16_MAX_PORTS
];
2099 mutex_lock(&priv
->reg_mutex
);
2100 /* flush all vlan translation unit entries */
2101 priv
->chip
->vtu_flush(priv
);
2103 memset(portmask
, 0, sizeof(portmask
));
2105 /* calculate the port destination masks and load vlans
2106 * into the vlan translation unit */
2107 for (j
= 0; j
< AR8X16_MAX_VLANS
; j
++) {
2108 u8 vp
= priv
->vlan_table
[j
];
2113 for (i
= 0; i
< dev
->ports
; i
++) {
2116 portmask
[i
] |= vp
& ~mask
;
2118 priv
->chip
->vtu_load_vlan(priv
, j
);
2122 * isolate all ports, but connect them to the cpu port */
2123 for (i
= 0; i
< dev
->ports
; i
++) {
2124 if (i
== AR8216_PORT_CPU
)
2127 portmask
[i
] = BIT(AR8216_PORT_CPU
);
2128 portmask
[AR8216_PORT_CPU
] |= BIT(i
);
2132 /* update the port destination mask registers and tag settings */
2133 for (i
= 0; i
< dev
->ports
; i
++) {
2134 priv
->chip
->setup_port(priv
, i
, portmask
[i
]);
2137 ar8xxx_set_mirror_regs(priv
);
2139 mutex_unlock(&priv
->reg_mutex
);
2144 ar8xxx_sw_reset_switch(struct switch_dev
*dev
)
2146 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
2149 mutex_lock(&priv
->reg_mutex
);
2150 memset(&priv
->vlan
, 0, sizeof(struct ar8xxx_priv
) -
2151 offsetof(struct ar8xxx_priv
, vlan
));
2153 for (i
= 0; i
< AR8X16_MAX_VLANS
; i
++)
2154 priv
->vlan_id
[i
] = i
;
2156 /* Configure all ports */
2157 for (i
= 0; i
< dev
->ports
; i
++)
2158 priv
->chip
->init_port(priv
, i
);
2160 priv
->mirror_rx
= false;
2161 priv
->mirror_tx
= false;
2162 priv
->source_port
= 0;
2163 priv
->monitor_port
= 0;
2165 priv
->chip
->init_globals(priv
);
2167 mutex_unlock(&priv
->reg_mutex
);
2169 return ar8xxx_sw_hw_apply(dev
);
2173 ar8xxx_sw_set_reset_mibs(struct switch_dev
*dev
,
2174 const struct switch_attr
*attr
,
2175 struct switch_val
*val
)
2177 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
2181 if (!ar8xxx_has_mib_counters(priv
))
2184 mutex_lock(&priv
->mib_lock
);
2186 len
= priv
->dev
.ports
* priv
->chip
->num_mibs
*
2187 sizeof(*priv
->mib_stats
);
2188 memset(priv
->mib_stats
, '\0', len
);
2189 ret
= ar8xxx_mib_flush(priv
);
2196 mutex_unlock(&priv
->mib_lock
);
2201 ar8xxx_sw_set_mirror_rx_enable(struct switch_dev
*dev
,
2202 const struct switch_attr
*attr
,
2203 struct switch_val
*val
)
2205 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
2207 mutex_lock(&priv
->reg_mutex
);
2208 priv
->mirror_rx
= !!val
->value
.i
;
2209 ar8xxx_set_mirror_regs(priv
);
2210 mutex_unlock(&priv
->reg_mutex
);
2216 ar8xxx_sw_get_mirror_rx_enable(struct switch_dev
*dev
,
2217 const struct switch_attr
*attr
,
2218 struct switch_val
*val
)
2220 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
2221 val
->value
.i
= priv
->mirror_rx
;
2226 ar8xxx_sw_set_mirror_tx_enable(struct switch_dev
*dev
,
2227 const struct switch_attr
*attr
,
2228 struct switch_val
*val
)
2230 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
2232 mutex_lock(&priv
->reg_mutex
);
2233 priv
->mirror_tx
= !!val
->value
.i
;
2234 ar8xxx_set_mirror_regs(priv
);
2235 mutex_unlock(&priv
->reg_mutex
);
2241 ar8xxx_sw_get_mirror_tx_enable(struct switch_dev
*dev
,
2242 const struct switch_attr
*attr
,
2243 struct switch_val
*val
)
2245 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
2246 val
->value
.i
= priv
->mirror_tx
;
2251 ar8xxx_sw_set_mirror_monitor_port(struct switch_dev
*dev
,
2252 const struct switch_attr
*attr
,
2253 struct switch_val
*val
)
2255 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
2257 mutex_lock(&priv
->reg_mutex
);
2258 priv
->monitor_port
= val
->value
.i
;
2259 ar8xxx_set_mirror_regs(priv
);
2260 mutex_unlock(&priv
->reg_mutex
);
2266 ar8xxx_sw_get_mirror_monitor_port(struct switch_dev
*dev
,
2267 const struct switch_attr
*attr
,
2268 struct switch_val
*val
)
2270 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
2271 val
->value
.i
= priv
->monitor_port
;
2276 ar8xxx_sw_set_mirror_source_port(struct switch_dev
*dev
,
2277 const struct switch_attr
*attr
,
2278 struct switch_val
*val
)
2280 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
2282 mutex_lock(&priv
->reg_mutex
);
2283 priv
->source_port
= val
->value
.i
;
2284 ar8xxx_set_mirror_regs(priv
);
2285 mutex_unlock(&priv
->reg_mutex
);
2291 ar8xxx_sw_get_mirror_source_port(struct switch_dev
*dev
,
2292 const struct switch_attr
*attr
,
2293 struct switch_val
*val
)
2295 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
2296 val
->value
.i
= priv
->source_port
;
2301 ar8xxx_sw_set_port_reset_mib(struct switch_dev
*dev
,
2302 const struct switch_attr
*attr
,
2303 struct switch_val
*val
)
2305 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
2309 if (!ar8xxx_has_mib_counters(priv
))
2312 port
= val
->port_vlan
;
2313 if (port
>= dev
->ports
)
2316 mutex_lock(&priv
->mib_lock
);
2317 ret
= ar8xxx_mib_capture(priv
);
2321 ar8xxx_mib_fetch_port_stat(priv
, port
, true);
2326 mutex_unlock(&priv
->mib_lock
);
2331 ar8xxx_sw_get_port_mib(struct switch_dev
*dev
,
2332 const struct switch_attr
*attr
,
2333 struct switch_val
*val
)
2335 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
2336 const struct ar8xxx_chip
*chip
= priv
->chip
;
2340 char *buf
= priv
->buf
;
2343 if (!ar8xxx_has_mib_counters(priv
))
2346 port
= val
->port_vlan
;
2347 if (port
>= dev
->ports
)
2350 mutex_lock(&priv
->mib_lock
);
2351 ret
= ar8xxx_mib_capture(priv
);
2355 ar8xxx_mib_fetch_port_stat(priv
, port
, false);
2357 len
+= snprintf(buf
+ len
, sizeof(priv
->buf
) - len
,
2358 "Port %d MIB counters\n",
2361 mib_stats
= &priv
->mib_stats
[port
* chip
->num_mibs
];
2362 for (i
= 0; i
< chip
->num_mibs
; i
++)
2363 len
+= snprintf(buf
+ len
, sizeof(priv
->buf
) - len
,
2365 chip
->mib_decs
[i
].name
,
2374 mutex_unlock(&priv
->mib_lock
);
2378 static struct switch_attr ar8xxx_sw_attr_globals
[] = {
2380 .type
= SWITCH_TYPE_INT
,
2381 .name
= "enable_vlan",
2382 .description
= "Enable VLAN mode",
2383 .set
= ar8xxx_sw_set_vlan
,
2384 .get
= ar8xxx_sw_get_vlan
,
2388 .type
= SWITCH_TYPE_NOVAL
,
2389 .name
= "reset_mibs",
2390 .description
= "Reset all MIB counters",
2391 .set
= ar8xxx_sw_set_reset_mibs
,
2394 .type
= SWITCH_TYPE_INT
,
2395 .name
= "enable_mirror_rx",
2396 .description
= "Enable mirroring of RX packets",
2397 .set
= ar8xxx_sw_set_mirror_rx_enable
,
2398 .get
= ar8xxx_sw_get_mirror_rx_enable
,
2402 .type
= SWITCH_TYPE_INT
,
2403 .name
= "enable_mirror_tx",
2404 .description
= "Enable mirroring of TX packets",
2405 .set
= ar8xxx_sw_set_mirror_tx_enable
,
2406 .get
= ar8xxx_sw_get_mirror_tx_enable
,
2410 .type
= SWITCH_TYPE_INT
,
2411 .name
= "mirror_monitor_port",
2412 .description
= "Mirror monitor port",
2413 .set
= ar8xxx_sw_set_mirror_monitor_port
,
2414 .get
= ar8xxx_sw_get_mirror_monitor_port
,
2415 .max
= AR8216_NUM_PORTS
- 1
2418 .type
= SWITCH_TYPE_INT
,
2419 .name
= "mirror_source_port",
2420 .description
= "Mirror source port",
2421 .set
= ar8xxx_sw_set_mirror_source_port
,
2422 .get
= ar8xxx_sw_get_mirror_source_port
,
2423 .max
= AR8216_NUM_PORTS
- 1
2427 static struct switch_attr ar8327_sw_attr_globals
[] = {
2429 .type
= SWITCH_TYPE_INT
,
2430 .name
= "enable_vlan",
2431 .description
= "Enable VLAN mode",
2432 .set
= ar8xxx_sw_set_vlan
,
2433 .get
= ar8xxx_sw_get_vlan
,
2437 .type
= SWITCH_TYPE_NOVAL
,
2438 .name
= "reset_mibs",
2439 .description
= "Reset all MIB counters",
2440 .set
= ar8xxx_sw_set_reset_mibs
,
2443 .type
= SWITCH_TYPE_INT
,
2444 .name
= "enable_mirror_rx",
2445 .description
= "Enable mirroring of RX packets",
2446 .set
= ar8xxx_sw_set_mirror_rx_enable
,
2447 .get
= ar8xxx_sw_get_mirror_rx_enable
,
2451 .type
= SWITCH_TYPE_INT
,
2452 .name
= "enable_mirror_tx",
2453 .description
= "Enable mirroring of TX packets",
2454 .set
= ar8xxx_sw_set_mirror_tx_enable
,
2455 .get
= ar8xxx_sw_get_mirror_tx_enable
,
2459 .type
= SWITCH_TYPE_INT
,
2460 .name
= "mirror_monitor_port",
2461 .description
= "Mirror monitor port",
2462 .set
= ar8xxx_sw_set_mirror_monitor_port
,
2463 .get
= ar8xxx_sw_get_mirror_monitor_port
,
2464 .max
= AR8327_NUM_PORTS
- 1
2467 .type
= SWITCH_TYPE_INT
,
2468 .name
= "mirror_source_port",
2469 .description
= "Mirror source port",
2470 .set
= ar8xxx_sw_set_mirror_source_port
,
2471 .get
= ar8xxx_sw_get_mirror_source_port
,
2472 .max
= AR8327_NUM_PORTS
- 1
2476 static struct switch_attr ar8xxx_sw_attr_port
[] = {
2478 .type
= SWITCH_TYPE_NOVAL
,
2479 .name
= "reset_mib",
2480 .description
= "Reset single port MIB counters",
2481 .set
= ar8xxx_sw_set_port_reset_mib
,
2484 .type
= SWITCH_TYPE_STRING
,
2486 .description
= "Get port's MIB counters",
2488 .get
= ar8xxx_sw_get_port_mib
,
2492 static struct switch_attr ar8xxx_sw_attr_vlan
[] = {
2494 .type
= SWITCH_TYPE_INT
,
2496 .description
= "VLAN ID (0-4094)",
2497 .set
= ar8xxx_sw_set_vid
,
2498 .get
= ar8xxx_sw_get_vid
,
2503 static const struct switch_dev_ops ar8xxx_sw_ops
= {
2505 .attr
= ar8xxx_sw_attr_globals
,
2506 .n_attr
= ARRAY_SIZE(ar8xxx_sw_attr_globals
),
2509 .attr
= ar8xxx_sw_attr_port
,
2510 .n_attr
= ARRAY_SIZE(ar8xxx_sw_attr_port
),
2513 .attr
= ar8xxx_sw_attr_vlan
,
2514 .n_attr
= ARRAY_SIZE(ar8xxx_sw_attr_vlan
),
2516 .get_port_pvid
= ar8xxx_sw_get_pvid
,
2517 .set_port_pvid
= ar8xxx_sw_set_pvid
,
2518 .get_vlan_ports
= ar8216_sw_get_ports
,
2519 .set_vlan_ports
= ar8216_sw_set_ports
,
2520 .apply_config
= ar8xxx_sw_hw_apply
,
2521 .reset_switch
= ar8xxx_sw_reset_switch
,
2522 .get_port_link
= ar8xxx_sw_get_port_link
,
2525 static const struct switch_dev_ops ar8327_sw_ops
= {
2527 .attr
= ar8327_sw_attr_globals
,
2528 .n_attr
= ARRAY_SIZE(ar8327_sw_attr_globals
),
2531 .attr
= ar8xxx_sw_attr_port
,
2532 .n_attr
= ARRAY_SIZE(ar8xxx_sw_attr_port
),
2535 .attr
= ar8xxx_sw_attr_vlan
,
2536 .n_attr
= ARRAY_SIZE(ar8xxx_sw_attr_vlan
),
2538 .get_port_pvid
= ar8xxx_sw_get_pvid
,
2539 .set_port_pvid
= ar8xxx_sw_set_pvid
,
2540 .get_vlan_ports
= ar8327_sw_get_ports
,
2541 .set_vlan_ports
= ar8327_sw_set_ports
,
2542 .apply_config
= ar8xxx_sw_hw_apply
,
2543 .reset_switch
= ar8xxx_sw_reset_switch
,
2544 .get_port_link
= ar8xxx_sw_get_port_link
,
2548 ar8xxx_id_chip(struct ar8xxx_priv
*priv
)
2554 val
= priv
->read(priv
, AR8216_REG_CTRL
);
2558 id
= val
& (AR8216_CTRL_REVISION
| AR8216_CTRL_VERSION
);
2559 for (i
= 0; i
< AR8X16_PROBE_RETRIES
; i
++) {
2562 val
= priv
->read(priv
, AR8216_REG_CTRL
);
2566 t
= val
& (AR8216_CTRL_REVISION
| AR8216_CTRL_VERSION
);
2571 priv
->chip_ver
= (id
& AR8216_CTRL_VERSION
) >> AR8216_CTRL_VERSION_S
;
2572 priv
->chip_rev
= (id
& AR8216_CTRL_REVISION
);
2574 switch (priv
->chip_ver
) {
2575 case AR8XXX_VER_AR8216
:
2576 priv
->chip
= &ar8216_chip
;
2578 case AR8XXX_VER_AR8236
:
2579 priv
->chip
= &ar8236_chip
;
2581 case AR8XXX_VER_AR8316
:
2582 priv
->chip
= &ar8316_chip
;
2584 case AR8XXX_VER_AR8327
:
2585 priv
->mii_lo_first
= true;
2586 priv
->chip
= &ar8327_chip
;
2588 case AR8XXX_VER_AR8337
:
2589 priv
->mii_lo_first
= true;
2590 priv
->chip
= &ar8327_chip
;
2593 pr_err("ar8216: Unknown Atheros device [ver=%d, rev=%d]\n",
2594 priv
->chip_ver
, priv
->chip_rev
);
2603 ar8xxx_mib_work_func(struct work_struct
*work
)
2605 struct ar8xxx_priv
*priv
;
2608 priv
= container_of(work
, struct ar8xxx_priv
, mib_work
.work
);
2610 mutex_lock(&priv
->mib_lock
);
2612 err
= ar8xxx_mib_capture(priv
);
2616 ar8xxx_mib_fetch_port_stat(priv
, priv
->mib_next_port
, false);
2619 priv
->mib_next_port
++;
2620 if (priv
->mib_next_port
>= priv
->dev
.ports
)
2621 priv
->mib_next_port
= 0;
2623 mutex_unlock(&priv
->mib_lock
);
2624 schedule_delayed_work(&priv
->mib_work
,
2625 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY
));
2629 ar8xxx_mib_init(struct ar8xxx_priv
*priv
)
2633 if (!ar8xxx_has_mib_counters(priv
))
2636 BUG_ON(!priv
->chip
->mib_decs
|| !priv
->chip
->num_mibs
);
2638 len
= priv
->dev
.ports
* priv
->chip
->num_mibs
*
2639 sizeof(*priv
->mib_stats
);
2640 priv
->mib_stats
= kzalloc(len
, GFP_KERNEL
);
2642 if (!priv
->mib_stats
)
2649 ar8xxx_mib_start(struct ar8xxx_priv
*priv
)
2651 if (!ar8xxx_has_mib_counters(priv
))
2654 schedule_delayed_work(&priv
->mib_work
,
2655 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY
));
2659 ar8xxx_mib_stop(struct ar8xxx_priv
*priv
)
2661 if (!ar8xxx_has_mib_counters(priv
))
2664 cancel_delayed_work(&priv
->mib_work
);
2667 static struct ar8xxx_priv
*
2670 struct ar8xxx_priv
*priv
;
2672 priv
= kzalloc(sizeof(struct ar8xxx_priv
), GFP_KERNEL
);
2676 mutex_init(&priv
->reg_mutex
);
2677 mutex_init(&priv
->mib_lock
);
2678 INIT_DELAYED_WORK(&priv
->mib_work
, ar8xxx_mib_work_func
);
2684 ar8xxx_free(struct ar8xxx_priv
*priv
)
2686 if (priv
->chip
&& priv
->chip
->cleanup
)
2687 priv
->chip
->cleanup(priv
);
2689 kfree(priv
->mib_stats
);
2693 static struct ar8xxx_priv
*
2694 ar8xxx_create_mii(struct mii_bus
*bus
)
2696 struct ar8xxx_priv
*priv
;
2698 priv
= ar8xxx_create();
2700 priv
->mii_bus
= bus
;
2701 priv
->read
= ar8xxx_mii_read
;
2702 priv
->write
= ar8xxx_mii_write
;
2703 priv
->rmw
= ar8xxx_mii_rmw
;
2710 ar8xxx_probe_switch(struct ar8xxx_priv
*priv
)
2712 struct switch_dev
*swdev
;
2715 ret
= ar8xxx_id_chip(priv
);
2720 swdev
->cpu_port
= AR8216_PORT_CPU
;
2721 swdev
->ops
= &ar8xxx_sw_ops
;
2723 if (chip_is_ar8316(priv
)) {
2724 swdev
->name
= "Atheros AR8316";
2725 swdev
->vlans
= AR8X16_MAX_VLANS
;
2726 swdev
->ports
= AR8216_NUM_PORTS
;
2727 } else if (chip_is_ar8236(priv
)) {
2728 swdev
->name
= "Atheros AR8236";
2729 swdev
->vlans
= AR8216_NUM_VLANS
;
2730 swdev
->ports
= AR8216_NUM_PORTS
;
2731 } else if (chip_is_ar8327(priv
)) {
2732 swdev
->name
= "Atheros AR8327";
2733 swdev
->vlans
= AR8X16_MAX_VLANS
;
2734 swdev
->ports
= AR8327_NUM_PORTS
;
2735 swdev
->ops
= &ar8327_sw_ops
;
2736 } else if (chip_is_ar8337(priv
)) {
2737 swdev
->name
= "Atheros AR8337";
2738 swdev
->vlans
= AR8X16_MAX_VLANS
;
2739 swdev
->ports
= AR8327_NUM_PORTS
;
2740 swdev
->ops
= &ar8327_sw_ops
;
2742 swdev
->name
= "Atheros AR8216";
2743 swdev
->vlans
= AR8216_NUM_VLANS
;
2744 swdev
->ports
= AR8216_NUM_PORTS
;
2747 ret
= ar8xxx_mib_init(priv
);
2755 ar8xxx_start(struct ar8xxx_priv
*priv
)
2761 ret
= priv
->chip
->hw_init(priv
);
2765 ret
= ar8xxx_sw_reset_switch(&priv
->dev
);
2771 ar8xxx_mib_start(priv
);
2777 ar8xxx_phy_config_init(struct phy_device
*phydev
)
2779 struct ar8xxx_priv
*priv
= phydev
->priv
;
2780 struct net_device
*dev
= phydev
->attached_dev
;
2786 if (chip_is_ar8327(priv
) || chip_is_ar8337(priv
))
2791 if (phydev
->addr
!= 0) {
2792 if (chip_is_ar8316(priv
)) {
2793 /* switch device has been initialized, reinit */
2794 priv
->dev
.ports
= (AR8216_NUM_PORTS
- 1);
2795 priv
->initialized
= false;
2796 priv
->port4_phy
= true;
2797 ar8316_hw_init(priv
);
2804 ret
= ar8xxx_start(priv
);
2808 /* VID fixup only needed on ar8216 */
2809 if (chip_is_ar8216(priv
)) {
2810 dev
->phy_ptr
= priv
;
2811 dev
->priv_flags
|= IFF_NO_IP_ALIGN
;
2812 dev
->eth_mangle_rx
= ar8216_mangle_rx
;
2813 dev
->eth_mangle_tx
= ar8216_mangle_tx
;
2820 ar8xxx_phy_read_status(struct phy_device
*phydev
)
2822 struct ar8xxx_priv
*priv
= phydev
->priv
;
2823 struct switch_port_link link
;
2826 if (phydev
->addr
!= 0)
2827 return genphy_read_status(phydev
);
2829 ar8216_read_port_link(priv
, phydev
->addr
, &link
);
2830 phydev
->link
= !!link
.link
;
2834 switch (link
.speed
) {
2835 case SWITCH_PORT_SPEED_10
:
2836 phydev
->speed
= SPEED_10
;
2838 case SWITCH_PORT_SPEED_100
:
2839 phydev
->speed
= SPEED_100
;
2841 case SWITCH_PORT_SPEED_1000
:
2842 phydev
->speed
= SPEED_1000
;
2847 phydev
->duplex
= link
.duplex
? DUPLEX_FULL
: DUPLEX_HALF
;
2849 /* flush the address translation unit */
2850 mutex_lock(&priv
->reg_mutex
);
2851 ret
= priv
->chip
->atu_flush(priv
);
2852 mutex_unlock(&priv
->reg_mutex
);
2854 phydev
->state
= PHY_RUNNING
;
2855 netif_carrier_on(phydev
->attached_dev
);
2856 phydev
->adjust_link(phydev
->attached_dev
);
2862 ar8xxx_phy_config_aneg(struct phy_device
*phydev
)
2864 if (phydev
->addr
== 0)
2867 return genphy_config_aneg(phydev
);
2870 static const u32 ar8xxx_phy_ids
[] = {
2872 0x004dd034, /* AR8327 */
2873 0x004dd036, /* AR8337 */
2879 ar8xxx_phy_match(u32 phy_id
)
2883 for (i
= 0; i
< ARRAY_SIZE(ar8xxx_phy_ids
); i
++)
2884 if (phy_id
== ar8xxx_phy_ids
[i
])
2891 ar8xxx_is_possible(struct mii_bus
*bus
)
2895 for (i
= 0; i
< 4; i
++) {
2898 phy_id
= mdiobus_read(bus
, i
, MII_PHYSID1
) << 16;
2899 phy_id
|= mdiobus_read(bus
, i
, MII_PHYSID2
);
2900 if (!ar8xxx_phy_match(phy_id
)) {
2901 pr_debug("ar8xxx: unknown PHY at %s:%02x id:%08x\n",
2902 dev_name(&bus
->dev
), i
, phy_id
);
2911 ar8xxx_phy_probe(struct phy_device
*phydev
)
2913 struct ar8xxx_priv
*priv
;
2914 struct switch_dev
*swdev
;
2917 /* skip PHYs at unused adresses */
2918 if (phydev
->addr
!= 0 && phydev
->addr
!= 4)
2921 if (!ar8xxx_is_possible(phydev
->bus
))
2924 mutex_lock(&ar8xxx_dev_list_lock
);
2925 list_for_each_entry(priv
, &ar8xxx_dev_list
, list
)
2926 if (priv
->mii_bus
== phydev
->bus
)
2929 priv
= ar8xxx_create_mii(phydev
->bus
);
2935 ret
= ar8xxx_probe_switch(priv
);
2940 swdev
->alias
= dev_name(&priv
->mii_bus
->dev
);
2941 ret
= register_switch(swdev
, NULL
);
2945 pr_info("%s: %s rev. %u switch registered on %s\n",
2946 swdev
->devname
, swdev
->name
, priv
->chip_rev
,
2947 dev_name(&priv
->mii_bus
->dev
));
2952 if (phydev
->addr
== 0) {
2953 if (ar8xxx_has_gige(priv
)) {
2954 phydev
->supported
= SUPPORTED_1000baseT_Full
;
2955 phydev
->advertising
= ADVERTISED_1000baseT_Full
;
2957 phydev
->supported
= SUPPORTED_100baseT_Full
;
2958 phydev
->advertising
= ADVERTISED_100baseT_Full
;
2961 if (chip_is_ar8327(priv
) || chip_is_ar8337(priv
)) {
2964 ret
= ar8xxx_start(priv
);
2966 goto err_unregister_switch
;
2969 if (ar8xxx_has_gige(priv
)) {
2970 phydev
->supported
|= SUPPORTED_1000baseT_Full
;
2971 phydev
->advertising
|= ADVERTISED_1000baseT_Full
;
2975 phydev
->priv
= priv
;
2977 list_add(&priv
->list
, &ar8xxx_dev_list
);
2979 mutex_unlock(&ar8xxx_dev_list_lock
);
2983 err_unregister_switch
:
2984 if (--priv
->use_count
)
2987 unregister_switch(&priv
->dev
);
2992 mutex_unlock(&ar8xxx_dev_list_lock
);
2997 ar8xxx_phy_detach(struct phy_device
*phydev
)
2999 struct net_device
*dev
= phydev
->attached_dev
;
3004 dev
->phy_ptr
= NULL
;
3005 dev
->priv_flags
&= ~IFF_NO_IP_ALIGN
;
3006 dev
->eth_mangle_rx
= NULL
;
3007 dev
->eth_mangle_tx
= NULL
;
3011 ar8xxx_phy_remove(struct phy_device
*phydev
)
3013 struct ar8xxx_priv
*priv
= phydev
->priv
;
3018 phydev
->priv
= NULL
;
3019 if (--priv
->use_count
> 0)
3022 mutex_lock(&ar8xxx_dev_list_lock
);
3023 list_del(&priv
->list
);
3024 mutex_unlock(&ar8xxx_dev_list_lock
);
3026 unregister_switch(&priv
->dev
);
3027 ar8xxx_mib_stop(priv
);
3031 static struct phy_driver ar8xxx_phy_driver
= {
3032 .phy_id
= 0x004d0000,
3033 .name
= "Atheros AR8216/AR8236/AR8316",
3034 .phy_id_mask
= 0xffff0000,
3035 .features
= PHY_BASIC_FEATURES
,
3036 .probe
= ar8xxx_phy_probe
,
3037 .remove
= ar8xxx_phy_remove
,
3038 .detach
= ar8xxx_phy_detach
,
3039 .config_init
= ar8xxx_phy_config_init
,
3040 .config_aneg
= ar8xxx_phy_config_aneg
,
3041 .read_status
= ar8xxx_phy_read_status
,
3042 .driver
= { .owner
= THIS_MODULE
},
3048 return phy_driver_register(&ar8xxx_phy_driver
);
3054 phy_driver_unregister(&ar8xxx_phy_driver
);
3057 module_init(ar8xxx_init
);
3058 module_exit(ar8xxx_exit
);
3059 MODULE_LICENSE("GPL");