2 * ar8216.c: AR8216 switch driver
4 * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/list.h>
22 #include <linux/if_ether.h>
23 #include <linux/skbuff.h>
24 #include <linux/netdevice.h>
25 #include <linux/netlink.h>
26 #include <linux/bitops.h>
27 #include <net/genetlink.h>
28 #include <linux/switch.h>
29 #include <linux/delay.h>
30 #include <linux/phy.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/lockdep.h>
34 #include <linux/ar8216_platform.h>
35 #include <linux/workqueue.h>
36 #include <linux/version.h>
40 extern const struct ar8xxx_chip ar8327_chip
;
41 extern const struct ar8xxx_chip ar8337_chip
;
43 #define AR8XXX_MIB_WORK_DELAY 2000 /* msecs */
45 #define MIB_DESC(_s , _o, _n) \
52 static const struct ar8xxx_mib_desc ar8216_mibs
[] = {
53 MIB_DESC(1, AR8216_STATS_RXBROAD
, "RxBroad"),
54 MIB_DESC(1, AR8216_STATS_RXPAUSE
, "RxPause"),
55 MIB_DESC(1, AR8216_STATS_RXMULTI
, "RxMulti"),
56 MIB_DESC(1, AR8216_STATS_RXFCSERR
, "RxFcsErr"),
57 MIB_DESC(1, AR8216_STATS_RXALIGNERR
, "RxAlignErr"),
58 MIB_DESC(1, AR8216_STATS_RXRUNT
, "RxRunt"),
59 MIB_DESC(1, AR8216_STATS_RXFRAGMENT
, "RxFragment"),
60 MIB_DESC(1, AR8216_STATS_RX64BYTE
, "Rx64Byte"),
61 MIB_DESC(1, AR8216_STATS_RX128BYTE
, "Rx128Byte"),
62 MIB_DESC(1, AR8216_STATS_RX256BYTE
, "Rx256Byte"),
63 MIB_DESC(1, AR8216_STATS_RX512BYTE
, "Rx512Byte"),
64 MIB_DESC(1, AR8216_STATS_RX1024BYTE
, "Rx1024Byte"),
65 MIB_DESC(1, AR8216_STATS_RXMAXBYTE
, "RxMaxByte"),
66 MIB_DESC(1, AR8216_STATS_RXTOOLONG
, "RxTooLong"),
67 MIB_DESC(2, AR8216_STATS_RXGOODBYTE
, "RxGoodByte"),
68 MIB_DESC(2, AR8216_STATS_RXBADBYTE
, "RxBadByte"),
69 MIB_DESC(1, AR8216_STATS_RXOVERFLOW
, "RxOverFlow"),
70 MIB_DESC(1, AR8216_STATS_FILTERED
, "Filtered"),
71 MIB_DESC(1, AR8216_STATS_TXBROAD
, "TxBroad"),
72 MIB_DESC(1, AR8216_STATS_TXPAUSE
, "TxPause"),
73 MIB_DESC(1, AR8216_STATS_TXMULTI
, "TxMulti"),
74 MIB_DESC(1, AR8216_STATS_TXUNDERRUN
, "TxUnderRun"),
75 MIB_DESC(1, AR8216_STATS_TX64BYTE
, "Tx64Byte"),
76 MIB_DESC(1, AR8216_STATS_TX128BYTE
, "Tx128Byte"),
77 MIB_DESC(1, AR8216_STATS_TX256BYTE
, "Tx256Byte"),
78 MIB_DESC(1, AR8216_STATS_TX512BYTE
, "Tx512Byte"),
79 MIB_DESC(1, AR8216_STATS_TX1024BYTE
, "Tx1024Byte"),
80 MIB_DESC(1, AR8216_STATS_TXMAXBYTE
, "TxMaxByte"),
81 MIB_DESC(1, AR8216_STATS_TXOVERSIZE
, "TxOverSize"),
82 MIB_DESC(2, AR8216_STATS_TXBYTE
, "TxByte"),
83 MIB_DESC(1, AR8216_STATS_TXCOLLISION
, "TxCollision"),
84 MIB_DESC(1, AR8216_STATS_TXABORTCOL
, "TxAbortCol"),
85 MIB_DESC(1, AR8216_STATS_TXMULTICOL
, "TxMultiCol"),
86 MIB_DESC(1, AR8216_STATS_TXSINGLECOL
, "TxSingleCol"),
87 MIB_DESC(1, AR8216_STATS_TXEXCDEFER
, "TxExcDefer"),
88 MIB_DESC(1, AR8216_STATS_TXDEFER
, "TxDefer"),
89 MIB_DESC(1, AR8216_STATS_TXLATECOL
, "TxLateCol"),
92 const struct ar8xxx_mib_desc ar8236_mibs
[39] = {
93 MIB_DESC(1, AR8236_STATS_RXBROAD
, "RxBroad"),
94 MIB_DESC(1, AR8236_STATS_RXPAUSE
, "RxPause"),
95 MIB_DESC(1, AR8236_STATS_RXMULTI
, "RxMulti"),
96 MIB_DESC(1, AR8236_STATS_RXFCSERR
, "RxFcsErr"),
97 MIB_DESC(1, AR8236_STATS_RXALIGNERR
, "RxAlignErr"),
98 MIB_DESC(1, AR8236_STATS_RXRUNT
, "RxRunt"),
99 MIB_DESC(1, AR8236_STATS_RXFRAGMENT
, "RxFragment"),
100 MIB_DESC(1, AR8236_STATS_RX64BYTE
, "Rx64Byte"),
101 MIB_DESC(1, AR8236_STATS_RX128BYTE
, "Rx128Byte"),
102 MIB_DESC(1, AR8236_STATS_RX256BYTE
, "Rx256Byte"),
103 MIB_DESC(1, AR8236_STATS_RX512BYTE
, "Rx512Byte"),
104 MIB_DESC(1, AR8236_STATS_RX1024BYTE
, "Rx1024Byte"),
105 MIB_DESC(1, AR8236_STATS_RX1518BYTE
, "Rx1518Byte"),
106 MIB_DESC(1, AR8236_STATS_RXMAXBYTE
, "RxMaxByte"),
107 MIB_DESC(1, AR8236_STATS_RXTOOLONG
, "RxTooLong"),
108 MIB_DESC(2, AR8236_STATS_RXGOODBYTE
, "RxGoodByte"),
109 MIB_DESC(2, AR8236_STATS_RXBADBYTE
, "RxBadByte"),
110 MIB_DESC(1, AR8236_STATS_RXOVERFLOW
, "RxOverFlow"),
111 MIB_DESC(1, AR8236_STATS_FILTERED
, "Filtered"),
112 MIB_DESC(1, AR8236_STATS_TXBROAD
, "TxBroad"),
113 MIB_DESC(1, AR8236_STATS_TXPAUSE
, "TxPause"),
114 MIB_DESC(1, AR8236_STATS_TXMULTI
, "TxMulti"),
115 MIB_DESC(1, AR8236_STATS_TXUNDERRUN
, "TxUnderRun"),
116 MIB_DESC(1, AR8236_STATS_TX64BYTE
, "Tx64Byte"),
117 MIB_DESC(1, AR8236_STATS_TX128BYTE
, "Tx128Byte"),
118 MIB_DESC(1, AR8236_STATS_TX256BYTE
, "Tx256Byte"),
119 MIB_DESC(1, AR8236_STATS_TX512BYTE
, "Tx512Byte"),
120 MIB_DESC(1, AR8236_STATS_TX1024BYTE
, "Tx1024Byte"),
121 MIB_DESC(1, AR8236_STATS_TX1518BYTE
, "Tx1518Byte"),
122 MIB_DESC(1, AR8236_STATS_TXMAXBYTE
, "TxMaxByte"),
123 MIB_DESC(1, AR8236_STATS_TXOVERSIZE
, "TxOverSize"),
124 MIB_DESC(2, AR8236_STATS_TXBYTE
, "TxByte"),
125 MIB_DESC(1, AR8236_STATS_TXCOLLISION
, "TxCollision"),
126 MIB_DESC(1, AR8236_STATS_TXABORTCOL
, "TxAbortCol"),
127 MIB_DESC(1, AR8236_STATS_TXMULTICOL
, "TxMultiCol"),
128 MIB_DESC(1, AR8236_STATS_TXSINGLECOL
, "TxSingleCol"),
129 MIB_DESC(1, AR8236_STATS_TXEXCDEFER
, "TxExcDefer"),
130 MIB_DESC(1, AR8236_STATS_TXDEFER
, "TxDefer"),
131 MIB_DESC(1, AR8236_STATS_TXLATECOL
, "TxLateCol"),
134 static DEFINE_MUTEX(ar8xxx_dev_list_lock
);
135 static LIST_HEAD(ar8xxx_dev_list
);
138 split_addr(u32 regaddr
, u16
*r1
, u16
*r2
, u16
*page
)
141 *r1
= regaddr
& 0x1e;
147 *page
= regaddr
& 0x1ff;
150 /* inspired by phy_poll_reset in drivers/net/phy/phy_device.c */
152 ar8xxx_phy_poll_reset(struct mii_bus
*bus
)
154 unsigned int sleep_msecs
= 20;
157 for (elapsed
= sleep_msecs
; elapsed
<= 600;
158 elapsed
+= sleep_msecs
) {
160 for (i
= 0; i
< AR8XXX_NUM_PHYS
; i
++) {
161 ret
= mdiobus_read(bus
, i
, MII_BMCR
);
164 if (ret
& BMCR_RESET
)
166 if (i
== AR8XXX_NUM_PHYS
- 1) {
167 usleep_range(1000, 2000);
176 ar8xxx_phy_check_aneg(struct phy_device
*phydev
)
180 if (phydev
->autoneg
!= AUTONEG_ENABLE
)
183 * BMCR_ANENABLE might have been cleared
184 * by phy_init_hw in certain kernel versions
185 * therefore check for it
187 ret
= phy_read(phydev
, MII_BMCR
);
190 if (ret
& BMCR_ANENABLE
)
193 dev_info(&phydev
->dev
, "ANEG disabled, re-enabling ...\n");
194 ret
|= BMCR_ANENABLE
| BMCR_ANRESTART
;
195 return phy_write(phydev
, MII_BMCR
, ret
);
199 ar8xxx_phy_init(struct ar8xxx_priv
*priv
)
205 for (i
= 0; i
< AR8XXX_NUM_PHYS
; i
++) {
206 if (priv
->chip
->phy_fixup
)
207 priv
->chip
->phy_fixup(priv
, i
);
209 /* initialize the port itself */
210 mdiobus_write(bus
, i
, MII_ADVERTISE
,
211 ADVERTISE_ALL
| ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
);
212 if (ar8xxx_has_gige(priv
))
213 mdiobus_write(bus
, i
, MII_CTRL1000
, ADVERTISE_1000FULL
);
214 mdiobus_write(bus
, i
, MII_BMCR
, BMCR_RESET
| BMCR_ANENABLE
);
217 ar8xxx_phy_poll_reset(bus
);
221 mii_read32(struct ar8xxx_priv
*priv
, int phy_id
, int regnum
)
223 struct mii_bus
*bus
= priv
->mii_bus
;
226 lo
= bus
->read(bus
, phy_id
, regnum
);
227 hi
= bus
->read(bus
, phy_id
, regnum
+ 1);
229 return (hi
<< 16) | lo
;
233 mii_write32(struct ar8xxx_priv
*priv
, int phy_id
, int regnum
, u32 val
)
235 struct mii_bus
*bus
= priv
->mii_bus
;
239 hi
= (u16
) (val
>> 16);
241 if (priv
->chip
->mii_lo_first
)
243 bus
->write(bus
, phy_id
, regnum
, lo
);
244 bus
->write(bus
, phy_id
, regnum
+ 1, hi
);
246 bus
->write(bus
, phy_id
, regnum
+ 1, hi
);
247 bus
->write(bus
, phy_id
, regnum
, lo
);
252 ar8xxx_read(struct ar8xxx_priv
*priv
, int reg
)
254 struct mii_bus
*bus
= priv
->mii_bus
;
258 split_addr((u32
) reg
, &r1
, &r2
, &page
);
260 mutex_lock(&bus
->mdio_lock
);
262 bus
->write(bus
, 0x18, 0, page
);
263 usleep_range(1000, 2000); /* wait for the page switch to propagate */
264 val
= mii_read32(priv
, 0x10 | r2
, r1
);
266 mutex_unlock(&bus
->mdio_lock
);
272 ar8xxx_write(struct ar8xxx_priv
*priv
, int reg
, u32 val
)
274 struct mii_bus
*bus
= priv
->mii_bus
;
277 split_addr((u32
) reg
, &r1
, &r2
, &page
);
279 mutex_lock(&bus
->mdio_lock
);
281 bus
->write(bus
, 0x18, 0, page
);
282 usleep_range(1000, 2000); /* wait for the page switch to propagate */
283 mii_write32(priv
, 0x10 | r2
, r1
, val
);
285 mutex_unlock(&bus
->mdio_lock
);
289 ar8xxx_rmw(struct ar8xxx_priv
*priv
, int reg
, u32 mask
, u32 val
)
291 struct mii_bus
*bus
= priv
->mii_bus
;
295 split_addr((u32
) reg
, &r1
, &r2
, &page
);
297 mutex_lock(&bus
->mdio_lock
);
299 bus
->write(bus
, 0x18, 0, page
);
300 usleep_range(1000, 2000); /* wait for the page switch to propagate */
302 ret
= mii_read32(priv
, 0x10 | r2
, r1
);
305 mii_write32(priv
, 0x10 | r2
, r1
, ret
);
307 mutex_unlock(&bus
->mdio_lock
);
313 ar8xxx_phy_dbg_write(struct ar8xxx_priv
*priv
, int phy_addr
,
314 u16 dbg_addr
, u16 dbg_data
)
316 struct mii_bus
*bus
= priv
->mii_bus
;
318 mutex_lock(&bus
->mdio_lock
);
319 bus
->write(bus
, phy_addr
, MII_ATH_DBG_ADDR
, dbg_addr
);
320 bus
->write(bus
, phy_addr
, MII_ATH_DBG_DATA
, dbg_data
);
321 mutex_unlock(&bus
->mdio_lock
);
325 ar8xxx_phy_mmd_write(struct ar8xxx_priv
*priv
, int phy_addr
, u16 addr
, u16 data
)
327 struct mii_bus
*bus
= priv
->mii_bus
;
329 mutex_lock(&bus
->mdio_lock
);
330 bus
->write(bus
, phy_addr
, MII_ATH_MMD_ADDR
, addr
);
331 bus
->write(bus
, phy_addr
, MII_ATH_MMD_DATA
, data
);
332 mutex_unlock(&bus
->mdio_lock
);
336 ar8xxx_phy_mmd_read(struct ar8xxx_priv
*priv
, int phy_addr
, u16 addr
)
338 struct mii_bus
*bus
= priv
->mii_bus
;
341 mutex_lock(&bus
->mdio_lock
);
342 bus
->write(bus
, phy_addr
, MII_ATH_MMD_ADDR
, addr
);
343 data
= bus
->read(bus
, phy_addr
, MII_ATH_MMD_DATA
);
344 mutex_unlock(&bus
->mdio_lock
);
350 ar8xxx_reg_wait(struct ar8xxx_priv
*priv
, u32 reg
, u32 mask
, u32 val
,
355 for (i
= 0; i
< timeout
; i
++) {
358 t
= ar8xxx_read(priv
, reg
);
359 if ((t
& mask
) == val
)
362 usleep_range(1000, 2000);
369 ar8xxx_mib_op(struct ar8xxx_priv
*priv
, u32 op
)
371 unsigned mib_func
= priv
->chip
->mib_func
;
374 lockdep_assert_held(&priv
->mib_lock
);
376 /* Capture the hardware statistics for all ports */
377 ar8xxx_rmw(priv
, mib_func
, AR8216_MIB_FUNC
, (op
<< AR8216_MIB_FUNC_S
));
379 /* Wait for the capturing to complete. */
380 ret
= ar8xxx_reg_wait(priv
, mib_func
, AR8216_MIB_BUSY
, 0, 10);
391 ar8xxx_mib_capture(struct ar8xxx_priv
*priv
)
393 return ar8xxx_mib_op(priv
, AR8216_MIB_FUNC_CAPTURE
);
397 ar8xxx_mib_flush(struct ar8xxx_priv
*priv
)
399 return ar8xxx_mib_op(priv
, AR8216_MIB_FUNC_FLUSH
);
403 ar8xxx_mib_fetch_port_stat(struct ar8xxx_priv
*priv
, int port
, bool flush
)
409 WARN_ON(port
>= priv
->dev
.ports
);
411 lockdep_assert_held(&priv
->mib_lock
);
413 base
= priv
->chip
->reg_port_stats_start
+
414 priv
->chip
->reg_port_stats_length
* port
;
416 mib_stats
= &priv
->mib_stats
[port
* priv
->chip
->num_mibs
];
417 for (i
= 0; i
< priv
->chip
->num_mibs
; i
++) {
418 const struct ar8xxx_mib_desc
*mib
;
421 mib
= &priv
->chip
->mib_decs
[i
];
422 t
= ar8xxx_read(priv
, base
+ mib
->offset
);
423 if (mib
->size
== 2) {
426 hi
= ar8xxx_read(priv
, base
+ mib
->offset
+ 4);
438 ar8216_read_port_link(struct ar8xxx_priv
*priv
, int port
,
439 struct switch_port_link
*link
)
444 memset(link
, '\0', sizeof(*link
));
446 status
= priv
->chip
->read_port_status(priv
, port
);
448 link
->aneg
= !!(status
& AR8216_PORT_STATUS_LINK_AUTO
);
450 link
->link
= !!(status
& AR8216_PORT_STATUS_LINK_UP
);
454 if (priv
->get_port_link
) {
457 err
= priv
->get_port_link(port
);
466 link
->duplex
= !!(status
& AR8216_PORT_STATUS_DUPLEX
);
467 link
->tx_flow
= !!(status
& AR8216_PORT_STATUS_TXFLOW
);
468 link
->rx_flow
= !!(status
& AR8216_PORT_STATUS_RXFLOW
);
470 if (link
->aneg
&& link
->duplex
&& priv
->chip
->read_port_eee_status
)
471 link
->eee
= priv
->chip
->read_port_eee_status(priv
, port
);
473 speed
= (status
& AR8216_PORT_STATUS_SPEED
) >>
474 AR8216_PORT_STATUS_SPEED_S
;
477 case AR8216_PORT_SPEED_10M
:
478 link
->speed
= SWITCH_PORT_SPEED_10
;
480 case AR8216_PORT_SPEED_100M
:
481 link
->speed
= SWITCH_PORT_SPEED_100
;
483 case AR8216_PORT_SPEED_1000M
:
484 link
->speed
= SWITCH_PORT_SPEED_1000
;
487 link
->speed
= SWITCH_PORT_SPEED_UNKNOWN
;
492 static struct sk_buff
*
493 ar8216_mangle_tx(struct net_device
*dev
, struct sk_buff
*skb
)
495 struct ar8xxx_priv
*priv
= dev
->phy_ptr
;
504 if (unlikely(skb_headroom(skb
) < 2)) {
505 if (pskb_expand_head(skb
, 2, 0, GFP_ATOMIC
) < 0)
509 buf
= skb_push(skb
, 2);
517 dev_kfree_skb_any(skb
);
522 ar8216_mangle_rx(struct net_device
*dev
, struct sk_buff
*skb
)
524 struct ar8xxx_priv
*priv
;
532 /* don't strip the header if vlan mode is disabled */
536 /* strip header, get vlan id */
540 /* check for vlan header presence */
541 if ((buf
[12 + 2] != 0x81) || (buf
[13 + 2] != 0x00))
546 /* no need to fix up packets coming from a tagged source */
547 if (priv
->vlan_tagged
& (1 << port
))
550 /* lookup port vid from local table, the switch passes an invalid vlan id */
551 vlan
= priv
->vlan_id
[priv
->pvid
[port
]];
554 buf
[14 + 2] |= vlan
>> 8;
555 buf
[15 + 2] = vlan
& 0xff;
559 ar8216_wait_bit(struct ar8xxx_priv
*priv
, int reg
, u32 mask
, u32 val
)
565 t
= ar8xxx_read(priv
, reg
);
566 if ((t
& mask
) == val
)
575 pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
576 (unsigned int) reg
, t
, mask
, val
);
581 ar8216_vtu_op(struct ar8xxx_priv
*priv
, u32 op
, u32 val
)
583 if (ar8216_wait_bit(priv
, AR8216_REG_VTU
, AR8216_VTU_ACTIVE
, 0))
585 if ((op
& AR8216_VTU_OP
) == AR8216_VTU_OP_LOAD
) {
586 val
&= AR8216_VTUDATA_MEMBER
;
587 val
|= AR8216_VTUDATA_VALID
;
588 ar8xxx_write(priv
, AR8216_REG_VTU_DATA
, val
);
590 op
|= AR8216_VTU_ACTIVE
;
591 ar8xxx_write(priv
, AR8216_REG_VTU
, op
);
595 ar8216_vtu_flush(struct ar8xxx_priv
*priv
)
597 ar8216_vtu_op(priv
, AR8216_VTU_OP_FLUSH
, 0);
601 ar8216_vtu_load_vlan(struct ar8xxx_priv
*priv
, u32 vid
, u32 port_mask
)
605 op
= AR8216_VTU_OP_LOAD
| (vid
<< AR8216_VTU_VID_S
);
606 ar8216_vtu_op(priv
, op
, port_mask
);
610 ar8216_atu_flush(struct ar8xxx_priv
*priv
)
614 ret
= ar8216_wait_bit(priv
, AR8216_REG_ATU
, AR8216_ATU_ACTIVE
, 0);
616 ar8xxx_write(priv
, AR8216_REG_ATU
, AR8216_ATU_OP_FLUSH
);
622 ar8216_read_port_status(struct ar8xxx_priv
*priv
, int port
)
624 return ar8xxx_read(priv
, AR8216_REG_PORT_STATUS(port
));
628 ar8216_setup_port(struct ar8xxx_priv
*priv
, int port
, u32 members
)
635 pvid
= priv
->vlan_id
[priv
->pvid
[port
]];
636 if (priv
->vlan_tagged
& (1 << port
))
637 egress
= AR8216_OUT_ADD_VLAN
;
639 egress
= AR8216_OUT_STRIP_VLAN
;
640 ingress
= AR8216_IN_SECURE
;
643 egress
= AR8216_OUT_KEEP
;
644 ingress
= AR8216_IN_PORT_ONLY
;
647 if (chip_is_ar8216(priv
) && priv
->vlan
&& port
== AR8216_PORT_CPU
)
648 header
= AR8216_PORT_CTRL_HEADER
;
652 ar8xxx_rmw(priv
, AR8216_REG_PORT_CTRL(port
),
653 AR8216_PORT_CTRL_LEARN
| AR8216_PORT_CTRL_VLAN_MODE
|
654 AR8216_PORT_CTRL_SINGLE_VLAN
| AR8216_PORT_CTRL_STATE
|
655 AR8216_PORT_CTRL_HEADER
| AR8216_PORT_CTRL_LEARN_LOCK
,
656 AR8216_PORT_CTRL_LEARN
| header
|
657 (egress
<< AR8216_PORT_CTRL_VLAN_MODE_S
) |
658 (AR8216_PORT_STATE_FORWARD
<< AR8216_PORT_CTRL_STATE_S
));
660 ar8xxx_rmw(priv
, AR8216_REG_PORT_VLAN(port
),
661 AR8216_PORT_VLAN_DEST_PORTS
| AR8216_PORT_VLAN_MODE
|
662 AR8216_PORT_VLAN_DEFAULT_ID
,
663 (members
<< AR8216_PORT_VLAN_DEST_PORTS_S
) |
664 (ingress
<< AR8216_PORT_VLAN_MODE_S
) |
665 (pvid
<< AR8216_PORT_VLAN_DEFAULT_ID_S
));
669 ar8216_hw_init(struct ar8xxx_priv
*priv
)
671 if (priv
->initialized
)
674 ar8xxx_phy_init(priv
);
676 priv
->initialized
= true;
681 ar8216_init_globals(struct ar8xxx_priv
*priv
)
683 /* standard atheros magic */
684 ar8xxx_write(priv
, 0x38, 0xc000050e);
686 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
687 AR8216_GCTRL_MTU
, 1518 + 8 + 2);
691 ar8216_init_port(struct ar8xxx_priv
*priv
, int port
)
693 /* Enable port learning and tx */
694 ar8xxx_write(priv
, AR8216_REG_PORT_CTRL(port
),
695 AR8216_PORT_CTRL_LEARN
|
696 (4 << AR8216_PORT_CTRL_STATE_S
));
698 ar8xxx_write(priv
, AR8216_REG_PORT_VLAN(port
), 0);
700 if (port
== AR8216_PORT_CPU
) {
701 ar8xxx_write(priv
, AR8216_REG_PORT_STATUS(port
),
702 AR8216_PORT_STATUS_LINK_UP
|
703 (ar8xxx_has_gige(priv
) ?
704 AR8216_PORT_SPEED_1000M
: AR8216_PORT_SPEED_100M
) |
705 AR8216_PORT_STATUS_TXMAC
|
706 AR8216_PORT_STATUS_RXMAC
|
707 (chip_is_ar8316(priv
) ? AR8216_PORT_STATUS_RXFLOW
: 0) |
708 (chip_is_ar8316(priv
) ? AR8216_PORT_STATUS_TXFLOW
: 0) |
709 AR8216_PORT_STATUS_DUPLEX
);
711 ar8xxx_write(priv
, AR8216_REG_PORT_STATUS(port
),
712 AR8216_PORT_STATUS_LINK_AUTO
);
717 ar8236_setup_port(struct ar8xxx_priv
*priv
, int port
, u32 members
)
723 pvid
= priv
->vlan_id
[priv
->pvid
[port
]];
724 if (priv
->vlan_tagged
& (1 << port
))
725 egress
= AR8216_OUT_ADD_VLAN
;
727 egress
= AR8216_OUT_STRIP_VLAN
;
728 ingress
= AR8216_IN_SECURE
;
731 egress
= AR8216_OUT_KEEP
;
732 ingress
= AR8216_IN_PORT_ONLY
;
735 ar8xxx_rmw(priv
, AR8216_REG_PORT_CTRL(port
),
736 AR8216_PORT_CTRL_LEARN
| AR8216_PORT_CTRL_VLAN_MODE
|
737 AR8216_PORT_CTRL_SINGLE_VLAN
| AR8216_PORT_CTRL_STATE
|
738 AR8216_PORT_CTRL_HEADER
| AR8216_PORT_CTRL_LEARN_LOCK
,
739 AR8216_PORT_CTRL_LEARN
|
740 (egress
<< AR8216_PORT_CTRL_VLAN_MODE_S
) |
741 (AR8216_PORT_STATE_FORWARD
<< AR8216_PORT_CTRL_STATE_S
));
743 ar8xxx_rmw(priv
, AR8236_REG_PORT_VLAN(port
),
744 AR8236_PORT_VLAN_DEFAULT_ID
,
745 (pvid
<< AR8236_PORT_VLAN_DEFAULT_ID_S
));
747 ar8xxx_rmw(priv
, AR8236_REG_PORT_VLAN2(port
),
748 AR8236_PORT_VLAN2_VLAN_MODE
|
749 AR8236_PORT_VLAN2_MEMBER
,
750 (ingress
<< AR8236_PORT_VLAN2_VLAN_MODE_S
) |
751 (members
<< AR8236_PORT_VLAN2_MEMBER_S
));
755 ar8236_init_globals(struct ar8xxx_priv
*priv
)
757 /* enable jumbo frames */
758 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
759 AR8316_GCTRL_MTU
, 9018 + 8 + 2);
761 /* enable cpu port to receive arp frames */
762 ar8xxx_reg_set(priv
, AR8216_REG_ATU_CTRL
,
763 AR8236_ATU_CTRL_RES
);
765 /* enable cpu port to receive multicast and broadcast frames */
766 ar8xxx_reg_set(priv
, AR8216_REG_FLOOD_MASK
,
767 AR8236_FM_CPU_BROADCAST_EN
| AR8236_FM_CPU_BCAST_FWD_EN
);
769 /* Enable MIB counters */
770 ar8xxx_rmw(priv
, AR8216_REG_MIB_FUNC
, AR8216_MIB_FUNC
| AR8236_MIB_EN
,
771 (AR8216_MIB_FUNC_NO_OP
<< AR8216_MIB_FUNC_S
) |
776 ar8316_hw_init(struct ar8xxx_priv
*priv
)
780 val
= ar8xxx_read(priv
, AR8316_REG_POSTRIP
);
782 if (priv
->phy
->interface
== PHY_INTERFACE_MODE_RGMII
) {
783 if (priv
->port4_phy
) {
784 /* value taken from Ubiquiti RouterStation Pro */
786 pr_info("ar8316: Using port 4 as PHY\n");
789 pr_info("ar8316: Using port 4 as switch port\n");
791 } else if (priv
->phy
->interface
== PHY_INTERFACE_MODE_GMII
) {
792 /* value taken from AVM Fritz!Box 7390 sources */
795 /* no known value for phy interface */
796 pr_err("ar8316: unsupported mii mode: %d.\n",
797 priv
->phy
->interface
);
804 ar8xxx_write(priv
, AR8316_REG_POSTRIP
, newval
);
806 if (priv
->port4_phy
&&
807 priv
->phy
->interface
== PHY_INTERFACE_MODE_RGMII
) {
808 /* work around for phy4 rgmii mode */
809 ar8xxx_phy_dbg_write(priv
, 4, 0x12, 0x480c);
811 ar8xxx_phy_dbg_write(priv
, 4, 0x0, 0x824e);
813 ar8xxx_phy_dbg_write(priv
, 4, 0x5, 0x3d47);
817 ar8xxx_phy_init(priv
);
820 priv
->initialized
= true;
825 ar8316_init_globals(struct ar8xxx_priv
*priv
)
827 /* standard atheros magic */
828 ar8xxx_write(priv
, 0x38, 0xc000050e);
830 /* enable cpu port to receive multicast and broadcast frames */
831 ar8xxx_write(priv
, AR8216_REG_FLOOD_MASK
, 0x003f003f);
833 /* enable jumbo frames */
834 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
835 AR8316_GCTRL_MTU
, 9018 + 8 + 2);
837 /* Enable MIB counters */
838 ar8xxx_rmw(priv
, AR8216_REG_MIB_FUNC
, AR8216_MIB_FUNC
| AR8236_MIB_EN
,
839 (AR8216_MIB_FUNC_NO_OP
<< AR8216_MIB_FUNC_S
) |
844 ar8xxx_sw_set_vlan(struct switch_dev
*dev
, const struct switch_attr
*attr
,
845 struct switch_val
*val
)
847 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
848 priv
->vlan
= !!val
->value
.i
;
853 ar8xxx_sw_get_vlan(struct switch_dev
*dev
, const struct switch_attr
*attr
,
854 struct switch_val
*val
)
856 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
857 val
->value
.i
= priv
->vlan
;
863 ar8xxx_sw_set_pvid(struct switch_dev
*dev
, int port
, int vlan
)
865 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
867 /* make sure no invalid PVIDs get set */
869 if (vlan
>= dev
->vlans
)
872 priv
->pvid
[port
] = vlan
;
877 ar8xxx_sw_get_pvid(struct switch_dev
*dev
, int port
, int *vlan
)
879 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
880 *vlan
= priv
->pvid
[port
];
885 ar8xxx_sw_set_vid(struct switch_dev
*dev
, const struct switch_attr
*attr
,
886 struct switch_val
*val
)
888 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
889 priv
->vlan_id
[val
->port_vlan
] = val
->value
.i
;
894 ar8xxx_sw_get_vid(struct switch_dev
*dev
, const struct switch_attr
*attr
,
895 struct switch_val
*val
)
897 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
898 val
->value
.i
= priv
->vlan_id
[val
->port_vlan
];
903 ar8xxx_sw_get_port_link(struct switch_dev
*dev
, int port
,
904 struct switch_port_link
*link
)
906 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
908 ar8216_read_port_link(priv
, port
, link
);
913 ar8xxx_sw_get_ports(struct switch_dev
*dev
, struct switch_val
*val
)
915 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
916 u8 ports
= priv
->vlan_table
[val
->port_vlan
];
920 for (i
= 0; i
< dev
->ports
; i
++) {
921 struct switch_port
*p
;
923 if (!(ports
& (1 << i
)))
926 p
= &val
->value
.ports
[val
->len
++];
928 if (priv
->vlan_tagged
& (1 << i
))
929 p
->flags
= (1 << SWITCH_PORT_FLAG_TAGGED
);
937 ar8xxx_sw_set_ports(struct switch_dev
*dev
, struct switch_val
*val
)
939 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
940 u8
*vt
= &priv
->vlan_table
[val
->port_vlan
];
944 for (i
= 0; i
< val
->len
; i
++) {
945 struct switch_port
*p
= &val
->value
.ports
[i
];
947 if (p
->flags
& (1 << SWITCH_PORT_FLAG_TAGGED
)) {
948 priv
->vlan_tagged
|= (1 << p
->id
);
950 priv
->vlan_tagged
&= ~(1 << p
->id
);
951 priv
->pvid
[p
->id
] = val
->port_vlan
;
953 /* make sure that an untagged port does not
954 * appear in other vlans */
955 for (j
= 0; j
< AR8X16_MAX_VLANS
; j
++) {
956 if (j
== val
->port_vlan
)
958 priv
->vlan_table
[j
] &= ~(1 << p
->id
);
968 ar8216_set_mirror_regs(struct ar8xxx_priv
*priv
)
972 /* reset all mirror registers */
973 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CPUPORT
,
974 AR8216_GLOBAL_CPUPORT_MIRROR_PORT
,
975 (0xF << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S
));
976 for (port
= 0; port
< AR8216_NUM_PORTS
; port
++) {
977 ar8xxx_reg_clear(priv
, AR8216_REG_PORT_CTRL(port
),
978 AR8216_PORT_CTRL_MIRROR_RX
);
980 ar8xxx_reg_clear(priv
, AR8216_REG_PORT_CTRL(port
),
981 AR8216_PORT_CTRL_MIRROR_TX
);
984 /* now enable mirroring if necessary */
985 if (priv
->source_port
>= AR8216_NUM_PORTS
||
986 priv
->monitor_port
>= AR8216_NUM_PORTS
||
987 priv
->source_port
== priv
->monitor_port
) {
991 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CPUPORT
,
992 AR8216_GLOBAL_CPUPORT_MIRROR_PORT
,
993 (priv
->monitor_port
<< AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S
));
996 ar8xxx_reg_set(priv
, AR8216_REG_PORT_CTRL(priv
->source_port
),
997 AR8216_PORT_CTRL_MIRROR_RX
);
1000 ar8xxx_reg_set(priv
, AR8216_REG_PORT_CTRL(priv
->source_port
),
1001 AR8216_PORT_CTRL_MIRROR_TX
);
1005 ar8xxx_sw_hw_apply(struct switch_dev
*dev
)
1007 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1008 u8 portmask
[AR8X16_MAX_PORTS
];
1011 mutex_lock(&priv
->reg_mutex
);
1012 /* flush all vlan translation unit entries */
1013 priv
->chip
->vtu_flush(priv
);
1015 memset(portmask
, 0, sizeof(portmask
));
1017 /* calculate the port destination masks and load vlans
1018 * into the vlan translation unit */
1019 for (j
= 0; j
< AR8X16_MAX_VLANS
; j
++) {
1020 u8 vp
= priv
->vlan_table
[j
];
1025 for (i
= 0; i
< dev
->ports
; i
++) {
1028 portmask
[i
] |= vp
& ~mask
;
1031 priv
->chip
->vtu_load_vlan(priv
, priv
->vlan_id
[j
],
1032 priv
->vlan_table
[j
]);
1036 * isolate all ports, but connect them to the cpu port */
1037 for (i
= 0; i
< dev
->ports
; i
++) {
1038 if (i
== AR8216_PORT_CPU
)
1041 portmask
[i
] = 1 << AR8216_PORT_CPU
;
1042 portmask
[AR8216_PORT_CPU
] |= (1 << i
);
1046 /* update the port destination mask registers and tag settings */
1047 for (i
= 0; i
< dev
->ports
; i
++) {
1048 priv
->chip
->setup_port(priv
, i
, portmask
[i
]);
1051 priv
->chip
->set_mirror_regs(priv
);
1053 mutex_unlock(&priv
->reg_mutex
);
1058 ar8xxx_sw_reset_switch(struct switch_dev
*dev
)
1060 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1061 const struct ar8xxx_chip
*chip
= priv
->chip
;
1064 mutex_lock(&priv
->reg_mutex
);
1065 memset(&priv
->vlan
, 0, sizeof(struct ar8xxx_priv
) -
1066 offsetof(struct ar8xxx_priv
, vlan
));
1068 for (i
= 0; i
< AR8X16_MAX_VLANS
; i
++)
1069 priv
->vlan_id
[i
] = i
;
1071 /* Configure all ports */
1072 for (i
= 0; i
< dev
->ports
; i
++)
1073 chip
->init_port(priv
, i
);
1075 priv
->mirror_rx
= false;
1076 priv
->mirror_tx
= false;
1077 priv
->source_port
= 0;
1078 priv
->monitor_port
= 0;
1080 chip
->init_globals(priv
);
1082 mutex_unlock(&priv
->reg_mutex
);
1084 return chip
->sw_hw_apply(dev
);
1088 ar8xxx_sw_set_reset_mibs(struct switch_dev
*dev
,
1089 const struct switch_attr
*attr
,
1090 struct switch_val
*val
)
1092 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1096 if (!ar8xxx_has_mib_counters(priv
))
1099 mutex_lock(&priv
->mib_lock
);
1101 len
= priv
->dev
.ports
* priv
->chip
->num_mibs
*
1102 sizeof(*priv
->mib_stats
);
1103 memset(priv
->mib_stats
, '\0', len
);
1104 ret
= ar8xxx_mib_flush(priv
);
1111 mutex_unlock(&priv
->mib_lock
);
1116 ar8xxx_sw_set_mirror_rx_enable(struct switch_dev
*dev
,
1117 const struct switch_attr
*attr
,
1118 struct switch_val
*val
)
1120 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1122 mutex_lock(&priv
->reg_mutex
);
1123 priv
->mirror_rx
= !!val
->value
.i
;
1124 priv
->chip
->set_mirror_regs(priv
);
1125 mutex_unlock(&priv
->reg_mutex
);
1131 ar8xxx_sw_get_mirror_rx_enable(struct switch_dev
*dev
,
1132 const struct switch_attr
*attr
,
1133 struct switch_val
*val
)
1135 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1136 val
->value
.i
= priv
->mirror_rx
;
1141 ar8xxx_sw_set_mirror_tx_enable(struct switch_dev
*dev
,
1142 const struct switch_attr
*attr
,
1143 struct switch_val
*val
)
1145 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1147 mutex_lock(&priv
->reg_mutex
);
1148 priv
->mirror_tx
= !!val
->value
.i
;
1149 priv
->chip
->set_mirror_regs(priv
);
1150 mutex_unlock(&priv
->reg_mutex
);
1156 ar8xxx_sw_get_mirror_tx_enable(struct switch_dev
*dev
,
1157 const struct switch_attr
*attr
,
1158 struct switch_val
*val
)
1160 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1161 val
->value
.i
= priv
->mirror_tx
;
1166 ar8xxx_sw_set_mirror_monitor_port(struct switch_dev
*dev
,
1167 const struct switch_attr
*attr
,
1168 struct switch_val
*val
)
1170 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1172 mutex_lock(&priv
->reg_mutex
);
1173 priv
->monitor_port
= val
->value
.i
;
1174 priv
->chip
->set_mirror_regs(priv
);
1175 mutex_unlock(&priv
->reg_mutex
);
1181 ar8xxx_sw_get_mirror_monitor_port(struct switch_dev
*dev
,
1182 const struct switch_attr
*attr
,
1183 struct switch_val
*val
)
1185 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1186 val
->value
.i
= priv
->monitor_port
;
1191 ar8xxx_sw_set_mirror_source_port(struct switch_dev
*dev
,
1192 const struct switch_attr
*attr
,
1193 struct switch_val
*val
)
1195 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1197 mutex_lock(&priv
->reg_mutex
);
1198 priv
->source_port
= val
->value
.i
;
1199 priv
->chip
->set_mirror_regs(priv
);
1200 mutex_unlock(&priv
->reg_mutex
);
1206 ar8xxx_sw_get_mirror_source_port(struct switch_dev
*dev
,
1207 const struct switch_attr
*attr
,
1208 struct switch_val
*val
)
1210 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1211 val
->value
.i
= priv
->source_port
;
1216 ar8xxx_sw_set_port_reset_mib(struct switch_dev
*dev
,
1217 const struct switch_attr
*attr
,
1218 struct switch_val
*val
)
1220 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1224 if (!ar8xxx_has_mib_counters(priv
))
1227 port
= val
->port_vlan
;
1228 if (port
>= dev
->ports
)
1231 mutex_lock(&priv
->mib_lock
);
1232 ret
= ar8xxx_mib_capture(priv
);
1236 ar8xxx_mib_fetch_port_stat(priv
, port
, true);
1241 mutex_unlock(&priv
->mib_lock
);
1246 ar8xxx_sw_get_port_mib(struct switch_dev
*dev
,
1247 const struct switch_attr
*attr
,
1248 struct switch_val
*val
)
1250 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1251 const struct ar8xxx_chip
*chip
= priv
->chip
;
1255 char *buf
= priv
->buf
;
1258 if (!ar8xxx_has_mib_counters(priv
))
1261 port
= val
->port_vlan
;
1262 if (port
>= dev
->ports
)
1265 mutex_lock(&priv
->mib_lock
);
1266 ret
= ar8xxx_mib_capture(priv
);
1270 ar8xxx_mib_fetch_port_stat(priv
, port
, false);
1272 len
+= snprintf(buf
+ len
, sizeof(priv
->buf
) - len
,
1273 "Port %d MIB counters\n",
1276 mib_stats
= &priv
->mib_stats
[port
* chip
->num_mibs
];
1277 for (i
= 0; i
< chip
->num_mibs
; i
++)
1278 len
+= snprintf(buf
+ len
, sizeof(priv
->buf
) - len
,
1280 chip
->mib_decs
[i
].name
,
1289 mutex_unlock(&priv
->mib_lock
);
1293 static const struct switch_attr ar8xxx_sw_attr_globals
[] = {
1295 .type
= SWITCH_TYPE_INT
,
1296 .name
= "enable_vlan",
1297 .description
= "Enable VLAN mode",
1298 .set
= ar8xxx_sw_set_vlan
,
1299 .get
= ar8xxx_sw_get_vlan
,
1303 .type
= SWITCH_TYPE_NOVAL
,
1304 .name
= "reset_mibs",
1305 .description
= "Reset all MIB counters",
1306 .set
= ar8xxx_sw_set_reset_mibs
,
1309 .type
= SWITCH_TYPE_INT
,
1310 .name
= "enable_mirror_rx",
1311 .description
= "Enable mirroring of RX packets",
1312 .set
= ar8xxx_sw_set_mirror_rx_enable
,
1313 .get
= ar8xxx_sw_get_mirror_rx_enable
,
1317 .type
= SWITCH_TYPE_INT
,
1318 .name
= "enable_mirror_tx",
1319 .description
= "Enable mirroring of TX packets",
1320 .set
= ar8xxx_sw_set_mirror_tx_enable
,
1321 .get
= ar8xxx_sw_get_mirror_tx_enable
,
1325 .type
= SWITCH_TYPE_INT
,
1326 .name
= "mirror_monitor_port",
1327 .description
= "Mirror monitor port",
1328 .set
= ar8xxx_sw_set_mirror_monitor_port
,
1329 .get
= ar8xxx_sw_get_mirror_monitor_port
,
1330 .max
= AR8216_NUM_PORTS
- 1
1333 .type
= SWITCH_TYPE_INT
,
1334 .name
= "mirror_source_port",
1335 .description
= "Mirror source port",
1336 .set
= ar8xxx_sw_set_mirror_source_port
,
1337 .get
= ar8xxx_sw_get_mirror_source_port
,
1338 .max
= AR8216_NUM_PORTS
- 1
1342 const struct switch_attr ar8xxx_sw_attr_port
[2] = {
1344 .type
= SWITCH_TYPE_NOVAL
,
1345 .name
= "reset_mib",
1346 .description
= "Reset single port MIB counters",
1347 .set
= ar8xxx_sw_set_port_reset_mib
,
1350 .type
= SWITCH_TYPE_STRING
,
1352 .description
= "Get port's MIB counters",
1354 .get
= ar8xxx_sw_get_port_mib
,
1358 const struct switch_attr ar8xxx_sw_attr_vlan
[1] = {
1360 .type
= SWITCH_TYPE_INT
,
1362 .description
= "VLAN ID (0-4094)",
1363 .set
= ar8xxx_sw_set_vid
,
1364 .get
= ar8xxx_sw_get_vid
,
1369 static const struct switch_dev_ops ar8xxx_sw_ops
= {
1371 .attr
= ar8xxx_sw_attr_globals
,
1372 .n_attr
= ARRAY_SIZE(ar8xxx_sw_attr_globals
),
1375 .attr
= ar8xxx_sw_attr_port
,
1376 .n_attr
= ARRAY_SIZE(ar8xxx_sw_attr_port
),
1379 .attr
= ar8xxx_sw_attr_vlan
,
1380 .n_attr
= ARRAY_SIZE(ar8xxx_sw_attr_vlan
),
1382 .get_port_pvid
= ar8xxx_sw_get_pvid
,
1383 .set_port_pvid
= ar8xxx_sw_set_pvid
,
1384 .get_vlan_ports
= ar8xxx_sw_get_ports
,
1385 .set_vlan_ports
= ar8xxx_sw_set_ports
,
1386 .apply_config
= ar8xxx_sw_hw_apply
,
1387 .reset_switch
= ar8xxx_sw_reset_switch
,
1388 .get_port_link
= ar8xxx_sw_get_port_link
,
1391 static const struct ar8xxx_chip ar8216_chip
= {
1392 .caps
= AR8XXX_CAP_MIB_COUNTERS
,
1394 .reg_port_stats_start
= 0x19000,
1395 .reg_port_stats_length
= 0xa0,
1397 .name
= "Atheros AR8216",
1398 .ports
= AR8216_NUM_PORTS
,
1399 .vlans
= AR8216_NUM_VLANS
,
1400 .swops
= &ar8xxx_sw_ops
,
1402 .hw_init
= ar8216_hw_init
,
1403 .init_globals
= ar8216_init_globals
,
1404 .init_port
= ar8216_init_port
,
1405 .setup_port
= ar8216_setup_port
,
1406 .read_port_status
= ar8216_read_port_status
,
1407 .atu_flush
= ar8216_atu_flush
,
1408 .vtu_flush
= ar8216_vtu_flush
,
1409 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
1410 .set_mirror_regs
= ar8216_set_mirror_regs
,
1411 .sw_hw_apply
= ar8xxx_sw_hw_apply
,
1413 .num_mibs
= ARRAY_SIZE(ar8216_mibs
),
1414 .mib_decs
= ar8216_mibs
,
1415 .mib_func
= AR8216_REG_MIB_FUNC
1418 static const struct ar8xxx_chip ar8236_chip
= {
1419 .caps
= AR8XXX_CAP_MIB_COUNTERS
,
1421 .reg_port_stats_start
= 0x20000,
1422 .reg_port_stats_length
= 0x100,
1424 .name
= "Atheros AR8236",
1425 .ports
= AR8216_NUM_PORTS
,
1426 .vlans
= AR8216_NUM_VLANS
,
1427 .swops
= &ar8xxx_sw_ops
,
1429 .hw_init
= ar8216_hw_init
,
1430 .init_globals
= ar8236_init_globals
,
1431 .init_port
= ar8216_init_port
,
1432 .setup_port
= ar8236_setup_port
,
1433 .read_port_status
= ar8216_read_port_status
,
1434 .atu_flush
= ar8216_atu_flush
,
1435 .vtu_flush
= ar8216_vtu_flush
,
1436 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
1437 .set_mirror_regs
= ar8216_set_mirror_regs
,
1438 .sw_hw_apply
= ar8xxx_sw_hw_apply
,
1440 .num_mibs
= ARRAY_SIZE(ar8236_mibs
),
1441 .mib_decs
= ar8236_mibs
,
1442 .mib_func
= AR8216_REG_MIB_FUNC
1445 static const struct ar8xxx_chip ar8316_chip
= {
1446 .caps
= AR8XXX_CAP_GIGE
| AR8XXX_CAP_MIB_COUNTERS
,
1448 .reg_port_stats_start
= 0x20000,
1449 .reg_port_stats_length
= 0x100,
1451 .name
= "Atheros AR8316",
1452 .ports
= AR8216_NUM_PORTS
,
1453 .vlans
= AR8X16_MAX_VLANS
,
1454 .swops
= &ar8xxx_sw_ops
,
1456 .hw_init
= ar8316_hw_init
,
1457 .init_globals
= ar8316_init_globals
,
1458 .init_port
= ar8216_init_port
,
1459 .setup_port
= ar8216_setup_port
,
1460 .read_port_status
= ar8216_read_port_status
,
1461 .atu_flush
= ar8216_atu_flush
,
1462 .vtu_flush
= ar8216_vtu_flush
,
1463 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
1464 .set_mirror_regs
= ar8216_set_mirror_regs
,
1465 .sw_hw_apply
= ar8xxx_sw_hw_apply
,
1467 .num_mibs
= ARRAY_SIZE(ar8236_mibs
),
1468 .mib_decs
= ar8236_mibs
,
1469 .mib_func
= AR8216_REG_MIB_FUNC
1473 ar8xxx_id_chip(struct ar8xxx_priv
*priv
)
1479 val
= ar8xxx_read(priv
, AR8216_REG_CTRL
);
1483 id
= val
& (AR8216_CTRL_REVISION
| AR8216_CTRL_VERSION
);
1484 for (i
= 0; i
< AR8X16_PROBE_RETRIES
; i
++) {
1487 val
= ar8xxx_read(priv
, AR8216_REG_CTRL
);
1491 t
= val
& (AR8216_CTRL_REVISION
| AR8216_CTRL_VERSION
);
1496 priv
->chip_ver
= (id
& AR8216_CTRL_VERSION
) >> AR8216_CTRL_VERSION_S
;
1497 priv
->chip_rev
= (id
& AR8216_CTRL_REVISION
);
1499 switch (priv
->chip_ver
) {
1500 case AR8XXX_VER_AR8216
:
1501 priv
->chip
= &ar8216_chip
;
1503 case AR8XXX_VER_AR8236
:
1504 priv
->chip
= &ar8236_chip
;
1506 case AR8XXX_VER_AR8316
:
1507 priv
->chip
= &ar8316_chip
;
1509 case AR8XXX_VER_AR8327
:
1510 priv
->chip
= &ar8327_chip
;
1512 case AR8XXX_VER_AR8337
:
1513 priv
->chip
= &ar8337_chip
;
1516 pr_err("ar8216: Unknown Atheros device [ver=%d, rev=%d]\n",
1517 priv
->chip_ver
, priv
->chip_rev
);
1526 ar8xxx_mib_work_func(struct work_struct
*work
)
1528 struct ar8xxx_priv
*priv
;
1531 priv
= container_of(work
, struct ar8xxx_priv
, mib_work
.work
);
1533 mutex_lock(&priv
->mib_lock
);
1535 err
= ar8xxx_mib_capture(priv
);
1539 ar8xxx_mib_fetch_port_stat(priv
, priv
->mib_next_port
, false);
1542 priv
->mib_next_port
++;
1543 if (priv
->mib_next_port
>= priv
->dev
.ports
)
1544 priv
->mib_next_port
= 0;
1546 mutex_unlock(&priv
->mib_lock
);
1547 schedule_delayed_work(&priv
->mib_work
,
1548 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY
));
1552 ar8xxx_mib_init(struct ar8xxx_priv
*priv
)
1556 if (!ar8xxx_has_mib_counters(priv
))
1559 BUG_ON(!priv
->chip
->mib_decs
|| !priv
->chip
->num_mibs
);
1561 len
= priv
->dev
.ports
* priv
->chip
->num_mibs
*
1562 sizeof(*priv
->mib_stats
);
1563 priv
->mib_stats
= kzalloc(len
, GFP_KERNEL
);
1565 if (!priv
->mib_stats
)
1572 ar8xxx_mib_start(struct ar8xxx_priv
*priv
)
1574 if (!ar8xxx_has_mib_counters(priv
))
1577 schedule_delayed_work(&priv
->mib_work
,
1578 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY
));
1582 ar8xxx_mib_stop(struct ar8xxx_priv
*priv
)
1584 if (!ar8xxx_has_mib_counters(priv
))
1587 cancel_delayed_work(&priv
->mib_work
);
1590 static struct ar8xxx_priv
*
1593 struct ar8xxx_priv
*priv
;
1595 priv
= kzalloc(sizeof(struct ar8xxx_priv
), GFP_KERNEL
);
1599 mutex_init(&priv
->reg_mutex
);
1600 mutex_init(&priv
->mib_lock
);
1601 INIT_DELAYED_WORK(&priv
->mib_work
, ar8xxx_mib_work_func
);
1607 ar8xxx_free(struct ar8xxx_priv
*priv
)
1609 if (priv
->chip
&& priv
->chip
->cleanup
)
1610 priv
->chip
->cleanup(priv
);
1612 kfree(priv
->chip_data
);
1613 kfree(priv
->mib_stats
);
1618 ar8xxx_probe_switch(struct ar8xxx_priv
*priv
)
1620 const struct ar8xxx_chip
*chip
;
1621 struct switch_dev
*swdev
;
1624 ret
= ar8xxx_id_chip(priv
);
1631 swdev
->cpu_port
= AR8216_PORT_CPU
;
1632 swdev
->name
= chip
->name
;
1633 swdev
->vlans
= chip
->vlans
;
1634 swdev
->ports
= chip
->ports
;
1635 swdev
->ops
= chip
->swops
;
1637 ret
= ar8xxx_mib_init(priv
);
1645 ar8xxx_start(struct ar8xxx_priv
*priv
)
1651 ret
= priv
->chip
->hw_init(priv
);
1655 ret
= ar8xxx_sw_reset_switch(&priv
->dev
);
1661 ar8xxx_mib_start(priv
);
1667 ar8xxx_phy_config_init(struct phy_device
*phydev
)
1669 struct ar8xxx_priv
*priv
= phydev
->priv
;
1670 struct net_device
*dev
= phydev
->attached_dev
;
1676 if (priv
->chip
->config_at_probe
)
1677 return ar8xxx_phy_check_aneg(phydev
);
1681 if (phydev
->addr
!= 0) {
1682 if (chip_is_ar8316(priv
)) {
1683 /* switch device has been initialized, reinit */
1684 priv
->dev
.ports
= (AR8216_NUM_PORTS
- 1);
1685 priv
->initialized
= false;
1686 priv
->port4_phy
= true;
1687 ar8316_hw_init(priv
);
1694 ret
= ar8xxx_start(priv
);
1698 /* VID fixup only needed on ar8216 */
1699 if (chip_is_ar8216(priv
)) {
1700 dev
->phy_ptr
= priv
;
1701 dev
->priv_flags
|= IFF_NO_IP_ALIGN
;
1702 dev
->eth_mangle_rx
= ar8216_mangle_rx
;
1703 dev
->eth_mangle_tx
= ar8216_mangle_tx
;
1710 ar8xxx_phy_read_status(struct phy_device
*phydev
)
1712 struct ar8xxx_priv
*priv
= phydev
->priv
;
1713 struct switch_port_link link
;
1716 if (phydev
->addr
!= 0)
1717 return genphy_read_status(phydev
);
1719 ar8216_read_port_link(priv
, phydev
->addr
, &link
);
1720 phydev
->link
= !!link
.link
;
1724 switch (link
.speed
) {
1725 case SWITCH_PORT_SPEED_10
:
1726 phydev
->speed
= SPEED_10
;
1728 case SWITCH_PORT_SPEED_100
:
1729 phydev
->speed
= SPEED_100
;
1731 case SWITCH_PORT_SPEED_1000
:
1732 phydev
->speed
= SPEED_1000
;
1737 phydev
->duplex
= link
.duplex
? DUPLEX_FULL
: DUPLEX_HALF
;
1739 /* flush the address translation unit */
1740 mutex_lock(&priv
->reg_mutex
);
1741 ret
= priv
->chip
->atu_flush(priv
);
1742 mutex_unlock(&priv
->reg_mutex
);
1744 phydev
->state
= PHY_RUNNING
;
1745 netif_carrier_on(phydev
->attached_dev
);
1746 phydev
->adjust_link(phydev
->attached_dev
);
1752 ar8xxx_phy_config_aneg(struct phy_device
*phydev
)
1754 if (phydev
->addr
== 0)
1757 return genphy_config_aneg(phydev
);
1760 static const u32 ar8xxx_phy_ids
[] = {
1762 0x004dd034, /* AR8327 */
1763 0x004dd036, /* AR8337 */
1766 0x004dd043, /* AR8236 */
1770 ar8xxx_phy_match(u32 phy_id
)
1774 for (i
= 0; i
< ARRAY_SIZE(ar8xxx_phy_ids
); i
++)
1775 if (phy_id
== ar8xxx_phy_ids
[i
])
1782 ar8xxx_is_possible(struct mii_bus
*bus
)
1786 for (i
= 0; i
< 4; i
++) {
1789 phy_id
= mdiobus_read(bus
, i
, MII_PHYSID1
) << 16;
1790 phy_id
|= mdiobus_read(bus
, i
, MII_PHYSID2
);
1791 if (!ar8xxx_phy_match(phy_id
)) {
1792 pr_debug("ar8xxx: unknown PHY at %s:%02x id:%08x\n",
1793 dev_name(&bus
->dev
), i
, phy_id
);
1802 ar8xxx_phy_probe(struct phy_device
*phydev
)
1804 struct ar8xxx_priv
*priv
;
1805 struct switch_dev
*swdev
;
1808 /* skip PHYs at unused adresses */
1809 if (phydev
->addr
!= 0 && phydev
->addr
!= 4)
1812 if (!ar8xxx_is_possible(phydev
->bus
))
1815 mutex_lock(&ar8xxx_dev_list_lock
);
1816 list_for_each_entry(priv
, &ar8xxx_dev_list
, list
)
1817 if (priv
->mii_bus
== phydev
->bus
)
1820 priv
= ar8xxx_create();
1826 priv
->mii_bus
= phydev
->bus
;
1828 ret
= ar8xxx_probe_switch(priv
);
1833 swdev
->alias
= dev_name(&priv
->mii_bus
->dev
);
1834 ret
= register_switch(swdev
, NULL
);
1838 pr_info("%s: %s rev. %u switch registered on %s\n",
1839 swdev
->devname
, swdev
->name
, priv
->chip_rev
,
1840 dev_name(&priv
->mii_bus
->dev
));
1845 if (phydev
->addr
== 0) {
1846 if (ar8xxx_has_gige(priv
)) {
1847 phydev
->supported
= SUPPORTED_1000baseT_Full
;
1848 phydev
->advertising
= ADVERTISED_1000baseT_Full
;
1850 phydev
->supported
= SUPPORTED_100baseT_Full
;
1851 phydev
->advertising
= ADVERTISED_100baseT_Full
;
1854 if (priv
->chip
->config_at_probe
) {
1857 ret
= ar8xxx_start(priv
);
1859 goto err_unregister_switch
;
1862 if (ar8xxx_has_gige(priv
)) {
1863 phydev
->supported
|= SUPPORTED_1000baseT_Full
;
1864 phydev
->advertising
|= ADVERTISED_1000baseT_Full
;
1868 phydev
->priv
= priv
;
1870 list_add(&priv
->list
, &ar8xxx_dev_list
);
1872 mutex_unlock(&ar8xxx_dev_list_lock
);
1876 err_unregister_switch
:
1877 if (--priv
->use_count
)
1880 unregister_switch(&priv
->dev
);
1885 mutex_unlock(&ar8xxx_dev_list_lock
);
1890 ar8xxx_phy_detach(struct phy_device
*phydev
)
1892 struct net_device
*dev
= phydev
->attached_dev
;
1897 dev
->phy_ptr
= NULL
;
1898 dev
->priv_flags
&= ~IFF_NO_IP_ALIGN
;
1899 dev
->eth_mangle_rx
= NULL
;
1900 dev
->eth_mangle_tx
= NULL
;
1904 ar8xxx_phy_remove(struct phy_device
*phydev
)
1906 struct ar8xxx_priv
*priv
= phydev
->priv
;
1911 phydev
->priv
= NULL
;
1912 if (--priv
->use_count
> 0)
1915 mutex_lock(&ar8xxx_dev_list_lock
);
1916 list_del(&priv
->list
);
1917 mutex_unlock(&ar8xxx_dev_list_lock
);
1919 unregister_switch(&priv
->dev
);
1920 ar8xxx_mib_stop(priv
);
1924 #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)
1926 ar8xxx_phy_soft_reset(struct phy_device
*phydev
)
1928 /* we don't need an extra reset */
1933 static struct phy_driver ar8xxx_phy_driver
= {
1934 .phy_id
= 0x004d0000,
1935 .name
= "Atheros AR8216/AR8236/AR8316",
1936 .phy_id_mask
= 0xffff0000,
1937 .features
= PHY_BASIC_FEATURES
,
1938 .probe
= ar8xxx_phy_probe
,
1939 .remove
= ar8xxx_phy_remove
,
1940 .detach
= ar8xxx_phy_detach
,
1941 .config_init
= ar8xxx_phy_config_init
,
1942 .config_aneg
= ar8xxx_phy_config_aneg
,
1943 .read_status
= ar8xxx_phy_read_status
,
1944 #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)
1945 .soft_reset
= ar8xxx_phy_soft_reset
,
1947 .driver
= { .owner
= THIS_MODULE
},
1953 return phy_driver_register(&ar8xxx_phy_driver
);
1959 phy_driver_unregister(&ar8xxx_phy_driver
);
1962 module_init(ar8xxx_init
);
1963 module_exit(ar8xxx_exit
);
1964 MODULE_LICENSE("GPL");