2 * ar8216.c: AR8216 switch driver
4 * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>
5 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/list.h>
22 #include <linux/if_ether.h>
23 #include <linux/skbuff.h>
24 #include <linux/netdevice.h>
25 #include <linux/netlink.h>
26 #include <linux/of_device.h>
27 #include <linux/of_mdio.h>
28 #include <linux/of_net.h>
29 #include <linux/bitops.h>
30 #include <net/genetlink.h>
31 #include <linux/switch.h>
32 #include <linux/delay.h>
33 #include <linux/phy.h>
34 #include <linux/etherdevice.h>
35 #include <linux/lockdep.h>
36 #include <linux/ar8216_platform.h>
37 #include <linux/workqueue.h>
38 #include <linux/version.h>
42 extern const struct ar8xxx_chip ar8327_chip
;
43 extern const struct ar8xxx_chip ar8337_chip
;
45 #define AR8XXX_MIB_WORK_DELAY 2000 /* msecs */
47 #define MIB_DESC(_s , _o, _n) \
54 static const struct ar8xxx_mib_desc ar8216_mibs
[] = {
55 MIB_DESC(1, AR8216_STATS_RXBROAD
, "RxBroad"),
56 MIB_DESC(1, AR8216_STATS_RXPAUSE
, "RxPause"),
57 MIB_DESC(1, AR8216_STATS_RXMULTI
, "RxMulti"),
58 MIB_DESC(1, AR8216_STATS_RXFCSERR
, "RxFcsErr"),
59 MIB_DESC(1, AR8216_STATS_RXALIGNERR
, "RxAlignErr"),
60 MIB_DESC(1, AR8216_STATS_RXRUNT
, "RxRunt"),
61 MIB_DESC(1, AR8216_STATS_RXFRAGMENT
, "RxFragment"),
62 MIB_DESC(1, AR8216_STATS_RX64BYTE
, "Rx64Byte"),
63 MIB_DESC(1, AR8216_STATS_RX128BYTE
, "Rx128Byte"),
64 MIB_DESC(1, AR8216_STATS_RX256BYTE
, "Rx256Byte"),
65 MIB_DESC(1, AR8216_STATS_RX512BYTE
, "Rx512Byte"),
66 MIB_DESC(1, AR8216_STATS_RX1024BYTE
, "Rx1024Byte"),
67 MIB_DESC(1, AR8216_STATS_RXMAXBYTE
, "RxMaxByte"),
68 MIB_DESC(1, AR8216_STATS_RXTOOLONG
, "RxTooLong"),
69 MIB_DESC(2, AR8216_STATS_RXGOODBYTE
, "RxGoodByte"),
70 MIB_DESC(2, AR8216_STATS_RXBADBYTE
, "RxBadByte"),
71 MIB_DESC(1, AR8216_STATS_RXOVERFLOW
, "RxOverFlow"),
72 MIB_DESC(1, AR8216_STATS_FILTERED
, "Filtered"),
73 MIB_DESC(1, AR8216_STATS_TXBROAD
, "TxBroad"),
74 MIB_DESC(1, AR8216_STATS_TXPAUSE
, "TxPause"),
75 MIB_DESC(1, AR8216_STATS_TXMULTI
, "TxMulti"),
76 MIB_DESC(1, AR8216_STATS_TXUNDERRUN
, "TxUnderRun"),
77 MIB_DESC(1, AR8216_STATS_TX64BYTE
, "Tx64Byte"),
78 MIB_DESC(1, AR8216_STATS_TX128BYTE
, "Tx128Byte"),
79 MIB_DESC(1, AR8216_STATS_TX256BYTE
, "Tx256Byte"),
80 MIB_DESC(1, AR8216_STATS_TX512BYTE
, "Tx512Byte"),
81 MIB_DESC(1, AR8216_STATS_TX1024BYTE
, "Tx1024Byte"),
82 MIB_DESC(1, AR8216_STATS_TXMAXBYTE
, "TxMaxByte"),
83 MIB_DESC(1, AR8216_STATS_TXOVERSIZE
, "TxOverSize"),
84 MIB_DESC(2, AR8216_STATS_TXBYTE
, "TxByte"),
85 MIB_DESC(1, AR8216_STATS_TXCOLLISION
, "TxCollision"),
86 MIB_DESC(1, AR8216_STATS_TXABORTCOL
, "TxAbortCol"),
87 MIB_DESC(1, AR8216_STATS_TXMULTICOL
, "TxMultiCol"),
88 MIB_DESC(1, AR8216_STATS_TXSINGLECOL
, "TxSingleCol"),
89 MIB_DESC(1, AR8216_STATS_TXEXCDEFER
, "TxExcDefer"),
90 MIB_DESC(1, AR8216_STATS_TXDEFER
, "TxDefer"),
91 MIB_DESC(1, AR8216_STATS_TXLATECOL
, "TxLateCol"),
94 const struct ar8xxx_mib_desc ar8236_mibs
[39] = {
95 MIB_DESC(1, AR8236_STATS_RXBROAD
, "RxBroad"),
96 MIB_DESC(1, AR8236_STATS_RXPAUSE
, "RxPause"),
97 MIB_DESC(1, AR8236_STATS_RXMULTI
, "RxMulti"),
98 MIB_DESC(1, AR8236_STATS_RXFCSERR
, "RxFcsErr"),
99 MIB_DESC(1, AR8236_STATS_RXALIGNERR
, "RxAlignErr"),
100 MIB_DESC(1, AR8236_STATS_RXRUNT
, "RxRunt"),
101 MIB_DESC(1, AR8236_STATS_RXFRAGMENT
, "RxFragment"),
102 MIB_DESC(1, AR8236_STATS_RX64BYTE
, "Rx64Byte"),
103 MIB_DESC(1, AR8236_STATS_RX128BYTE
, "Rx128Byte"),
104 MIB_DESC(1, AR8236_STATS_RX256BYTE
, "Rx256Byte"),
105 MIB_DESC(1, AR8236_STATS_RX512BYTE
, "Rx512Byte"),
106 MIB_DESC(1, AR8236_STATS_RX1024BYTE
, "Rx1024Byte"),
107 MIB_DESC(1, AR8236_STATS_RX1518BYTE
, "Rx1518Byte"),
108 MIB_DESC(1, AR8236_STATS_RXMAXBYTE
, "RxMaxByte"),
109 MIB_DESC(1, AR8236_STATS_RXTOOLONG
, "RxTooLong"),
110 MIB_DESC(2, AR8236_STATS_RXGOODBYTE
, "RxGoodByte"),
111 MIB_DESC(2, AR8236_STATS_RXBADBYTE
, "RxBadByte"),
112 MIB_DESC(1, AR8236_STATS_RXOVERFLOW
, "RxOverFlow"),
113 MIB_DESC(1, AR8236_STATS_FILTERED
, "Filtered"),
114 MIB_DESC(1, AR8236_STATS_TXBROAD
, "TxBroad"),
115 MIB_DESC(1, AR8236_STATS_TXPAUSE
, "TxPause"),
116 MIB_DESC(1, AR8236_STATS_TXMULTI
, "TxMulti"),
117 MIB_DESC(1, AR8236_STATS_TXUNDERRUN
, "TxUnderRun"),
118 MIB_DESC(1, AR8236_STATS_TX64BYTE
, "Tx64Byte"),
119 MIB_DESC(1, AR8236_STATS_TX128BYTE
, "Tx128Byte"),
120 MIB_DESC(1, AR8236_STATS_TX256BYTE
, "Tx256Byte"),
121 MIB_DESC(1, AR8236_STATS_TX512BYTE
, "Tx512Byte"),
122 MIB_DESC(1, AR8236_STATS_TX1024BYTE
, "Tx1024Byte"),
123 MIB_DESC(1, AR8236_STATS_TX1518BYTE
, "Tx1518Byte"),
124 MIB_DESC(1, AR8236_STATS_TXMAXBYTE
, "TxMaxByte"),
125 MIB_DESC(1, AR8236_STATS_TXOVERSIZE
, "TxOverSize"),
126 MIB_DESC(2, AR8236_STATS_TXBYTE
, "TxByte"),
127 MIB_DESC(1, AR8236_STATS_TXCOLLISION
, "TxCollision"),
128 MIB_DESC(1, AR8236_STATS_TXABORTCOL
, "TxAbortCol"),
129 MIB_DESC(1, AR8236_STATS_TXMULTICOL
, "TxMultiCol"),
130 MIB_DESC(1, AR8236_STATS_TXSINGLECOL
, "TxSingleCol"),
131 MIB_DESC(1, AR8236_STATS_TXEXCDEFER
, "TxExcDefer"),
132 MIB_DESC(1, AR8236_STATS_TXDEFER
, "TxDefer"),
133 MIB_DESC(1, AR8236_STATS_TXLATECOL
, "TxLateCol"),
136 static DEFINE_MUTEX(ar8xxx_dev_list_lock
);
137 static LIST_HEAD(ar8xxx_dev_list
);
139 /* inspired by phy_poll_reset in drivers/net/phy/phy_device.c */
141 ar8xxx_phy_poll_reset(struct mii_bus
*bus
)
143 unsigned int sleep_msecs
= 20;
146 for (elapsed
= sleep_msecs
; elapsed
<= 600;
147 elapsed
+= sleep_msecs
) {
149 for (i
= 0; i
< AR8XXX_NUM_PHYS
; i
++) {
150 ret
= mdiobus_read(bus
, i
, MII_BMCR
);
153 if (ret
& BMCR_RESET
)
155 if (i
== AR8XXX_NUM_PHYS
- 1) {
156 usleep_range(1000, 2000);
165 ar8xxx_phy_check_aneg(struct phy_device
*phydev
)
169 if (phydev
->autoneg
!= AUTONEG_ENABLE
)
172 * BMCR_ANENABLE might have been cleared
173 * by phy_init_hw in certain kernel versions
174 * therefore check for it
176 ret
= phy_read(phydev
, MII_BMCR
);
179 if (ret
& BMCR_ANENABLE
)
182 dev_info(&phydev
->mdio
.dev
, "ANEG disabled, re-enabling ...\n");
183 ret
|= BMCR_ANENABLE
| BMCR_ANRESTART
;
184 return phy_write(phydev
, MII_BMCR
, ret
);
188 ar8xxx_phy_init(struct ar8xxx_priv
*priv
)
193 bus
= priv
->sw_mii_bus
?: priv
->mii_bus
;
194 for (i
= 0; i
< AR8XXX_NUM_PHYS
; i
++) {
195 if (priv
->chip
->phy_fixup
)
196 priv
->chip
->phy_fixup(priv
, i
);
198 /* initialize the port itself */
199 mdiobus_write(bus
, i
, MII_ADVERTISE
,
200 ADVERTISE_ALL
| ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
);
201 if (ar8xxx_has_gige(priv
))
202 mdiobus_write(bus
, i
, MII_CTRL1000
, ADVERTISE_1000FULL
);
203 mdiobus_write(bus
, i
, MII_BMCR
, BMCR_RESET
| BMCR_ANENABLE
);
206 ar8xxx_phy_poll_reset(bus
);
210 ar8xxx_mii_read32(struct ar8xxx_priv
*priv
, int phy_id
, int regnum
)
212 struct mii_bus
*bus
= priv
->mii_bus
;
215 lo
= bus
->read(bus
, phy_id
, regnum
);
216 hi
= bus
->read(bus
, phy_id
, regnum
+ 1);
218 return (hi
<< 16) | lo
;
222 ar8xxx_mii_write32(struct ar8xxx_priv
*priv
, int phy_id
, int regnum
, u32 val
)
224 struct mii_bus
*bus
= priv
->mii_bus
;
228 hi
= (u16
) (val
>> 16);
230 if (priv
->chip
->mii_lo_first
)
232 bus
->write(bus
, phy_id
, regnum
, lo
);
233 bus
->write(bus
, phy_id
, regnum
+ 1, hi
);
235 bus
->write(bus
, phy_id
, regnum
+ 1, hi
);
236 bus
->write(bus
, phy_id
, regnum
, lo
);
241 ar8xxx_read(struct ar8xxx_priv
*priv
, int reg
)
243 struct mii_bus
*bus
= priv
->mii_bus
;
247 split_addr((u32
) reg
, &r1
, &r2
, &page
);
249 mutex_lock(&bus
->mdio_lock
);
251 bus
->write(bus
, 0x18, 0, page
);
252 wait_for_page_switch();
253 val
= ar8xxx_mii_read32(priv
, 0x10 | r2
, r1
);
255 mutex_unlock(&bus
->mdio_lock
);
261 ar8xxx_write(struct ar8xxx_priv
*priv
, int reg
, u32 val
)
263 struct mii_bus
*bus
= priv
->mii_bus
;
266 split_addr((u32
) reg
, &r1
, &r2
, &page
);
268 mutex_lock(&bus
->mdio_lock
);
270 bus
->write(bus
, 0x18, 0, page
);
271 wait_for_page_switch();
272 ar8xxx_mii_write32(priv
, 0x10 | r2
, r1
, val
);
274 mutex_unlock(&bus
->mdio_lock
);
278 ar8xxx_rmw(struct ar8xxx_priv
*priv
, int reg
, u32 mask
, u32 val
)
280 struct mii_bus
*bus
= priv
->mii_bus
;
284 split_addr((u32
) reg
, &r1
, &r2
, &page
);
286 mutex_lock(&bus
->mdio_lock
);
288 bus
->write(bus
, 0x18, 0, page
);
289 wait_for_page_switch();
291 ret
= ar8xxx_mii_read32(priv
, 0x10 | r2
, r1
);
294 ar8xxx_mii_write32(priv
, 0x10 | r2
, r1
, ret
);
296 mutex_unlock(&bus
->mdio_lock
);
301 ar8xxx_phy_dbg_read(struct ar8xxx_priv
*priv
, int phy_addr
,
302 u16 dbg_addr
, u16
*dbg_data
)
304 struct mii_bus
*bus
= priv
->mii_bus
;
306 mutex_lock(&bus
->mdio_lock
);
307 bus
->write(bus
, phy_addr
, MII_ATH_DBG_ADDR
, dbg_addr
);
308 *dbg_data
= bus
->read(bus
, phy_addr
, MII_ATH_DBG_DATA
);
309 mutex_unlock(&bus
->mdio_lock
);
313 ar8xxx_phy_dbg_write(struct ar8xxx_priv
*priv
, int phy_addr
,
314 u16 dbg_addr
, u16 dbg_data
)
316 struct mii_bus
*bus
= priv
->mii_bus
;
318 mutex_lock(&bus
->mdio_lock
);
319 bus
->write(bus
, phy_addr
, MII_ATH_DBG_ADDR
, dbg_addr
);
320 bus
->write(bus
, phy_addr
, MII_ATH_DBG_DATA
, dbg_data
);
321 mutex_unlock(&bus
->mdio_lock
);
325 ar8xxx_phy_mmd_prep(struct mii_bus
*bus
, int phy_addr
, u16 addr
, u16 reg
)
327 bus
->write(bus
, phy_addr
, MII_ATH_MMD_ADDR
, addr
);
328 bus
->write(bus
, phy_addr
, MII_ATH_MMD_DATA
, reg
);
329 bus
->write(bus
, phy_addr
, MII_ATH_MMD_ADDR
, addr
| 0x4000);
333 ar8xxx_phy_mmd_write(struct ar8xxx_priv
*priv
, int phy_addr
, u16 addr
, u16 reg
, u16 data
)
335 struct mii_bus
*bus
= priv
->mii_bus
;
337 mutex_lock(&bus
->mdio_lock
);
338 ar8xxx_phy_mmd_prep(bus
, phy_addr
, addr
, reg
);
339 bus
->write(bus
, phy_addr
, MII_ATH_MMD_DATA
, data
);
340 mutex_unlock(&bus
->mdio_lock
);
344 ar8xxx_phy_mmd_read(struct ar8xxx_priv
*priv
, int phy_addr
, u16 addr
, u16 reg
)
346 struct mii_bus
*bus
= priv
->mii_bus
;
349 mutex_lock(&bus
->mdio_lock
);
350 ar8xxx_phy_mmd_prep(bus
, phy_addr
, addr
, reg
);
351 data
= bus
->read(bus
, phy_addr
, MII_ATH_MMD_DATA
);
352 mutex_unlock(&bus
->mdio_lock
);
358 ar8xxx_reg_wait(struct ar8xxx_priv
*priv
, u32 reg
, u32 mask
, u32 val
,
363 for (i
= 0; i
< timeout
; i
++) {
366 t
= ar8xxx_read(priv
, reg
);
367 if ((t
& mask
) == val
)
370 usleep_range(1000, 2000);
378 ar8xxx_mib_op(struct ar8xxx_priv
*priv
, u32 op
)
380 unsigned mib_func
= priv
->chip
->mib_func
;
383 lockdep_assert_held(&priv
->mib_lock
);
385 /* Capture the hardware statistics for all ports */
386 ar8xxx_rmw(priv
, mib_func
, AR8216_MIB_FUNC
, (op
<< AR8216_MIB_FUNC_S
));
388 /* Wait for the capturing to complete. */
389 ret
= ar8xxx_reg_wait(priv
, mib_func
, AR8216_MIB_BUSY
, 0, 10);
400 ar8xxx_mib_capture(struct ar8xxx_priv
*priv
)
402 return ar8xxx_mib_op(priv
, AR8216_MIB_FUNC_CAPTURE
);
406 ar8xxx_mib_flush(struct ar8xxx_priv
*priv
)
408 return ar8xxx_mib_op(priv
, AR8216_MIB_FUNC_FLUSH
);
412 ar8xxx_mib_fetch_port_stat(struct ar8xxx_priv
*priv
, int port
, bool flush
)
418 WARN_ON(port
>= priv
->dev
.ports
);
420 lockdep_assert_held(&priv
->mib_lock
);
422 base
= priv
->chip
->reg_port_stats_start
+
423 priv
->chip
->reg_port_stats_length
* port
;
425 mib_stats
= &priv
->mib_stats
[port
* priv
->chip
->num_mibs
];
426 for (i
= 0; i
< priv
->chip
->num_mibs
; i
++) {
427 const struct ar8xxx_mib_desc
*mib
;
430 mib
= &priv
->chip
->mib_decs
[i
];
431 t
= ar8xxx_read(priv
, base
+ mib
->offset
);
432 if (mib
->size
== 2) {
435 hi
= ar8xxx_read(priv
, base
+ mib
->offset
+ 4);
448 ar8216_read_port_link(struct ar8xxx_priv
*priv
, int port
,
449 struct switch_port_link
*link
)
454 memset(link
, '\0', sizeof(*link
));
456 status
= priv
->chip
->read_port_status(priv
, port
);
458 link
->aneg
= !!(status
& AR8216_PORT_STATUS_LINK_AUTO
);
460 link
->link
= !!(status
& AR8216_PORT_STATUS_LINK_UP
);
464 if (priv
->get_port_link
) {
467 err
= priv
->get_port_link(port
);
476 link
->duplex
= !!(status
& AR8216_PORT_STATUS_DUPLEX
);
477 link
->tx_flow
= !!(status
& AR8216_PORT_STATUS_TXFLOW
);
478 link
->rx_flow
= !!(status
& AR8216_PORT_STATUS_RXFLOW
);
480 if (link
->aneg
&& link
->duplex
&& priv
->chip
->read_port_eee_status
)
481 link
->eee
= priv
->chip
->read_port_eee_status(priv
, port
);
483 speed
= (status
& AR8216_PORT_STATUS_SPEED
) >>
484 AR8216_PORT_STATUS_SPEED_S
;
487 case AR8216_PORT_SPEED_10M
:
488 link
->speed
= SWITCH_PORT_SPEED_10
;
490 case AR8216_PORT_SPEED_100M
:
491 link
->speed
= SWITCH_PORT_SPEED_100
;
493 case AR8216_PORT_SPEED_1000M
:
494 link
->speed
= SWITCH_PORT_SPEED_1000
;
497 link
->speed
= SWITCH_PORT_SPEED_UNKNOWN
;
502 static struct sk_buff
*
503 ar8216_mangle_tx(struct net_device
*dev
, struct sk_buff
*skb
)
505 struct ar8xxx_priv
*priv
= dev
->phy_ptr
;
514 if (unlikely(skb_headroom(skb
) < 2)) {
515 if (pskb_expand_head(skb
, 2, 0, GFP_ATOMIC
) < 0)
519 buf
= skb_push(skb
, 2);
527 dev_kfree_skb_any(skb
);
532 ar8216_mangle_rx(struct net_device
*dev
, struct sk_buff
*skb
)
534 struct ar8xxx_priv
*priv
;
542 /* don't strip the header if vlan mode is disabled */
546 /* strip header, get vlan id */
550 /* check for vlan header presence */
551 if ((buf
[12 + 2] != 0x81) || (buf
[13 + 2] != 0x00))
556 /* no need to fix up packets coming from a tagged source */
557 if (priv
->vlan_tagged
& (1 << port
))
560 /* lookup port vid from local table, the switch passes an invalid vlan id */
561 vlan
= priv
->vlan_id
[priv
->pvid
[port
]];
564 buf
[14 + 2] |= vlan
>> 8;
565 buf
[15 + 2] = vlan
& 0xff;
569 ar8216_wait_bit(struct ar8xxx_priv
*priv
, int reg
, u32 mask
, u32 val
)
575 t
= ar8xxx_read(priv
, reg
);
576 if ((t
& mask
) == val
)
586 pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
587 (unsigned int) reg
, t
, mask
, val
);
592 ar8216_vtu_op(struct ar8xxx_priv
*priv
, u32 op
, u32 val
)
594 if (ar8216_wait_bit(priv
, AR8216_REG_VTU
, AR8216_VTU_ACTIVE
, 0))
596 if ((op
& AR8216_VTU_OP
) == AR8216_VTU_OP_LOAD
) {
597 val
&= AR8216_VTUDATA_MEMBER
;
598 val
|= AR8216_VTUDATA_VALID
;
599 ar8xxx_write(priv
, AR8216_REG_VTU_DATA
, val
);
601 op
|= AR8216_VTU_ACTIVE
;
602 ar8xxx_write(priv
, AR8216_REG_VTU
, op
);
606 ar8216_vtu_flush(struct ar8xxx_priv
*priv
)
608 ar8216_vtu_op(priv
, AR8216_VTU_OP_FLUSH
, 0);
612 ar8216_vtu_load_vlan(struct ar8xxx_priv
*priv
, u32 vid
, u32 port_mask
)
616 op
= AR8216_VTU_OP_LOAD
| (vid
<< AR8216_VTU_VID_S
);
617 ar8216_vtu_op(priv
, op
, port_mask
);
621 ar8216_atu_flush(struct ar8xxx_priv
*priv
)
625 ret
= ar8216_wait_bit(priv
, AR8216_REG_ATU_FUNC0
, AR8216_ATU_ACTIVE
, 0);
627 ar8xxx_write(priv
, AR8216_REG_ATU_FUNC0
, AR8216_ATU_OP_FLUSH
|
634 ar8216_atu_flush_port(struct ar8xxx_priv
*priv
, int port
)
639 ret
= ar8216_wait_bit(priv
, AR8216_REG_ATU_FUNC0
, AR8216_ATU_ACTIVE
, 0);
641 t
= (port
<< AR8216_ATU_PORT_NUM_S
) | AR8216_ATU_OP_FLUSH_PORT
;
642 t
|= AR8216_ATU_ACTIVE
;
643 ar8xxx_write(priv
, AR8216_REG_ATU_FUNC0
, t
);
650 ar8216_read_port_status(struct ar8xxx_priv
*priv
, int port
)
652 return ar8xxx_read(priv
, AR8216_REG_PORT_STATUS(port
));
656 __ar8216_setup_port(struct ar8xxx_priv
*priv
, int port
, u32 members
,
664 pvid
= priv
->vlan_id
[priv
->pvid
[port
]];
665 if (priv
->vlan_tagged
& (1 << port
))
666 egress
= AR8216_OUT_ADD_VLAN
;
668 egress
= AR8216_OUT_STRIP_VLAN
;
669 ingress
= AR8216_IN_SECURE
;
672 egress
= AR8216_OUT_KEEP
;
673 ingress
= AR8216_IN_PORT_ONLY
;
676 header
= ath_hdr_en
? AR8216_PORT_CTRL_HEADER
: 0;
678 ar8xxx_rmw(priv
, AR8216_REG_PORT_CTRL(port
),
679 AR8216_PORT_CTRL_LEARN
| AR8216_PORT_CTRL_VLAN_MODE
|
680 AR8216_PORT_CTRL_SINGLE_VLAN
| AR8216_PORT_CTRL_STATE
|
681 AR8216_PORT_CTRL_HEADER
| AR8216_PORT_CTRL_LEARN_LOCK
,
682 AR8216_PORT_CTRL_LEARN
| header
|
683 (egress
<< AR8216_PORT_CTRL_VLAN_MODE_S
) |
684 (AR8216_PORT_STATE_FORWARD
<< AR8216_PORT_CTRL_STATE_S
));
686 ar8xxx_rmw(priv
, AR8216_REG_PORT_VLAN(port
),
687 AR8216_PORT_VLAN_DEST_PORTS
| AR8216_PORT_VLAN_MODE
|
688 AR8216_PORT_VLAN_DEFAULT_ID
,
689 (members
<< AR8216_PORT_VLAN_DEST_PORTS_S
) |
690 (ingress
<< AR8216_PORT_VLAN_MODE_S
) |
691 (pvid
<< AR8216_PORT_VLAN_DEFAULT_ID_S
));
695 ar8216_setup_port(struct ar8xxx_priv
*priv
, int port
, u32 members
)
697 return __ar8216_setup_port(priv
, port
, members
,
698 chip_is_ar8216(priv
) && priv
->vlan
&&
699 port
== AR8216_PORT_CPU
);
703 ar8216_hw_init(struct ar8xxx_priv
*priv
)
705 if (priv
->initialized
)
708 ar8xxx_write(priv
, AR8216_REG_CTRL
, AR8216_CTRL_RESET
);
709 ar8xxx_reg_wait(priv
, AR8216_REG_CTRL
, AR8216_CTRL_RESET
, 0, 1000);
711 ar8xxx_phy_init(priv
);
713 priv
->initialized
= true;
718 ar8216_init_globals(struct ar8xxx_priv
*priv
)
720 /* standard atheros magic */
721 ar8xxx_write(priv
, 0x38, 0xc000050e);
723 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
724 AR8216_GCTRL_MTU
, 1518 + 8 + 2);
728 __ar8216_init_port(struct ar8xxx_priv
*priv
, int port
,
729 bool cpu_ge
, bool flow_en
)
731 /* Enable port learning and tx */
732 ar8xxx_write(priv
, AR8216_REG_PORT_CTRL(port
),
733 AR8216_PORT_CTRL_LEARN
|
734 (4 << AR8216_PORT_CTRL_STATE_S
));
736 ar8xxx_write(priv
, AR8216_REG_PORT_VLAN(port
), 0);
738 if (port
== AR8216_PORT_CPU
) {
739 ar8xxx_write(priv
, AR8216_REG_PORT_STATUS(port
),
740 AR8216_PORT_STATUS_LINK_UP
|
741 (cpu_ge
? AR8216_PORT_SPEED_1000M
: AR8216_PORT_SPEED_100M
) |
742 AR8216_PORT_STATUS_TXMAC
|
743 AR8216_PORT_STATUS_RXMAC
|
744 (flow_en
? AR8216_PORT_STATUS_RXFLOW
: 0) |
745 (flow_en
? AR8216_PORT_STATUS_TXFLOW
: 0) |
746 AR8216_PORT_STATUS_DUPLEX
);
748 ar8xxx_write(priv
, AR8216_REG_PORT_STATUS(port
),
749 AR8216_PORT_STATUS_LINK_AUTO
);
754 ar8216_init_port(struct ar8xxx_priv
*priv
, int port
)
756 __ar8216_init_port(priv
, port
, ar8xxx_has_gige(priv
),
757 chip_is_ar8316(priv
));
761 ar8216_wait_atu_ready(struct ar8xxx_priv
*priv
, u16 r2
, u16 r1
)
765 while (ar8xxx_mii_read32(priv
, r2
, r1
) & AR8216_ATU_ACTIVE
&& --timeout
) {
771 pr_err("ar8216: timeout waiting for atu to become ready\n");
774 static void ar8216_get_arl_entry(struct ar8xxx_priv
*priv
,
775 struct arl_entry
*a
, u32
*status
, enum arl_op op
)
777 struct mii_bus
*bus
= priv
->mii_bus
;
779 u16 r1_func0
, r1_func1
, r1_func2
;
780 u32 t
, val0
, val1
, val2
;
782 split_addr(AR8216_REG_ATU_FUNC0
, &r1_func0
, &r2
, &page
);
785 r1_func1
= (AR8216_REG_ATU_FUNC1
>> 1) & 0x1e;
786 r1_func2
= (AR8216_REG_ATU_FUNC2
>> 1) & 0x1e;
789 case AR8XXX_ARL_INITIALIZE
:
790 /* all ATU registers are on the same page
791 * therefore set page only once
793 bus
->write(bus
, 0x18, 0, page
);
794 wait_for_page_switch();
796 ar8216_wait_atu_ready(priv
, r2
, r1_func0
);
798 ar8xxx_mii_write32(priv
, r2
, r1_func0
, AR8216_ATU_OP_GET_NEXT
);
799 ar8xxx_mii_write32(priv
, r2
, r1_func1
, 0);
800 ar8xxx_mii_write32(priv
, r2
, r1_func2
, 0);
802 case AR8XXX_ARL_GET_NEXT
:
803 t
= ar8xxx_mii_read32(priv
, r2
, r1_func0
);
804 t
|= AR8216_ATU_ACTIVE
;
805 ar8xxx_mii_write32(priv
, r2
, r1_func0
, t
);
806 ar8216_wait_atu_ready(priv
, r2
, r1_func0
);
808 val0
= ar8xxx_mii_read32(priv
, r2
, r1_func0
);
809 val1
= ar8xxx_mii_read32(priv
, r2
, r1_func1
);
810 val2
= ar8xxx_mii_read32(priv
, r2
, r1_func2
);
812 *status
= (val2
& AR8216_ATU_STATUS
) >> AR8216_ATU_STATUS_S
;
816 a
->portmap
= (val2
& AR8216_ATU_PORTS
) >> AR8216_ATU_PORTS_S
;
817 a
->mac
[0] = (val0
& AR8216_ATU_ADDR5
) >> AR8216_ATU_ADDR5_S
;
818 a
->mac
[1] = (val0
& AR8216_ATU_ADDR4
) >> AR8216_ATU_ADDR4_S
;
819 a
->mac
[2] = (val1
& AR8216_ATU_ADDR3
) >> AR8216_ATU_ADDR3_S
;
820 a
->mac
[3] = (val1
& AR8216_ATU_ADDR2
) >> AR8216_ATU_ADDR2_S
;
821 a
->mac
[4] = (val1
& AR8216_ATU_ADDR1
) >> AR8216_ATU_ADDR1_S
;
822 a
->mac
[5] = (val1
& AR8216_ATU_ADDR0
) >> AR8216_ATU_ADDR0_S
;
828 ar8216_phy_read(struct ar8xxx_priv
*priv
, int addr
, int regnum
)
833 if (addr
>= AR8216_NUM_PORTS
)
835 t
= (regnum
<< AR8216_MDIO_CTRL_REG_ADDR_S
) |
836 (addr
<< AR8216_MDIO_CTRL_PHY_ADDR_S
) |
837 AR8216_MDIO_CTRL_MASTER_EN
|
838 AR8216_MDIO_CTRL_BUSY
|
839 AR8216_MDIO_CTRL_CMD_READ
;
841 ar8xxx_write(priv
, AR8216_REG_MDIO_CTRL
, t
);
842 err
= ar8xxx_reg_wait(priv
, AR8216_REG_MDIO_CTRL
,
843 AR8216_MDIO_CTRL_BUSY
, 0, 5);
845 val
= ar8xxx_read(priv
, AR8216_REG_MDIO_CTRL
);
847 return val
& AR8216_MDIO_CTRL_DATA_M
;
851 ar8216_phy_write(struct ar8xxx_priv
*priv
, int addr
, int regnum
, u16 val
)
856 if (addr
>= AR8216_NUM_PORTS
)
859 t
= (addr
<< AR8216_MDIO_CTRL_PHY_ADDR_S
) |
860 (regnum
<< AR8216_MDIO_CTRL_REG_ADDR_S
) |
861 AR8216_MDIO_CTRL_MASTER_EN
|
862 AR8216_MDIO_CTRL_BUSY
|
863 AR8216_MDIO_CTRL_CMD_WRITE
|
866 ar8xxx_write(priv
, AR8216_REG_MDIO_CTRL
, t
);
867 ret
= ar8xxx_reg_wait(priv
, AR8216_REG_MDIO_CTRL
,
868 AR8216_MDIO_CTRL_BUSY
, 0, 5);
874 ar8229_hw_init(struct ar8xxx_priv
*priv
)
878 if (priv
->initialized
)
881 ar8xxx_write(priv
, AR8216_REG_CTRL
, AR8216_CTRL_RESET
);
882 ar8xxx_reg_wait(priv
, AR8216_REG_CTRL
, AR8216_CTRL_RESET
, 0, 1000);
884 phy_if_mode
= of_get_phy_mode(priv
->pdev
->of_node
);
886 if (phy_if_mode
== PHY_INTERFACE_MODE_GMII
) {
887 ar8xxx_write(priv
, AR8229_REG_OPER_MODE0
,
888 AR8229_OPER_MODE0_MAC_GMII_EN
);
889 } else if (phy_if_mode
== PHY_INTERFACE_MODE_MII
) {
890 ar8xxx_write(priv
, AR8229_REG_OPER_MODE0
,
891 AR8229_OPER_MODE0_PHY_MII_EN
);
893 pr_err("ar8229: unsupported mii mode\n");
897 if (priv
->port4_phy
) {
898 ar8xxx_write(priv
, AR8229_REG_OPER_MODE1
,
899 AR8229_REG_OPER_MODE1_PHY4_MII_EN
);
900 /* disable port5 to prevent mii conflict */
901 ar8xxx_write(priv
, AR8216_REG_PORT_STATUS(5), 0);
904 ar8xxx_phy_init(priv
);
906 priv
->initialized
= true;
911 ar8229_init_globals(struct ar8xxx_priv
*priv
)
914 /* Enable CPU port, and disable mirror port */
915 ar8xxx_write(priv
, AR8216_REG_GLOBAL_CPUPORT
,
916 AR8216_GLOBAL_CPUPORT_EN
|
917 (15 << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S
));
919 /* Setup TAG priority mapping */
920 ar8xxx_write(priv
, AR8216_REG_TAG_PRIORITY
, 0xfa50);
922 /* Enable aging, MAC replacing */
923 ar8xxx_write(priv
, AR8216_REG_ATU_CTRL
,
924 0x2b /* 5 min age time */ |
925 AR8216_ATU_CTRL_AGE_EN
|
926 AR8216_ATU_CTRL_LEARN_CHANGE
);
928 /* Enable ARP frame acknowledge */
929 ar8xxx_reg_set(priv
, AR8229_REG_QM_CTRL
,
930 AR8229_QM_CTRL_ARP_EN
);
932 /* Enable Broadcast/Multicast frames transmitted to the CPU */
933 ar8xxx_reg_set(priv
, AR8216_REG_FLOOD_MASK
,
934 AR8229_FLOOD_MASK_BC_DP(0) |
935 AR8229_FLOOD_MASK_MC_DP(0));
938 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
939 AR8236_GCTRL_MTU
, AR8236_GCTRL_MTU
);
941 /* Enable MIB counters */
942 ar8xxx_reg_set(priv
, AR8216_REG_MIB_FUNC
,
945 /* setup Service TAG */
946 ar8xxx_rmw(priv
, AR8216_REG_SERVICE_TAG
, AR8216_SERVICE_TAG_M
, 0);
950 ar8229_init_port(struct ar8xxx_priv
*priv
, int port
)
952 __ar8216_init_port(priv
, port
, true, true);
957 ar7240sw_hw_init(struct ar8xxx_priv
*priv
)
959 if (priv
->initialized
)
962 ar8xxx_write(priv
, AR8216_REG_CTRL
, AR8216_CTRL_RESET
);
963 ar8xxx_reg_wait(priv
, AR8216_REG_CTRL
, AR8216_CTRL_RESET
, 0, 1000);
966 /* disable port5 to prevent mii conflict */
967 ar8xxx_write(priv
, AR8216_REG_PORT_STATUS(5), 0);
969 ar8xxx_phy_init(priv
);
971 priv
->initialized
= true;
976 ar7240sw_init_globals(struct ar8xxx_priv
*priv
)
979 /* Enable CPU port, and disable mirror port */
980 ar8xxx_write(priv
, AR8216_REG_GLOBAL_CPUPORT
,
981 AR8216_GLOBAL_CPUPORT_EN
|
982 (15 << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S
));
984 /* Setup TAG priority mapping */
985 ar8xxx_write(priv
, AR8216_REG_TAG_PRIORITY
, 0xfa50);
987 /* Enable ARP frame acknowledge, aging, MAC replacing */
988 ar8xxx_write(priv
, AR8216_REG_ATU_CTRL
,
989 AR8216_ATU_CTRL_RESERVED
|
990 0x2b /* 5 min age time */ |
991 AR8216_ATU_CTRL_AGE_EN
|
992 AR8216_ATU_CTRL_ARP_EN
|
993 AR8216_ATU_CTRL_LEARN_CHANGE
);
995 /* Enable Broadcast frames transmitted to the CPU */
996 ar8xxx_reg_set(priv
, AR8216_REG_FLOOD_MASK
,
997 AR8236_FM_CPU_BROADCAST_EN
);
1000 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
1004 /* setup Service TAG */
1005 ar8xxx_rmw(priv
, AR8216_REG_SERVICE_TAG
, AR8216_SERVICE_TAG_M
, 0);
1009 ar7240sw_setup_port(struct ar8xxx_priv
*priv
, int port
, u32 members
)
1011 return __ar8216_setup_port(priv
, port
, members
, false);
1015 ar8236_setup_port(struct ar8xxx_priv
*priv
, int port
, u32 members
)
1017 u32 egress
, ingress
;
1021 pvid
= priv
->vlan_id
[priv
->pvid
[port
]];
1022 if (priv
->vlan_tagged
& (1 << port
))
1023 egress
= AR8216_OUT_ADD_VLAN
;
1025 egress
= AR8216_OUT_STRIP_VLAN
;
1026 ingress
= AR8216_IN_SECURE
;
1029 egress
= AR8216_OUT_KEEP
;
1030 ingress
= AR8216_IN_PORT_ONLY
;
1033 ar8xxx_rmw(priv
, AR8216_REG_PORT_CTRL(port
),
1034 AR8216_PORT_CTRL_LEARN
| AR8216_PORT_CTRL_VLAN_MODE
|
1035 AR8216_PORT_CTRL_SINGLE_VLAN
| AR8216_PORT_CTRL_STATE
|
1036 AR8216_PORT_CTRL_HEADER
| AR8216_PORT_CTRL_LEARN_LOCK
,
1037 AR8216_PORT_CTRL_LEARN
|
1038 (egress
<< AR8216_PORT_CTRL_VLAN_MODE_S
) |
1039 (AR8216_PORT_STATE_FORWARD
<< AR8216_PORT_CTRL_STATE_S
));
1041 ar8xxx_rmw(priv
, AR8236_REG_PORT_VLAN(port
),
1042 AR8236_PORT_VLAN_DEFAULT_ID
,
1043 (pvid
<< AR8236_PORT_VLAN_DEFAULT_ID_S
));
1045 ar8xxx_rmw(priv
, AR8236_REG_PORT_VLAN2(port
),
1046 AR8236_PORT_VLAN2_VLAN_MODE
|
1047 AR8236_PORT_VLAN2_MEMBER
,
1048 (ingress
<< AR8236_PORT_VLAN2_VLAN_MODE_S
) |
1049 (members
<< AR8236_PORT_VLAN2_MEMBER_S
));
1053 ar8236_init_globals(struct ar8xxx_priv
*priv
)
1055 /* enable jumbo frames */
1056 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
1057 AR8316_GCTRL_MTU
, 9018 + 8 + 2);
1059 /* enable cpu port to receive arp frames */
1060 ar8xxx_reg_set(priv
, AR8216_REG_ATU_CTRL
,
1061 AR8236_ATU_CTRL_RES
);
1063 /* enable cpu port to receive multicast and broadcast frames */
1064 ar8xxx_reg_set(priv
, AR8216_REG_FLOOD_MASK
,
1065 AR8236_FM_CPU_BROADCAST_EN
| AR8236_FM_CPU_BCAST_FWD_EN
);
1067 /* Enable MIB counters */
1068 ar8xxx_rmw(priv
, AR8216_REG_MIB_FUNC
, AR8216_MIB_FUNC
| AR8236_MIB_EN
,
1069 (AR8216_MIB_FUNC_NO_OP
<< AR8216_MIB_FUNC_S
) |
1074 ar8316_hw_init(struct ar8xxx_priv
*priv
)
1078 val
= ar8xxx_read(priv
, AR8316_REG_POSTRIP
);
1080 if (priv
->phy
->interface
== PHY_INTERFACE_MODE_RGMII
) {
1081 if (priv
->port4_phy
) {
1082 /* value taken from Ubiquiti RouterStation Pro */
1083 newval
= 0x81461bea;
1084 pr_info("ar8316: Using port 4 as PHY\n");
1086 newval
= 0x01261be2;
1087 pr_info("ar8316: Using port 4 as switch port\n");
1089 } else if (priv
->phy
->interface
== PHY_INTERFACE_MODE_GMII
) {
1090 /* value taken from AVM Fritz!Box 7390 sources */
1091 newval
= 0x010e5b71;
1093 /* no known value for phy interface */
1094 pr_err("ar8316: unsupported mii mode: %d.\n",
1095 priv
->phy
->interface
);
1102 ar8xxx_write(priv
, AR8316_REG_POSTRIP
, newval
);
1104 if (priv
->port4_phy
&&
1105 priv
->phy
->interface
== PHY_INTERFACE_MODE_RGMII
) {
1106 /* work around for phy4 rgmii mode */
1107 ar8xxx_phy_dbg_write(priv
, 4, 0x12, 0x480c);
1109 ar8xxx_phy_dbg_write(priv
, 4, 0x0, 0x824e);
1111 ar8xxx_phy_dbg_write(priv
, 4, 0x5, 0x3d47);
1115 ar8xxx_phy_init(priv
);
1118 priv
->initialized
= true;
1123 ar8316_init_globals(struct ar8xxx_priv
*priv
)
1125 /* standard atheros magic */
1126 ar8xxx_write(priv
, 0x38, 0xc000050e);
1128 /* enable cpu port to receive multicast and broadcast frames */
1129 ar8xxx_write(priv
, AR8216_REG_FLOOD_MASK
, 0x003f003f);
1131 /* enable jumbo frames */
1132 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
1133 AR8316_GCTRL_MTU
, 9018 + 8 + 2);
1135 /* Enable MIB counters */
1136 ar8xxx_rmw(priv
, AR8216_REG_MIB_FUNC
, AR8216_MIB_FUNC
| AR8236_MIB_EN
,
1137 (AR8216_MIB_FUNC_NO_OP
<< AR8216_MIB_FUNC_S
) |
1142 ar8xxx_sw_set_vlan(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1143 struct switch_val
*val
)
1145 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1146 priv
->vlan
= !!val
->value
.i
;
1151 ar8xxx_sw_get_vlan(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1152 struct switch_val
*val
)
1154 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1155 val
->value
.i
= priv
->vlan
;
1161 ar8xxx_sw_set_pvid(struct switch_dev
*dev
, int port
, int vlan
)
1163 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1165 /* make sure no invalid PVIDs get set */
1167 if (vlan
< 0 || vlan
>= dev
->vlans
||
1168 port
< 0 || port
>= AR8X16_MAX_PORTS
)
1171 priv
->pvid
[port
] = vlan
;
1176 ar8xxx_sw_get_pvid(struct switch_dev
*dev
, int port
, int *vlan
)
1178 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1180 if (port
< 0 || port
>= AR8X16_MAX_PORTS
)
1183 *vlan
= priv
->pvid
[port
];
1188 ar8xxx_sw_set_vid(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1189 struct switch_val
*val
)
1191 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1193 if (val
->port_vlan
>= AR8X16_MAX_VLANS
)
1196 priv
->vlan_id
[val
->port_vlan
] = val
->value
.i
;
1201 ar8xxx_sw_get_vid(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1202 struct switch_val
*val
)
1204 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1205 val
->value
.i
= priv
->vlan_id
[val
->port_vlan
];
1210 ar8xxx_sw_get_port_link(struct switch_dev
*dev
, int port
,
1211 struct switch_port_link
*link
)
1213 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1215 ar8216_read_port_link(priv
, port
, link
);
1220 ar8xxx_sw_get_ports(struct switch_dev
*dev
, struct switch_val
*val
)
1222 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1226 if (val
->port_vlan
>= AR8X16_MAX_VLANS
)
1229 ports
= priv
->vlan_table
[val
->port_vlan
];
1231 for (i
= 0; i
< dev
->ports
; i
++) {
1232 struct switch_port
*p
;
1234 if (!(ports
& (1 << i
)))
1237 p
= &val
->value
.ports
[val
->len
++];
1239 if (priv
->vlan_tagged
& (1 << i
))
1240 p
->flags
= (1 << SWITCH_PORT_FLAG_TAGGED
);
1248 ar8xxx_sw_set_ports(struct switch_dev
*dev
, struct switch_val
*val
)
1250 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1251 u8
*vt
= &priv
->vlan_table
[val
->port_vlan
];
1255 for (i
= 0; i
< val
->len
; i
++) {
1256 struct switch_port
*p
= &val
->value
.ports
[i
];
1258 if (p
->flags
& (1 << SWITCH_PORT_FLAG_TAGGED
)) {
1259 priv
->vlan_tagged
|= (1 << p
->id
);
1261 priv
->vlan_tagged
&= ~(1 << p
->id
);
1262 priv
->pvid
[p
->id
] = val
->port_vlan
;
1264 /* make sure that an untagged port does not
1265 * appear in other vlans */
1266 for (j
= 0; j
< AR8X16_MAX_VLANS
; j
++) {
1267 if (j
== val
->port_vlan
)
1269 priv
->vlan_table
[j
] &= ~(1 << p
->id
);
1279 ar8216_set_mirror_regs(struct ar8xxx_priv
*priv
)
1283 /* reset all mirror registers */
1284 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CPUPORT
,
1285 AR8216_GLOBAL_CPUPORT_MIRROR_PORT
,
1286 (0xF << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S
));
1287 for (port
= 0; port
< AR8216_NUM_PORTS
; port
++) {
1288 ar8xxx_reg_clear(priv
, AR8216_REG_PORT_CTRL(port
),
1289 AR8216_PORT_CTRL_MIRROR_RX
);
1291 ar8xxx_reg_clear(priv
, AR8216_REG_PORT_CTRL(port
),
1292 AR8216_PORT_CTRL_MIRROR_TX
);
1295 /* now enable mirroring if necessary */
1296 if (priv
->source_port
>= AR8216_NUM_PORTS
||
1297 priv
->monitor_port
>= AR8216_NUM_PORTS
||
1298 priv
->source_port
== priv
->monitor_port
) {
1302 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CPUPORT
,
1303 AR8216_GLOBAL_CPUPORT_MIRROR_PORT
,
1304 (priv
->monitor_port
<< AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S
));
1306 if (priv
->mirror_rx
)
1307 ar8xxx_reg_set(priv
, AR8216_REG_PORT_CTRL(priv
->source_port
),
1308 AR8216_PORT_CTRL_MIRROR_RX
);
1310 if (priv
->mirror_tx
)
1311 ar8xxx_reg_set(priv
, AR8216_REG_PORT_CTRL(priv
->source_port
),
1312 AR8216_PORT_CTRL_MIRROR_TX
);
1316 ar8xxx_age_time_val(int age_time
)
1318 return (age_time
+ AR8XXX_REG_ARL_CTRL_AGE_TIME_SECS
/ 2) /
1319 AR8XXX_REG_ARL_CTRL_AGE_TIME_SECS
;
1323 ar8xxx_set_age_time(struct ar8xxx_priv
*priv
, int reg
)
1325 u32 age_time
= ar8xxx_age_time_val(priv
->arl_age_time
);
1326 ar8xxx_rmw(priv
, reg
, AR8216_ATU_CTRL_AGE_TIME
, age_time
<< AR8216_ATU_CTRL_AGE_TIME_S
);
1330 ar8xxx_sw_hw_apply(struct switch_dev
*dev
)
1332 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1333 const struct ar8xxx_chip
*chip
= priv
->chip
;
1334 u8 portmask
[AR8X16_MAX_PORTS
];
1337 mutex_lock(&priv
->reg_mutex
);
1338 /* flush all vlan translation unit entries */
1339 priv
->chip
->vtu_flush(priv
);
1341 memset(portmask
, 0, sizeof(portmask
));
1343 /* calculate the port destination masks and load vlans
1344 * into the vlan translation unit */
1345 for (j
= 0; j
< AR8X16_MAX_VLANS
; j
++) {
1346 u8 vp
= priv
->vlan_table
[j
];
1351 for (i
= 0; i
< dev
->ports
; i
++) {
1354 portmask
[i
] |= vp
& ~mask
;
1357 chip
->vtu_load_vlan(priv
, priv
->vlan_id
[j
],
1358 priv
->vlan_table
[j
]);
1362 * isolate all ports, but connect them to the cpu port */
1363 for (i
= 0; i
< dev
->ports
; i
++) {
1364 if (i
== AR8216_PORT_CPU
)
1367 portmask
[i
] = 1 << AR8216_PORT_CPU
;
1368 portmask
[AR8216_PORT_CPU
] |= (1 << i
);
1372 /* update the port destination mask registers and tag settings */
1373 for (i
= 0; i
< dev
->ports
; i
++) {
1374 chip
->setup_port(priv
, i
, portmask
[i
]);
1377 chip
->set_mirror_regs(priv
);
1380 if (chip
->reg_arl_ctrl
)
1381 ar8xxx_set_age_time(priv
, chip
->reg_arl_ctrl
);
1383 mutex_unlock(&priv
->reg_mutex
);
1388 ar8xxx_sw_reset_switch(struct switch_dev
*dev
)
1390 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1391 const struct ar8xxx_chip
*chip
= priv
->chip
;
1394 mutex_lock(&priv
->reg_mutex
);
1395 memset(&priv
->vlan
, 0, sizeof(struct ar8xxx_priv
) -
1396 offsetof(struct ar8xxx_priv
, vlan
));
1398 for (i
= 0; i
< AR8X16_MAX_VLANS
; i
++)
1399 priv
->vlan_id
[i
] = i
;
1401 /* Configure all ports */
1402 for (i
= 0; i
< dev
->ports
; i
++)
1403 chip
->init_port(priv
, i
);
1405 priv
->mirror_rx
= false;
1406 priv
->mirror_tx
= false;
1407 priv
->source_port
= 0;
1408 priv
->monitor_port
= 0;
1409 priv
->arl_age_time
= AR8XXX_DEFAULT_ARL_AGE_TIME
;
1411 chip
->init_globals(priv
);
1412 chip
->atu_flush(priv
);
1414 mutex_unlock(&priv
->reg_mutex
);
1416 return chip
->sw_hw_apply(dev
);
1420 ar8xxx_sw_set_reset_mibs(struct switch_dev
*dev
,
1421 const struct switch_attr
*attr
,
1422 struct switch_val
*val
)
1424 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1428 if (!ar8xxx_has_mib_counters(priv
))
1431 mutex_lock(&priv
->mib_lock
);
1433 len
= priv
->dev
.ports
* priv
->chip
->num_mibs
*
1434 sizeof(*priv
->mib_stats
);
1435 memset(priv
->mib_stats
, '\0', len
);
1436 ret
= ar8xxx_mib_flush(priv
);
1443 mutex_unlock(&priv
->mib_lock
);
1448 ar8xxx_sw_set_mirror_rx_enable(struct switch_dev
*dev
,
1449 const struct switch_attr
*attr
,
1450 struct switch_val
*val
)
1452 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1454 mutex_lock(&priv
->reg_mutex
);
1455 priv
->mirror_rx
= !!val
->value
.i
;
1456 priv
->chip
->set_mirror_regs(priv
);
1457 mutex_unlock(&priv
->reg_mutex
);
1463 ar8xxx_sw_get_mirror_rx_enable(struct switch_dev
*dev
,
1464 const struct switch_attr
*attr
,
1465 struct switch_val
*val
)
1467 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1468 val
->value
.i
= priv
->mirror_rx
;
1473 ar8xxx_sw_set_mirror_tx_enable(struct switch_dev
*dev
,
1474 const struct switch_attr
*attr
,
1475 struct switch_val
*val
)
1477 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1479 mutex_lock(&priv
->reg_mutex
);
1480 priv
->mirror_tx
= !!val
->value
.i
;
1481 priv
->chip
->set_mirror_regs(priv
);
1482 mutex_unlock(&priv
->reg_mutex
);
1488 ar8xxx_sw_get_mirror_tx_enable(struct switch_dev
*dev
,
1489 const struct switch_attr
*attr
,
1490 struct switch_val
*val
)
1492 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1493 val
->value
.i
= priv
->mirror_tx
;
1498 ar8xxx_sw_set_mirror_monitor_port(struct switch_dev
*dev
,
1499 const struct switch_attr
*attr
,
1500 struct switch_val
*val
)
1502 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1504 mutex_lock(&priv
->reg_mutex
);
1505 priv
->monitor_port
= val
->value
.i
;
1506 priv
->chip
->set_mirror_regs(priv
);
1507 mutex_unlock(&priv
->reg_mutex
);
1513 ar8xxx_sw_get_mirror_monitor_port(struct switch_dev
*dev
,
1514 const struct switch_attr
*attr
,
1515 struct switch_val
*val
)
1517 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1518 val
->value
.i
= priv
->monitor_port
;
1523 ar8xxx_sw_set_mirror_source_port(struct switch_dev
*dev
,
1524 const struct switch_attr
*attr
,
1525 struct switch_val
*val
)
1527 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1529 mutex_lock(&priv
->reg_mutex
);
1530 priv
->source_port
= val
->value
.i
;
1531 priv
->chip
->set_mirror_regs(priv
);
1532 mutex_unlock(&priv
->reg_mutex
);
1538 ar8xxx_sw_get_mirror_source_port(struct switch_dev
*dev
,
1539 const struct switch_attr
*attr
,
1540 struct switch_val
*val
)
1542 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1543 val
->value
.i
= priv
->source_port
;
1548 ar8xxx_sw_set_port_reset_mib(struct switch_dev
*dev
,
1549 const struct switch_attr
*attr
,
1550 struct switch_val
*val
)
1552 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1556 if (!ar8xxx_has_mib_counters(priv
))
1559 port
= val
->port_vlan
;
1560 if (port
>= dev
->ports
)
1563 mutex_lock(&priv
->mib_lock
);
1564 ret
= ar8xxx_mib_capture(priv
);
1568 ar8xxx_mib_fetch_port_stat(priv
, port
, true);
1573 mutex_unlock(&priv
->mib_lock
);
1578 ar8xxx_byte_to_str(char *buf
, int len
, u64 byte
)
1583 if (byte
>= 0x40000000) { /* 1 GiB */
1584 b
= byte
* 10 / 0x40000000;
1586 } else if (byte
>= 0x100000) { /* 1 MiB */
1587 b
= byte
* 10 / 0x100000;
1589 } else if (byte
>= 0x400) { /* 1 KiB */
1590 b
= byte
* 10 / 0x400;
1596 if (strcmp(unit
, "Byte"))
1597 snprintf(buf
, len
, "%lu.%lu %s", b
/ 10, b
% 10, unit
);
1599 snprintf(buf
, len
, "%lu %s", b
, unit
);
1603 ar8xxx_sw_get_port_mib(struct switch_dev
*dev
,
1604 const struct switch_attr
*attr
,
1605 struct switch_val
*val
)
1607 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1608 const struct ar8xxx_chip
*chip
= priv
->chip
;
1609 u64
*mib_stats
, mib_data
;
1612 char *buf
= priv
->buf
;
1614 const char *mib_name
;
1616 bool mib_stats_empty
= true;
1618 if (!ar8xxx_has_mib_counters(priv
))
1621 port
= val
->port_vlan
;
1622 if (port
>= dev
->ports
)
1625 mutex_lock(&priv
->mib_lock
);
1626 ret
= ar8xxx_mib_capture(priv
);
1630 ar8xxx_mib_fetch_port_stat(priv
, port
, false);
1632 len
+= snprintf(buf
+ len
, sizeof(priv
->buf
) - len
,
1635 mib_stats
= &priv
->mib_stats
[port
* chip
->num_mibs
];
1636 for (i
= 0; i
< chip
->num_mibs
; i
++) {
1637 mib_name
= chip
->mib_decs
[i
].name
;
1638 mib_data
= mib_stats
[i
];
1639 len
+= snprintf(buf
+ len
, sizeof(priv
->buf
) - len
,
1640 "%-12s: %llu\n", mib_name
, mib_data
);
1641 if ((!strcmp(mib_name
, "TxByte") ||
1642 !strcmp(mib_name
, "RxGoodByte")) &&
1644 ar8xxx_byte_to_str(buf1
, sizeof(buf1
), mib_data
);
1645 --len
; /* discard newline at the end of buf */
1646 len
+= snprintf(buf
+ len
, sizeof(priv
->buf
) - len
,
1649 if (mib_stats_empty
&& mib_data
)
1650 mib_stats_empty
= false;
1653 if (mib_stats_empty
)
1654 len
= snprintf(buf
, sizeof(priv
->buf
), "No MIB data");
1662 mutex_unlock(&priv
->mib_lock
);
1667 ar8xxx_sw_set_arl_age_time(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1668 struct switch_val
*val
)
1670 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1671 int age_time
= val
->value
.i
;
1677 age_time_val
= ar8xxx_age_time_val(age_time
);
1678 if (age_time_val
== 0 || age_time_val
> 0xffff)
1681 priv
->arl_age_time
= age_time
;
1686 ar8xxx_sw_get_arl_age_time(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1687 struct switch_val
*val
)
1689 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1690 val
->value
.i
= priv
->arl_age_time
;
1695 ar8xxx_sw_get_arl_table(struct switch_dev
*dev
,
1696 const struct switch_attr
*attr
,
1697 struct switch_val
*val
)
1699 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1700 struct mii_bus
*bus
= priv
->mii_bus
;
1701 const struct ar8xxx_chip
*chip
= priv
->chip
;
1702 char *buf
= priv
->arl_buf
;
1703 int i
, j
, k
, len
= 0;
1704 struct arl_entry
*a
, *a1
;
1707 if (!chip
->get_arl_entry
)
1710 mutex_lock(&priv
->reg_mutex
);
1711 mutex_lock(&bus
->mdio_lock
);
1713 chip
->get_arl_entry(priv
, NULL
, NULL
, AR8XXX_ARL_INITIALIZE
);
1715 for(i
= 0; i
< AR8XXX_NUM_ARL_RECORDS
; ++i
) {
1716 a
= &priv
->arl_table
[i
];
1718 chip
->get_arl_entry(priv
, a
, &status
, AR8XXX_ARL_GET_NEXT
);
1724 * ARL table can include multiple valid entries
1725 * per MAC, just with differing status codes
1727 for (j
= 0; j
< i
; ++j
) {
1728 a1
= &priv
->arl_table
[j
];
1729 if (!memcmp(a
->mac
, a1
->mac
, sizeof(a
->mac
))) {
1730 /* ignore ports already seen in former entry */
1731 a
->portmap
&= ~a1
->portmap
;
1738 mutex_unlock(&bus
->mdio_lock
);
1740 len
+= snprintf(buf
+ len
, sizeof(priv
->arl_buf
) - len
,
1741 "address resolution table\n");
1743 if (i
== AR8XXX_NUM_ARL_RECORDS
)
1744 len
+= snprintf(buf
+ len
, sizeof(priv
->arl_buf
) - len
,
1745 "Too many entries found, displaying the first %d only!\n",
1746 AR8XXX_NUM_ARL_RECORDS
);
1748 for (j
= 0; j
< priv
->dev
.ports
; ++j
) {
1749 for (k
= 0; k
< i
; ++k
) {
1750 a
= &priv
->arl_table
[k
];
1751 if (!(a
->portmap
& BIT(j
)))
1753 len
+= snprintf(buf
+ len
, sizeof(priv
->arl_buf
) - len
,
1754 "Port %d: MAC %02x:%02x:%02x:%02x:%02x:%02x\n",
1756 a
->mac
[5], a
->mac
[4], a
->mac
[3],
1757 a
->mac
[2], a
->mac
[1], a
->mac
[0]);
1764 mutex_unlock(&priv
->reg_mutex
);
1770 ar8xxx_sw_set_flush_arl_table(struct switch_dev
*dev
,
1771 const struct switch_attr
*attr
,
1772 struct switch_val
*val
)
1774 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1777 mutex_lock(&priv
->reg_mutex
);
1778 ret
= priv
->chip
->atu_flush(priv
);
1779 mutex_unlock(&priv
->reg_mutex
);
1785 ar8xxx_sw_set_flush_port_arl_table(struct switch_dev
*dev
,
1786 const struct switch_attr
*attr
,
1787 struct switch_val
*val
)
1789 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1792 port
= val
->port_vlan
;
1793 if (port
>= dev
->ports
)
1796 mutex_lock(&priv
->reg_mutex
);
1797 ret
= priv
->chip
->atu_flush_port(priv
, port
);
1798 mutex_unlock(&priv
->reg_mutex
);
1804 ar8xxx_sw_get_port_stats(struct switch_dev
*dev
, int port
,
1805 struct switch_port_stats
*stats
)
1807 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1810 if (!ar8xxx_has_mib_counters(priv
))
1813 if (!(priv
->chip
->mib_rxb_id
|| priv
->chip
->mib_txb_id
))
1816 if (port
>= dev
->ports
)
1819 mutex_lock(&priv
->mib_lock
);
1821 mib_stats
= &priv
->mib_stats
[port
* priv
->chip
->num_mibs
];
1823 stats
->tx_bytes
= mib_stats
[priv
->chip
->mib_txb_id
];
1824 stats
->rx_bytes
= mib_stats
[priv
->chip
->mib_rxb_id
];
1826 mutex_unlock(&priv
->mib_lock
);
1831 ar8xxx_phy_read(struct mii_bus
*bus
, int phy_addr
, int reg_addr
)
1833 struct ar8xxx_priv
*priv
= bus
->priv
;
1834 return priv
->chip
->phy_read(priv
, phy_addr
, reg_addr
);
1838 ar8xxx_phy_write(struct mii_bus
*bus
, int phy_addr
, int reg_addr
,
1841 struct ar8xxx_priv
*priv
= bus
->priv
;
1842 return priv
->chip
->phy_write(priv
, phy_addr
, reg_addr
, reg_val
);
1845 static const struct switch_attr ar8xxx_sw_attr_globals
[] = {
1847 .type
= SWITCH_TYPE_INT
,
1848 .name
= "enable_vlan",
1849 .description
= "Enable VLAN mode",
1850 .set
= ar8xxx_sw_set_vlan
,
1851 .get
= ar8xxx_sw_get_vlan
,
1855 .type
= SWITCH_TYPE_NOVAL
,
1856 .name
= "reset_mibs",
1857 .description
= "Reset all MIB counters",
1858 .set
= ar8xxx_sw_set_reset_mibs
,
1861 .type
= SWITCH_TYPE_INT
,
1862 .name
= "enable_mirror_rx",
1863 .description
= "Enable mirroring of RX packets",
1864 .set
= ar8xxx_sw_set_mirror_rx_enable
,
1865 .get
= ar8xxx_sw_get_mirror_rx_enable
,
1869 .type
= SWITCH_TYPE_INT
,
1870 .name
= "enable_mirror_tx",
1871 .description
= "Enable mirroring of TX packets",
1872 .set
= ar8xxx_sw_set_mirror_tx_enable
,
1873 .get
= ar8xxx_sw_get_mirror_tx_enable
,
1877 .type
= SWITCH_TYPE_INT
,
1878 .name
= "mirror_monitor_port",
1879 .description
= "Mirror monitor port",
1880 .set
= ar8xxx_sw_set_mirror_monitor_port
,
1881 .get
= ar8xxx_sw_get_mirror_monitor_port
,
1882 .max
= AR8216_NUM_PORTS
- 1
1885 .type
= SWITCH_TYPE_INT
,
1886 .name
= "mirror_source_port",
1887 .description
= "Mirror source port",
1888 .set
= ar8xxx_sw_set_mirror_source_port
,
1889 .get
= ar8xxx_sw_get_mirror_source_port
,
1890 .max
= AR8216_NUM_PORTS
- 1
1893 .type
= SWITCH_TYPE_STRING
,
1894 .name
= "arl_table",
1895 .description
= "Get ARL table",
1897 .get
= ar8xxx_sw_get_arl_table
,
1900 .type
= SWITCH_TYPE_NOVAL
,
1901 .name
= "flush_arl_table",
1902 .description
= "Flush ARL table",
1903 .set
= ar8xxx_sw_set_flush_arl_table
,
1907 const struct switch_attr ar8xxx_sw_attr_port
[] = {
1909 .type
= SWITCH_TYPE_NOVAL
,
1910 .name
= "reset_mib",
1911 .description
= "Reset single port MIB counters",
1912 .set
= ar8xxx_sw_set_port_reset_mib
,
1915 .type
= SWITCH_TYPE_STRING
,
1917 .description
= "Get port's MIB counters",
1919 .get
= ar8xxx_sw_get_port_mib
,
1922 .type
= SWITCH_TYPE_NOVAL
,
1923 .name
= "flush_arl_table",
1924 .description
= "Flush port's ARL table entries",
1925 .set
= ar8xxx_sw_set_flush_port_arl_table
,
1929 const struct switch_attr ar8xxx_sw_attr_vlan
[1] = {
1931 .type
= SWITCH_TYPE_INT
,
1933 .description
= "VLAN ID (0-4094)",
1934 .set
= ar8xxx_sw_set_vid
,
1935 .get
= ar8xxx_sw_get_vid
,
1940 static const struct switch_dev_ops ar8xxx_sw_ops
= {
1942 .attr
= ar8xxx_sw_attr_globals
,
1943 .n_attr
= ARRAY_SIZE(ar8xxx_sw_attr_globals
),
1946 .attr
= ar8xxx_sw_attr_port
,
1947 .n_attr
= ARRAY_SIZE(ar8xxx_sw_attr_port
),
1950 .attr
= ar8xxx_sw_attr_vlan
,
1951 .n_attr
= ARRAY_SIZE(ar8xxx_sw_attr_vlan
),
1953 .get_port_pvid
= ar8xxx_sw_get_pvid
,
1954 .set_port_pvid
= ar8xxx_sw_set_pvid
,
1955 .get_vlan_ports
= ar8xxx_sw_get_ports
,
1956 .set_vlan_ports
= ar8xxx_sw_set_ports
,
1957 .apply_config
= ar8xxx_sw_hw_apply
,
1958 .reset_switch
= ar8xxx_sw_reset_switch
,
1959 .get_port_link
= ar8xxx_sw_get_port_link
,
1960 .get_port_stats
= ar8xxx_sw_get_port_stats
,
1963 static const struct ar8xxx_chip ar7240sw_chip
= {
1964 .caps
= AR8XXX_CAP_MIB_COUNTERS
,
1966 .reg_port_stats_start
= 0x20000,
1967 .reg_port_stats_length
= 0x100,
1968 .reg_arl_ctrl
= AR8216_REG_ATU_CTRL
,
1970 .name
= "Atheros AR724X/AR933X built-in",
1971 .ports
= AR7240SW_NUM_PORTS
,
1972 .vlans
= AR8216_NUM_VLANS
,
1973 .swops
= &ar8xxx_sw_ops
,
1975 .hw_init
= ar7240sw_hw_init
,
1976 .init_globals
= ar7240sw_init_globals
,
1977 .init_port
= ar8229_init_port
,
1978 .phy_read
= ar8216_phy_read
,
1979 .phy_write
= ar8216_phy_write
,
1980 .setup_port
= ar7240sw_setup_port
,
1981 .read_port_status
= ar8216_read_port_status
,
1982 .atu_flush
= ar8216_atu_flush
,
1983 .atu_flush_port
= ar8216_atu_flush_port
,
1984 .vtu_flush
= ar8216_vtu_flush
,
1985 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
1986 .set_mirror_regs
= ar8216_set_mirror_regs
,
1987 .get_arl_entry
= ar8216_get_arl_entry
,
1988 .sw_hw_apply
= ar8xxx_sw_hw_apply
,
1990 .num_mibs
= ARRAY_SIZE(ar8236_mibs
),
1991 .mib_decs
= ar8236_mibs
,
1992 .mib_func
= AR8216_REG_MIB_FUNC
,
1993 .mib_rxb_id
= AR8236_MIB_RXB_ID
,
1994 .mib_txb_id
= AR8236_MIB_TXB_ID
,
1997 static const struct ar8xxx_chip ar8216_chip
= {
1998 .caps
= AR8XXX_CAP_MIB_COUNTERS
,
2000 .reg_port_stats_start
= 0x19000,
2001 .reg_port_stats_length
= 0xa0,
2002 .reg_arl_ctrl
= AR8216_REG_ATU_CTRL
,
2004 .name
= "Atheros AR8216",
2005 .ports
= AR8216_NUM_PORTS
,
2006 .vlans
= AR8216_NUM_VLANS
,
2007 .swops
= &ar8xxx_sw_ops
,
2009 .hw_init
= ar8216_hw_init
,
2010 .init_globals
= ar8216_init_globals
,
2011 .init_port
= ar8216_init_port
,
2012 .setup_port
= ar8216_setup_port
,
2013 .read_port_status
= ar8216_read_port_status
,
2014 .atu_flush
= ar8216_atu_flush
,
2015 .atu_flush_port
= ar8216_atu_flush_port
,
2016 .vtu_flush
= ar8216_vtu_flush
,
2017 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
2018 .set_mirror_regs
= ar8216_set_mirror_regs
,
2019 .get_arl_entry
= ar8216_get_arl_entry
,
2020 .sw_hw_apply
= ar8xxx_sw_hw_apply
,
2022 .num_mibs
= ARRAY_SIZE(ar8216_mibs
),
2023 .mib_decs
= ar8216_mibs
,
2024 .mib_func
= AR8216_REG_MIB_FUNC
,
2025 .mib_rxb_id
= AR8216_MIB_RXB_ID
,
2026 .mib_txb_id
= AR8216_MIB_TXB_ID
,
2029 static const struct ar8xxx_chip ar8229_chip
= {
2030 .caps
= AR8XXX_CAP_MIB_COUNTERS
,
2032 .reg_port_stats_start
= 0x20000,
2033 .reg_port_stats_length
= 0x100,
2034 .reg_arl_ctrl
= AR8216_REG_ATU_CTRL
,
2036 .name
= "Atheros AR8229",
2037 .ports
= AR8216_NUM_PORTS
,
2038 .vlans
= AR8216_NUM_VLANS
,
2039 .swops
= &ar8xxx_sw_ops
,
2041 .hw_init
= ar8229_hw_init
,
2042 .init_globals
= ar8229_init_globals
,
2043 .init_port
= ar8229_init_port
,
2044 .phy_read
= ar8216_phy_read
,
2045 .phy_write
= ar8216_phy_write
,
2046 .setup_port
= ar8236_setup_port
,
2047 .read_port_status
= ar8216_read_port_status
,
2048 .atu_flush
= ar8216_atu_flush
,
2049 .atu_flush_port
= ar8216_atu_flush_port
,
2050 .vtu_flush
= ar8216_vtu_flush
,
2051 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
2052 .set_mirror_regs
= ar8216_set_mirror_regs
,
2053 .get_arl_entry
= ar8216_get_arl_entry
,
2054 .sw_hw_apply
= ar8xxx_sw_hw_apply
,
2056 .num_mibs
= ARRAY_SIZE(ar8236_mibs
),
2057 .mib_decs
= ar8236_mibs
,
2058 .mib_func
= AR8216_REG_MIB_FUNC
,
2059 .mib_rxb_id
= AR8236_MIB_RXB_ID
,
2060 .mib_txb_id
= AR8236_MIB_TXB_ID
,
2063 static const struct ar8xxx_chip ar8236_chip
= {
2064 .caps
= AR8XXX_CAP_MIB_COUNTERS
,
2066 .reg_port_stats_start
= 0x20000,
2067 .reg_port_stats_length
= 0x100,
2068 .reg_arl_ctrl
= AR8216_REG_ATU_CTRL
,
2070 .name
= "Atheros AR8236",
2071 .ports
= AR8216_NUM_PORTS
,
2072 .vlans
= AR8216_NUM_VLANS
,
2073 .swops
= &ar8xxx_sw_ops
,
2075 .hw_init
= ar8216_hw_init
,
2076 .init_globals
= ar8236_init_globals
,
2077 .init_port
= ar8216_init_port
,
2078 .setup_port
= ar8236_setup_port
,
2079 .read_port_status
= ar8216_read_port_status
,
2080 .atu_flush
= ar8216_atu_flush
,
2081 .atu_flush_port
= ar8216_atu_flush_port
,
2082 .vtu_flush
= ar8216_vtu_flush
,
2083 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
2084 .set_mirror_regs
= ar8216_set_mirror_regs
,
2085 .get_arl_entry
= ar8216_get_arl_entry
,
2086 .sw_hw_apply
= ar8xxx_sw_hw_apply
,
2088 .num_mibs
= ARRAY_SIZE(ar8236_mibs
),
2089 .mib_decs
= ar8236_mibs
,
2090 .mib_func
= AR8216_REG_MIB_FUNC
,
2091 .mib_rxb_id
= AR8236_MIB_RXB_ID
,
2092 .mib_txb_id
= AR8236_MIB_TXB_ID
,
2095 static const struct ar8xxx_chip ar8316_chip
= {
2096 .caps
= AR8XXX_CAP_GIGE
| AR8XXX_CAP_MIB_COUNTERS
,
2098 .reg_port_stats_start
= 0x20000,
2099 .reg_port_stats_length
= 0x100,
2100 .reg_arl_ctrl
= AR8216_REG_ATU_CTRL
,
2102 .name
= "Atheros AR8316",
2103 .ports
= AR8216_NUM_PORTS
,
2104 .vlans
= AR8X16_MAX_VLANS
,
2105 .swops
= &ar8xxx_sw_ops
,
2107 .hw_init
= ar8316_hw_init
,
2108 .init_globals
= ar8316_init_globals
,
2109 .init_port
= ar8216_init_port
,
2110 .setup_port
= ar8216_setup_port
,
2111 .read_port_status
= ar8216_read_port_status
,
2112 .atu_flush
= ar8216_atu_flush
,
2113 .atu_flush_port
= ar8216_atu_flush_port
,
2114 .vtu_flush
= ar8216_vtu_flush
,
2115 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
2116 .set_mirror_regs
= ar8216_set_mirror_regs
,
2117 .get_arl_entry
= ar8216_get_arl_entry
,
2118 .sw_hw_apply
= ar8xxx_sw_hw_apply
,
2120 .num_mibs
= ARRAY_SIZE(ar8236_mibs
),
2121 .mib_decs
= ar8236_mibs
,
2122 .mib_func
= AR8216_REG_MIB_FUNC
,
2123 .mib_rxb_id
= AR8236_MIB_RXB_ID
,
2124 .mib_txb_id
= AR8236_MIB_TXB_ID
,
2128 ar8xxx_read_id(struct ar8xxx_priv
*priv
)
2134 val
= ar8xxx_read(priv
, AR8216_REG_CTRL
);
2138 id
= val
& (AR8216_CTRL_REVISION
| AR8216_CTRL_VERSION
);
2139 for (i
= 0; i
< AR8X16_PROBE_RETRIES
; i
++) {
2142 val
= ar8xxx_read(priv
, AR8216_REG_CTRL
);
2146 t
= val
& (AR8216_CTRL_REVISION
| AR8216_CTRL_VERSION
);
2151 priv
->chip_ver
= (id
& AR8216_CTRL_VERSION
) >> AR8216_CTRL_VERSION_S
;
2152 priv
->chip_rev
= (id
& AR8216_CTRL_REVISION
);
2157 ar8xxx_id_chip(struct ar8xxx_priv
*priv
)
2161 ret
= ar8xxx_read_id(priv
);
2165 switch (priv
->chip_ver
) {
2166 case AR8XXX_VER_AR8216
:
2167 priv
->chip
= &ar8216_chip
;
2169 case AR8XXX_VER_AR8236
:
2170 priv
->chip
= &ar8236_chip
;
2172 case AR8XXX_VER_AR8316
:
2173 priv
->chip
= &ar8316_chip
;
2175 case AR8XXX_VER_AR8327
:
2176 priv
->chip
= &ar8327_chip
;
2178 case AR8XXX_VER_AR8337
:
2179 priv
->chip
= &ar8337_chip
;
2182 pr_err("ar8216: Unknown Atheros device [ver=%d, rev=%d]\n",
2183 priv
->chip_ver
, priv
->chip_rev
);
2192 ar8xxx_mib_work_func(struct work_struct
*work
)
2194 struct ar8xxx_priv
*priv
;
2197 priv
= container_of(work
, struct ar8xxx_priv
, mib_work
.work
);
2199 mutex_lock(&priv
->mib_lock
);
2201 err
= ar8xxx_mib_capture(priv
);
2205 for (i
= 0; i
< priv
->dev
.ports
; i
++)
2206 ar8xxx_mib_fetch_port_stat(priv
, i
, false);
2209 mutex_unlock(&priv
->mib_lock
);
2210 schedule_delayed_work(&priv
->mib_work
,
2211 msecs_to_jiffies(priv
->mib_poll_interval
));
2215 ar8xxx_mib_init(struct ar8xxx_priv
*priv
)
2219 if (!ar8xxx_has_mib_counters(priv
))
2222 BUG_ON(!priv
->chip
->mib_decs
|| !priv
->chip
->num_mibs
);
2224 len
= priv
->dev
.ports
* priv
->chip
->num_mibs
*
2225 sizeof(*priv
->mib_stats
);
2226 priv
->mib_stats
= kzalloc(len
, GFP_KERNEL
);
2228 if (!priv
->mib_stats
)
2235 ar8xxx_mib_start(struct ar8xxx_priv
*priv
)
2237 if (!ar8xxx_has_mib_counters(priv
))
2240 schedule_delayed_work(&priv
->mib_work
,
2241 msecs_to_jiffies(priv
->mib_poll_interval
));
2245 ar8xxx_mib_stop(struct ar8xxx_priv
*priv
)
2247 if (!ar8xxx_has_mib_counters(priv
))
2250 cancel_delayed_work_sync(&priv
->mib_work
);
2253 static struct ar8xxx_priv
*
2256 struct ar8xxx_priv
*priv
;
2258 priv
= kzalloc(sizeof(struct ar8xxx_priv
), GFP_KERNEL
);
2262 mutex_init(&priv
->reg_mutex
);
2263 mutex_init(&priv
->mib_lock
);
2264 INIT_DELAYED_WORK(&priv
->mib_work
, ar8xxx_mib_work_func
);
2270 ar8xxx_free(struct ar8xxx_priv
*priv
)
2272 if (priv
->chip
&& priv
->chip
->cleanup
)
2273 priv
->chip
->cleanup(priv
);
2275 kfree(priv
->chip_data
);
2276 kfree(priv
->mib_stats
);
2281 ar8xxx_probe_switch(struct ar8xxx_priv
*priv
)
2283 const struct ar8xxx_chip
*chip
;
2284 struct switch_dev
*swdev
;
2290 swdev
->cpu_port
= AR8216_PORT_CPU
;
2291 swdev
->name
= chip
->name
;
2292 swdev
->vlans
= chip
->vlans
;
2293 swdev
->ports
= chip
->ports
;
2294 swdev
->ops
= chip
->swops
;
2296 ret
= ar8xxx_mib_init(priv
);
2304 ar8xxx_start(struct ar8xxx_priv
*priv
)
2310 ret
= priv
->chip
->hw_init(priv
);
2314 ret
= ar8xxx_sw_reset_switch(&priv
->dev
);
2320 ar8xxx_mib_start(priv
);
2326 ar8xxx_phy_config_init(struct phy_device
*phydev
)
2328 struct ar8xxx_priv
*priv
= phydev
->priv
;
2329 struct net_device
*dev
= phydev
->attached_dev
;
2335 if (priv
->chip
->config_at_probe
)
2336 return ar8xxx_phy_check_aneg(phydev
);
2340 if (phydev
->mdio
.addr
!= 0) {
2341 if (chip_is_ar8316(priv
)) {
2342 /* switch device has been initialized, reinit */
2343 priv
->dev
.ports
= (AR8216_NUM_PORTS
- 1);
2344 priv
->initialized
= false;
2345 priv
->port4_phy
= true;
2346 ar8316_hw_init(priv
);
2353 ret
= ar8xxx_start(priv
);
2357 /* VID fixup only needed on ar8216 */
2358 if (chip_is_ar8216(priv
)) {
2359 dev
->phy_ptr
= priv
;
2360 dev
->priv_flags
|= IFF_NO_IP_ALIGN
;
2361 dev
->eth_mangle_rx
= ar8216_mangle_rx
;
2362 dev
->eth_mangle_tx
= ar8216_mangle_tx
;
2369 ar8xxx_check_link_states(struct ar8xxx_priv
*priv
)
2371 bool link_new
, changed
= false;
2375 mutex_lock(&priv
->reg_mutex
);
2377 for (i
= 0; i
< priv
->dev
.ports
; i
++) {
2378 status
= priv
->chip
->read_port_status(priv
, i
);
2379 link_new
= !!(status
& AR8216_PORT_STATUS_LINK_UP
);
2380 if (link_new
== priv
->link_up
[i
])
2383 priv
->link_up
[i
] = link_new
;
2385 /* flush ARL entries for this port if it went down*/
2387 priv
->chip
->atu_flush_port(priv
, i
);
2388 dev_info(&priv
->phy
->mdio
.dev
, "Port %d is %s\n",
2389 i
, link_new
? "up" : "down");
2392 mutex_unlock(&priv
->reg_mutex
);
2398 ar8xxx_phy_read_status(struct phy_device
*phydev
)
2400 struct ar8xxx_priv
*priv
= phydev
->priv
;
2401 struct switch_port_link link
;
2403 /* check for switch port link changes */
2404 if (phydev
->state
== PHY_CHANGELINK
)
2405 ar8xxx_check_link_states(priv
);
2407 if (phydev
->mdio
.addr
!= 0)
2408 return genphy_read_status(phydev
);
2410 ar8216_read_port_link(priv
, phydev
->mdio
.addr
, &link
);
2411 phydev
->link
= !!link
.link
;
2415 switch (link
.speed
) {
2416 case SWITCH_PORT_SPEED_10
:
2417 phydev
->speed
= SPEED_10
;
2419 case SWITCH_PORT_SPEED_100
:
2420 phydev
->speed
= SPEED_100
;
2422 case SWITCH_PORT_SPEED_1000
:
2423 phydev
->speed
= SPEED_1000
;
2428 phydev
->duplex
= link
.duplex
? DUPLEX_FULL
: DUPLEX_HALF
;
2430 phydev
->state
= PHY_RUNNING
;
2431 netif_carrier_on(phydev
->attached_dev
);
2432 if (phydev
->adjust_link
)
2433 phydev
->adjust_link(phydev
->attached_dev
);
2439 ar8xxx_phy_config_aneg(struct phy_device
*phydev
)
2441 if (phydev
->mdio
.addr
== 0)
2444 return genphy_config_aneg(phydev
);
2447 static const u32 ar8xxx_phy_ids
[] = {
2449 0x004dd034, /* AR8327 */
2450 0x004dd036, /* AR8337 */
2453 0x004dd043, /* AR8236 */
2457 ar8xxx_phy_match(u32 phy_id
)
2461 for (i
= 0; i
< ARRAY_SIZE(ar8xxx_phy_ids
); i
++)
2462 if (phy_id
== ar8xxx_phy_ids
[i
])
2469 ar8xxx_is_possible(struct mii_bus
*bus
)
2471 unsigned int i
, found_phys
= 0;
2473 for (i
= 0; i
< 5; i
++) {
2476 phy_id
= mdiobus_read(bus
, i
, MII_PHYSID1
) << 16;
2477 phy_id
|= mdiobus_read(bus
, i
, MII_PHYSID2
);
2478 if (ar8xxx_phy_match(phy_id
)) {
2480 } else if (phy_id
) {
2481 pr_debug("ar8xxx: unknown PHY at %s:%02x id:%08x\n",
2482 dev_name(&bus
->dev
), i
, phy_id
);
2485 return !!found_phys
;
2489 ar8xxx_phy_probe(struct phy_device
*phydev
)
2491 struct ar8xxx_priv
*priv
;
2492 struct switch_dev
*swdev
;
2495 /* skip PHYs at unused adresses */
2496 if (phydev
->mdio
.addr
!= 0 && phydev
->mdio
.addr
!= 3 && phydev
->mdio
.addr
!= 4)
2499 if (!ar8xxx_is_possible(phydev
->mdio
.bus
))
2502 mutex_lock(&ar8xxx_dev_list_lock
);
2503 list_for_each_entry(priv
, &ar8xxx_dev_list
, list
)
2504 if (priv
->mii_bus
== phydev
->mdio
.bus
)
2507 priv
= ar8xxx_create();
2513 priv
->mii_bus
= phydev
->mdio
.bus
;
2514 priv
->pdev
= &phydev
->mdio
.dev
;
2516 ret
= of_property_read_u32(priv
->pdev
->of_node
, "qca,mib-poll-interval",
2517 &priv
->mib_poll_interval
);
2519 priv
->mib_poll_interval
= AR8XXX_MIB_WORK_DELAY
;
2521 ret
= ar8xxx_id_chip(priv
);
2525 ret
= ar8xxx_probe_switch(priv
);
2530 swdev
->alias
= dev_name(&priv
->mii_bus
->dev
);
2531 ret
= register_switch(swdev
, NULL
);
2535 pr_info("%s: %s rev. %u switch registered on %s\n",
2536 swdev
->devname
, swdev
->name
, priv
->chip_rev
,
2537 dev_name(&priv
->mii_bus
->dev
));
2539 list_add(&priv
->list
, &ar8xxx_dev_list
);
2544 if (phydev
->mdio
.addr
== 0) {
2545 if (ar8xxx_has_gige(priv
)) {
2546 phydev
->supported
= SUPPORTED_1000baseT_Full
;
2547 phydev
->advertising
= ADVERTISED_1000baseT_Full
;
2549 phydev
->supported
= SUPPORTED_100baseT_Full
;
2550 phydev
->advertising
= ADVERTISED_100baseT_Full
;
2553 if (priv
->chip
->config_at_probe
) {
2556 ret
= ar8xxx_start(priv
);
2558 goto err_unregister_switch
;
2561 if (ar8xxx_has_gige(priv
)) {
2562 phydev
->supported
|= SUPPORTED_1000baseT_Full
;
2563 phydev
->advertising
|= ADVERTISED_1000baseT_Full
;
2565 if (priv
->chip
->phy_rgmii_set
)
2566 priv
->chip
->phy_rgmii_set(priv
, phydev
);
2569 phydev
->priv
= priv
;
2571 mutex_unlock(&ar8xxx_dev_list_lock
);
2575 err_unregister_switch
:
2576 if (--priv
->use_count
)
2579 unregister_switch(&priv
->dev
);
2584 mutex_unlock(&ar8xxx_dev_list_lock
);
2589 ar8xxx_phy_detach(struct phy_device
*phydev
)
2591 struct net_device
*dev
= phydev
->attached_dev
;
2596 dev
->phy_ptr
= NULL
;
2597 dev
->priv_flags
&= ~IFF_NO_IP_ALIGN
;
2598 dev
->eth_mangle_rx
= NULL
;
2599 dev
->eth_mangle_tx
= NULL
;
2603 ar8xxx_phy_remove(struct phy_device
*phydev
)
2605 struct ar8xxx_priv
*priv
= phydev
->priv
;
2610 phydev
->priv
= NULL
;
2612 mutex_lock(&ar8xxx_dev_list_lock
);
2614 if (--priv
->use_count
> 0) {
2615 mutex_unlock(&ar8xxx_dev_list_lock
);
2619 list_del(&priv
->list
);
2620 mutex_unlock(&ar8xxx_dev_list_lock
);
2622 unregister_switch(&priv
->dev
);
2623 ar8xxx_mib_stop(priv
);
2628 ar8xxx_phy_soft_reset(struct phy_device
*phydev
)
2630 /* we don't need an extra reset */
2634 static struct phy_driver ar8xxx_phy_driver
[] = {
2636 .phy_id
= 0x004d0000,
2637 .name
= "Atheros AR8216/AR8236/AR8316",
2638 .phy_id_mask
= 0xffff0000,
2639 .features
= PHY_BASIC_FEATURES
,
2640 .probe
= ar8xxx_phy_probe
,
2641 .remove
= ar8xxx_phy_remove
,
2642 .detach
= ar8xxx_phy_detach
,
2643 .config_init
= ar8xxx_phy_config_init
,
2644 .config_aneg
= ar8xxx_phy_config_aneg
,
2645 .read_status
= ar8xxx_phy_read_status
,
2646 .soft_reset
= ar8xxx_phy_soft_reset
,
2650 static const struct of_device_id ar8xxx_mdiodev_of_match
[] = {
2652 .compatible
= "qca,ar7240sw",
2653 .data
= &ar7240sw_chip
,
2655 .compatible
= "qca,ar8229",
2656 .data
= &ar8229_chip
,
2658 .compatible
= "qca,ar8236",
2659 .data
= &ar8236_chip
,
2661 .compatible
= "qca,ar8327",
2662 .data
= &ar8327_chip
,
2668 ar8xxx_mdiodev_probe(struct mdio_device
*mdiodev
)
2670 const struct of_device_id
*match
;
2671 struct ar8xxx_priv
*priv
;
2672 struct switch_dev
*swdev
;
2673 struct device_node
*mdio_node
;
2676 match
= of_match_device(ar8xxx_mdiodev_of_match
, &mdiodev
->dev
);
2680 priv
= ar8xxx_create();
2684 priv
->mii_bus
= mdiodev
->bus
;
2685 priv
->pdev
= &mdiodev
->dev
;
2686 priv
->chip
= (const struct ar8xxx_chip
*) match
->data
;
2688 ret
= of_property_read_u32(priv
->pdev
->of_node
, "qca,mib-poll-interval",
2689 &priv
->mib_poll_interval
);
2691 priv
->mib_poll_interval
= AR8XXX_MIB_WORK_DELAY
;
2693 ret
= ar8xxx_read_id(priv
);
2697 ret
= ar8xxx_probe_switch(priv
);
2701 if (priv
->chip
->phy_read
&& priv
->chip
->phy_write
) {
2702 priv
->sw_mii_bus
= devm_mdiobus_alloc(&mdiodev
->dev
);
2703 priv
->sw_mii_bus
->name
= "ar8xxx-mdio";
2704 priv
->sw_mii_bus
->read
= ar8xxx_phy_read
;
2705 priv
->sw_mii_bus
->write
= ar8xxx_phy_write
;
2706 priv
->sw_mii_bus
->priv
= priv
;
2707 priv
->sw_mii_bus
->parent
= &mdiodev
->dev
;
2708 snprintf(priv
->sw_mii_bus
->id
, MII_BUS_ID_SIZE
, "%s",
2709 dev_name(&mdiodev
->dev
));
2710 mdio_node
= of_get_child_by_name(priv
->pdev
->of_node
, "mdio-bus");
2711 ret
= of_mdiobus_register(priv
->sw_mii_bus
, mdio_node
);
2717 swdev
->alias
= dev_name(&mdiodev
->dev
);
2719 if (of_property_read_bool(priv
->pdev
->of_node
, "qca,phy4-mii-enable")) {
2720 priv
->port4_phy
= true;
2724 ret
= register_switch(swdev
, NULL
);
2728 pr_info("%s: %s rev. %u switch registered on %s\n",
2729 swdev
->devname
, swdev
->name
, priv
->chip_rev
,
2730 dev_name(&priv
->mii_bus
->dev
));
2732 mutex_lock(&ar8xxx_dev_list_lock
);
2733 list_add(&priv
->list
, &ar8xxx_dev_list
);
2734 mutex_unlock(&ar8xxx_dev_list_lock
);
2738 ret
= ar8xxx_start(priv
);
2740 goto err_unregister_switch
;
2742 dev_set_drvdata(&mdiodev
->dev
, priv
);
2746 err_unregister_switch
:
2747 if (--priv
->use_count
)
2750 unregister_switch(&priv
->dev
);
2758 ar8xxx_mdiodev_remove(struct mdio_device
*mdiodev
)
2760 struct ar8xxx_priv
*priv
= dev_get_drvdata(&mdiodev
->dev
);
2765 mutex_lock(&ar8xxx_dev_list_lock
);
2767 if (--priv
->use_count
> 0) {
2768 mutex_unlock(&ar8xxx_dev_list_lock
);
2772 list_del(&priv
->list
);
2773 mutex_unlock(&ar8xxx_dev_list_lock
);
2775 unregister_switch(&priv
->dev
);
2776 ar8xxx_mib_stop(priv
);
2777 if(priv
->sw_mii_bus
)
2778 mdiobus_unregister(priv
->sw_mii_bus
);
2782 static struct mdio_driver ar8xxx_mdio_driver
= {
2783 .probe
= ar8xxx_mdiodev_probe
,
2784 .remove
= ar8xxx_mdiodev_remove
,
2786 .name
= "ar8xxx-switch",
2787 .of_match_table
= ar8xxx_mdiodev_of_match
,
2791 static int __init
ar8216_init(void)
2795 ret
= phy_drivers_register(ar8xxx_phy_driver
,
2796 ARRAY_SIZE(ar8xxx_phy_driver
),
2801 ret
= mdio_driver_register(&ar8xxx_mdio_driver
);
2803 phy_drivers_unregister(ar8xxx_phy_driver
,
2804 ARRAY_SIZE(ar8xxx_phy_driver
));
2808 module_init(ar8216_init
);
2810 static void __exit
ar8216_exit(void)
2812 mdio_driver_unregister(&ar8xxx_mdio_driver
);
2813 phy_drivers_unregister(ar8xxx_phy_driver
,
2814 ARRAY_SIZE(ar8xxx_phy_driver
));
2816 module_exit(ar8216_exit
);
2818 MODULE_LICENSE("GPL");