2 * ar8216.c: AR8216 switch driver
4 * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/list.h>
22 #include <linux/if_ether.h>
23 #include <linux/skbuff.h>
24 #include <linux/netdevice.h>
25 #include <linux/netlink.h>
26 #include <linux/bitops.h>
27 #include <net/genetlink.h>
28 #include <linux/switch.h>
29 #include <linux/delay.h>
30 #include <linux/phy.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/lockdep.h>
34 #include <linux/ar8216_platform.h>
35 #include <linux/workqueue.h>
36 #include <linux/version.h>
40 extern const struct ar8xxx_chip ar8327_chip
;
41 extern const struct ar8xxx_chip ar8337_chip
;
43 #define AR8XXX_MIB_WORK_DELAY 2000 /* msecs */
45 #define MIB_DESC(_s , _o, _n) \
52 static const struct ar8xxx_mib_desc ar8216_mibs
[] = {
53 MIB_DESC(1, AR8216_STATS_RXBROAD
, "RxBroad"),
54 MIB_DESC(1, AR8216_STATS_RXPAUSE
, "RxPause"),
55 MIB_DESC(1, AR8216_STATS_RXMULTI
, "RxMulti"),
56 MIB_DESC(1, AR8216_STATS_RXFCSERR
, "RxFcsErr"),
57 MIB_DESC(1, AR8216_STATS_RXALIGNERR
, "RxAlignErr"),
58 MIB_DESC(1, AR8216_STATS_RXRUNT
, "RxRunt"),
59 MIB_DESC(1, AR8216_STATS_RXFRAGMENT
, "RxFragment"),
60 MIB_DESC(1, AR8216_STATS_RX64BYTE
, "Rx64Byte"),
61 MIB_DESC(1, AR8216_STATS_RX128BYTE
, "Rx128Byte"),
62 MIB_DESC(1, AR8216_STATS_RX256BYTE
, "Rx256Byte"),
63 MIB_DESC(1, AR8216_STATS_RX512BYTE
, "Rx512Byte"),
64 MIB_DESC(1, AR8216_STATS_RX1024BYTE
, "Rx1024Byte"),
65 MIB_DESC(1, AR8216_STATS_RXMAXBYTE
, "RxMaxByte"),
66 MIB_DESC(1, AR8216_STATS_RXTOOLONG
, "RxTooLong"),
67 MIB_DESC(2, AR8216_STATS_RXGOODBYTE
, "RxGoodByte"),
68 MIB_DESC(2, AR8216_STATS_RXBADBYTE
, "RxBadByte"),
69 MIB_DESC(1, AR8216_STATS_RXOVERFLOW
, "RxOverFlow"),
70 MIB_DESC(1, AR8216_STATS_FILTERED
, "Filtered"),
71 MIB_DESC(1, AR8216_STATS_TXBROAD
, "TxBroad"),
72 MIB_DESC(1, AR8216_STATS_TXPAUSE
, "TxPause"),
73 MIB_DESC(1, AR8216_STATS_TXMULTI
, "TxMulti"),
74 MIB_DESC(1, AR8216_STATS_TXUNDERRUN
, "TxUnderRun"),
75 MIB_DESC(1, AR8216_STATS_TX64BYTE
, "Tx64Byte"),
76 MIB_DESC(1, AR8216_STATS_TX128BYTE
, "Tx128Byte"),
77 MIB_DESC(1, AR8216_STATS_TX256BYTE
, "Tx256Byte"),
78 MIB_DESC(1, AR8216_STATS_TX512BYTE
, "Tx512Byte"),
79 MIB_DESC(1, AR8216_STATS_TX1024BYTE
, "Tx1024Byte"),
80 MIB_DESC(1, AR8216_STATS_TXMAXBYTE
, "TxMaxByte"),
81 MIB_DESC(1, AR8216_STATS_TXOVERSIZE
, "TxOverSize"),
82 MIB_DESC(2, AR8216_STATS_TXBYTE
, "TxByte"),
83 MIB_DESC(1, AR8216_STATS_TXCOLLISION
, "TxCollision"),
84 MIB_DESC(1, AR8216_STATS_TXABORTCOL
, "TxAbortCol"),
85 MIB_DESC(1, AR8216_STATS_TXMULTICOL
, "TxMultiCol"),
86 MIB_DESC(1, AR8216_STATS_TXSINGLECOL
, "TxSingleCol"),
87 MIB_DESC(1, AR8216_STATS_TXEXCDEFER
, "TxExcDefer"),
88 MIB_DESC(1, AR8216_STATS_TXDEFER
, "TxDefer"),
89 MIB_DESC(1, AR8216_STATS_TXLATECOL
, "TxLateCol"),
92 const struct ar8xxx_mib_desc ar8236_mibs
[39] = {
93 MIB_DESC(1, AR8236_STATS_RXBROAD
, "RxBroad"),
94 MIB_DESC(1, AR8236_STATS_RXPAUSE
, "RxPause"),
95 MIB_DESC(1, AR8236_STATS_RXMULTI
, "RxMulti"),
96 MIB_DESC(1, AR8236_STATS_RXFCSERR
, "RxFcsErr"),
97 MIB_DESC(1, AR8236_STATS_RXALIGNERR
, "RxAlignErr"),
98 MIB_DESC(1, AR8236_STATS_RXRUNT
, "RxRunt"),
99 MIB_DESC(1, AR8236_STATS_RXFRAGMENT
, "RxFragment"),
100 MIB_DESC(1, AR8236_STATS_RX64BYTE
, "Rx64Byte"),
101 MIB_DESC(1, AR8236_STATS_RX128BYTE
, "Rx128Byte"),
102 MIB_DESC(1, AR8236_STATS_RX256BYTE
, "Rx256Byte"),
103 MIB_DESC(1, AR8236_STATS_RX512BYTE
, "Rx512Byte"),
104 MIB_DESC(1, AR8236_STATS_RX1024BYTE
, "Rx1024Byte"),
105 MIB_DESC(1, AR8236_STATS_RX1518BYTE
, "Rx1518Byte"),
106 MIB_DESC(1, AR8236_STATS_RXMAXBYTE
, "RxMaxByte"),
107 MIB_DESC(1, AR8236_STATS_RXTOOLONG
, "RxTooLong"),
108 MIB_DESC(2, AR8236_STATS_RXGOODBYTE
, "RxGoodByte"),
109 MIB_DESC(2, AR8236_STATS_RXBADBYTE
, "RxBadByte"),
110 MIB_DESC(1, AR8236_STATS_RXOVERFLOW
, "RxOverFlow"),
111 MIB_DESC(1, AR8236_STATS_FILTERED
, "Filtered"),
112 MIB_DESC(1, AR8236_STATS_TXBROAD
, "TxBroad"),
113 MIB_DESC(1, AR8236_STATS_TXPAUSE
, "TxPause"),
114 MIB_DESC(1, AR8236_STATS_TXMULTI
, "TxMulti"),
115 MIB_DESC(1, AR8236_STATS_TXUNDERRUN
, "TxUnderRun"),
116 MIB_DESC(1, AR8236_STATS_TX64BYTE
, "Tx64Byte"),
117 MIB_DESC(1, AR8236_STATS_TX128BYTE
, "Tx128Byte"),
118 MIB_DESC(1, AR8236_STATS_TX256BYTE
, "Tx256Byte"),
119 MIB_DESC(1, AR8236_STATS_TX512BYTE
, "Tx512Byte"),
120 MIB_DESC(1, AR8236_STATS_TX1024BYTE
, "Tx1024Byte"),
121 MIB_DESC(1, AR8236_STATS_TX1518BYTE
, "Tx1518Byte"),
122 MIB_DESC(1, AR8236_STATS_TXMAXBYTE
, "TxMaxByte"),
123 MIB_DESC(1, AR8236_STATS_TXOVERSIZE
, "TxOverSize"),
124 MIB_DESC(2, AR8236_STATS_TXBYTE
, "TxByte"),
125 MIB_DESC(1, AR8236_STATS_TXCOLLISION
, "TxCollision"),
126 MIB_DESC(1, AR8236_STATS_TXABORTCOL
, "TxAbortCol"),
127 MIB_DESC(1, AR8236_STATS_TXMULTICOL
, "TxMultiCol"),
128 MIB_DESC(1, AR8236_STATS_TXSINGLECOL
, "TxSingleCol"),
129 MIB_DESC(1, AR8236_STATS_TXEXCDEFER
, "TxExcDefer"),
130 MIB_DESC(1, AR8236_STATS_TXDEFER
, "TxDefer"),
131 MIB_DESC(1, AR8236_STATS_TXLATECOL
, "TxLateCol"),
134 static DEFINE_MUTEX(ar8xxx_dev_list_lock
);
135 static LIST_HEAD(ar8xxx_dev_list
);
138 split_addr(u32 regaddr
, u16
*r1
, u16
*r2
, u16
*page
)
141 *r1
= regaddr
& 0x1e;
147 *page
= regaddr
& 0x1ff;
150 /* inspired by phy_poll_reset in drivers/net/phy/phy_device.c */
152 ar8xxx_phy_poll_reset(struct mii_bus
*bus
)
154 unsigned int sleep_msecs
= 20;
157 for (elapsed
= sleep_msecs
; elapsed
<= 600;
158 elapsed
+= sleep_msecs
) {
160 for (i
= 0; i
< AR8XXX_NUM_PHYS
; i
++) {
161 ret
= mdiobus_read(bus
, i
, MII_BMCR
);
164 if (ret
& BMCR_RESET
)
166 if (i
== AR8XXX_NUM_PHYS
- 1) {
167 usleep_range(1000, 2000);
176 ar8xxx_phy_check_aneg(struct phy_device
*phydev
)
180 if (phydev
->autoneg
!= AUTONEG_ENABLE
)
183 * BMCR_ANENABLE might have been cleared
184 * by phy_init_hw in certain kernel versions
185 * therefore check for it
187 ret
= phy_read(phydev
, MII_BMCR
);
190 if (ret
& BMCR_ANENABLE
)
193 dev_info(&phydev
->dev
, "ANEG disabled, re-enabling ...\n");
194 ret
|= BMCR_ANENABLE
| BMCR_ANRESTART
;
195 return phy_write(phydev
, MII_BMCR
, ret
);
199 ar8xxx_phy_init(struct ar8xxx_priv
*priv
)
205 for (i
= 0; i
< AR8XXX_NUM_PHYS
; i
++) {
206 if (priv
->chip
->phy_fixup
)
207 priv
->chip
->phy_fixup(priv
, i
);
209 /* initialize the port itself */
210 mdiobus_write(bus
, i
, MII_ADVERTISE
,
211 ADVERTISE_ALL
| ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
);
212 if (ar8xxx_has_gige(priv
))
213 mdiobus_write(bus
, i
, MII_CTRL1000
, ADVERTISE_1000FULL
);
214 mdiobus_write(bus
, i
, MII_BMCR
, BMCR_RESET
| BMCR_ANENABLE
);
217 ar8xxx_phy_poll_reset(bus
);
221 mii_read32(struct ar8xxx_priv
*priv
, int phy_id
, int regnum
)
223 struct mii_bus
*bus
= priv
->mii_bus
;
226 lo
= bus
->read(bus
, phy_id
, regnum
);
227 hi
= bus
->read(bus
, phy_id
, regnum
+ 1);
229 return (hi
<< 16) | lo
;
233 mii_write32(struct ar8xxx_priv
*priv
, int phy_id
, int regnum
, u32 val
)
235 struct mii_bus
*bus
= priv
->mii_bus
;
239 hi
= (u16
) (val
>> 16);
241 if (priv
->chip
->mii_lo_first
)
243 bus
->write(bus
, phy_id
, regnum
, lo
);
244 bus
->write(bus
, phy_id
, regnum
+ 1, hi
);
246 bus
->write(bus
, phy_id
, regnum
+ 1, hi
);
247 bus
->write(bus
, phy_id
, regnum
, lo
);
252 ar8xxx_read(struct ar8xxx_priv
*priv
, int reg
)
254 struct mii_bus
*bus
= priv
->mii_bus
;
258 split_addr((u32
) reg
, &r1
, &r2
, &page
);
260 mutex_lock(&bus
->mdio_lock
);
262 bus
->write(bus
, 0x18, 0, page
);
263 usleep_range(1000, 2000); /* wait for the page switch to propagate */
264 val
= mii_read32(priv
, 0x10 | r2
, r1
);
266 mutex_unlock(&bus
->mdio_lock
);
272 ar8xxx_write(struct ar8xxx_priv
*priv
, int reg
, u32 val
)
274 struct mii_bus
*bus
= priv
->mii_bus
;
277 split_addr((u32
) reg
, &r1
, &r2
, &page
);
279 mutex_lock(&bus
->mdio_lock
);
281 bus
->write(bus
, 0x18, 0, page
);
282 usleep_range(1000, 2000); /* wait for the page switch to propagate */
283 mii_write32(priv
, 0x10 | r2
, r1
, val
);
285 mutex_unlock(&bus
->mdio_lock
);
289 ar8xxx_rmw(struct ar8xxx_priv
*priv
, int reg
, u32 mask
, u32 val
)
291 struct mii_bus
*bus
= priv
->mii_bus
;
295 split_addr((u32
) reg
, &r1
, &r2
, &page
);
297 mutex_lock(&bus
->mdio_lock
);
299 bus
->write(bus
, 0x18, 0, page
);
300 usleep_range(1000, 2000); /* wait for the page switch to propagate */
302 ret
= mii_read32(priv
, 0x10 | r2
, r1
);
305 mii_write32(priv
, 0x10 | r2
, r1
, ret
);
307 mutex_unlock(&bus
->mdio_lock
);
313 ar8xxx_phy_dbg_write(struct ar8xxx_priv
*priv
, int phy_addr
,
314 u16 dbg_addr
, u16 dbg_data
)
316 struct mii_bus
*bus
= priv
->mii_bus
;
318 mutex_lock(&bus
->mdio_lock
);
319 bus
->write(bus
, phy_addr
, MII_ATH_DBG_ADDR
, dbg_addr
);
320 bus
->write(bus
, phy_addr
, MII_ATH_DBG_DATA
, dbg_data
);
321 mutex_unlock(&bus
->mdio_lock
);
325 ar8xxx_phy_mmd_write(struct ar8xxx_priv
*priv
, int phy_addr
, u16 addr
, u16 data
)
327 struct mii_bus
*bus
= priv
->mii_bus
;
329 mutex_lock(&bus
->mdio_lock
);
330 bus
->write(bus
, phy_addr
, MII_ATH_MMD_ADDR
, addr
);
331 bus
->write(bus
, phy_addr
, MII_ATH_MMD_DATA
, data
);
332 mutex_unlock(&bus
->mdio_lock
);
336 ar8xxx_reg_wait(struct ar8xxx_priv
*priv
, u32 reg
, u32 mask
, u32 val
,
341 for (i
= 0; i
< timeout
; i
++) {
344 t
= ar8xxx_read(priv
, reg
);
345 if ((t
& mask
) == val
)
348 usleep_range(1000, 2000);
355 ar8xxx_mib_op(struct ar8xxx_priv
*priv
, u32 op
)
357 unsigned mib_func
= priv
->chip
->mib_func
;
360 lockdep_assert_held(&priv
->mib_lock
);
362 /* Capture the hardware statistics for all ports */
363 ar8xxx_rmw(priv
, mib_func
, AR8216_MIB_FUNC
, (op
<< AR8216_MIB_FUNC_S
));
365 /* Wait for the capturing to complete. */
366 ret
= ar8xxx_reg_wait(priv
, mib_func
, AR8216_MIB_BUSY
, 0, 10);
377 ar8xxx_mib_capture(struct ar8xxx_priv
*priv
)
379 return ar8xxx_mib_op(priv
, AR8216_MIB_FUNC_CAPTURE
);
383 ar8xxx_mib_flush(struct ar8xxx_priv
*priv
)
385 return ar8xxx_mib_op(priv
, AR8216_MIB_FUNC_FLUSH
);
389 ar8xxx_mib_fetch_port_stat(struct ar8xxx_priv
*priv
, int port
, bool flush
)
395 WARN_ON(port
>= priv
->dev
.ports
);
397 lockdep_assert_held(&priv
->mib_lock
);
399 base
= priv
->chip
->reg_port_stats_start
+
400 priv
->chip
->reg_port_stats_length
* port
;
402 mib_stats
= &priv
->mib_stats
[port
* priv
->chip
->num_mibs
];
403 for (i
= 0; i
< priv
->chip
->num_mibs
; i
++) {
404 const struct ar8xxx_mib_desc
*mib
;
407 mib
= &priv
->chip
->mib_decs
[i
];
408 t
= ar8xxx_read(priv
, base
+ mib
->offset
);
409 if (mib
->size
== 2) {
412 hi
= ar8xxx_read(priv
, base
+ mib
->offset
+ 4);
424 ar8216_read_port_link(struct ar8xxx_priv
*priv
, int port
,
425 struct switch_port_link
*link
)
430 memset(link
, '\0', sizeof(*link
));
432 status
= priv
->chip
->read_port_status(priv
, port
);
434 link
->aneg
= !!(status
& AR8216_PORT_STATUS_LINK_AUTO
);
436 link
->link
= !!(status
& AR8216_PORT_STATUS_LINK_UP
);
440 if (priv
->get_port_link
) {
443 err
= priv
->get_port_link(port
);
452 link
->duplex
= !!(status
& AR8216_PORT_STATUS_DUPLEX
);
453 link
->tx_flow
= !!(status
& AR8216_PORT_STATUS_TXFLOW
);
454 link
->rx_flow
= !!(status
& AR8216_PORT_STATUS_RXFLOW
);
456 speed
= (status
& AR8216_PORT_STATUS_SPEED
) >>
457 AR8216_PORT_STATUS_SPEED_S
;
460 case AR8216_PORT_SPEED_10M
:
461 link
->speed
= SWITCH_PORT_SPEED_10
;
463 case AR8216_PORT_SPEED_100M
:
464 link
->speed
= SWITCH_PORT_SPEED_100
;
466 case AR8216_PORT_SPEED_1000M
:
467 link
->speed
= SWITCH_PORT_SPEED_1000
;
470 link
->speed
= SWITCH_PORT_SPEED_UNKNOWN
;
475 static struct sk_buff
*
476 ar8216_mangle_tx(struct net_device
*dev
, struct sk_buff
*skb
)
478 struct ar8xxx_priv
*priv
= dev
->phy_ptr
;
487 if (unlikely(skb_headroom(skb
) < 2)) {
488 if (pskb_expand_head(skb
, 2, 0, GFP_ATOMIC
) < 0)
492 buf
= skb_push(skb
, 2);
500 dev_kfree_skb_any(skb
);
505 ar8216_mangle_rx(struct net_device
*dev
, struct sk_buff
*skb
)
507 struct ar8xxx_priv
*priv
;
515 /* don't strip the header if vlan mode is disabled */
519 /* strip header, get vlan id */
523 /* check for vlan header presence */
524 if ((buf
[12 + 2] != 0x81) || (buf
[13 + 2] != 0x00))
529 /* no need to fix up packets coming from a tagged source */
530 if (priv
->vlan_tagged
& (1 << port
))
533 /* lookup port vid from local table, the switch passes an invalid vlan id */
534 vlan
= priv
->vlan_id
[priv
->pvid
[port
]];
537 buf
[14 + 2] |= vlan
>> 8;
538 buf
[15 + 2] = vlan
& 0xff;
542 ar8216_wait_bit(struct ar8xxx_priv
*priv
, int reg
, u32 mask
, u32 val
)
548 t
= ar8xxx_read(priv
, reg
);
549 if ((t
& mask
) == val
)
558 pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
559 (unsigned int) reg
, t
, mask
, val
);
564 ar8216_vtu_op(struct ar8xxx_priv
*priv
, u32 op
, u32 val
)
566 if (ar8216_wait_bit(priv
, AR8216_REG_VTU
, AR8216_VTU_ACTIVE
, 0))
568 if ((op
& AR8216_VTU_OP
) == AR8216_VTU_OP_LOAD
) {
569 val
&= AR8216_VTUDATA_MEMBER
;
570 val
|= AR8216_VTUDATA_VALID
;
571 ar8xxx_write(priv
, AR8216_REG_VTU_DATA
, val
);
573 op
|= AR8216_VTU_ACTIVE
;
574 ar8xxx_write(priv
, AR8216_REG_VTU
, op
);
578 ar8216_vtu_flush(struct ar8xxx_priv
*priv
)
580 ar8216_vtu_op(priv
, AR8216_VTU_OP_FLUSH
, 0);
584 ar8216_vtu_load_vlan(struct ar8xxx_priv
*priv
, u32 vid
, u32 port_mask
)
588 op
= AR8216_VTU_OP_LOAD
| (vid
<< AR8216_VTU_VID_S
);
589 ar8216_vtu_op(priv
, op
, port_mask
);
593 ar8216_atu_flush(struct ar8xxx_priv
*priv
)
597 ret
= ar8216_wait_bit(priv
, AR8216_REG_ATU
, AR8216_ATU_ACTIVE
, 0);
599 ar8xxx_write(priv
, AR8216_REG_ATU
, AR8216_ATU_OP_FLUSH
);
605 ar8216_read_port_status(struct ar8xxx_priv
*priv
, int port
)
607 return ar8xxx_read(priv
, AR8216_REG_PORT_STATUS(port
));
611 ar8216_setup_port(struct ar8xxx_priv
*priv
, int port
, u32 members
)
618 pvid
= priv
->vlan_id
[priv
->pvid
[port
]];
619 if (priv
->vlan_tagged
& (1 << port
))
620 egress
= AR8216_OUT_ADD_VLAN
;
622 egress
= AR8216_OUT_STRIP_VLAN
;
623 ingress
= AR8216_IN_SECURE
;
626 egress
= AR8216_OUT_KEEP
;
627 ingress
= AR8216_IN_PORT_ONLY
;
630 if (chip_is_ar8216(priv
) && priv
->vlan
&& port
== AR8216_PORT_CPU
)
631 header
= AR8216_PORT_CTRL_HEADER
;
635 ar8xxx_rmw(priv
, AR8216_REG_PORT_CTRL(port
),
636 AR8216_PORT_CTRL_LEARN
| AR8216_PORT_CTRL_VLAN_MODE
|
637 AR8216_PORT_CTRL_SINGLE_VLAN
| AR8216_PORT_CTRL_STATE
|
638 AR8216_PORT_CTRL_HEADER
| AR8216_PORT_CTRL_LEARN_LOCK
,
639 AR8216_PORT_CTRL_LEARN
| header
|
640 (egress
<< AR8216_PORT_CTRL_VLAN_MODE_S
) |
641 (AR8216_PORT_STATE_FORWARD
<< AR8216_PORT_CTRL_STATE_S
));
643 ar8xxx_rmw(priv
, AR8216_REG_PORT_VLAN(port
),
644 AR8216_PORT_VLAN_DEST_PORTS
| AR8216_PORT_VLAN_MODE
|
645 AR8216_PORT_VLAN_DEFAULT_ID
,
646 (members
<< AR8216_PORT_VLAN_DEST_PORTS_S
) |
647 (ingress
<< AR8216_PORT_VLAN_MODE_S
) |
648 (pvid
<< AR8216_PORT_VLAN_DEFAULT_ID_S
));
652 ar8216_hw_init(struct ar8xxx_priv
*priv
)
654 if (priv
->initialized
)
657 ar8xxx_phy_init(priv
);
659 priv
->initialized
= true;
664 ar8216_init_globals(struct ar8xxx_priv
*priv
)
666 /* standard atheros magic */
667 ar8xxx_write(priv
, 0x38, 0xc000050e);
669 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
670 AR8216_GCTRL_MTU
, 1518 + 8 + 2);
674 ar8216_init_port(struct ar8xxx_priv
*priv
, int port
)
676 /* Enable port learning and tx */
677 ar8xxx_write(priv
, AR8216_REG_PORT_CTRL(port
),
678 AR8216_PORT_CTRL_LEARN
|
679 (4 << AR8216_PORT_CTRL_STATE_S
));
681 ar8xxx_write(priv
, AR8216_REG_PORT_VLAN(port
), 0);
683 if (port
== AR8216_PORT_CPU
) {
684 ar8xxx_write(priv
, AR8216_REG_PORT_STATUS(port
),
685 AR8216_PORT_STATUS_LINK_UP
|
686 (ar8xxx_has_gige(priv
) ?
687 AR8216_PORT_SPEED_1000M
: AR8216_PORT_SPEED_100M
) |
688 AR8216_PORT_STATUS_TXMAC
|
689 AR8216_PORT_STATUS_RXMAC
|
690 (chip_is_ar8316(priv
) ? AR8216_PORT_STATUS_RXFLOW
: 0) |
691 (chip_is_ar8316(priv
) ? AR8216_PORT_STATUS_TXFLOW
: 0) |
692 AR8216_PORT_STATUS_DUPLEX
);
694 ar8xxx_write(priv
, AR8216_REG_PORT_STATUS(port
),
695 AR8216_PORT_STATUS_LINK_AUTO
);
700 ar8236_setup_port(struct ar8xxx_priv
*priv
, int port
, u32 members
)
706 pvid
= priv
->vlan_id
[priv
->pvid
[port
]];
707 if (priv
->vlan_tagged
& (1 << port
))
708 egress
= AR8216_OUT_ADD_VLAN
;
710 egress
= AR8216_OUT_STRIP_VLAN
;
711 ingress
= AR8216_IN_SECURE
;
714 egress
= AR8216_OUT_KEEP
;
715 ingress
= AR8216_IN_PORT_ONLY
;
718 ar8xxx_rmw(priv
, AR8216_REG_PORT_CTRL(port
),
719 AR8216_PORT_CTRL_LEARN
| AR8216_PORT_CTRL_VLAN_MODE
|
720 AR8216_PORT_CTRL_SINGLE_VLAN
| AR8216_PORT_CTRL_STATE
|
721 AR8216_PORT_CTRL_HEADER
| AR8216_PORT_CTRL_LEARN_LOCK
,
722 AR8216_PORT_CTRL_LEARN
|
723 (egress
<< AR8216_PORT_CTRL_VLAN_MODE_S
) |
724 (AR8216_PORT_STATE_FORWARD
<< AR8216_PORT_CTRL_STATE_S
));
726 ar8xxx_rmw(priv
, AR8236_REG_PORT_VLAN(port
),
727 AR8236_PORT_VLAN_DEFAULT_ID
,
728 (pvid
<< AR8236_PORT_VLAN_DEFAULT_ID_S
));
730 ar8xxx_rmw(priv
, AR8236_REG_PORT_VLAN2(port
),
731 AR8236_PORT_VLAN2_VLAN_MODE
|
732 AR8236_PORT_VLAN2_MEMBER
,
733 (ingress
<< AR8236_PORT_VLAN2_VLAN_MODE_S
) |
734 (members
<< AR8236_PORT_VLAN2_MEMBER_S
));
738 ar8236_init_globals(struct ar8xxx_priv
*priv
)
740 /* enable jumbo frames */
741 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
742 AR8316_GCTRL_MTU
, 9018 + 8 + 2);
744 /* enable cpu port to receive arp frames */
745 ar8xxx_rmw(priv
, AR8216_REG_ATU_CTRL
,
746 AR8236_ATU_CTRL_RES
, AR8236_ATU_CTRL_RES
);
748 /* enable cpu port to receive multicast and broadcast frames */
749 ar8xxx_rmw(priv
, AR8216_REG_FLOOD_MASK
,
750 AR8236_FM_CPU_BROADCAST_EN
| AR8236_FM_CPU_BCAST_FWD_EN
,
751 AR8236_FM_CPU_BROADCAST_EN
| AR8236_FM_CPU_BCAST_FWD_EN
);
753 /* Enable MIB counters */
754 ar8xxx_rmw(priv
, AR8216_REG_MIB_FUNC
, AR8216_MIB_FUNC
| AR8236_MIB_EN
,
755 (AR8216_MIB_FUNC_NO_OP
<< AR8216_MIB_FUNC_S
) |
760 ar8316_hw_init(struct ar8xxx_priv
*priv
)
764 val
= ar8xxx_read(priv
, AR8316_REG_POSTRIP
);
766 if (priv
->phy
->interface
== PHY_INTERFACE_MODE_RGMII
) {
767 if (priv
->port4_phy
) {
768 /* value taken from Ubiquiti RouterStation Pro */
770 pr_info("ar8316: Using port 4 as PHY\n");
773 pr_info("ar8316: Using port 4 as switch port\n");
775 } else if (priv
->phy
->interface
== PHY_INTERFACE_MODE_GMII
) {
776 /* value taken from AVM Fritz!Box 7390 sources */
779 /* no known value for phy interface */
780 pr_err("ar8316: unsupported mii mode: %d.\n",
781 priv
->phy
->interface
);
788 ar8xxx_write(priv
, AR8316_REG_POSTRIP
, newval
);
790 if (priv
->port4_phy
&&
791 priv
->phy
->interface
== PHY_INTERFACE_MODE_RGMII
) {
792 /* work around for phy4 rgmii mode */
793 ar8xxx_phy_dbg_write(priv
, 4, 0x12, 0x480c);
795 ar8xxx_phy_dbg_write(priv
, 4, 0x0, 0x824e);
797 ar8xxx_phy_dbg_write(priv
, 4, 0x5, 0x3d47);
801 ar8xxx_phy_init(priv
);
804 priv
->initialized
= true;
809 ar8316_init_globals(struct ar8xxx_priv
*priv
)
811 /* standard atheros magic */
812 ar8xxx_write(priv
, 0x38, 0xc000050e);
814 /* enable cpu port to receive multicast and broadcast frames */
815 ar8xxx_write(priv
, AR8216_REG_FLOOD_MASK
, 0x003f003f);
817 /* enable jumbo frames */
818 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
819 AR8316_GCTRL_MTU
, 9018 + 8 + 2);
821 /* Enable MIB counters */
822 ar8xxx_rmw(priv
, AR8216_REG_MIB_FUNC
, AR8216_MIB_FUNC
| AR8236_MIB_EN
,
823 (AR8216_MIB_FUNC_NO_OP
<< AR8216_MIB_FUNC_S
) |
828 ar8xxx_sw_set_vlan(struct switch_dev
*dev
, const struct switch_attr
*attr
,
829 struct switch_val
*val
)
831 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
832 priv
->vlan
= !!val
->value
.i
;
837 ar8xxx_sw_get_vlan(struct switch_dev
*dev
, const struct switch_attr
*attr
,
838 struct switch_val
*val
)
840 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
841 val
->value
.i
= priv
->vlan
;
847 ar8xxx_sw_set_pvid(struct switch_dev
*dev
, int port
, int vlan
)
849 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
851 /* make sure no invalid PVIDs get set */
853 if (vlan
>= dev
->vlans
)
856 priv
->pvid
[port
] = vlan
;
861 ar8xxx_sw_get_pvid(struct switch_dev
*dev
, int port
, int *vlan
)
863 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
864 *vlan
= priv
->pvid
[port
];
869 ar8xxx_sw_set_vid(struct switch_dev
*dev
, const struct switch_attr
*attr
,
870 struct switch_val
*val
)
872 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
873 priv
->vlan_id
[val
->port_vlan
] = val
->value
.i
;
878 ar8xxx_sw_get_vid(struct switch_dev
*dev
, const struct switch_attr
*attr
,
879 struct switch_val
*val
)
881 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
882 val
->value
.i
= priv
->vlan_id
[val
->port_vlan
];
887 ar8xxx_sw_get_port_link(struct switch_dev
*dev
, int port
,
888 struct switch_port_link
*link
)
890 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
892 ar8216_read_port_link(priv
, port
, link
);
897 ar8xxx_sw_get_ports(struct switch_dev
*dev
, struct switch_val
*val
)
899 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
900 u8 ports
= priv
->vlan_table
[val
->port_vlan
];
904 for (i
= 0; i
< dev
->ports
; i
++) {
905 struct switch_port
*p
;
907 if (!(ports
& (1 << i
)))
910 p
= &val
->value
.ports
[val
->len
++];
912 if (priv
->vlan_tagged
& (1 << i
))
913 p
->flags
= (1 << SWITCH_PORT_FLAG_TAGGED
);
921 ar8xxx_sw_set_ports(struct switch_dev
*dev
, struct switch_val
*val
)
923 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
924 u8
*vt
= &priv
->vlan_table
[val
->port_vlan
];
928 for (i
= 0; i
< val
->len
; i
++) {
929 struct switch_port
*p
= &val
->value
.ports
[i
];
931 if (p
->flags
& (1 << SWITCH_PORT_FLAG_TAGGED
)) {
932 priv
->vlan_tagged
|= (1 << p
->id
);
934 priv
->vlan_tagged
&= ~(1 << p
->id
);
935 priv
->pvid
[p
->id
] = val
->port_vlan
;
937 /* make sure that an untagged port does not
938 * appear in other vlans */
939 for (j
= 0; j
< AR8X16_MAX_VLANS
; j
++) {
940 if (j
== val
->port_vlan
)
942 priv
->vlan_table
[j
] &= ~(1 << p
->id
);
952 ar8216_set_mirror_regs(struct ar8xxx_priv
*priv
)
956 /* reset all mirror registers */
957 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CPUPORT
,
958 AR8216_GLOBAL_CPUPORT_MIRROR_PORT
,
959 (0xF << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S
));
960 for (port
= 0; port
< AR8216_NUM_PORTS
; port
++) {
961 ar8xxx_rmw(priv
, AR8216_REG_PORT_CTRL(port
),
962 AR8216_PORT_CTRL_MIRROR_RX
,
965 ar8xxx_rmw(priv
, AR8216_REG_PORT_CTRL(port
),
966 AR8216_PORT_CTRL_MIRROR_TX
,
970 /* now enable mirroring if necessary */
971 if (priv
->source_port
>= AR8216_NUM_PORTS
||
972 priv
->monitor_port
>= AR8216_NUM_PORTS
||
973 priv
->source_port
== priv
->monitor_port
) {
977 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CPUPORT
,
978 AR8216_GLOBAL_CPUPORT_MIRROR_PORT
,
979 (priv
->monitor_port
<< AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S
));
982 ar8xxx_rmw(priv
, AR8216_REG_PORT_CTRL(priv
->source_port
),
983 AR8216_PORT_CTRL_MIRROR_RX
,
984 AR8216_PORT_CTRL_MIRROR_RX
);
987 ar8xxx_rmw(priv
, AR8216_REG_PORT_CTRL(priv
->source_port
),
988 AR8216_PORT_CTRL_MIRROR_TX
,
989 AR8216_PORT_CTRL_MIRROR_TX
);
993 ar8xxx_sw_hw_apply(struct switch_dev
*dev
)
995 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
996 u8 portmask
[AR8X16_MAX_PORTS
];
999 mutex_lock(&priv
->reg_mutex
);
1000 /* flush all vlan translation unit entries */
1001 priv
->chip
->vtu_flush(priv
);
1003 memset(portmask
, 0, sizeof(portmask
));
1005 /* calculate the port destination masks and load vlans
1006 * into the vlan translation unit */
1007 for (j
= 0; j
< AR8X16_MAX_VLANS
; j
++) {
1008 u8 vp
= priv
->vlan_table
[j
];
1013 for (i
= 0; i
< dev
->ports
; i
++) {
1016 portmask
[i
] |= vp
& ~mask
;
1019 priv
->chip
->vtu_load_vlan(priv
, priv
->vlan_id
[j
],
1020 priv
->vlan_table
[j
]);
1024 * isolate all ports, but connect them to the cpu port */
1025 for (i
= 0; i
< dev
->ports
; i
++) {
1026 if (i
== AR8216_PORT_CPU
)
1029 portmask
[i
] = 1 << AR8216_PORT_CPU
;
1030 portmask
[AR8216_PORT_CPU
] |= (1 << i
);
1034 /* update the port destination mask registers and tag settings */
1035 for (i
= 0; i
< dev
->ports
; i
++) {
1036 priv
->chip
->setup_port(priv
, i
, portmask
[i
]);
1039 priv
->chip
->set_mirror_regs(priv
);
1041 mutex_unlock(&priv
->reg_mutex
);
1046 ar8xxx_sw_reset_switch(struct switch_dev
*dev
)
1048 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1051 mutex_lock(&priv
->reg_mutex
);
1052 memset(&priv
->vlan
, 0, sizeof(struct ar8xxx_priv
) -
1053 offsetof(struct ar8xxx_priv
, vlan
));
1055 for (i
= 0; i
< AR8X16_MAX_VLANS
; i
++)
1056 priv
->vlan_id
[i
] = i
;
1058 /* Configure all ports */
1059 for (i
= 0; i
< dev
->ports
; i
++)
1060 priv
->chip
->init_port(priv
, i
);
1062 priv
->mirror_rx
= false;
1063 priv
->mirror_tx
= false;
1064 priv
->source_port
= 0;
1065 priv
->monitor_port
= 0;
1067 priv
->chip
->init_globals(priv
);
1069 mutex_unlock(&priv
->reg_mutex
);
1071 return ar8xxx_sw_hw_apply(dev
);
1075 ar8xxx_sw_set_reset_mibs(struct switch_dev
*dev
,
1076 const struct switch_attr
*attr
,
1077 struct switch_val
*val
)
1079 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1083 if (!ar8xxx_has_mib_counters(priv
))
1086 mutex_lock(&priv
->mib_lock
);
1088 len
= priv
->dev
.ports
* priv
->chip
->num_mibs
*
1089 sizeof(*priv
->mib_stats
);
1090 memset(priv
->mib_stats
, '\0', len
);
1091 ret
= ar8xxx_mib_flush(priv
);
1098 mutex_unlock(&priv
->mib_lock
);
1103 ar8xxx_sw_set_mirror_rx_enable(struct switch_dev
*dev
,
1104 const struct switch_attr
*attr
,
1105 struct switch_val
*val
)
1107 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1109 mutex_lock(&priv
->reg_mutex
);
1110 priv
->mirror_rx
= !!val
->value
.i
;
1111 priv
->chip
->set_mirror_regs(priv
);
1112 mutex_unlock(&priv
->reg_mutex
);
1118 ar8xxx_sw_get_mirror_rx_enable(struct switch_dev
*dev
,
1119 const struct switch_attr
*attr
,
1120 struct switch_val
*val
)
1122 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1123 val
->value
.i
= priv
->mirror_rx
;
1128 ar8xxx_sw_set_mirror_tx_enable(struct switch_dev
*dev
,
1129 const struct switch_attr
*attr
,
1130 struct switch_val
*val
)
1132 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1134 mutex_lock(&priv
->reg_mutex
);
1135 priv
->mirror_tx
= !!val
->value
.i
;
1136 priv
->chip
->set_mirror_regs(priv
);
1137 mutex_unlock(&priv
->reg_mutex
);
1143 ar8xxx_sw_get_mirror_tx_enable(struct switch_dev
*dev
,
1144 const struct switch_attr
*attr
,
1145 struct switch_val
*val
)
1147 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1148 val
->value
.i
= priv
->mirror_tx
;
1153 ar8xxx_sw_set_mirror_monitor_port(struct switch_dev
*dev
,
1154 const struct switch_attr
*attr
,
1155 struct switch_val
*val
)
1157 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1159 mutex_lock(&priv
->reg_mutex
);
1160 priv
->monitor_port
= val
->value
.i
;
1161 priv
->chip
->set_mirror_regs(priv
);
1162 mutex_unlock(&priv
->reg_mutex
);
1168 ar8xxx_sw_get_mirror_monitor_port(struct switch_dev
*dev
,
1169 const struct switch_attr
*attr
,
1170 struct switch_val
*val
)
1172 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1173 val
->value
.i
= priv
->monitor_port
;
1178 ar8xxx_sw_set_mirror_source_port(struct switch_dev
*dev
,
1179 const struct switch_attr
*attr
,
1180 struct switch_val
*val
)
1182 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1184 mutex_lock(&priv
->reg_mutex
);
1185 priv
->source_port
= val
->value
.i
;
1186 priv
->chip
->set_mirror_regs(priv
);
1187 mutex_unlock(&priv
->reg_mutex
);
1193 ar8xxx_sw_get_mirror_source_port(struct switch_dev
*dev
,
1194 const struct switch_attr
*attr
,
1195 struct switch_val
*val
)
1197 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1198 val
->value
.i
= priv
->source_port
;
1203 ar8xxx_sw_set_port_reset_mib(struct switch_dev
*dev
,
1204 const struct switch_attr
*attr
,
1205 struct switch_val
*val
)
1207 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1211 if (!ar8xxx_has_mib_counters(priv
))
1214 port
= val
->port_vlan
;
1215 if (port
>= dev
->ports
)
1218 mutex_lock(&priv
->mib_lock
);
1219 ret
= ar8xxx_mib_capture(priv
);
1223 ar8xxx_mib_fetch_port_stat(priv
, port
, true);
1228 mutex_unlock(&priv
->mib_lock
);
1233 ar8xxx_sw_get_port_mib(struct switch_dev
*dev
,
1234 const struct switch_attr
*attr
,
1235 struct switch_val
*val
)
1237 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1238 const struct ar8xxx_chip
*chip
= priv
->chip
;
1242 char *buf
= priv
->buf
;
1245 if (!ar8xxx_has_mib_counters(priv
))
1248 port
= val
->port_vlan
;
1249 if (port
>= dev
->ports
)
1252 mutex_lock(&priv
->mib_lock
);
1253 ret
= ar8xxx_mib_capture(priv
);
1257 ar8xxx_mib_fetch_port_stat(priv
, port
, false);
1259 len
+= snprintf(buf
+ len
, sizeof(priv
->buf
) - len
,
1260 "Port %d MIB counters\n",
1263 mib_stats
= &priv
->mib_stats
[port
* chip
->num_mibs
];
1264 for (i
= 0; i
< chip
->num_mibs
; i
++)
1265 len
+= snprintf(buf
+ len
, sizeof(priv
->buf
) - len
,
1267 chip
->mib_decs
[i
].name
,
1276 mutex_unlock(&priv
->mib_lock
);
1280 static struct switch_attr ar8xxx_sw_attr_globals
[] = {
1282 .type
= SWITCH_TYPE_INT
,
1283 .name
= "enable_vlan",
1284 .description
= "Enable VLAN mode",
1285 .set
= ar8xxx_sw_set_vlan
,
1286 .get
= ar8xxx_sw_get_vlan
,
1290 .type
= SWITCH_TYPE_NOVAL
,
1291 .name
= "reset_mibs",
1292 .description
= "Reset all MIB counters",
1293 .set
= ar8xxx_sw_set_reset_mibs
,
1296 .type
= SWITCH_TYPE_INT
,
1297 .name
= "enable_mirror_rx",
1298 .description
= "Enable mirroring of RX packets",
1299 .set
= ar8xxx_sw_set_mirror_rx_enable
,
1300 .get
= ar8xxx_sw_get_mirror_rx_enable
,
1304 .type
= SWITCH_TYPE_INT
,
1305 .name
= "enable_mirror_tx",
1306 .description
= "Enable mirroring of TX packets",
1307 .set
= ar8xxx_sw_set_mirror_tx_enable
,
1308 .get
= ar8xxx_sw_get_mirror_tx_enable
,
1312 .type
= SWITCH_TYPE_INT
,
1313 .name
= "mirror_monitor_port",
1314 .description
= "Mirror monitor port",
1315 .set
= ar8xxx_sw_set_mirror_monitor_port
,
1316 .get
= ar8xxx_sw_get_mirror_monitor_port
,
1317 .max
= AR8216_NUM_PORTS
- 1
1320 .type
= SWITCH_TYPE_INT
,
1321 .name
= "mirror_source_port",
1322 .description
= "Mirror source port",
1323 .set
= ar8xxx_sw_set_mirror_source_port
,
1324 .get
= ar8xxx_sw_get_mirror_source_port
,
1325 .max
= AR8216_NUM_PORTS
- 1
1329 struct switch_attr ar8xxx_sw_attr_port
[2] = {
1331 .type
= SWITCH_TYPE_NOVAL
,
1332 .name
= "reset_mib",
1333 .description
= "Reset single port MIB counters",
1334 .set
= ar8xxx_sw_set_port_reset_mib
,
1337 .type
= SWITCH_TYPE_STRING
,
1339 .description
= "Get port's MIB counters",
1341 .get
= ar8xxx_sw_get_port_mib
,
1345 struct switch_attr ar8xxx_sw_attr_vlan
[1] = {
1347 .type
= SWITCH_TYPE_INT
,
1349 .description
= "VLAN ID (0-4094)",
1350 .set
= ar8xxx_sw_set_vid
,
1351 .get
= ar8xxx_sw_get_vid
,
1356 static const struct switch_dev_ops ar8xxx_sw_ops
= {
1358 .attr
= ar8xxx_sw_attr_globals
,
1359 .n_attr
= ARRAY_SIZE(ar8xxx_sw_attr_globals
),
1362 .attr
= ar8xxx_sw_attr_port
,
1363 .n_attr
= ARRAY_SIZE(ar8xxx_sw_attr_port
),
1366 .attr
= ar8xxx_sw_attr_vlan
,
1367 .n_attr
= ARRAY_SIZE(ar8xxx_sw_attr_vlan
),
1369 .get_port_pvid
= ar8xxx_sw_get_pvid
,
1370 .set_port_pvid
= ar8xxx_sw_set_pvid
,
1371 .get_vlan_ports
= ar8xxx_sw_get_ports
,
1372 .set_vlan_ports
= ar8xxx_sw_set_ports
,
1373 .apply_config
= ar8xxx_sw_hw_apply
,
1374 .reset_switch
= ar8xxx_sw_reset_switch
,
1375 .get_port_link
= ar8xxx_sw_get_port_link
,
1378 static const struct ar8xxx_chip ar8216_chip
= {
1379 .caps
= AR8XXX_CAP_MIB_COUNTERS
,
1381 .reg_port_stats_start
= 0x19000,
1382 .reg_port_stats_length
= 0xa0,
1384 .name
= "Atheros AR8216",
1385 .ports
= AR8216_NUM_PORTS
,
1386 .vlans
= AR8216_NUM_VLANS
,
1387 .swops
= &ar8xxx_sw_ops
,
1389 .hw_init
= ar8216_hw_init
,
1390 .init_globals
= ar8216_init_globals
,
1391 .init_port
= ar8216_init_port
,
1392 .setup_port
= ar8216_setup_port
,
1393 .read_port_status
= ar8216_read_port_status
,
1394 .atu_flush
= ar8216_atu_flush
,
1395 .vtu_flush
= ar8216_vtu_flush
,
1396 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
1397 .set_mirror_regs
= ar8216_set_mirror_regs
,
1399 .num_mibs
= ARRAY_SIZE(ar8216_mibs
),
1400 .mib_decs
= ar8216_mibs
,
1401 .mib_func
= AR8216_REG_MIB_FUNC
1404 static const struct ar8xxx_chip ar8236_chip
= {
1405 .caps
= AR8XXX_CAP_MIB_COUNTERS
,
1407 .reg_port_stats_start
= 0x20000,
1408 .reg_port_stats_length
= 0x100,
1410 .name
= "Atheros AR8236",
1411 .ports
= AR8216_NUM_PORTS
,
1412 .vlans
= AR8216_NUM_VLANS
,
1413 .swops
= &ar8xxx_sw_ops
,
1415 .hw_init
= ar8216_hw_init
,
1416 .init_globals
= ar8236_init_globals
,
1417 .init_port
= ar8216_init_port
,
1418 .setup_port
= ar8236_setup_port
,
1419 .read_port_status
= ar8216_read_port_status
,
1420 .atu_flush
= ar8216_atu_flush
,
1421 .vtu_flush
= ar8216_vtu_flush
,
1422 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
1423 .set_mirror_regs
= ar8216_set_mirror_regs
,
1425 .num_mibs
= ARRAY_SIZE(ar8236_mibs
),
1426 .mib_decs
= ar8236_mibs
,
1427 .mib_func
= AR8216_REG_MIB_FUNC
1430 static const struct ar8xxx_chip ar8316_chip
= {
1431 .caps
= AR8XXX_CAP_GIGE
| AR8XXX_CAP_MIB_COUNTERS
,
1433 .reg_port_stats_start
= 0x20000,
1434 .reg_port_stats_length
= 0x100,
1436 .name
= "Atheros AR8316",
1437 .ports
= AR8216_NUM_PORTS
,
1438 .vlans
= AR8X16_MAX_VLANS
,
1439 .swops
= &ar8xxx_sw_ops
,
1441 .hw_init
= ar8316_hw_init
,
1442 .init_globals
= ar8316_init_globals
,
1443 .init_port
= ar8216_init_port
,
1444 .setup_port
= ar8216_setup_port
,
1445 .read_port_status
= ar8216_read_port_status
,
1446 .atu_flush
= ar8216_atu_flush
,
1447 .vtu_flush
= ar8216_vtu_flush
,
1448 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
1449 .set_mirror_regs
= ar8216_set_mirror_regs
,
1451 .num_mibs
= ARRAY_SIZE(ar8236_mibs
),
1452 .mib_decs
= ar8236_mibs
,
1453 .mib_func
= AR8216_REG_MIB_FUNC
1457 ar8xxx_id_chip(struct ar8xxx_priv
*priv
)
1463 val
= ar8xxx_read(priv
, AR8216_REG_CTRL
);
1467 id
= val
& (AR8216_CTRL_REVISION
| AR8216_CTRL_VERSION
);
1468 for (i
= 0; i
< AR8X16_PROBE_RETRIES
; i
++) {
1471 val
= ar8xxx_read(priv
, AR8216_REG_CTRL
);
1475 t
= val
& (AR8216_CTRL_REVISION
| AR8216_CTRL_VERSION
);
1480 priv
->chip_ver
= (id
& AR8216_CTRL_VERSION
) >> AR8216_CTRL_VERSION_S
;
1481 priv
->chip_rev
= (id
& AR8216_CTRL_REVISION
);
1483 switch (priv
->chip_ver
) {
1484 case AR8XXX_VER_AR8216
:
1485 priv
->chip
= &ar8216_chip
;
1487 case AR8XXX_VER_AR8236
:
1488 priv
->chip
= &ar8236_chip
;
1490 case AR8XXX_VER_AR8316
:
1491 priv
->chip
= &ar8316_chip
;
1493 case AR8XXX_VER_AR8327
:
1494 priv
->chip
= &ar8327_chip
;
1496 case AR8XXX_VER_AR8337
:
1497 priv
->chip
= &ar8337_chip
;
1500 pr_err("ar8216: Unknown Atheros device [ver=%d, rev=%d]\n",
1501 priv
->chip_ver
, priv
->chip_rev
);
1510 ar8xxx_mib_work_func(struct work_struct
*work
)
1512 struct ar8xxx_priv
*priv
;
1515 priv
= container_of(work
, struct ar8xxx_priv
, mib_work
.work
);
1517 mutex_lock(&priv
->mib_lock
);
1519 err
= ar8xxx_mib_capture(priv
);
1523 ar8xxx_mib_fetch_port_stat(priv
, priv
->mib_next_port
, false);
1526 priv
->mib_next_port
++;
1527 if (priv
->mib_next_port
>= priv
->dev
.ports
)
1528 priv
->mib_next_port
= 0;
1530 mutex_unlock(&priv
->mib_lock
);
1531 schedule_delayed_work(&priv
->mib_work
,
1532 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY
));
1536 ar8xxx_mib_init(struct ar8xxx_priv
*priv
)
1540 if (!ar8xxx_has_mib_counters(priv
))
1543 BUG_ON(!priv
->chip
->mib_decs
|| !priv
->chip
->num_mibs
);
1545 len
= priv
->dev
.ports
* priv
->chip
->num_mibs
*
1546 sizeof(*priv
->mib_stats
);
1547 priv
->mib_stats
= kzalloc(len
, GFP_KERNEL
);
1549 if (!priv
->mib_stats
)
1556 ar8xxx_mib_start(struct ar8xxx_priv
*priv
)
1558 if (!ar8xxx_has_mib_counters(priv
))
1561 schedule_delayed_work(&priv
->mib_work
,
1562 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY
));
1566 ar8xxx_mib_stop(struct ar8xxx_priv
*priv
)
1568 if (!ar8xxx_has_mib_counters(priv
))
1571 cancel_delayed_work(&priv
->mib_work
);
1574 static struct ar8xxx_priv
*
1577 struct ar8xxx_priv
*priv
;
1579 priv
= kzalloc(sizeof(struct ar8xxx_priv
), GFP_KERNEL
);
1583 mutex_init(&priv
->reg_mutex
);
1584 mutex_init(&priv
->mib_lock
);
1585 INIT_DELAYED_WORK(&priv
->mib_work
, ar8xxx_mib_work_func
);
1591 ar8xxx_free(struct ar8xxx_priv
*priv
)
1593 if (priv
->chip
&& priv
->chip
->cleanup
)
1594 priv
->chip
->cleanup(priv
);
1596 kfree(priv
->chip_data
);
1597 kfree(priv
->mib_stats
);
1602 ar8xxx_probe_switch(struct ar8xxx_priv
*priv
)
1604 const struct ar8xxx_chip
*chip
;
1605 struct switch_dev
*swdev
;
1608 ret
= ar8xxx_id_chip(priv
);
1615 swdev
->cpu_port
= AR8216_PORT_CPU
;
1616 swdev
->name
= chip
->name
;
1617 swdev
->vlans
= chip
->vlans
;
1618 swdev
->ports
= chip
->ports
;
1619 swdev
->ops
= chip
->swops
;
1621 ret
= ar8xxx_mib_init(priv
);
1629 ar8xxx_start(struct ar8xxx_priv
*priv
)
1635 ret
= priv
->chip
->hw_init(priv
);
1639 ret
= ar8xxx_sw_reset_switch(&priv
->dev
);
1645 ar8xxx_mib_start(priv
);
1651 ar8xxx_phy_config_init(struct phy_device
*phydev
)
1653 struct ar8xxx_priv
*priv
= phydev
->priv
;
1654 struct net_device
*dev
= phydev
->attached_dev
;
1660 if (priv
->chip
->config_at_probe
)
1661 return ar8xxx_phy_check_aneg(phydev
);
1665 if (phydev
->addr
!= 0) {
1666 if (chip_is_ar8316(priv
)) {
1667 /* switch device has been initialized, reinit */
1668 priv
->dev
.ports
= (AR8216_NUM_PORTS
- 1);
1669 priv
->initialized
= false;
1670 priv
->port4_phy
= true;
1671 ar8316_hw_init(priv
);
1678 ret
= ar8xxx_start(priv
);
1682 /* VID fixup only needed on ar8216 */
1683 if (chip_is_ar8216(priv
)) {
1684 dev
->phy_ptr
= priv
;
1685 dev
->priv_flags
|= IFF_NO_IP_ALIGN
;
1686 dev
->eth_mangle_rx
= ar8216_mangle_rx
;
1687 dev
->eth_mangle_tx
= ar8216_mangle_tx
;
1694 ar8xxx_phy_read_status(struct phy_device
*phydev
)
1696 struct ar8xxx_priv
*priv
= phydev
->priv
;
1697 struct switch_port_link link
;
1700 if (phydev
->addr
!= 0)
1701 return genphy_read_status(phydev
);
1703 ar8216_read_port_link(priv
, phydev
->addr
, &link
);
1704 phydev
->link
= !!link
.link
;
1708 switch (link
.speed
) {
1709 case SWITCH_PORT_SPEED_10
:
1710 phydev
->speed
= SPEED_10
;
1712 case SWITCH_PORT_SPEED_100
:
1713 phydev
->speed
= SPEED_100
;
1715 case SWITCH_PORT_SPEED_1000
:
1716 phydev
->speed
= SPEED_1000
;
1721 phydev
->duplex
= link
.duplex
? DUPLEX_FULL
: DUPLEX_HALF
;
1723 /* flush the address translation unit */
1724 mutex_lock(&priv
->reg_mutex
);
1725 ret
= priv
->chip
->atu_flush(priv
);
1726 mutex_unlock(&priv
->reg_mutex
);
1728 phydev
->state
= PHY_RUNNING
;
1729 netif_carrier_on(phydev
->attached_dev
);
1730 phydev
->adjust_link(phydev
->attached_dev
);
1736 ar8xxx_phy_config_aneg(struct phy_device
*phydev
)
1738 if (phydev
->addr
== 0)
1741 return genphy_config_aneg(phydev
);
1744 static const u32 ar8xxx_phy_ids
[] = {
1746 0x004dd034, /* AR8327 */
1747 0x004dd036, /* AR8337 */
1750 0x004dd043, /* AR8236 */
1754 ar8xxx_phy_match(u32 phy_id
)
1758 for (i
= 0; i
< ARRAY_SIZE(ar8xxx_phy_ids
); i
++)
1759 if (phy_id
== ar8xxx_phy_ids
[i
])
1766 ar8xxx_is_possible(struct mii_bus
*bus
)
1770 for (i
= 0; i
< 4; i
++) {
1773 phy_id
= mdiobus_read(bus
, i
, MII_PHYSID1
) << 16;
1774 phy_id
|= mdiobus_read(bus
, i
, MII_PHYSID2
);
1775 if (!ar8xxx_phy_match(phy_id
)) {
1776 pr_debug("ar8xxx: unknown PHY at %s:%02x id:%08x\n",
1777 dev_name(&bus
->dev
), i
, phy_id
);
1786 ar8xxx_phy_probe(struct phy_device
*phydev
)
1788 struct ar8xxx_priv
*priv
;
1789 struct switch_dev
*swdev
;
1792 /* skip PHYs at unused adresses */
1793 if (phydev
->addr
!= 0 && phydev
->addr
!= 4)
1796 if (!ar8xxx_is_possible(phydev
->bus
))
1799 mutex_lock(&ar8xxx_dev_list_lock
);
1800 list_for_each_entry(priv
, &ar8xxx_dev_list
, list
)
1801 if (priv
->mii_bus
== phydev
->bus
)
1804 priv
= ar8xxx_create();
1810 priv
->mii_bus
= phydev
->bus
;
1812 ret
= ar8xxx_probe_switch(priv
);
1817 swdev
->alias
= dev_name(&priv
->mii_bus
->dev
);
1818 ret
= register_switch(swdev
, NULL
);
1822 pr_info("%s: %s rev. %u switch registered on %s\n",
1823 swdev
->devname
, swdev
->name
, priv
->chip_rev
,
1824 dev_name(&priv
->mii_bus
->dev
));
1829 if (phydev
->addr
== 0) {
1830 if (ar8xxx_has_gige(priv
)) {
1831 phydev
->supported
= SUPPORTED_1000baseT_Full
;
1832 phydev
->advertising
= ADVERTISED_1000baseT_Full
;
1834 phydev
->supported
= SUPPORTED_100baseT_Full
;
1835 phydev
->advertising
= ADVERTISED_100baseT_Full
;
1838 if (priv
->chip
->config_at_probe
) {
1841 ret
= ar8xxx_start(priv
);
1843 goto err_unregister_switch
;
1846 if (ar8xxx_has_gige(priv
)) {
1847 phydev
->supported
|= SUPPORTED_1000baseT_Full
;
1848 phydev
->advertising
|= ADVERTISED_1000baseT_Full
;
1852 phydev
->priv
= priv
;
1854 list_add(&priv
->list
, &ar8xxx_dev_list
);
1856 mutex_unlock(&ar8xxx_dev_list_lock
);
1860 err_unregister_switch
:
1861 if (--priv
->use_count
)
1864 unregister_switch(&priv
->dev
);
1869 mutex_unlock(&ar8xxx_dev_list_lock
);
1874 ar8xxx_phy_detach(struct phy_device
*phydev
)
1876 struct net_device
*dev
= phydev
->attached_dev
;
1881 dev
->phy_ptr
= NULL
;
1882 dev
->priv_flags
&= ~IFF_NO_IP_ALIGN
;
1883 dev
->eth_mangle_rx
= NULL
;
1884 dev
->eth_mangle_tx
= NULL
;
1888 ar8xxx_phy_remove(struct phy_device
*phydev
)
1890 struct ar8xxx_priv
*priv
= phydev
->priv
;
1895 phydev
->priv
= NULL
;
1896 if (--priv
->use_count
> 0)
1899 mutex_lock(&ar8xxx_dev_list_lock
);
1900 list_del(&priv
->list
);
1901 mutex_unlock(&ar8xxx_dev_list_lock
);
1903 unregister_switch(&priv
->dev
);
1904 ar8xxx_mib_stop(priv
);
1908 #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)
1910 ar8xxx_phy_soft_reset(struct phy_device
*phydev
)
1912 /* we don't need an extra reset */
1917 static struct phy_driver ar8xxx_phy_driver
= {
1918 .phy_id
= 0x004d0000,
1919 .name
= "Atheros AR8216/AR8236/AR8316",
1920 .phy_id_mask
= 0xffff0000,
1921 .features
= PHY_BASIC_FEATURES
,
1922 .probe
= ar8xxx_phy_probe
,
1923 .remove
= ar8xxx_phy_remove
,
1924 .detach
= ar8xxx_phy_detach
,
1925 .config_init
= ar8xxx_phy_config_init
,
1926 .config_aneg
= ar8xxx_phy_config_aneg
,
1927 .read_status
= ar8xxx_phy_read_status
,
1928 #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)
1929 .soft_reset
= ar8xxx_phy_soft_reset
,
1931 .driver
= { .owner
= THIS_MODULE
},
1937 return phy_driver_register(&ar8xxx_phy_driver
);
1943 phy_driver_unregister(&ar8xxx_phy_driver
);
1946 module_init(ar8xxx_init
);
1947 module_exit(ar8xxx_exit
);
1948 MODULE_LICENSE("GPL");