2 * ar8216.c: AR8216 switch driver
4 * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>
5 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/list.h>
22 #include <linux/if_ether.h>
23 #include <linux/skbuff.h>
24 #include <linux/netdevice.h>
25 #include <linux/netlink.h>
26 #include <linux/of_device.h>
27 #include <linux/bitops.h>
28 #include <net/genetlink.h>
29 #include <linux/switch.h>
30 #include <linux/delay.h>
31 #include <linux/phy.h>
32 #include <linux/etherdevice.h>
33 #include <linux/lockdep.h>
34 #include <linux/ar8216_platform.h>
35 #include <linux/workqueue.h>
36 #include <linux/version.h>
40 extern const struct ar8xxx_chip ar8327_chip
;
41 extern const struct ar8xxx_chip ar8337_chip
;
43 #define AR8XXX_MIB_WORK_DELAY 2000 /* msecs */
45 #define MIB_DESC(_s , _o, _n) \
52 static const struct ar8xxx_mib_desc ar8216_mibs
[] = {
53 MIB_DESC(1, AR8216_STATS_RXBROAD
, "RxBroad"),
54 MIB_DESC(1, AR8216_STATS_RXPAUSE
, "RxPause"),
55 MIB_DESC(1, AR8216_STATS_RXMULTI
, "RxMulti"),
56 MIB_DESC(1, AR8216_STATS_RXFCSERR
, "RxFcsErr"),
57 MIB_DESC(1, AR8216_STATS_RXALIGNERR
, "RxAlignErr"),
58 MIB_DESC(1, AR8216_STATS_RXRUNT
, "RxRunt"),
59 MIB_DESC(1, AR8216_STATS_RXFRAGMENT
, "RxFragment"),
60 MIB_DESC(1, AR8216_STATS_RX64BYTE
, "Rx64Byte"),
61 MIB_DESC(1, AR8216_STATS_RX128BYTE
, "Rx128Byte"),
62 MIB_DESC(1, AR8216_STATS_RX256BYTE
, "Rx256Byte"),
63 MIB_DESC(1, AR8216_STATS_RX512BYTE
, "Rx512Byte"),
64 MIB_DESC(1, AR8216_STATS_RX1024BYTE
, "Rx1024Byte"),
65 MIB_DESC(1, AR8216_STATS_RXMAXBYTE
, "RxMaxByte"),
66 MIB_DESC(1, AR8216_STATS_RXTOOLONG
, "RxTooLong"),
67 MIB_DESC(2, AR8216_STATS_RXGOODBYTE
, "RxGoodByte"),
68 MIB_DESC(2, AR8216_STATS_RXBADBYTE
, "RxBadByte"),
69 MIB_DESC(1, AR8216_STATS_RXOVERFLOW
, "RxOverFlow"),
70 MIB_DESC(1, AR8216_STATS_FILTERED
, "Filtered"),
71 MIB_DESC(1, AR8216_STATS_TXBROAD
, "TxBroad"),
72 MIB_DESC(1, AR8216_STATS_TXPAUSE
, "TxPause"),
73 MIB_DESC(1, AR8216_STATS_TXMULTI
, "TxMulti"),
74 MIB_DESC(1, AR8216_STATS_TXUNDERRUN
, "TxUnderRun"),
75 MIB_DESC(1, AR8216_STATS_TX64BYTE
, "Tx64Byte"),
76 MIB_DESC(1, AR8216_STATS_TX128BYTE
, "Tx128Byte"),
77 MIB_DESC(1, AR8216_STATS_TX256BYTE
, "Tx256Byte"),
78 MIB_DESC(1, AR8216_STATS_TX512BYTE
, "Tx512Byte"),
79 MIB_DESC(1, AR8216_STATS_TX1024BYTE
, "Tx1024Byte"),
80 MIB_DESC(1, AR8216_STATS_TXMAXBYTE
, "TxMaxByte"),
81 MIB_DESC(1, AR8216_STATS_TXOVERSIZE
, "TxOverSize"),
82 MIB_DESC(2, AR8216_STATS_TXBYTE
, "TxByte"),
83 MIB_DESC(1, AR8216_STATS_TXCOLLISION
, "TxCollision"),
84 MIB_DESC(1, AR8216_STATS_TXABORTCOL
, "TxAbortCol"),
85 MIB_DESC(1, AR8216_STATS_TXMULTICOL
, "TxMultiCol"),
86 MIB_DESC(1, AR8216_STATS_TXSINGLECOL
, "TxSingleCol"),
87 MIB_DESC(1, AR8216_STATS_TXEXCDEFER
, "TxExcDefer"),
88 MIB_DESC(1, AR8216_STATS_TXDEFER
, "TxDefer"),
89 MIB_DESC(1, AR8216_STATS_TXLATECOL
, "TxLateCol"),
92 const struct ar8xxx_mib_desc ar8236_mibs
[39] = {
93 MIB_DESC(1, AR8236_STATS_RXBROAD
, "RxBroad"),
94 MIB_DESC(1, AR8236_STATS_RXPAUSE
, "RxPause"),
95 MIB_DESC(1, AR8236_STATS_RXMULTI
, "RxMulti"),
96 MIB_DESC(1, AR8236_STATS_RXFCSERR
, "RxFcsErr"),
97 MIB_DESC(1, AR8236_STATS_RXALIGNERR
, "RxAlignErr"),
98 MIB_DESC(1, AR8236_STATS_RXRUNT
, "RxRunt"),
99 MIB_DESC(1, AR8236_STATS_RXFRAGMENT
, "RxFragment"),
100 MIB_DESC(1, AR8236_STATS_RX64BYTE
, "Rx64Byte"),
101 MIB_DESC(1, AR8236_STATS_RX128BYTE
, "Rx128Byte"),
102 MIB_DESC(1, AR8236_STATS_RX256BYTE
, "Rx256Byte"),
103 MIB_DESC(1, AR8236_STATS_RX512BYTE
, "Rx512Byte"),
104 MIB_DESC(1, AR8236_STATS_RX1024BYTE
, "Rx1024Byte"),
105 MIB_DESC(1, AR8236_STATS_RX1518BYTE
, "Rx1518Byte"),
106 MIB_DESC(1, AR8236_STATS_RXMAXBYTE
, "RxMaxByte"),
107 MIB_DESC(1, AR8236_STATS_RXTOOLONG
, "RxTooLong"),
108 MIB_DESC(2, AR8236_STATS_RXGOODBYTE
, "RxGoodByte"),
109 MIB_DESC(2, AR8236_STATS_RXBADBYTE
, "RxBadByte"),
110 MIB_DESC(1, AR8236_STATS_RXOVERFLOW
, "RxOverFlow"),
111 MIB_DESC(1, AR8236_STATS_FILTERED
, "Filtered"),
112 MIB_DESC(1, AR8236_STATS_TXBROAD
, "TxBroad"),
113 MIB_DESC(1, AR8236_STATS_TXPAUSE
, "TxPause"),
114 MIB_DESC(1, AR8236_STATS_TXMULTI
, "TxMulti"),
115 MIB_DESC(1, AR8236_STATS_TXUNDERRUN
, "TxUnderRun"),
116 MIB_DESC(1, AR8236_STATS_TX64BYTE
, "Tx64Byte"),
117 MIB_DESC(1, AR8236_STATS_TX128BYTE
, "Tx128Byte"),
118 MIB_DESC(1, AR8236_STATS_TX256BYTE
, "Tx256Byte"),
119 MIB_DESC(1, AR8236_STATS_TX512BYTE
, "Tx512Byte"),
120 MIB_DESC(1, AR8236_STATS_TX1024BYTE
, "Tx1024Byte"),
121 MIB_DESC(1, AR8236_STATS_TX1518BYTE
, "Tx1518Byte"),
122 MIB_DESC(1, AR8236_STATS_TXMAXBYTE
, "TxMaxByte"),
123 MIB_DESC(1, AR8236_STATS_TXOVERSIZE
, "TxOverSize"),
124 MIB_DESC(2, AR8236_STATS_TXBYTE
, "TxByte"),
125 MIB_DESC(1, AR8236_STATS_TXCOLLISION
, "TxCollision"),
126 MIB_DESC(1, AR8236_STATS_TXABORTCOL
, "TxAbortCol"),
127 MIB_DESC(1, AR8236_STATS_TXMULTICOL
, "TxMultiCol"),
128 MIB_DESC(1, AR8236_STATS_TXSINGLECOL
, "TxSingleCol"),
129 MIB_DESC(1, AR8236_STATS_TXEXCDEFER
, "TxExcDefer"),
130 MIB_DESC(1, AR8236_STATS_TXDEFER
, "TxDefer"),
131 MIB_DESC(1, AR8236_STATS_TXLATECOL
, "TxLateCol"),
134 static DEFINE_MUTEX(ar8xxx_dev_list_lock
);
135 static LIST_HEAD(ar8xxx_dev_list
);
137 /* inspired by phy_poll_reset in drivers/net/phy/phy_device.c */
139 ar8xxx_phy_poll_reset(struct mii_bus
*bus
)
141 unsigned int sleep_msecs
= 20;
144 for (elapsed
= sleep_msecs
; elapsed
<= 600;
145 elapsed
+= sleep_msecs
) {
147 for (i
= 0; i
< AR8XXX_NUM_PHYS
; i
++) {
148 ret
= mdiobus_read(bus
, i
, MII_BMCR
);
151 if (ret
& BMCR_RESET
)
153 if (i
== AR8XXX_NUM_PHYS
- 1) {
154 usleep_range(1000, 2000);
163 ar8xxx_phy_check_aneg(struct phy_device
*phydev
)
167 if (phydev
->autoneg
!= AUTONEG_ENABLE
)
170 * BMCR_ANENABLE might have been cleared
171 * by phy_init_hw in certain kernel versions
172 * therefore check for it
174 ret
= phy_read(phydev
, MII_BMCR
);
177 if (ret
& BMCR_ANENABLE
)
180 dev_info(&phydev
->mdio
.dev
, "ANEG disabled, re-enabling ...\n");
181 ret
|= BMCR_ANENABLE
| BMCR_ANRESTART
;
182 return phy_write(phydev
, MII_BMCR
, ret
);
186 ar8xxx_phy_init(struct ar8xxx_priv
*priv
)
192 for (i
= 0; i
< AR8XXX_NUM_PHYS
; i
++) {
193 if (priv
->chip
->phy_fixup
)
194 priv
->chip
->phy_fixup(priv
, i
);
196 /* initialize the port itself */
197 mdiobus_write(bus
, i
, MII_ADVERTISE
,
198 ADVERTISE_ALL
| ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
);
199 if (ar8xxx_has_gige(priv
))
200 mdiobus_write(bus
, i
, MII_CTRL1000
, ADVERTISE_1000FULL
);
201 mdiobus_write(bus
, i
, MII_BMCR
, BMCR_RESET
| BMCR_ANENABLE
);
204 ar8xxx_phy_poll_reset(bus
);
208 ar8xxx_mii_read32(struct ar8xxx_priv
*priv
, int phy_id
, int regnum
)
210 struct mii_bus
*bus
= priv
->mii_bus
;
213 lo
= bus
->read(bus
, phy_id
, regnum
);
214 hi
= bus
->read(bus
, phy_id
, regnum
+ 1);
216 return (hi
<< 16) | lo
;
220 ar8xxx_mii_write32(struct ar8xxx_priv
*priv
, int phy_id
, int regnum
, u32 val
)
222 struct mii_bus
*bus
= priv
->mii_bus
;
226 hi
= (u16
) (val
>> 16);
228 if (priv
->chip
->mii_lo_first
)
230 bus
->write(bus
, phy_id
, regnum
, lo
);
231 bus
->write(bus
, phy_id
, regnum
+ 1, hi
);
233 bus
->write(bus
, phy_id
, regnum
+ 1, hi
);
234 bus
->write(bus
, phy_id
, regnum
, lo
);
239 ar8xxx_read(struct ar8xxx_priv
*priv
, int reg
)
241 struct mii_bus
*bus
= priv
->mii_bus
;
245 split_addr((u32
) reg
, &r1
, &r2
, &page
);
247 mutex_lock(&bus
->mdio_lock
);
249 bus
->write(bus
, 0x18, 0, page
);
250 wait_for_page_switch();
251 val
= ar8xxx_mii_read32(priv
, 0x10 | r2
, r1
);
253 mutex_unlock(&bus
->mdio_lock
);
259 ar8xxx_write(struct ar8xxx_priv
*priv
, int reg
, u32 val
)
261 struct mii_bus
*bus
= priv
->mii_bus
;
264 split_addr((u32
) reg
, &r1
, &r2
, &page
);
266 mutex_lock(&bus
->mdio_lock
);
268 bus
->write(bus
, 0x18, 0, page
);
269 wait_for_page_switch();
270 ar8xxx_mii_write32(priv
, 0x10 | r2
, r1
, val
);
272 mutex_unlock(&bus
->mdio_lock
);
276 ar8xxx_rmw(struct ar8xxx_priv
*priv
, int reg
, u32 mask
, u32 val
)
278 struct mii_bus
*bus
= priv
->mii_bus
;
282 split_addr((u32
) reg
, &r1
, &r2
, &page
);
284 mutex_lock(&bus
->mdio_lock
);
286 bus
->write(bus
, 0x18, 0, page
);
287 wait_for_page_switch();
289 ret
= ar8xxx_mii_read32(priv
, 0x10 | r2
, r1
);
292 ar8xxx_mii_write32(priv
, 0x10 | r2
, r1
, ret
);
294 mutex_unlock(&bus
->mdio_lock
);
299 ar8xxx_phy_dbg_read(struct ar8xxx_priv
*priv
, int phy_addr
,
300 u16 dbg_addr
, u16
*dbg_data
)
302 struct mii_bus
*bus
= priv
->mii_bus
;
304 mutex_lock(&bus
->mdio_lock
);
305 bus
->write(bus
, phy_addr
, MII_ATH_DBG_ADDR
, dbg_addr
);
306 *dbg_data
= bus
->read(bus
, phy_addr
, MII_ATH_DBG_DATA
);
307 mutex_unlock(&bus
->mdio_lock
);
311 ar8xxx_phy_dbg_write(struct ar8xxx_priv
*priv
, int phy_addr
,
312 u16 dbg_addr
, u16 dbg_data
)
314 struct mii_bus
*bus
= priv
->mii_bus
;
316 mutex_lock(&bus
->mdio_lock
);
317 bus
->write(bus
, phy_addr
, MII_ATH_DBG_ADDR
, dbg_addr
);
318 bus
->write(bus
, phy_addr
, MII_ATH_DBG_DATA
, dbg_data
);
319 mutex_unlock(&bus
->mdio_lock
);
323 ar8xxx_phy_mmd_prep(struct mii_bus
*bus
, int phy_addr
, u16 addr
, u16 reg
)
325 bus
->write(bus
, phy_addr
, MII_ATH_MMD_ADDR
, addr
);
326 bus
->write(bus
, phy_addr
, MII_ATH_MMD_DATA
, reg
);
327 bus
->write(bus
, phy_addr
, MII_ATH_MMD_ADDR
, addr
| 0x4000);
331 ar8xxx_phy_mmd_write(struct ar8xxx_priv
*priv
, int phy_addr
, u16 addr
, u16 reg
, u16 data
)
333 struct mii_bus
*bus
= priv
->mii_bus
;
335 mutex_lock(&bus
->mdio_lock
);
336 ar8xxx_phy_mmd_prep(bus
, phy_addr
, addr
, reg
);
337 bus
->write(bus
, phy_addr
, MII_ATH_MMD_DATA
, data
);
338 mutex_unlock(&bus
->mdio_lock
);
342 ar8xxx_phy_mmd_read(struct ar8xxx_priv
*priv
, int phy_addr
, u16 addr
, u16 reg
)
344 struct mii_bus
*bus
= priv
->mii_bus
;
347 mutex_lock(&bus
->mdio_lock
);
348 ar8xxx_phy_mmd_prep(bus
, phy_addr
, addr
, reg
);
349 data
= bus
->read(bus
, phy_addr
, MII_ATH_MMD_DATA
);
350 mutex_unlock(&bus
->mdio_lock
);
356 ar8xxx_reg_wait(struct ar8xxx_priv
*priv
, u32 reg
, u32 mask
, u32 val
,
361 for (i
= 0; i
< timeout
; i
++) {
364 t
= ar8xxx_read(priv
, reg
);
365 if ((t
& mask
) == val
)
368 usleep_range(1000, 2000);
376 ar8xxx_mib_op(struct ar8xxx_priv
*priv
, u32 op
)
378 unsigned mib_func
= priv
->chip
->mib_func
;
381 lockdep_assert_held(&priv
->mib_lock
);
383 /* Capture the hardware statistics for all ports */
384 ar8xxx_rmw(priv
, mib_func
, AR8216_MIB_FUNC
, (op
<< AR8216_MIB_FUNC_S
));
386 /* Wait for the capturing to complete. */
387 ret
= ar8xxx_reg_wait(priv
, mib_func
, AR8216_MIB_BUSY
, 0, 10);
398 ar8xxx_mib_capture(struct ar8xxx_priv
*priv
)
400 return ar8xxx_mib_op(priv
, AR8216_MIB_FUNC_CAPTURE
);
404 ar8xxx_mib_flush(struct ar8xxx_priv
*priv
)
406 return ar8xxx_mib_op(priv
, AR8216_MIB_FUNC_FLUSH
);
410 ar8xxx_mib_fetch_port_stat(struct ar8xxx_priv
*priv
, int port
, bool flush
)
416 WARN_ON(port
>= priv
->dev
.ports
);
418 lockdep_assert_held(&priv
->mib_lock
);
420 base
= priv
->chip
->reg_port_stats_start
+
421 priv
->chip
->reg_port_stats_length
* port
;
423 mib_stats
= &priv
->mib_stats
[port
* priv
->chip
->num_mibs
];
424 for (i
= 0; i
< priv
->chip
->num_mibs
; i
++) {
425 const struct ar8xxx_mib_desc
*mib
;
428 mib
= &priv
->chip
->mib_decs
[i
];
429 t
= ar8xxx_read(priv
, base
+ mib
->offset
);
430 if (mib
->size
== 2) {
433 hi
= ar8xxx_read(priv
, base
+ mib
->offset
+ 4);
446 ar8216_read_port_link(struct ar8xxx_priv
*priv
, int port
,
447 struct switch_port_link
*link
)
452 memset(link
, '\0', sizeof(*link
));
454 status
= priv
->chip
->read_port_status(priv
, port
);
456 link
->aneg
= !!(status
& AR8216_PORT_STATUS_LINK_AUTO
);
458 link
->link
= !!(status
& AR8216_PORT_STATUS_LINK_UP
);
462 if (priv
->get_port_link
) {
465 err
= priv
->get_port_link(port
);
474 link
->duplex
= !!(status
& AR8216_PORT_STATUS_DUPLEX
);
475 link
->tx_flow
= !!(status
& AR8216_PORT_STATUS_TXFLOW
);
476 link
->rx_flow
= !!(status
& AR8216_PORT_STATUS_RXFLOW
);
478 if (link
->aneg
&& link
->duplex
&& priv
->chip
->read_port_eee_status
)
479 link
->eee
= priv
->chip
->read_port_eee_status(priv
, port
);
481 speed
= (status
& AR8216_PORT_STATUS_SPEED
) >>
482 AR8216_PORT_STATUS_SPEED_S
;
485 case AR8216_PORT_SPEED_10M
:
486 link
->speed
= SWITCH_PORT_SPEED_10
;
488 case AR8216_PORT_SPEED_100M
:
489 link
->speed
= SWITCH_PORT_SPEED_100
;
491 case AR8216_PORT_SPEED_1000M
:
492 link
->speed
= SWITCH_PORT_SPEED_1000
;
495 link
->speed
= SWITCH_PORT_SPEED_UNKNOWN
;
500 static struct sk_buff
*
501 ar8216_mangle_tx(struct net_device
*dev
, struct sk_buff
*skb
)
503 struct ar8xxx_priv
*priv
= dev
->phy_ptr
;
512 if (unlikely(skb_headroom(skb
) < 2)) {
513 if (pskb_expand_head(skb
, 2, 0, GFP_ATOMIC
) < 0)
517 buf
= skb_push(skb
, 2);
525 dev_kfree_skb_any(skb
);
530 ar8216_mangle_rx(struct net_device
*dev
, struct sk_buff
*skb
)
532 struct ar8xxx_priv
*priv
;
540 /* don't strip the header if vlan mode is disabled */
544 /* strip header, get vlan id */
548 /* check for vlan header presence */
549 if ((buf
[12 + 2] != 0x81) || (buf
[13 + 2] != 0x00))
554 /* no need to fix up packets coming from a tagged source */
555 if (priv
->vlan_tagged
& (1 << port
))
558 /* lookup port vid from local table, the switch passes an invalid vlan id */
559 vlan
= priv
->vlan_id
[priv
->pvid
[port
]];
562 buf
[14 + 2] |= vlan
>> 8;
563 buf
[15 + 2] = vlan
& 0xff;
567 ar8216_wait_bit(struct ar8xxx_priv
*priv
, int reg
, u32 mask
, u32 val
)
573 t
= ar8xxx_read(priv
, reg
);
574 if ((t
& mask
) == val
)
584 pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
585 (unsigned int) reg
, t
, mask
, val
);
590 ar8216_vtu_op(struct ar8xxx_priv
*priv
, u32 op
, u32 val
)
592 if (ar8216_wait_bit(priv
, AR8216_REG_VTU
, AR8216_VTU_ACTIVE
, 0))
594 if ((op
& AR8216_VTU_OP
) == AR8216_VTU_OP_LOAD
) {
595 val
&= AR8216_VTUDATA_MEMBER
;
596 val
|= AR8216_VTUDATA_VALID
;
597 ar8xxx_write(priv
, AR8216_REG_VTU_DATA
, val
);
599 op
|= AR8216_VTU_ACTIVE
;
600 ar8xxx_write(priv
, AR8216_REG_VTU
, op
);
604 ar8216_vtu_flush(struct ar8xxx_priv
*priv
)
606 ar8216_vtu_op(priv
, AR8216_VTU_OP_FLUSH
, 0);
610 ar8216_vtu_load_vlan(struct ar8xxx_priv
*priv
, u32 vid
, u32 port_mask
)
614 op
= AR8216_VTU_OP_LOAD
| (vid
<< AR8216_VTU_VID_S
);
615 ar8216_vtu_op(priv
, op
, port_mask
);
619 ar8216_atu_flush(struct ar8xxx_priv
*priv
)
623 ret
= ar8216_wait_bit(priv
, AR8216_REG_ATU_FUNC0
, AR8216_ATU_ACTIVE
, 0);
625 ar8xxx_write(priv
, AR8216_REG_ATU_FUNC0
, AR8216_ATU_OP_FLUSH
|
632 ar8216_atu_flush_port(struct ar8xxx_priv
*priv
, int port
)
637 ret
= ar8216_wait_bit(priv
, AR8216_REG_ATU_FUNC0
, AR8216_ATU_ACTIVE
, 0);
639 t
= (port
<< AR8216_ATU_PORT_NUM_S
) | AR8216_ATU_OP_FLUSH_PORT
;
640 t
|= AR8216_ATU_ACTIVE
;
641 ar8xxx_write(priv
, AR8216_REG_ATU_FUNC0
, t
);
648 ar8216_read_port_status(struct ar8xxx_priv
*priv
, int port
)
650 return ar8xxx_read(priv
, AR8216_REG_PORT_STATUS(port
));
654 ar8216_setup_port(struct ar8xxx_priv
*priv
, int port
, u32 members
)
661 pvid
= priv
->vlan_id
[priv
->pvid
[port
]];
662 if (priv
->vlan_tagged
& (1 << port
))
663 egress
= AR8216_OUT_ADD_VLAN
;
665 egress
= AR8216_OUT_STRIP_VLAN
;
666 ingress
= AR8216_IN_SECURE
;
669 egress
= AR8216_OUT_KEEP
;
670 ingress
= AR8216_IN_PORT_ONLY
;
673 if (chip_is_ar8216(priv
) && priv
->vlan
&& port
== AR8216_PORT_CPU
)
674 header
= AR8216_PORT_CTRL_HEADER
;
678 ar8xxx_rmw(priv
, AR8216_REG_PORT_CTRL(port
),
679 AR8216_PORT_CTRL_LEARN
| AR8216_PORT_CTRL_VLAN_MODE
|
680 AR8216_PORT_CTRL_SINGLE_VLAN
| AR8216_PORT_CTRL_STATE
|
681 AR8216_PORT_CTRL_HEADER
| AR8216_PORT_CTRL_LEARN_LOCK
,
682 AR8216_PORT_CTRL_LEARN
| header
|
683 (egress
<< AR8216_PORT_CTRL_VLAN_MODE_S
) |
684 (AR8216_PORT_STATE_FORWARD
<< AR8216_PORT_CTRL_STATE_S
));
686 ar8xxx_rmw(priv
, AR8216_REG_PORT_VLAN(port
),
687 AR8216_PORT_VLAN_DEST_PORTS
| AR8216_PORT_VLAN_MODE
|
688 AR8216_PORT_VLAN_DEFAULT_ID
,
689 (members
<< AR8216_PORT_VLAN_DEST_PORTS_S
) |
690 (ingress
<< AR8216_PORT_VLAN_MODE_S
) |
691 (pvid
<< AR8216_PORT_VLAN_DEFAULT_ID_S
));
695 ar8216_hw_init(struct ar8xxx_priv
*priv
)
697 if (priv
->initialized
)
700 ar8xxx_phy_init(priv
);
702 priv
->initialized
= true;
707 ar8216_init_globals(struct ar8xxx_priv
*priv
)
709 /* standard atheros magic */
710 ar8xxx_write(priv
, 0x38, 0xc000050e);
712 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
713 AR8216_GCTRL_MTU
, 1518 + 8 + 2);
717 ar8216_init_port(struct ar8xxx_priv
*priv
, int port
)
719 /* Enable port learning and tx */
720 ar8xxx_write(priv
, AR8216_REG_PORT_CTRL(port
),
721 AR8216_PORT_CTRL_LEARN
|
722 (4 << AR8216_PORT_CTRL_STATE_S
));
724 ar8xxx_write(priv
, AR8216_REG_PORT_VLAN(port
), 0);
726 if (port
== AR8216_PORT_CPU
) {
727 ar8xxx_write(priv
, AR8216_REG_PORT_STATUS(port
),
728 AR8216_PORT_STATUS_LINK_UP
|
729 (ar8xxx_has_gige(priv
) ?
730 AR8216_PORT_SPEED_1000M
: AR8216_PORT_SPEED_100M
) |
731 AR8216_PORT_STATUS_TXMAC
|
732 AR8216_PORT_STATUS_RXMAC
|
733 (chip_is_ar8316(priv
) ? AR8216_PORT_STATUS_RXFLOW
: 0) |
734 (chip_is_ar8316(priv
) ? AR8216_PORT_STATUS_TXFLOW
: 0) |
735 AR8216_PORT_STATUS_DUPLEX
);
737 ar8xxx_write(priv
, AR8216_REG_PORT_STATUS(port
),
738 AR8216_PORT_STATUS_LINK_AUTO
);
743 ar8216_wait_atu_ready(struct ar8xxx_priv
*priv
, u16 r2
, u16 r1
)
747 while (ar8xxx_mii_read32(priv
, r2
, r1
) & AR8216_ATU_ACTIVE
&& --timeout
) {
753 pr_err("ar8216: timeout waiting for atu to become ready\n");
756 static void ar8216_get_arl_entry(struct ar8xxx_priv
*priv
,
757 struct arl_entry
*a
, u32
*status
, enum arl_op op
)
759 struct mii_bus
*bus
= priv
->mii_bus
;
761 u16 r1_func0
, r1_func1
, r1_func2
;
762 u32 t
, val0
, val1
, val2
;
764 split_addr(AR8216_REG_ATU_FUNC0
, &r1_func0
, &r2
, &page
);
767 r1_func1
= (AR8216_REG_ATU_FUNC1
>> 1) & 0x1e;
768 r1_func2
= (AR8216_REG_ATU_FUNC2
>> 1) & 0x1e;
771 case AR8XXX_ARL_INITIALIZE
:
772 /* all ATU registers are on the same page
773 * therefore set page only once
775 bus
->write(bus
, 0x18, 0, page
);
776 wait_for_page_switch();
778 ar8216_wait_atu_ready(priv
, r2
, r1_func0
);
780 ar8xxx_mii_write32(priv
, r2
, r1_func0
, AR8216_ATU_OP_GET_NEXT
);
781 ar8xxx_mii_write32(priv
, r2
, r1_func1
, 0);
782 ar8xxx_mii_write32(priv
, r2
, r1_func2
, 0);
784 case AR8XXX_ARL_GET_NEXT
:
785 t
= ar8xxx_mii_read32(priv
, r2
, r1_func0
);
786 t
|= AR8216_ATU_ACTIVE
;
787 ar8xxx_mii_write32(priv
, r2
, r1_func0
, t
);
788 ar8216_wait_atu_ready(priv
, r2
, r1_func0
);
790 val0
= ar8xxx_mii_read32(priv
, r2
, r1_func0
);
791 val1
= ar8xxx_mii_read32(priv
, r2
, r1_func1
);
792 val2
= ar8xxx_mii_read32(priv
, r2
, r1_func2
);
794 *status
= (val2
& AR8216_ATU_STATUS
) >> AR8216_ATU_STATUS_S
;
798 a
->portmap
= (val2
& AR8216_ATU_PORTS
) >> AR8216_ATU_PORTS_S
;
799 a
->mac
[0] = (val0
& AR8216_ATU_ADDR5
) >> AR8216_ATU_ADDR5_S
;
800 a
->mac
[1] = (val0
& AR8216_ATU_ADDR4
) >> AR8216_ATU_ADDR4_S
;
801 a
->mac
[2] = (val1
& AR8216_ATU_ADDR3
) >> AR8216_ATU_ADDR3_S
;
802 a
->mac
[3] = (val1
& AR8216_ATU_ADDR2
) >> AR8216_ATU_ADDR2_S
;
803 a
->mac
[4] = (val1
& AR8216_ATU_ADDR1
) >> AR8216_ATU_ADDR1_S
;
804 a
->mac
[5] = (val1
& AR8216_ATU_ADDR0
) >> AR8216_ATU_ADDR0_S
;
810 ar8236_setup_port(struct ar8xxx_priv
*priv
, int port
, u32 members
)
816 pvid
= priv
->vlan_id
[priv
->pvid
[port
]];
817 if (priv
->vlan_tagged
& (1 << port
))
818 egress
= AR8216_OUT_ADD_VLAN
;
820 egress
= AR8216_OUT_STRIP_VLAN
;
821 ingress
= AR8216_IN_SECURE
;
824 egress
= AR8216_OUT_KEEP
;
825 ingress
= AR8216_IN_PORT_ONLY
;
828 ar8xxx_rmw(priv
, AR8216_REG_PORT_CTRL(port
),
829 AR8216_PORT_CTRL_LEARN
| AR8216_PORT_CTRL_VLAN_MODE
|
830 AR8216_PORT_CTRL_SINGLE_VLAN
| AR8216_PORT_CTRL_STATE
|
831 AR8216_PORT_CTRL_HEADER
| AR8216_PORT_CTRL_LEARN_LOCK
,
832 AR8216_PORT_CTRL_LEARN
|
833 (egress
<< AR8216_PORT_CTRL_VLAN_MODE_S
) |
834 (AR8216_PORT_STATE_FORWARD
<< AR8216_PORT_CTRL_STATE_S
));
836 ar8xxx_rmw(priv
, AR8236_REG_PORT_VLAN(port
),
837 AR8236_PORT_VLAN_DEFAULT_ID
,
838 (pvid
<< AR8236_PORT_VLAN_DEFAULT_ID_S
));
840 ar8xxx_rmw(priv
, AR8236_REG_PORT_VLAN2(port
),
841 AR8236_PORT_VLAN2_VLAN_MODE
|
842 AR8236_PORT_VLAN2_MEMBER
,
843 (ingress
<< AR8236_PORT_VLAN2_VLAN_MODE_S
) |
844 (members
<< AR8236_PORT_VLAN2_MEMBER_S
));
848 ar8236_init_globals(struct ar8xxx_priv
*priv
)
850 /* enable jumbo frames */
851 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
852 AR8316_GCTRL_MTU
, 9018 + 8 + 2);
854 /* enable cpu port to receive arp frames */
855 ar8xxx_reg_set(priv
, AR8216_REG_ATU_CTRL
,
856 AR8236_ATU_CTRL_RES
);
858 /* enable cpu port to receive multicast and broadcast frames */
859 ar8xxx_reg_set(priv
, AR8216_REG_FLOOD_MASK
,
860 AR8236_FM_CPU_BROADCAST_EN
| AR8236_FM_CPU_BCAST_FWD_EN
);
862 /* Enable MIB counters */
863 ar8xxx_rmw(priv
, AR8216_REG_MIB_FUNC
, AR8216_MIB_FUNC
| AR8236_MIB_EN
,
864 (AR8216_MIB_FUNC_NO_OP
<< AR8216_MIB_FUNC_S
) |
869 ar8316_hw_init(struct ar8xxx_priv
*priv
)
873 val
= ar8xxx_read(priv
, AR8316_REG_POSTRIP
);
875 if (priv
->phy
->interface
== PHY_INTERFACE_MODE_RGMII
) {
876 if (priv
->port4_phy
) {
877 /* value taken from Ubiquiti RouterStation Pro */
879 pr_info("ar8316: Using port 4 as PHY\n");
882 pr_info("ar8316: Using port 4 as switch port\n");
884 } else if (priv
->phy
->interface
== PHY_INTERFACE_MODE_GMII
) {
885 /* value taken from AVM Fritz!Box 7390 sources */
888 /* no known value for phy interface */
889 pr_err("ar8316: unsupported mii mode: %d.\n",
890 priv
->phy
->interface
);
897 ar8xxx_write(priv
, AR8316_REG_POSTRIP
, newval
);
899 if (priv
->port4_phy
&&
900 priv
->phy
->interface
== PHY_INTERFACE_MODE_RGMII
) {
901 /* work around for phy4 rgmii mode */
902 ar8xxx_phy_dbg_write(priv
, 4, 0x12, 0x480c);
904 ar8xxx_phy_dbg_write(priv
, 4, 0x0, 0x824e);
906 ar8xxx_phy_dbg_write(priv
, 4, 0x5, 0x3d47);
910 ar8xxx_phy_init(priv
);
913 priv
->initialized
= true;
918 ar8316_init_globals(struct ar8xxx_priv
*priv
)
920 /* standard atheros magic */
921 ar8xxx_write(priv
, 0x38, 0xc000050e);
923 /* enable cpu port to receive multicast and broadcast frames */
924 ar8xxx_write(priv
, AR8216_REG_FLOOD_MASK
, 0x003f003f);
926 /* enable jumbo frames */
927 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
928 AR8316_GCTRL_MTU
, 9018 + 8 + 2);
930 /* Enable MIB counters */
931 ar8xxx_rmw(priv
, AR8216_REG_MIB_FUNC
, AR8216_MIB_FUNC
| AR8236_MIB_EN
,
932 (AR8216_MIB_FUNC_NO_OP
<< AR8216_MIB_FUNC_S
) |
937 ar8xxx_sw_set_vlan(struct switch_dev
*dev
, const struct switch_attr
*attr
,
938 struct switch_val
*val
)
940 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
941 priv
->vlan
= !!val
->value
.i
;
946 ar8xxx_sw_get_vlan(struct switch_dev
*dev
, const struct switch_attr
*attr
,
947 struct switch_val
*val
)
949 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
950 val
->value
.i
= priv
->vlan
;
956 ar8xxx_sw_set_pvid(struct switch_dev
*dev
, int port
, int vlan
)
958 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
960 /* make sure no invalid PVIDs get set */
962 if (vlan
< 0 || vlan
>= dev
->vlans
||
963 port
< 0 || port
>= AR8X16_MAX_PORTS
)
966 priv
->pvid
[port
] = vlan
;
971 ar8xxx_sw_get_pvid(struct switch_dev
*dev
, int port
, int *vlan
)
973 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
975 if (port
< 0 || port
>= AR8X16_MAX_PORTS
)
978 *vlan
= priv
->pvid
[port
];
983 ar8xxx_sw_set_vid(struct switch_dev
*dev
, const struct switch_attr
*attr
,
984 struct switch_val
*val
)
986 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
988 if (val
->port_vlan
>= AR8X16_MAX_VLANS
)
991 priv
->vlan_id
[val
->port_vlan
] = val
->value
.i
;
996 ar8xxx_sw_get_vid(struct switch_dev
*dev
, const struct switch_attr
*attr
,
997 struct switch_val
*val
)
999 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1000 val
->value
.i
= priv
->vlan_id
[val
->port_vlan
];
1005 ar8xxx_sw_get_port_link(struct switch_dev
*dev
, int port
,
1006 struct switch_port_link
*link
)
1008 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1010 ar8216_read_port_link(priv
, port
, link
);
1015 ar8xxx_sw_get_ports(struct switch_dev
*dev
, struct switch_val
*val
)
1017 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1021 if (val
->port_vlan
>= AR8X16_MAX_VLANS
)
1024 ports
= priv
->vlan_table
[val
->port_vlan
];
1026 for (i
= 0; i
< dev
->ports
; i
++) {
1027 struct switch_port
*p
;
1029 if (!(ports
& (1 << i
)))
1032 p
= &val
->value
.ports
[val
->len
++];
1034 if (priv
->vlan_tagged
& (1 << i
))
1035 p
->flags
= (1 << SWITCH_PORT_FLAG_TAGGED
);
1043 ar8xxx_sw_set_ports(struct switch_dev
*dev
, struct switch_val
*val
)
1045 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1046 u8
*vt
= &priv
->vlan_table
[val
->port_vlan
];
1050 for (i
= 0; i
< val
->len
; i
++) {
1051 struct switch_port
*p
= &val
->value
.ports
[i
];
1053 if (p
->flags
& (1 << SWITCH_PORT_FLAG_TAGGED
)) {
1054 priv
->vlan_tagged
|= (1 << p
->id
);
1056 priv
->vlan_tagged
&= ~(1 << p
->id
);
1057 priv
->pvid
[p
->id
] = val
->port_vlan
;
1059 /* make sure that an untagged port does not
1060 * appear in other vlans */
1061 for (j
= 0; j
< AR8X16_MAX_VLANS
; j
++) {
1062 if (j
== val
->port_vlan
)
1064 priv
->vlan_table
[j
] &= ~(1 << p
->id
);
1074 ar8216_set_mirror_regs(struct ar8xxx_priv
*priv
)
1078 /* reset all mirror registers */
1079 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CPUPORT
,
1080 AR8216_GLOBAL_CPUPORT_MIRROR_PORT
,
1081 (0xF << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S
));
1082 for (port
= 0; port
< AR8216_NUM_PORTS
; port
++) {
1083 ar8xxx_reg_clear(priv
, AR8216_REG_PORT_CTRL(port
),
1084 AR8216_PORT_CTRL_MIRROR_RX
);
1086 ar8xxx_reg_clear(priv
, AR8216_REG_PORT_CTRL(port
),
1087 AR8216_PORT_CTRL_MIRROR_TX
);
1090 /* now enable mirroring if necessary */
1091 if (priv
->source_port
>= AR8216_NUM_PORTS
||
1092 priv
->monitor_port
>= AR8216_NUM_PORTS
||
1093 priv
->source_port
== priv
->monitor_port
) {
1097 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CPUPORT
,
1098 AR8216_GLOBAL_CPUPORT_MIRROR_PORT
,
1099 (priv
->monitor_port
<< AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S
));
1101 if (priv
->mirror_rx
)
1102 ar8xxx_reg_set(priv
, AR8216_REG_PORT_CTRL(priv
->source_port
),
1103 AR8216_PORT_CTRL_MIRROR_RX
);
1105 if (priv
->mirror_tx
)
1106 ar8xxx_reg_set(priv
, AR8216_REG_PORT_CTRL(priv
->source_port
),
1107 AR8216_PORT_CTRL_MIRROR_TX
);
1111 ar8xxx_age_time_val(int age_time
)
1113 return (age_time
+ AR8XXX_REG_ARL_CTRL_AGE_TIME_SECS
/ 2) /
1114 AR8XXX_REG_ARL_CTRL_AGE_TIME_SECS
;
1118 ar8xxx_set_age_time(struct ar8xxx_priv
*priv
, int reg
)
1120 u32 age_time
= ar8xxx_age_time_val(priv
->arl_age_time
);
1121 ar8xxx_rmw(priv
, reg
, AR8216_ATU_CTRL_AGE_TIME
, age_time
<< AR8216_ATU_CTRL_AGE_TIME_S
);
1125 ar8xxx_sw_hw_apply(struct switch_dev
*dev
)
1127 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1128 const struct ar8xxx_chip
*chip
= priv
->chip
;
1129 u8 portmask
[AR8X16_MAX_PORTS
];
1132 mutex_lock(&priv
->reg_mutex
);
1133 /* flush all vlan translation unit entries */
1134 priv
->chip
->vtu_flush(priv
);
1136 memset(portmask
, 0, sizeof(portmask
));
1138 /* calculate the port destination masks and load vlans
1139 * into the vlan translation unit */
1140 for (j
= 0; j
< AR8X16_MAX_VLANS
; j
++) {
1141 u8 vp
= priv
->vlan_table
[j
];
1146 for (i
= 0; i
< dev
->ports
; i
++) {
1149 portmask
[i
] |= vp
& ~mask
;
1152 chip
->vtu_load_vlan(priv
, priv
->vlan_id
[j
],
1153 priv
->vlan_table
[j
]);
1157 * isolate all ports, but connect them to the cpu port */
1158 for (i
= 0; i
< dev
->ports
; i
++) {
1159 if (i
== AR8216_PORT_CPU
)
1162 portmask
[i
] = 1 << AR8216_PORT_CPU
;
1163 portmask
[AR8216_PORT_CPU
] |= (1 << i
);
1167 /* update the port destination mask registers and tag settings */
1168 for (i
= 0; i
< dev
->ports
; i
++) {
1169 chip
->setup_port(priv
, i
, portmask
[i
]);
1172 chip
->set_mirror_regs(priv
);
1175 if (chip
->reg_arl_ctrl
)
1176 ar8xxx_set_age_time(priv
, chip
->reg_arl_ctrl
);
1178 mutex_unlock(&priv
->reg_mutex
);
1183 ar8xxx_sw_reset_switch(struct switch_dev
*dev
)
1185 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1186 const struct ar8xxx_chip
*chip
= priv
->chip
;
1189 mutex_lock(&priv
->reg_mutex
);
1190 memset(&priv
->vlan
, 0, sizeof(struct ar8xxx_priv
) -
1191 offsetof(struct ar8xxx_priv
, vlan
));
1193 for (i
= 0; i
< AR8X16_MAX_VLANS
; i
++)
1194 priv
->vlan_id
[i
] = i
;
1196 /* Configure all ports */
1197 for (i
= 0; i
< dev
->ports
; i
++)
1198 chip
->init_port(priv
, i
);
1200 priv
->mirror_rx
= false;
1201 priv
->mirror_tx
= false;
1202 priv
->source_port
= 0;
1203 priv
->monitor_port
= 0;
1204 priv
->arl_age_time
= AR8XXX_DEFAULT_ARL_AGE_TIME
;
1206 chip
->init_globals(priv
);
1207 chip
->atu_flush(priv
);
1209 mutex_unlock(&priv
->reg_mutex
);
1211 return chip
->sw_hw_apply(dev
);
1215 ar8xxx_sw_set_reset_mibs(struct switch_dev
*dev
,
1216 const struct switch_attr
*attr
,
1217 struct switch_val
*val
)
1219 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1223 if (!ar8xxx_has_mib_counters(priv
))
1226 mutex_lock(&priv
->mib_lock
);
1228 len
= priv
->dev
.ports
* priv
->chip
->num_mibs
*
1229 sizeof(*priv
->mib_stats
);
1230 memset(priv
->mib_stats
, '\0', len
);
1231 ret
= ar8xxx_mib_flush(priv
);
1238 mutex_unlock(&priv
->mib_lock
);
1243 ar8xxx_sw_set_mirror_rx_enable(struct switch_dev
*dev
,
1244 const struct switch_attr
*attr
,
1245 struct switch_val
*val
)
1247 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1249 mutex_lock(&priv
->reg_mutex
);
1250 priv
->mirror_rx
= !!val
->value
.i
;
1251 priv
->chip
->set_mirror_regs(priv
);
1252 mutex_unlock(&priv
->reg_mutex
);
1258 ar8xxx_sw_get_mirror_rx_enable(struct switch_dev
*dev
,
1259 const struct switch_attr
*attr
,
1260 struct switch_val
*val
)
1262 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1263 val
->value
.i
= priv
->mirror_rx
;
1268 ar8xxx_sw_set_mirror_tx_enable(struct switch_dev
*dev
,
1269 const struct switch_attr
*attr
,
1270 struct switch_val
*val
)
1272 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1274 mutex_lock(&priv
->reg_mutex
);
1275 priv
->mirror_tx
= !!val
->value
.i
;
1276 priv
->chip
->set_mirror_regs(priv
);
1277 mutex_unlock(&priv
->reg_mutex
);
1283 ar8xxx_sw_get_mirror_tx_enable(struct switch_dev
*dev
,
1284 const struct switch_attr
*attr
,
1285 struct switch_val
*val
)
1287 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1288 val
->value
.i
= priv
->mirror_tx
;
1293 ar8xxx_sw_set_mirror_monitor_port(struct switch_dev
*dev
,
1294 const struct switch_attr
*attr
,
1295 struct switch_val
*val
)
1297 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1299 mutex_lock(&priv
->reg_mutex
);
1300 priv
->monitor_port
= val
->value
.i
;
1301 priv
->chip
->set_mirror_regs(priv
);
1302 mutex_unlock(&priv
->reg_mutex
);
1308 ar8xxx_sw_get_mirror_monitor_port(struct switch_dev
*dev
,
1309 const struct switch_attr
*attr
,
1310 struct switch_val
*val
)
1312 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1313 val
->value
.i
= priv
->monitor_port
;
1318 ar8xxx_sw_set_mirror_source_port(struct switch_dev
*dev
,
1319 const struct switch_attr
*attr
,
1320 struct switch_val
*val
)
1322 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1324 mutex_lock(&priv
->reg_mutex
);
1325 priv
->source_port
= val
->value
.i
;
1326 priv
->chip
->set_mirror_regs(priv
);
1327 mutex_unlock(&priv
->reg_mutex
);
1333 ar8xxx_sw_get_mirror_source_port(struct switch_dev
*dev
,
1334 const struct switch_attr
*attr
,
1335 struct switch_val
*val
)
1337 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1338 val
->value
.i
= priv
->source_port
;
1343 ar8xxx_sw_set_port_reset_mib(struct switch_dev
*dev
,
1344 const struct switch_attr
*attr
,
1345 struct switch_val
*val
)
1347 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1351 if (!ar8xxx_has_mib_counters(priv
))
1354 port
= val
->port_vlan
;
1355 if (port
>= dev
->ports
)
1358 mutex_lock(&priv
->mib_lock
);
1359 ret
= ar8xxx_mib_capture(priv
);
1363 ar8xxx_mib_fetch_port_stat(priv
, port
, true);
1368 mutex_unlock(&priv
->mib_lock
);
1373 ar8xxx_byte_to_str(char *buf
, int len
, u64 byte
)
1378 if (byte
>= 0x40000000) { /* 1 GiB */
1379 b
= byte
* 10 / 0x40000000;
1381 } else if (byte
>= 0x100000) { /* 1 MiB */
1382 b
= byte
* 10 / 0x100000;
1384 } else if (byte
>= 0x400) { /* 1 KiB */
1385 b
= byte
* 10 / 0x400;
1391 if (strcmp(unit
, "Byte"))
1392 snprintf(buf
, len
, "%lu.%lu %s", b
/ 10, b
% 10, unit
);
1394 snprintf(buf
, len
, "%lu %s", b
, unit
);
1398 ar8xxx_sw_get_port_mib(struct switch_dev
*dev
,
1399 const struct switch_attr
*attr
,
1400 struct switch_val
*val
)
1402 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1403 const struct ar8xxx_chip
*chip
= priv
->chip
;
1404 u64
*mib_stats
, mib_data
;
1407 char *buf
= priv
->buf
;
1409 const char *mib_name
;
1411 bool mib_stats_empty
= true;
1413 if (!ar8xxx_has_mib_counters(priv
))
1416 port
= val
->port_vlan
;
1417 if (port
>= dev
->ports
)
1420 mutex_lock(&priv
->mib_lock
);
1421 ret
= ar8xxx_mib_capture(priv
);
1425 ar8xxx_mib_fetch_port_stat(priv
, port
, false);
1427 len
+= snprintf(buf
+ len
, sizeof(priv
->buf
) - len
,
1430 mib_stats
= &priv
->mib_stats
[port
* chip
->num_mibs
];
1431 for (i
= 0; i
< chip
->num_mibs
; i
++) {
1432 mib_name
= chip
->mib_decs
[i
].name
;
1433 mib_data
= mib_stats
[i
];
1434 len
+= snprintf(buf
+ len
, sizeof(priv
->buf
) - len
,
1435 "%-12s: %llu\n", mib_name
, mib_data
);
1436 if ((!strcmp(mib_name
, "TxByte") ||
1437 !strcmp(mib_name
, "RxGoodByte")) &&
1439 ar8xxx_byte_to_str(buf1
, sizeof(buf1
), mib_data
);
1440 --len
; /* discard newline at the end of buf */
1441 len
+= snprintf(buf
+ len
, sizeof(priv
->buf
) - len
,
1444 if (mib_stats_empty
&& mib_data
)
1445 mib_stats_empty
= false;
1448 if (mib_stats_empty
)
1449 len
= snprintf(buf
, sizeof(priv
->buf
), "No MIB data");
1457 mutex_unlock(&priv
->mib_lock
);
1462 ar8xxx_sw_set_arl_age_time(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1463 struct switch_val
*val
)
1465 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1466 int age_time
= val
->value
.i
;
1472 age_time_val
= ar8xxx_age_time_val(age_time
);
1473 if (age_time_val
== 0 || age_time_val
> 0xffff)
1476 priv
->arl_age_time
= age_time
;
1481 ar8xxx_sw_get_arl_age_time(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1482 struct switch_val
*val
)
1484 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1485 val
->value
.i
= priv
->arl_age_time
;
1490 ar8xxx_sw_get_arl_table(struct switch_dev
*dev
,
1491 const struct switch_attr
*attr
,
1492 struct switch_val
*val
)
1494 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1495 struct mii_bus
*bus
= priv
->mii_bus
;
1496 const struct ar8xxx_chip
*chip
= priv
->chip
;
1497 char *buf
= priv
->arl_buf
;
1498 int i
, j
, k
, len
= 0;
1499 struct arl_entry
*a
, *a1
;
1502 if (!chip
->get_arl_entry
)
1505 mutex_lock(&priv
->reg_mutex
);
1506 mutex_lock(&bus
->mdio_lock
);
1508 chip
->get_arl_entry(priv
, NULL
, NULL
, AR8XXX_ARL_INITIALIZE
);
1510 for(i
= 0; i
< AR8XXX_NUM_ARL_RECORDS
; ++i
) {
1511 a
= &priv
->arl_table
[i
];
1513 chip
->get_arl_entry(priv
, a
, &status
, AR8XXX_ARL_GET_NEXT
);
1519 * ARL table can include multiple valid entries
1520 * per MAC, just with differing status codes
1522 for (j
= 0; j
< i
; ++j
) {
1523 a1
= &priv
->arl_table
[j
];
1524 if (!memcmp(a
->mac
, a1
->mac
, sizeof(a
->mac
))) {
1525 /* ignore ports already seen in former entry */
1526 a
->portmap
&= ~a1
->portmap
;
1533 mutex_unlock(&bus
->mdio_lock
);
1535 len
+= snprintf(buf
+ len
, sizeof(priv
->arl_buf
) - len
,
1536 "address resolution table\n");
1538 if (i
== AR8XXX_NUM_ARL_RECORDS
)
1539 len
+= snprintf(buf
+ len
, sizeof(priv
->arl_buf
) - len
,
1540 "Too many entries found, displaying the first %d only!\n",
1541 AR8XXX_NUM_ARL_RECORDS
);
1543 for (j
= 0; j
< priv
->dev
.ports
; ++j
) {
1544 for (k
= 0; k
< i
; ++k
) {
1545 a
= &priv
->arl_table
[k
];
1546 if (!(a
->portmap
& BIT(j
)))
1548 len
+= snprintf(buf
+ len
, sizeof(priv
->arl_buf
) - len
,
1549 "Port %d: MAC %02x:%02x:%02x:%02x:%02x:%02x\n",
1551 a
->mac
[5], a
->mac
[4], a
->mac
[3],
1552 a
->mac
[2], a
->mac
[1], a
->mac
[0]);
1559 mutex_unlock(&priv
->reg_mutex
);
1565 ar8xxx_sw_set_flush_arl_table(struct switch_dev
*dev
,
1566 const struct switch_attr
*attr
,
1567 struct switch_val
*val
)
1569 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1572 mutex_lock(&priv
->reg_mutex
);
1573 ret
= priv
->chip
->atu_flush(priv
);
1574 mutex_unlock(&priv
->reg_mutex
);
1580 ar8xxx_sw_set_flush_port_arl_table(struct switch_dev
*dev
,
1581 const struct switch_attr
*attr
,
1582 struct switch_val
*val
)
1584 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1587 port
= val
->port_vlan
;
1588 if (port
>= dev
->ports
)
1591 mutex_lock(&priv
->reg_mutex
);
1592 ret
= priv
->chip
->atu_flush_port(priv
, port
);
1593 mutex_unlock(&priv
->reg_mutex
);
1598 static const struct switch_attr ar8xxx_sw_attr_globals
[] = {
1600 .type
= SWITCH_TYPE_INT
,
1601 .name
= "enable_vlan",
1602 .description
= "Enable VLAN mode",
1603 .set
= ar8xxx_sw_set_vlan
,
1604 .get
= ar8xxx_sw_get_vlan
,
1608 .type
= SWITCH_TYPE_NOVAL
,
1609 .name
= "reset_mibs",
1610 .description
= "Reset all MIB counters",
1611 .set
= ar8xxx_sw_set_reset_mibs
,
1614 .type
= SWITCH_TYPE_INT
,
1615 .name
= "enable_mirror_rx",
1616 .description
= "Enable mirroring of RX packets",
1617 .set
= ar8xxx_sw_set_mirror_rx_enable
,
1618 .get
= ar8xxx_sw_get_mirror_rx_enable
,
1622 .type
= SWITCH_TYPE_INT
,
1623 .name
= "enable_mirror_tx",
1624 .description
= "Enable mirroring of TX packets",
1625 .set
= ar8xxx_sw_set_mirror_tx_enable
,
1626 .get
= ar8xxx_sw_get_mirror_tx_enable
,
1630 .type
= SWITCH_TYPE_INT
,
1631 .name
= "mirror_monitor_port",
1632 .description
= "Mirror monitor port",
1633 .set
= ar8xxx_sw_set_mirror_monitor_port
,
1634 .get
= ar8xxx_sw_get_mirror_monitor_port
,
1635 .max
= AR8216_NUM_PORTS
- 1
1638 .type
= SWITCH_TYPE_INT
,
1639 .name
= "mirror_source_port",
1640 .description
= "Mirror source port",
1641 .set
= ar8xxx_sw_set_mirror_source_port
,
1642 .get
= ar8xxx_sw_get_mirror_source_port
,
1643 .max
= AR8216_NUM_PORTS
- 1
1646 .type
= SWITCH_TYPE_STRING
,
1647 .name
= "arl_table",
1648 .description
= "Get ARL table",
1650 .get
= ar8xxx_sw_get_arl_table
,
1653 .type
= SWITCH_TYPE_NOVAL
,
1654 .name
= "flush_arl_table",
1655 .description
= "Flush ARL table",
1656 .set
= ar8xxx_sw_set_flush_arl_table
,
1660 const struct switch_attr ar8xxx_sw_attr_port
[] = {
1662 .type
= SWITCH_TYPE_NOVAL
,
1663 .name
= "reset_mib",
1664 .description
= "Reset single port MIB counters",
1665 .set
= ar8xxx_sw_set_port_reset_mib
,
1668 .type
= SWITCH_TYPE_STRING
,
1670 .description
= "Get port's MIB counters",
1672 .get
= ar8xxx_sw_get_port_mib
,
1675 .type
= SWITCH_TYPE_NOVAL
,
1676 .name
= "flush_arl_table",
1677 .description
= "Flush port's ARL table entries",
1678 .set
= ar8xxx_sw_set_flush_port_arl_table
,
1682 const struct switch_attr ar8xxx_sw_attr_vlan
[1] = {
1684 .type
= SWITCH_TYPE_INT
,
1686 .description
= "VLAN ID (0-4094)",
1687 .set
= ar8xxx_sw_set_vid
,
1688 .get
= ar8xxx_sw_get_vid
,
1693 static const struct switch_dev_ops ar8xxx_sw_ops
= {
1695 .attr
= ar8xxx_sw_attr_globals
,
1696 .n_attr
= ARRAY_SIZE(ar8xxx_sw_attr_globals
),
1699 .attr
= ar8xxx_sw_attr_port
,
1700 .n_attr
= ARRAY_SIZE(ar8xxx_sw_attr_port
),
1703 .attr
= ar8xxx_sw_attr_vlan
,
1704 .n_attr
= ARRAY_SIZE(ar8xxx_sw_attr_vlan
),
1706 .get_port_pvid
= ar8xxx_sw_get_pvid
,
1707 .set_port_pvid
= ar8xxx_sw_set_pvid
,
1708 .get_vlan_ports
= ar8xxx_sw_get_ports
,
1709 .set_vlan_ports
= ar8xxx_sw_set_ports
,
1710 .apply_config
= ar8xxx_sw_hw_apply
,
1711 .reset_switch
= ar8xxx_sw_reset_switch
,
1712 .get_port_link
= ar8xxx_sw_get_port_link
,
1713 /* The following op is disabled as it hogs the CPU and degrades performance.
1714 An implementation has been attempted in 4d8a66d but reading MIB data is slow
1717 The high CPU load has been traced down to the ar8xxx_reg_wait() call in
1718 ar8xxx_mib_op(), which has to usleep_range() till the MIB busy flag set by
1719 the request to update the MIB counter is cleared. */
1721 .get_port_stats
= ar8xxx_sw_get_port_stats
,
1725 static const struct ar8xxx_chip ar8216_chip
= {
1726 .caps
= AR8XXX_CAP_MIB_COUNTERS
,
1728 .reg_port_stats_start
= 0x19000,
1729 .reg_port_stats_length
= 0xa0,
1730 .reg_arl_ctrl
= AR8216_REG_ATU_CTRL
,
1732 .name
= "Atheros AR8216",
1733 .ports
= AR8216_NUM_PORTS
,
1734 .vlans
= AR8216_NUM_VLANS
,
1735 .swops
= &ar8xxx_sw_ops
,
1737 .hw_init
= ar8216_hw_init
,
1738 .init_globals
= ar8216_init_globals
,
1739 .init_port
= ar8216_init_port
,
1740 .setup_port
= ar8216_setup_port
,
1741 .read_port_status
= ar8216_read_port_status
,
1742 .atu_flush
= ar8216_atu_flush
,
1743 .atu_flush_port
= ar8216_atu_flush_port
,
1744 .vtu_flush
= ar8216_vtu_flush
,
1745 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
1746 .set_mirror_regs
= ar8216_set_mirror_regs
,
1747 .get_arl_entry
= ar8216_get_arl_entry
,
1748 .sw_hw_apply
= ar8xxx_sw_hw_apply
,
1750 .num_mibs
= ARRAY_SIZE(ar8216_mibs
),
1751 .mib_decs
= ar8216_mibs
,
1752 .mib_func
= AR8216_REG_MIB_FUNC
1755 static const struct ar8xxx_chip ar8236_chip
= {
1756 .caps
= AR8XXX_CAP_MIB_COUNTERS
,
1758 .reg_port_stats_start
= 0x20000,
1759 .reg_port_stats_length
= 0x100,
1760 .reg_arl_ctrl
= AR8216_REG_ATU_CTRL
,
1762 .name
= "Atheros AR8236",
1763 .ports
= AR8216_NUM_PORTS
,
1764 .vlans
= AR8216_NUM_VLANS
,
1765 .swops
= &ar8xxx_sw_ops
,
1767 .hw_init
= ar8216_hw_init
,
1768 .init_globals
= ar8236_init_globals
,
1769 .init_port
= ar8216_init_port
,
1770 .setup_port
= ar8236_setup_port
,
1771 .read_port_status
= ar8216_read_port_status
,
1772 .atu_flush
= ar8216_atu_flush
,
1773 .atu_flush_port
= ar8216_atu_flush_port
,
1774 .vtu_flush
= ar8216_vtu_flush
,
1775 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
1776 .set_mirror_regs
= ar8216_set_mirror_regs
,
1777 .get_arl_entry
= ar8216_get_arl_entry
,
1778 .sw_hw_apply
= ar8xxx_sw_hw_apply
,
1780 .num_mibs
= ARRAY_SIZE(ar8236_mibs
),
1781 .mib_decs
= ar8236_mibs
,
1782 .mib_func
= AR8216_REG_MIB_FUNC
1785 static const struct ar8xxx_chip ar8316_chip
= {
1786 .caps
= AR8XXX_CAP_GIGE
| AR8XXX_CAP_MIB_COUNTERS
,
1788 .reg_port_stats_start
= 0x20000,
1789 .reg_port_stats_length
= 0x100,
1790 .reg_arl_ctrl
= AR8216_REG_ATU_CTRL
,
1792 .name
= "Atheros AR8316",
1793 .ports
= AR8216_NUM_PORTS
,
1794 .vlans
= AR8X16_MAX_VLANS
,
1795 .swops
= &ar8xxx_sw_ops
,
1797 .hw_init
= ar8316_hw_init
,
1798 .init_globals
= ar8316_init_globals
,
1799 .init_port
= ar8216_init_port
,
1800 .setup_port
= ar8216_setup_port
,
1801 .read_port_status
= ar8216_read_port_status
,
1802 .atu_flush
= ar8216_atu_flush
,
1803 .atu_flush_port
= ar8216_atu_flush_port
,
1804 .vtu_flush
= ar8216_vtu_flush
,
1805 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
1806 .set_mirror_regs
= ar8216_set_mirror_regs
,
1807 .get_arl_entry
= ar8216_get_arl_entry
,
1808 .sw_hw_apply
= ar8xxx_sw_hw_apply
,
1810 .num_mibs
= ARRAY_SIZE(ar8236_mibs
),
1811 .mib_decs
= ar8236_mibs
,
1812 .mib_func
= AR8216_REG_MIB_FUNC
1816 ar8xxx_read_id(struct ar8xxx_priv
*priv
)
1822 val
= ar8xxx_read(priv
, AR8216_REG_CTRL
);
1826 id
= val
& (AR8216_CTRL_REVISION
| AR8216_CTRL_VERSION
);
1827 for (i
= 0; i
< AR8X16_PROBE_RETRIES
; i
++) {
1830 val
= ar8xxx_read(priv
, AR8216_REG_CTRL
);
1834 t
= val
& (AR8216_CTRL_REVISION
| AR8216_CTRL_VERSION
);
1839 priv
->chip_ver
= (id
& AR8216_CTRL_VERSION
) >> AR8216_CTRL_VERSION_S
;
1840 priv
->chip_rev
= (id
& AR8216_CTRL_REVISION
);
1845 ar8xxx_id_chip(struct ar8xxx_priv
*priv
)
1849 ret
= ar8xxx_read_id(priv
);
1853 switch (priv
->chip_ver
) {
1854 case AR8XXX_VER_AR8216
:
1855 priv
->chip
= &ar8216_chip
;
1857 case AR8XXX_VER_AR8236
:
1858 priv
->chip
= &ar8236_chip
;
1860 case AR8XXX_VER_AR8316
:
1861 priv
->chip
= &ar8316_chip
;
1863 case AR8XXX_VER_AR8327
:
1864 priv
->chip
= &ar8327_chip
;
1866 case AR8XXX_VER_AR8337
:
1867 priv
->chip
= &ar8337_chip
;
1870 pr_err("ar8216: Unknown Atheros device [ver=%d, rev=%d]\n",
1871 priv
->chip_ver
, priv
->chip_rev
);
1880 ar8xxx_mib_work_func(struct work_struct
*work
)
1882 struct ar8xxx_priv
*priv
;
1885 priv
= container_of(work
, struct ar8xxx_priv
, mib_work
.work
);
1887 mutex_lock(&priv
->mib_lock
);
1889 err
= ar8xxx_mib_capture(priv
);
1893 ar8xxx_mib_fetch_port_stat(priv
, priv
->mib_next_port
, false);
1896 priv
->mib_next_port
++;
1897 if (priv
->mib_next_port
>= priv
->dev
.ports
)
1898 priv
->mib_next_port
= 0;
1900 mutex_unlock(&priv
->mib_lock
);
1901 schedule_delayed_work(&priv
->mib_work
,
1902 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY
));
1906 ar8xxx_mib_init(struct ar8xxx_priv
*priv
)
1910 if (!ar8xxx_has_mib_counters(priv
))
1913 BUG_ON(!priv
->chip
->mib_decs
|| !priv
->chip
->num_mibs
);
1915 len
= priv
->dev
.ports
* priv
->chip
->num_mibs
*
1916 sizeof(*priv
->mib_stats
);
1917 priv
->mib_stats
= kzalloc(len
, GFP_KERNEL
);
1919 if (!priv
->mib_stats
)
1926 ar8xxx_mib_start(struct ar8xxx_priv
*priv
)
1928 if (!ar8xxx_has_mib_counters(priv
))
1931 schedule_delayed_work(&priv
->mib_work
,
1932 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY
));
1936 ar8xxx_mib_stop(struct ar8xxx_priv
*priv
)
1938 if (!ar8xxx_has_mib_counters(priv
))
1941 cancel_delayed_work_sync(&priv
->mib_work
);
1944 static struct ar8xxx_priv
*
1947 struct ar8xxx_priv
*priv
;
1949 priv
= kzalloc(sizeof(struct ar8xxx_priv
), GFP_KERNEL
);
1953 mutex_init(&priv
->reg_mutex
);
1954 mutex_init(&priv
->mib_lock
);
1955 INIT_DELAYED_WORK(&priv
->mib_work
, ar8xxx_mib_work_func
);
1961 ar8xxx_free(struct ar8xxx_priv
*priv
)
1963 if (priv
->chip
&& priv
->chip
->cleanup
)
1964 priv
->chip
->cleanup(priv
);
1966 kfree(priv
->chip_data
);
1967 kfree(priv
->mib_stats
);
1972 ar8xxx_probe_switch(struct ar8xxx_priv
*priv
)
1974 const struct ar8xxx_chip
*chip
;
1975 struct switch_dev
*swdev
;
1981 swdev
->cpu_port
= AR8216_PORT_CPU
;
1982 swdev
->name
= chip
->name
;
1983 swdev
->vlans
= chip
->vlans
;
1984 swdev
->ports
= chip
->ports
;
1985 swdev
->ops
= chip
->swops
;
1987 ret
= ar8xxx_mib_init(priv
);
1995 ar8xxx_start(struct ar8xxx_priv
*priv
)
2001 ret
= priv
->chip
->hw_init(priv
);
2005 ret
= ar8xxx_sw_reset_switch(&priv
->dev
);
2011 ar8xxx_mib_start(priv
);
2017 ar8xxx_phy_config_init(struct phy_device
*phydev
)
2019 struct ar8xxx_priv
*priv
= phydev
->priv
;
2020 struct net_device
*dev
= phydev
->attached_dev
;
2026 if (priv
->chip
->config_at_probe
)
2027 return ar8xxx_phy_check_aneg(phydev
);
2031 if (phydev
->mdio
.addr
!= 0) {
2032 if (chip_is_ar8316(priv
)) {
2033 /* switch device has been initialized, reinit */
2034 priv
->dev
.ports
= (AR8216_NUM_PORTS
- 1);
2035 priv
->initialized
= false;
2036 priv
->port4_phy
= true;
2037 ar8316_hw_init(priv
);
2044 ret
= ar8xxx_start(priv
);
2048 /* VID fixup only needed on ar8216 */
2049 if (chip_is_ar8216(priv
)) {
2050 dev
->phy_ptr
= priv
;
2051 dev
->priv_flags
|= IFF_NO_IP_ALIGN
;
2052 dev
->eth_mangle_rx
= ar8216_mangle_rx
;
2053 dev
->eth_mangle_tx
= ar8216_mangle_tx
;
2060 ar8xxx_check_link_states(struct ar8xxx_priv
*priv
)
2062 bool link_new
, changed
= false;
2066 mutex_lock(&priv
->reg_mutex
);
2068 for (i
= 0; i
< priv
->dev
.ports
; i
++) {
2069 status
= priv
->chip
->read_port_status(priv
, i
);
2070 link_new
= !!(status
& AR8216_PORT_STATUS_LINK_UP
);
2071 if (link_new
== priv
->link_up
[i
])
2074 priv
->link_up
[i
] = link_new
;
2076 /* flush ARL entries for this port if it went down*/
2078 priv
->chip
->atu_flush_port(priv
, i
);
2079 dev_info(&priv
->phy
->mdio
.dev
, "Port %d is %s\n",
2080 i
, link_new
? "up" : "down");
2083 mutex_unlock(&priv
->reg_mutex
);
2089 ar8xxx_phy_read_status(struct phy_device
*phydev
)
2091 struct ar8xxx_priv
*priv
= phydev
->priv
;
2092 struct switch_port_link link
;
2094 /* check for switch port link changes */
2095 if (phydev
->state
== PHY_CHANGELINK
)
2096 ar8xxx_check_link_states(priv
);
2098 if (phydev
->mdio
.addr
!= 0)
2099 return genphy_read_status(phydev
);
2101 ar8216_read_port_link(priv
, phydev
->mdio
.addr
, &link
);
2102 phydev
->link
= !!link
.link
;
2106 switch (link
.speed
) {
2107 case SWITCH_PORT_SPEED_10
:
2108 phydev
->speed
= SPEED_10
;
2110 case SWITCH_PORT_SPEED_100
:
2111 phydev
->speed
= SPEED_100
;
2113 case SWITCH_PORT_SPEED_1000
:
2114 phydev
->speed
= SPEED_1000
;
2119 phydev
->duplex
= link
.duplex
? DUPLEX_FULL
: DUPLEX_HALF
;
2121 phydev
->state
= PHY_RUNNING
;
2122 netif_carrier_on(phydev
->attached_dev
);
2123 if (phydev
->adjust_link
)
2124 phydev
->adjust_link(phydev
->attached_dev
);
2130 ar8xxx_phy_config_aneg(struct phy_device
*phydev
)
2132 if (phydev
->mdio
.addr
== 0)
2135 return genphy_config_aneg(phydev
);
2138 static const u32 ar8xxx_phy_ids
[] = {
2140 0x004dd034, /* AR8327 */
2141 0x004dd036, /* AR8337 */
2144 0x004dd043, /* AR8236 */
2148 ar8xxx_phy_match(u32 phy_id
)
2152 for (i
= 0; i
< ARRAY_SIZE(ar8xxx_phy_ids
); i
++)
2153 if (phy_id
== ar8xxx_phy_ids
[i
])
2160 ar8xxx_is_possible(struct mii_bus
*bus
)
2162 unsigned int i
, found_phys
= 0;
2164 for (i
= 0; i
< 5; i
++) {
2167 phy_id
= mdiobus_read(bus
, i
, MII_PHYSID1
) << 16;
2168 phy_id
|= mdiobus_read(bus
, i
, MII_PHYSID2
);
2169 if (ar8xxx_phy_match(phy_id
)) {
2171 } else if (phy_id
) {
2172 pr_debug("ar8xxx: unknown PHY at %s:%02x id:%08x\n",
2173 dev_name(&bus
->dev
), i
, phy_id
);
2176 return !!found_phys
;
2180 ar8xxx_phy_probe(struct phy_device
*phydev
)
2182 struct ar8xxx_priv
*priv
;
2183 struct switch_dev
*swdev
;
2186 /* skip PHYs at unused adresses */
2187 if (phydev
->mdio
.addr
!= 0 && phydev
->mdio
.addr
!= 3 && phydev
->mdio
.addr
!= 4)
2190 if (!ar8xxx_is_possible(phydev
->mdio
.bus
))
2193 mutex_lock(&ar8xxx_dev_list_lock
);
2194 list_for_each_entry(priv
, &ar8xxx_dev_list
, list
)
2195 if (priv
->mii_bus
== phydev
->mdio
.bus
)
2198 priv
= ar8xxx_create();
2204 priv
->mii_bus
= phydev
->mdio
.bus
;
2205 priv
->pdev
= &phydev
->mdio
.dev
;
2207 ret
= ar8xxx_id_chip(priv
);
2211 ret
= ar8xxx_probe_switch(priv
);
2216 swdev
->alias
= dev_name(&priv
->mii_bus
->dev
);
2217 ret
= register_switch(swdev
, NULL
);
2221 pr_info("%s: %s rev. %u switch registered on %s\n",
2222 swdev
->devname
, swdev
->name
, priv
->chip_rev
,
2223 dev_name(&priv
->mii_bus
->dev
));
2225 list_add(&priv
->list
, &ar8xxx_dev_list
);
2230 if (phydev
->mdio
.addr
== 0) {
2231 if (ar8xxx_has_gige(priv
)) {
2232 phydev
->supported
= SUPPORTED_1000baseT_Full
;
2233 phydev
->advertising
= ADVERTISED_1000baseT_Full
;
2235 phydev
->supported
= SUPPORTED_100baseT_Full
;
2236 phydev
->advertising
= ADVERTISED_100baseT_Full
;
2239 if (priv
->chip
->config_at_probe
) {
2242 ret
= ar8xxx_start(priv
);
2244 goto err_unregister_switch
;
2247 if (ar8xxx_has_gige(priv
)) {
2248 phydev
->supported
|= SUPPORTED_1000baseT_Full
;
2249 phydev
->advertising
|= ADVERTISED_1000baseT_Full
;
2251 if (priv
->chip
->phy_rgmii_set
)
2252 priv
->chip
->phy_rgmii_set(priv
, phydev
);
2255 phydev
->priv
= priv
;
2257 mutex_unlock(&ar8xxx_dev_list_lock
);
2261 err_unregister_switch
:
2262 if (--priv
->use_count
)
2265 unregister_switch(&priv
->dev
);
2270 mutex_unlock(&ar8xxx_dev_list_lock
);
2275 ar8xxx_phy_detach(struct phy_device
*phydev
)
2277 struct net_device
*dev
= phydev
->attached_dev
;
2282 dev
->phy_ptr
= NULL
;
2283 dev
->priv_flags
&= ~IFF_NO_IP_ALIGN
;
2284 dev
->eth_mangle_rx
= NULL
;
2285 dev
->eth_mangle_tx
= NULL
;
2289 ar8xxx_phy_remove(struct phy_device
*phydev
)
2291 struct ar8xxx_priv
*priv
= phydev
->priv
;
2296 phydev
->priv
= NULL
;
2298 mutex_lock(&ar8xxx_dev_list_lock
);
2300 if (--priv
->use_count
> 0) {
2301 mutex_unlock(&ar8xxx_dev_list_lock
);
2305 list_del(&priv
->list
);
2306 mutex_unlock(&ar8xxx_dev_list_lock
);
2308 unregister_switch(&priv
->dev
);
2309 ar8xxx_mib_stop(priv
);
2314 ar8xxx_phy_soft_reset(struct phy_device
*phydev
)
2316 /* we don't need an extra reset */
2320 static struct phy_driver ar8xxx_phy_driver
[] = {
2322 .phy_id
= 0x004d0000,
2323 .name
= "Atheros AR8216/AR8236/AR8316",
2324 .phy_id_mask
= 0xffff0000,
2325 .features
= PHY_BASIC_FEATURES
,
2326 .probe
= ar8xxx_phy_probe
,
2327 .remove
= ar8xxx_phy_remove
,
2328 .detach
= ar8xxx_phy_detach
,
2329 .config_init
= ar8xxx_phy_config_init
,
2330 .config_aneg
= ar8xxx_phy_config_aneg
,
2331 .read_status
= ar8xxx_phy_read_status
,
2332 .soft_reset
= ar8xxx_phy_soft_reset
,
2336 module_phy_driver(ar8xxx_phy_driver
);
2337 MODULE_LICENSE("GPL");