2 * ar8216.c: AR8216 switch driver
4 * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/list.h>
22 #include <linux/if_ether.h>
23 #include <linux/skbuff.h>
24 #include <linux/netdevice.h>
25 #include <linux/netlink.h>
26 #include <linux/bitops.h>
27 #include <net/genetlink.h>
28 #include <linux/switch.h>
29 #include <linux/delay.h>
30 #include <linux/phy.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/lockdep.h>
34 #include <linux/ar8216_platform.h>
35 #include <linux/workqueue.h>
36 #include <linux/of_device.h>
40 /* size of the vlan table */
41 #define AR8X16_MAX_VLANS 128
42 #define AR8X16_PROBE_RETRIES 10
43 #define AR8X16_MAX_PORTS 8
45 #define AR8XXX_MIB_WORK_DELAY 2000 /* msecs */
49 #define AR8XXX_CAP_GIGE BIT(0)
50 #define AR8XXX_CAP_MIB_COUNTERS BIT(1)
53 AR8XXX_VER_AR8216
= 0x01,
54 AR8XXX_VER_AR8236
= 0x03,
55 AR8XXX_VER_AR8316
= 0x10,
56 AR8XXX_VER_AR8327
= 0x12,
59 struct ar8xxx_mib_desc
{
68 int (*hw_init
)(struct ar8xxx_priv
*priv
);
69 void (*init_globals
)(struct ar8xxx_priv
*priv
);
70 void (*init_port
)(struct ar8xxx_priv
*priv
, int port
);
71 void (*setup_port
)(struct ar8xxx_priv
*priv
, int port
, u32 egress
,
72 u32 ingress
, u32 members
, u32 pvid
);
73 u32 (*read_port_status
)(struct ar8xxx_priv
*priv
, int port
);
74 int (*atu_flush
)(struct ar8xxx_priv
*priv
);
75 void (*vtu_flush
)(struct ar8xxx_priv
*priv
);
76 void (*vtu_load_vlan
)(struct ar8xxx_priv
*priv
, u32 vid
, u32 port_mask
);
78 const struct ar8xxx_mib_desc
*mib_decs
;
88 struct switch_dev dev
;
89 struct mii_bus
*mii_bus
;
90 struct phy_device
*phy
;
92 u32 (*read
)(struct ar8xxx_priv
*priv
, int reg
);
93 void (*write
)(struct ar8xxx_priv
*priv
, int reg
, u32 val
);
95 int (*get_port_link
)(unsigned port
);
97 const struct net_device_ops
*ndo_old
;
98 struct net_device_ops ndo
;
99 struct mutex reg_mutex
;
102 const struct ar8xxx_chip
*chip
;
104 struct ar8327_data ar8327
;
113 struct mutex mib_lock
;
114 struct delayed_work mib_work
;
118 struct list_head list
;
119 unsigned int use_count
;
121 /* all fields below are cleared on reset */
123 u16 vlan_id
[AR8X16_MAX_VLANS
];
124 u8 vlan_table
[AR8X16_MAX_VLANS
];
126 u16 pvid
[AR8X16_MAX_PORTS
];
135 #define MIB_DESC(_s , _o, _n) \
142 static const struct ar8xxx_mib_desc ar8216_mibs
[] = {
143 MIB_DESC(1, AR8216_STATS_RXBROAD
, "RxBroad"),
144 MIB_DESC(1, AR8216_STATS_RXPAUSE
, "RxPause"),
145 MIB_DESC(1, AR8216_STATS_RXMULTI
, "RxMulti"),
146 MIB_DESC(1, AR8216_STATS_RXFCSERR
, "RxFcsErr"),
147 MIB_DESC(1, AR8216_STATS_RXALIGNERR
, "RxAlignErr"),
148 MIB_DESC(1, AR8216_STATS_RXRUNT
, "RxRunt"),
149 MIB_DESC(1, AR8216_STATS_RXFRAGMENT
, "RxFragment"),
150 MIB_DESC(1, AR8216_STATS_RX64BYTE
, "Rx64Byte"),
151 MIB_DESC(1, AR8216_STATS_RX128BYTE
, "Rx128Byte"),
152 MIB_DESC(1, AR8216_STATS_RX256BYTE
, "Rx256Byte"),
153 MIB_DESC(1, AR8216_STATS_RX512BYTE
, "Rx512Byte"),
154 MIB_DESC(1, AR8216_STATS_RX1024BYTE
, "Rx1024Byte"),
155 MIB_DESC(1, AR8216_STATS_RXMAXBYTE
, "RxMaxByte"),
156 MIB_DESC(1, AR8216_STATS_RXTOOLONG
, "RxTooLong"),
157 MIB_DESC(2, AR8216_STATS_RXGOODBYTE
, "RxGoodByte"),
158 MIB_DESC(2, AR8216_STATS_RXBADBYTE
, "RxBadByte"),
159 MIB_DESC(1, AR8216_STATS_RXOVERFLOW
, "RxOverFlow"),
160 MIB_DESC(1, AR8216_STATS_FILTERED
, "Filtered"),
161 MIB_DESC(1, AR8216_STATS_TXBROAD
, "TxBroad"),
162 MIB_DESC(1, AR8216_STATS_TXPAUSE
, "TxPause"),
163 MIB_DESC(1, AR8216_STATS_TXMULTI
, "TxMulti"),
164 MIB_DESC(1, AR8216_STATS_TXUNDERRUN
, "TxUnderRun"),
165 MIB_DESC(1, AR8216_STATS_TX64BYTE
, "Tx64Byte"),
166 MIB_DESC(1, AR8216_STATS_TX128BYTE
, "Tx128Byte"),
167 MIB_DESC(1, AR8216_STATS_TX256BYTE
, "Tx256Byte"),
168 MIB_DESC(1, AR8216_STATS_TX512BYTE
, "Tx512Byte"),
169 MIB_DESC(1, AR8216_STATS_TX1024BYTE
, "Tx1024Byte"),
170 MIB_DESC(1, AR8216_STATS_TXMAXBYTE
, "TxMaxByte"),
171 MIB_DESC(1, AR8216_STATS_TXOVERSIZE
, "TxOverSize"),
172 MIB_DESC(2, AR8216_STATS_TXBYTE
, "TxByte"),
173 MIB_DESC(1, AR8216_STATS_TXCOLLISION
, "TxCollision"),
174 MIB_DESC(1, AR8216_STATS_TXABORTCOL
, "TxAbortCol"),
175 MIB_DESC(1, AR8216_STATS_TXMULTICOL
, "TxMultiCol"),
176 MIB_DESC(1, AR8216_STATS_TXSINGLECOL
, "TxSingleCol"),
177 MIB_DESC(1, AR8216_STATS_TXEXCDEFER
, "TxExcDefer"),
178 MIB_DESC(1, AR8216_STATS_TXDEFER
, "TxDefer"),
179 MIB_DESC(1, AR8216_STATS_TXLATECOL
, "TxLateCol"),
182 static const struct ar8xxx_mib_desc ar8236_mibs
[] = {
183 MIB_DESC(1, AR8236_STATS_RXBROAD
, "RxBroad"),
184 MIB_DESC(1, AR8236_STATS_RXPAUSE
, "RxPause"),
185 MIB_DESC(1, AR8236_STATS_RXMULTI
, "RxMulti"),
186 MIB_DESC(1, AR8236_STATS_RXFCSERR
, "RxFcsErr"),
187 MIB_DESC(1, AR8236_STATS_RXALIGNERR
, "RxAlignErr"),
188 MIB_DESC(1, AR8236_STATS_RXRUNT
, "RxRunt"),
189 MIB_DESC(1, AR8236_STATS_RXFRAGMENT
, "RxFragment"),
190 MIB_DESC(1, AR8236_STATS_RX64BYTE
, "Rx64Byte"),
191 MIB_DESC(1, AR8236_STATS_RX128BYTE
, "Rx128Byte"),
192 MIB_DESC(1, AR8236_STATS_RX256BYTE
, "Rx256Byte"),
193 MIB_DESC(1, AR8236_STATS_RX512BYTE
, "Rx512Byte"),
194 MIB_DESC(1, AR8236_STATS_RX1024BYTE
, "Rx1024Byte"),
195 MIB_DESC(1, AR8236_STATS_RX1518BYTE
, "Rx1518Byte"),
196 MIB_DESC(1, AR8236_STATS_RXMAXBYTE
, "RxMaxByte"),
197 MIB_DESC(1, AR8236_STATS_RXTOOLONG
, "RxTooLong"),
198 MIB_DESC(2, AR8236_STATS_RXGOODBYTE
, "RxGoodByte"),
199 MIB_DESC(2, AR8236_STATS_RXBADBYTE
, "RxBadByte"),
200 MIB_DESC(1, AR8236_STATS_RXOVERFLOW
, "RxOverFlow"),
201 MIB_DESC(1, AR8236_STATS_FILTERED
, "Filtered"),
202 MIB_DESC(1, AR8236_STATS_TXBROAD
, "TxBroad"),
203 MIB_DESC(1, AR8236_STATS_TXPAUSE
, "TxPause"),
204 MIB_DESC(1, AR8236_STATS_TXMULTI
, "TxMulti"),
205 MIB_DESC(1, AR8236_STATS_TXUNDERRUN
, "TxUnderRun"),
206 MIB_DESC(1, AR8236_STATS_TX64BYTE
, "Tx64Byte"),
207 MIB_DESC(1, AR8236_STATS_TX128BYTE
, "Tx128Byte"),
208 MIB_DESC(1, AR8236_STATS_TX256BYTE
, "Tx256Byte"),
209 MIB_DESC(1, AR8236_STATS_TX512BYTE
, "Tx512Byte"),
210 MIB_DESC(1, AR8236_STATS_TX1024BYTE
, "Tx1024Byte"),
211 MIB_DESC(1, AR8236_STATS_TX1518BYTE
, "Tx1518Byte"),
212 MIB_DESC(1, AR8236_STATS_TXMAXBYTE
, "TxMaxByte"),
213 MIB_DESC(1, AR8236_STATS_TXOVERSIZE
, "TxOverSize"),
214 MIB_DESC(2, AR8236_STATS_TXBYTE
, "TxByte"),
215 MIB_DESC(1, AR8236_STATS_TXCOLLISION
, "TxCollision"),
216 MIB_DESC(1, AR8236_STATS_TXABORTCOL
, "TxAbortCol"),
217 MIB_DESC(1, AR8236_STATS_TXMULTICOL
, "TxMultiCol"),
218 MIB_DESC(1, AR8236_STATS_TXSINGLECOL
, "TxSingleCol"),
219 MIB_DESC(1, AR8236_STATS_TXEXCDEFER
, "TxExcDefer"),
220 MIB_DESC(1, AR8236_STATS_TXDEFER
, "TxDefer"),
221 MIB_DESC(1, AR8236_STATS_TXLATECOL
, "TxLateCol"),
224 static DEFINE_MUTEX(ar8xxx_dev_list_lock
);
225 static LIST_HEAD(ar8xxx_dev_list
);
227 static inline struct ar8xxx_priv
*
228 swdev_to_ar8xxx(struct switch_dev
*swdev
)
230 return container_of(swdev
, struct ar8xxx_priv
, dev
);
233 static inline bool ar8xxx_has_gige(struct ar8xxx_priv
*priv
)
235 return priv
->chip
->caps
& AR8XXX_CAP_GIGE
;
238 static inline bool ar8xxx_has_mib_counters(struct ar8xxx_priv
*priv
)
240 return priv
->chip
->caps
& AR8XXX_CAP_MIB_COUNTERS
;
243 static inline bool chip_is_ar8216(struct ar8xxx_priv
*priv
)
245 return priv
->chip_ver
== AR8XXX_VER_AR8216
;
248 static inline bool chip_is_ar8236(struct ar8xxx_priv
*priv
)
250 return priv
->chip_ver
== AR8XXX_VER_AR8236
;
253 static inline bool chip_is_ar8316(struct ar8xxx_priv
*priv
)
255 return priv
->chip_ver
== AR8XXX_VER_AR8316
;
258 static inline bool chip_is_ar8327(struct ar8xxx_priv
*priv
)
260 return priv
->chip_ver
== AR8XXX_VER_AR8327
;
264 split_addr(u32 regaddr
, u16
*r1
, u16
*r2
, u16
*page
)
267 *r1
= regaddr
& 0x1e;
273 *page
= regaddr
& 0x1ff;
277 ar8xxx_mii_read(struct ar8xxx_priv
*priv
, int reg
)
279 struct mii_bus
*bus
= priv
->mii_bus
;
283 split_addr((u32
) reg
, &r1
, &r2
, &page
);
285 mutex_lock(&bus
->mdio_lock
);
287 bus
->write(bus
, 0x18, 0, page
);
288 usleep_range(1000, 2000); /* wait for the page switch to propagate */
289 lo
= bus
->read(bus
, 0x10 | r2
, r1
);
290 hi
= bus
->read(bus
, 0x10 | r2
, r1
+ 1);
292 mutex_unlock(&bus
->mdio_lock
);
294 return (hi
<< 16) | lo
;
298 ar8xxx_mii_write(struct ar8xxx_priv
*priv
, int reg
, u32 val
)
300 struct mii_bus
*bus
= priv
->mii_bus
;
304 split_addr((u32
) reg
, &r1
, &r2
, &r3
);
306 hi
= (u16
) (val
>> 16);
308 mutex_lock(&bus
->mdio_lock
);
310 bus
->write(bus
, 0x18, 0, r3
);
311 usleep_range(1000, 2000); /* wait for the page switch to propagate */
312 if (priv
->mii_lo_first
) {
313 bus
->write(bus
, 0x10 | r2
, r1
, lo
);
314 bus
->write(bus
, 0x10 | r2
, r1
+ 1, hi
);
316 bus
->write(bus
, 0x10 | r2
, r1
+ 1, hi
);
317 bus
->write(bus
, 0x10 | r2
, r1
, lo
);
320 mutex_unlock(&bus
->mdio_lock
);
324 ar8xxx_phy_dbg_write(struct ar8xxx_priv
*priv
, int phy_addr
,
325 u16 dbg_addr
, u16 dbg_data
)
327 struct mii_bus
*bus
= priv
->mii_bus
;
329 mutex_lock(&bus
->mdio_lock
);
330 bus
->write(bus
, phy_addr
, MII_ATH_DBG_ADDR
, dbg_addr
);
331 bus
->write(bus
, phy_addr
, MII_ATH_DBG_DATA
, dbg_data
);
332 mutex_unlock(&bus
->mdio_lock
);
336 ar8xxx_phy_mmd_write(struct ar8xxx_priv
*priv
, int phy_addr
, u16 addr
, u16 data
)
338 struct mii_bus
*bus
= priv
->mii_bus
;
340 mutex_lock(&bus
->mdio_lock
);
341 bus
->write(bus
, phy_addr
, MII_ATH_MMD_ADDR
, addr
);
342 bus
->write(bus
, phy_addr
, MII_ATH_MMD_DATA
, data
);
343 mutex_unlock(&bus
->mdio_lock
);
347 ar8xxx_rmw(struct ar8xxx_priv
*priv
, int reg
, u32 mask
, u32 val
)
351 lockdep_assert_held(&priv
->reg_mutex
);
353 v
= priv
->read(priv
, reg
);
356 priv
->write(priv
, reg
, v
);
362 ar8xxx_reg_set(struct ar8xxx_priv
*priv
, int reg
, u32 val
)
366 lockdep_assert_held(&priv
->reg_mutex
);
368 v
= priv
->read(priv
, reg
);
370 priv
->write(priv
, reg
, v
);
374 ar8xxx_reg_wait(struct ar8xxx_priv
*priv
, u32 reg
, u32 mask
, u32 val
,
379 for (i
= 0; i
< timeout
; i
++) {
382 t
= priv
->read(priv
, reg
);
383 if ((t
& mask
) == val
)
386 usleep_range(1000, 2000);
393 ar8xxx_mib_op(struct ar8xxx_priv
*priv
, u32 op
)
398 lockdep_assert_held(&priv
->mib_lock
);
400 if (chip_is_ar8327(priv
))
401 mib_func
= AR8327_REG_MIB_FUNC
;
403 mib_func
= AR8216_REG_MIB_FUNC
;
405 mutex_lock(&priv
->reg_mutex
);
406 /* Capture the hardware statistics for all ports */
407 ar8xxx_rmw(priv
, mib_func
, AR8216_MIB_FUNC
, (op
<< AR8216_MIB_FUNC_S
));
408 mutex_unlock(&priv
->reg_mutex
);
410 /* Wait for the capturing to complete. */
411 ret
= ar8xxx_reg_wait(priv
, mib_func
, AR8216_MIB_BUSY
, 0, 10);
422 ar8xxx_mib_capture(struct ar8xxx_priv
*priv
)
424 return ar8xxx_mib_op(priv
, AR8216_MIB_FUNC_CAPTURE
);
428 ar8xxx_mib_flush(struct ar8xxx_priv
*priv
)
430 return ar8xxx_mib_op(priv
, AR8216_MIB_FUNC_FLUSH
);
434 ar8xxx_mib_fetch_port_stat(struct ar8xxx_priv
*priv
, int port
, bool flush
)
440 WARN_ON(port
>= priv
->dev
.ports
);
442 lockdep_assert_held(&priv
->mib_lock
);
444 if (chip_is_ar8327(priv
))
445 base
= AR8327_REG_PORT_STATS_BASE(port
);
446 else if (chip_is_ar8236(priv
) ||
447 chip_is_ar8316(priv
))
448 base
= AR8236_REG_PORT_STATS_BASE(port
);
450 base
= AR8216_REG_PORT_STATS_BASE(port
);
452 mib_stats
= &priv
->mib_stats
[port
* priv
->chip
->num_mibs
];
453 for (i
= 0; i
< priv
->chip
->num_mibs
; i
++) {
454 const struct ar8xxx_mib_desc
*mib
;
457 mib
= &priv
->chip
->mib_decs
[i
];
458 t
= priv
->read(priv
, base
+ mib
->offset
);
459 if (mib
->size
== 2) {
462 hi
= priv
->read(priv
, base
+ mib
->offset
+ 4);
474 ar8216_read_port_link(struct ar8xxx_priv
*priv
, int port
,
475 struct switch_port_link
*link
)
480 memset(link
, '\0', sizeof(*link
));
482 status
= priv
->chip
->read_port_status(priv
, port
);
484 link
->aneg
= !!(status
& AR8216_PORT_STATUS_LINK_AUTO
);
486 link
->link
= !!(status
& AR8216_PORT_STATUS_LINK_UP
);
490 if (priv
->get_port_link
) {
493 err
= priv
->get_port_link(port
);
502 link
->duplex
= !!(status
& AR8216_PORT_STATUS_DUPLEX
);
503 link
->tx_flow
= !!(status
& AR8216_PORT_STATUS_TXFLOW
);
504 link
->rx_flow
= !!(status
& AR8216_PORT_STATUS_RXFLOW
);
506 speed
= (status
& AR8216_PORT_STATUS_SPEED
) >>
507 AR8216_PORT_STATUS_SPEED_S
;
510 case AR8216_PORT_SPEED_10M
:
511 link
->speed
= SWITCH_PORT_SPEED_10
;
513 case AR8216_PORT_SPEED_100M
:
514 link
->speed
= SWITCH_PORT_SPEED_100
;
516 case AR8216_PORT_SPEED_1000M
:
517 link
->speed
= SWITCH_PORT_SPEED_1000
;
520 link
->speed
= SWITCH_PORT_SPEED_UNKNOWN
;
525 static struct sk_buff
*
526 ar8216_mangle_tx(struct net_device
*dev
, struct sk_buff
*skb
)
528 struct ar8xxx_priv
*priv
= dev
->phy_ptr
;
537 if (unlikely(skb_headroom(skb
) < 2)) {
538 if (pskb_expand_head(skb
, 2, 0, GFP_ATOMIC
) < 0)
542 buf
= skb_push(skb
, 2);
550 dev_kfree_skb_any(skb
);
555 ar8216_mangle_rx(struct net_device
*dev
, struct sk_buff
*skb
)
557 struct ar8xxx_priv
*priv
;
565 /* don't strip the header if vlan mode is disabled */
569 /* strip header, get vlan id */
573 /* check for vlan header presence */
574 if ((buf
[12 + 2] != 0x81) || (buf
[13 + 2] != 0x00))
579 /* no need to fix up packets coming from a tagged source */
580 if (priv
->vlan_tagged
& (1 << port
))
583 /* lookup port vid from local table, the switch passes an invalid vlan id */
584 vlan
= priv
->vlan_id
[priv
->pvid
[port
]];
587 buf
[14 + 2] |= vlan
>> 8;
588 buf
[15 + 2] = vlan
& 0xff;
592 ar8216_wait_bit(struct ar8xxx_priv
*priv
, int reg
, u32 mask
, u32 val
)
598 t
= priv
->read(priv
, reg
);
599 if ((t
& mask
) == val
)
608 pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
609 (unsigned int) reg
, t
, mask
, val
);
614 ar8216_vtu_op(struct ar8xxx_priv
*priv
, u32 op
, u32 val
)
616 if (ar8216_wait_bit(priv
, AR8216_REG_VTU
, AR8216_VTU_ACTIVE
, 0))
618 if ((op
& AR8216_VTU_OP
) == AR8216_VTU_OP_LOAD
) {
619 val
&= AR8216_VTUDATA_MEMBER
;
620 val
|= AR8216_VTUDATA_VALID
;
621 priv
->write(priv
, AR8216_REG_VTU_DATA
, val
);
623 op
|= AR8216_VTU_ACTIVE
;
624 priv
->write(priv
, AR8216_REG_VTU
, op
);
628 ar8216_vtu_flush(struct ar8xxx_priv
*priv
)
630 ar8216_vtu_op(priv
, AR8216_VTU_OP_FLUSH
, 0);
634 ar8216_vtu_load_vlan(struct ar8xxx_priv
*priv
, u32 vid
, u32 port_mask
)
638 op
= AR8216_VTU_OP_LOAD
| (vid
<< AR8216_VTU_VID_S
);
639 ar8216_vtu_op(priv
, op
, port_mask
);
643 ar8216_atu_flush(struct ar8xxx_priv
*priv
)
647 ret
= ar8216_wait_bit(priv
, AR8216_REG_ATU
, AR8216_ATU_ACTIVE
, 0);
649 priv
->write(priv
, AR8216_REG_ATU
, AR8216_ATU_OP_FLUSH
);
655 ar8216_read_port_status(struct ar8xxx_priv
*priv
, int port
)
657 return priv
->read(priv
, AR8216_REG_PORT_STATUS(port
));
661 ar8216_setup_port(struct ar8xxx_priv
*priv
, int port
, u32 egress
, u32 ingress
,
662 u32 members
, u32 pvid
)
666 if (chip_is_ar8216(priv
) && priv
->vlan
&& port
== AR8216_PORT_CPU
)
667 header
= AR8216_PORT_CTRL_HEADER
;
671 ar8xxx_rmw(priv
, AR8216_REG_PORT_CTRL(port
),
672 AR8216_PORT_CTRL_LEARN
| AR8216_PORT_CTRL_VLAN_MODE
|
673 AR8216_PORT_CTRL_SINGLE_VLAN
| AR8216_PORT_CTRL_STATE
|
674 AR8216_PORT_CTRL_HEADER
| AR8216_PORT_CTRL_LEARN_LOCK
,
675 AR8216_PORT_CTRL_LEARN
| header
|
676 (egress
<< AR8216_PORT_CTRL_VLAN_MODE_S
) |
677 (AR8216_PORT_STATE_FORWARD
<< AR8216_PORT_CTRL_STATE_S
));
679 ar8xxx_rmw(priv
, AR8216_REG_PORT_VLAN(port
),
680 AR8216_PORT_VLAN_DEST_PORTS
| AR8216_PORT_VLAN_MODE
|
681 AR8216_PORT_VLAN_DEFAULT_ID
,
682 (members
<< AR8216_PORT_VLAN_DEST_PORTS_S
) |
683 (ingress
<< AR8216_PORT_VLAN_MODE_S
) |
684 (pvid
<< AR8216_PORT_VLAN_DEFAULT_ID_S
));
688 ar8216_hw_init(struct ar8xxx_priv
*priv
)
694 ar8216_init_globals(struct ar8xxx_priv
*priv
)
696 /* standard atheros magic */
697 priv
->write(priv
, 0x38, 0xc000050e);
699 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
700 AR8216_GCTRL_MTU
, 1518 + 8 + 2);
704 ar8216_init_port(struct ar8xxx_priv
*priv
, int port
)
706 /* Enable port learning and tx */
707 priv
->write(priv
, AR8216_REG_PORT_CTRL(port
),
708 AR8216_PORT_CTRL_LEARN
|
709 (4 << AR8216_PORT_CTRL_STATE_S
));
711 priv
->write(priv
, AR8216_REG_PORT_VLAN(port
), 0);
713 if (port
== AR8216_PORT_CPU
) {
714 priv
->write(priv
, AR8216_REG_PORT_STATUS(port
),
715 AR8216_PORT_STATUS_LINK_UP
|
716 (ar8xxx_has_gige(priv
) ?
717 AR8216_PORT_SPEED_1000M
: AR8216_PORT_SPEED_100M
) |
718 AR8216_PORT_STATUS_TXMAC
|
719 AR8216_PORT_STATUS_RXMAC
|
720 (chip_is_ar8316(priv
) ? AR8216_PORT_STATUS_RXFLOW
: 0) |
721 (chip_is_ar8316(priv
) ? AR8216_PORT_STATUS_TXFLOW
: 0) |
722 AR8216_PORT_STATUS_DUPLEX
);
724 priv
->write(priv
, AR8216_REG_PORT_STATUS(port
),
725 AR8216_PORT_STATUS_LINK_AUTO
);
729 static const struct ar8xxx_chip ar8216_chip
= {
730 .caps
= AR8XXX_CAP_MIB_COUNTERS
,
732 .hw_init
= ar8216_hw_init
,
733 .init_globals
= ar8216_init_globals
,
734 .init_port
= ar8216_init_port
,
735 .setup_port
= ar8216_setup_port
,
736 .read_port_status
= ar8216_read_port_status
,
737 .atu_flush
= ar8216_atu_flush
,
738 .vtu_flush
= ar8216_vtu_flush
,
739 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
741 .num_mibs
= ARRAY_SIZE(ar8216_mibs
),
742 .mib_decs
= ar8216_mibs
,
746 ar8236_setup_port(struct ar8xxx_priv
*priv
, int port
, u32 egress
, u32 ingress
,
747 u32 members
, u32 pvid
)
749 ar8xxx_rmw(priv
, AR8216_REG_PORT_CTRL(port
),
750 AR8216_PORT_CTRL_LEARN
| AR8216_PORT_CTRL_VLAN_MODE
|
751 AR8216_PORT_CTRL_SINGLE_VLAN
| AR8216_PORT_CTRL_STATE
|
752 AR8216_PORT_CTRL_HEADER
| AR8216_PORT_CTRL_LEARN_LOCK
,
753 AR8216_PORT_CTRL_LEARN
|
754 (egress
<< AR8216_PORT_CTRL_VLAN_MODE_S
) |
755 (AR8216_PORT_STATE_FORWARD
<< AR8216_PORT_CTRL_STATE_S
));
757 ar8xxx_rmw(priv
, AR8236_REG_PORT_VLAN(port
),
758 AR8236_PORT_VLAN_DEFAULT_ID
,
759 (pvid
<< AR8236_PORT_VLAN_DEFAULT_ID_S
));
761 ar8xxx_rmw(priv
, AR8236_REG_PORT_VLAN2(port
),
762 AR8236_PORT_VLAN2_VLAN_MODE
|
763 AR8236_PORT_VLAN2_MEMBER
,
764 (ingress
<< AR8236_PORT_VLAN2_VLAN_MODE_S
) |
765 (members
<< AR8236_PORT_VLAN2_MEMBER_S
));
769 ar8236_hw_init(struct ar8xxx_priv
*priv
)
774 if (priv
->initialized
)
777 /* Initialize the PHYs */
779 for (i
= 0; i
< 5; i
++) {
780 mdiobus_write(bus
, i
, MII_ADVERTISE
,
781 ADVERTISE_ALL
| ADVERTISE_PAUSE_CAP
|
782 ADVERTISE_PAUSE_ASYM
);
783 mdiobus_write(bus
, i
, MII_BMCR
, BMCR_RESET
| BMCR_ANENABLE
);
787 priv
->initialized
= true;
792 ar8236_init_globals(struct ar8xxx_priv
*priv
)
794 /* enable jumbo frames */
795 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
796 AR8316_GCTRL_MTU
, 9018 + 8 + 2);
798 /* Enable MIB counters */
799 ar8xxx_rmw(priv
, AR8216_REG_MIB_FUNC
, AR8216_MIB_FUNC
| AR8236_MIB_EN
,
800 (AR8216_MIB_FUNC_NO_OP
<< AR8216_MIB_FUNC_S
) |
804 static const struct ar8xxx_chip ar8236_chip
= {
805 .caps
= AR8XXX_CAP_MIB_COUNTERS
,
806 .hw_init
= ar8236_hw_init
,
807 .init_globals
= ar8236_init_globals
,
808 .init_port
= ar8216_init_port
,
809 .setup_port
= ar8236_setup_port
,
810 .read_port_status
= ar8216_read_port_status
,
811 .atu_flush
= ar8216_atu_flush
,
812 .vtu_flush
= ar8216_vtu_flush
,
813 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
815 .num_mibs
= ARRAY_SIZE(ar8236_mibs
),
816 .mib_decs
= ar8236_mibs
,
820 ar8316_hw_init(struct ar8xxx_priv
*priv
)
826 val
= priv
->read(priv
, AR8316_REG_POSTRIP
);
828 if (priv
->phy
->interface
== PHY_INTERFACE_MODE_RGMII
) {
829 if (priv
->port4_phy
) {
830 /* value taken from Ubiquiti RouterStation Pro */
832 pr_info("ar8316: Using port 4 as PHY\n");
835 pr_info("ar8316: Using port 4 as switch port\n");
837 } else if (priv
->phy
->interface
== PHY_INTERFACE_MODE_GMII
) {
838 /* value taken from AVM Fritz!Box 7390 sources */
841 /* no known value for phy interface */
842 pr_err("ar8316: unsupported mii mode: %d.\n",
843 priv
->phy
->interface
);
850 priv
->write(priv
, AR8316_REG_POSTRIP
, newval
);
852 if (priv
->port4_phy
&&
853 priv
->phy
->interface
== PHY_INTERFACE_MODE_RGMII
) {
854 /* work around for phy4 rgmii mode */
855 ar8xxx_phy_dbg_write(priv
, 4, 0x12, 0x480c);
857 ar8xxx_phy_dbg_write(priv
, 4, 0x0, 0x824e);
859 ar8xxx_phy_dbg_write(priv
, 4, 0x5, 0x3d47);
863 /* Initialize the ports */
865 for (i
= 0; i
< 5; i
++) {
866 /* initialize the port itself */
867 mdiobus_write(bus
, i
, MII_ADVERTISE
,
868 ADVERTISE_ALL
| ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
);
869 mdiobus_write(bus
, i
, MII_CTRL1000
, ADVERTISE_1000FULL
);
870 mdiobus_write(bus
, i
, MII_BMCR
, BMCR_RESET
| BMCR_ANENABLE
);
876 priv
->initialized
= true;
881 ar8316_init_globals(struct ar8xxx_priv
*priv
)
883 /* standard atheros magic */
884 priv
->write(priv
, 0x38, 0xc000050e);
886 /* enable cpu port to receive multicast and broadcast frames */
887 priv
->write(priv
, AR8216_REG_FLOOD_MASK
, 0x003f003f);
889 /* enable jumbo frames */
890 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
891 AR8316_GCTRL_MTU
, 9018 + 8 + 2);
893 /* Enable MIB counters */
894 ar8xxx_rmw(priv
, AR8216_REG_MIB_FUNC
, AR8216_MIB_FUNC
| AR8236_MIB_EN
,
895 (AR8216_MIB_FUNC_NO_OP
<< AR8216_MIB_FUNC_S
) |
899 static const struct ar8xxx_chip ar8316_chip
= {
900 .caps
= AR8XXX_CAP_GIGE
| AR8XXX_CAP_MIB_COUNTERS
,
901 .hw_init
= ar8316_hw_init
,
902 .init_globals
= ar8316_init_globals
,
903 .init_port
= ar8216_init_port
,
904 .setup_port
= ar8216_setup_port
,
905 .read_port_status
= ar8216_read_port_status
,
906 .atu_flush
= ar8216_atu_flush
,
907 .vtu_flush
= ar8216_vtu_flush
,
908 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
910 .num_mibs
= ARRAY_SIZE(ar8236_mibs
),
911 .mib_decs
= ar8236_mibs
,
915 ar8327_get_pad_cfg(struct ar8327_pad_cfg
*cfg
)
927 case AR8327_PAD_MAC2MAC_MII
:
928 t
= AR8327_PAD_MAC_MII_EN
;
930 t
|= AR8327_PAD_MAC_MII_RXCLK_SEL
;
932 t
|= AR8327_PAD_MAC_MII_TXCLK_SEL
;
935 case AR8327_PAD_MAC2MAC_GMII
:
936 t
= AR8327_PAD_MAC_GMII_EN
;
938 t
|= AR8327_PAD_MAC_GMII_RXCLK_SEL
;
940 t
|= AR8327_PAD_MAC_GMII_TXCLK_SEL
;
943 case AR8327_PAD_MAC_SGMII
:
944 t
= AR8327_PAD_SGMII_EN
;
947 * WAR for the QUalcomm Atheros AP136 board.
948 * It seems that RGMII TX/RX delay settings needs to be
949 * applied for SGMII mode as well, The ethernet is not
950 * reliable without this.
952 t
|= cfg
->txclk_delay_sel
<< AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S
;
953 t
|= cfg
->rxclk_delay_sel
<< AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S
;
954 if (cfg
->rxclk_delay_en
)
955 t
|= AR8327_PAD_RGMII_RXCLK_DELAY_EN
;
956 if (cfg
->txclk_delay_en
)
957 t
|= AR8327_PAD_RGMII_TXCLK_DELAY_EN
;
959 if (cfg
->sgmii_delay_en
)
960 t
|= AR8327_PAD_SGMII_DELAY_EN
;
964 case AR8327_PAD_MAC2PHY_MII
:
965 t
= AR8327_PAD_PHY_MII_EN
;
967 t
|= AR8327_PAD_PHY_MII_RXCLK_SEL
;
969 t
|= AR8327_PAD_PHY_MII_TXCLK_SEL
;
972 case AR8327_PAD_MAC2PHY_GMII
:
973 t
= AR8327_PAD_PHY_GMII_EN
;
974 if (cfg
->pipe_rxclk_sel
)
975 t
|= AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL
;
977 t
|= AR8327_PAD_PHY_GMII_RXCLK_SEL
;
979 t
|= AR8327_PAD_PHY_GMII_TXCLK_SEL
;
982 case AR8327_PAD_MAC_RGMII
:
983 t
= AR8327_PAD_RGMII_EN
;
984 t
|= cfg
->txclk_delay_sel
<< AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S
;
985 t
|= cfg
->rxclk_delay_sel
<< AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S
;
986 if (cfg
->rxclk_delay_en
)
987 t
|= AR8327_PAD_RGMII_RXCLK_DELAY_EN
;
988 if (cfg
->txclk_delay_en
)
989 t
|= AR8327_PAD_RGMII_TXCLK_DELAY_EN
;
992 case AR8327_PAD_PHY_GMII
:
993 t
= AR8327_PAD_PHYX_GMII_EN
;
996 case AR8327_PAD_PHY_RGMII
:
997 t
= AR8327_PAD_PHYX_RGMII_EN
;
1000 case AR8327_PAD_PHY_MII
:
1001 t
= AR8327_PAD_PHYX_MII_EN
;
1009 ar8327_phy_fixup(struct ar8xxx_priv
*priv
, int phy
)
1011 switch (priv
->chip_rev
) {
1013 /* For 100M waveform */
1014 ar8xxx_phy_dbg_write(priv
, phy
, 0, 0x02ea);
1015 /* Turn on Gigabit clock */
1016 ar8xxx_phy_dbg_write(priv
, phy
, 0x3d, 0x68a0);
1020 ar8xxx_phy_mmd_write(priv
, phy
, 0x7, 0x3c);
1021 ar8xxx_phy_mmd_write(priv
, phy
, 0x4007, 0x0);
1024 ar8xxx_phy_mmd_write(priv
, phy
, 0x3, 0x800d);
1025 ar8xxx_phy_mmd_write(priv
, phy
, 0x4003, 0x803f);
1027 ar8xxx_phy_dbg_write(priv
, phy
, 0x3d, 0x6860);
1028 ar8xxx_phy_dbg_write(priv
, phy
, 0x5, 0x2c46);
1029 ar8xxx_phy_dbg_write(priv
, phy
, 0x3c, 0x6000);
1035 ar8327_get_port_init_status(struct ar8327_port_cfg
*cfg
)
1039 if (!cfg
->force_link
)
1040 return AR8216_PORT_STATUS_LINK_AUTO
;
1042 t
= AR8216_PORT_STATUS_TXMAC
| AR8216_PORT_STATUS_RXMAC
;
1043 t
|= cfg
->duplex
? AR8216_PORT_STATUS_DUPLEX
: 0;
1044 t
|= cfg
->rxpause
? AR8216_PORT_STATUS_RXFLOW
: 0;
1045 t
|= cfg
->txpause
? AR8216_PORT_STATUS_TXFLOW
: 0;
1047 switch (cfg
->speed
) {
1048 case AR8327_PORT_SPEED_10
:
1049 t
|= AR8216_PORT_SPEED_10M
;
1051 case AR8327_PORT_SPEED_100
:
1052 t
|= AR8216_PORT_SPEED_100M
;
1054 case AR8327_PORT_SPEED_1000
:
1055 t
|= AR8216_PORT_SPEED_1000M
;
1063 ar8327_hw_config_pdata(struct ar8xxx_priv
*priv
,
1064 struct ar8327_platform_data
*pdata
)
1066 struct ar8327_led_cfg
*led_cfg
;
1067 struct ar8327_data
*data
;
1074 priv
->get_port_link
= pdata
->get_port_link
;
1076 data
= &priv
->chip_data
.ar8327
;
1078 data
->port0_status
= ar8327_get_port_init_status(&pdata
->port0_cfg
);
1079 data
->port6_status
= ar8327_get_port_init_status(&pdata
->port6_cfg
);
1081 t
= ar8327_get_pad_cfg(pdata
->pad0_cfg
);
1082 priv
->write(priv
, AR8327_REG_PAD0_MODE
, t
);
1083 t
= ar8327_get_pad_cfg(pdata
->pad5_cfg
);
1084 priv
->write(priv
, AR8327_REG_PAD5_MODE
, t
);
1085 t
= ar8327_get_pad_cfg(pdata
->pad6_cfg
);
1086 priv
->write(priv
, AR8327_REG_PAD6_MODE
, t
);
1088 pos
= priv
->read(priv
, AR8327_REG_POWER_ON_STRIP
);
1091 led_cfg
= pdata
->led_cfg
;
1093 if (led_cfg
->open_drain
)
1094 new_pos
|= AR8327_POWER_ON_STRIP_LED_OPEN_EN
;
1096 new_pos
&= ~AR8327_POWER_ON_STRIP_LED_OPEN_EN
;
1098 priv
->write(priv
, AR8327_REG_LED_CTRL0
, led_cfg
->led_ctrl0
);
1099 priv
->write(priv
, AR8327_REG_LED_CTRL1
, led_cfg
->led_ctrl1
);
1100 priv
->write(priv
, AR8327_REG_LED_CTRL2
, led_cfg
->led_ctrl2
);
1101 priv
->write(priv
, AR8327_REG_LED_CTRL3
, led_cfg
->led_ctrl3
);
1104 if (new_pos
!= pos
) {
1105 new_pos
|= AR8327_POWER_ON_STRIP_POWER_ON_SEL
;
1106 priv
->write(priv
, AR8327_REG_POWER_ON_STRIP
, new_pos
);
1114 ar8327_hw_config_of(struct ar8xxx_priv
*priv
, struct device_node
*np
)
1116 const __be32
*paddr
;
1120 paddr
= of_get_property(np
, "qca,ar8327-initvals", &len
);
1121 if (!paddr
|| len
< (2 * sizeof(*paddr
)))
1124 len
/= sizeof(*paddr
);
1126 for (i
= 0; i
< len
- 1; i
+= 2) {
1130 reg
= be32_to_cpup(paddr
+ i
);
1131 val
= be32_to_cpup(paddr
+ i
+ 1);
1134 case AR8327_REG_PORT_STATUS(0):
1135 priv
->chip_data
.ar8327
.port0_status
= val
;
1137 case AR8327_REG_PORT_STATUS(6):
1138 priv
->chip_data
.ar8327
.port6_status
= val
;
1141 priv
->write(priv
, reg
, val
);
1150 ar8327_hw_config_of(struct ar8xxx_priv
*priv
, struct device_node
*np
)
1157 ar8327_hw_init(struct ar8xxx_priv
*priv
)
1159 struct mii_bus
*bus
;
1163 if (priv
->phy
->dev
.of_node
)
1164 ret
= ar8327_hw_config_of(priv
, priv
->phy
->dev
.of_node
);
1166 ret
= ar8327_hw_config_pdata(priv
,
1167 priv
->phy
->dev
.platform_data
);
1172 bus
= priv
->mii_bus
;
1173 for (i
= 0; i
< AR8327_NUM_PHYS
; i
++) {
1174 ar8327_phy_fixup(priv
, i
);
1176 /* start aneg on the PHY */
1177 mdiobus_write(bus
, i
, MII_ADVERTISE
, ADVERTISE_ALL
|
1178 ADVERTISE_PAUSE_CAP
|
1179 ADVERTISE_PAUSE_ASYM
);
1180 mdiobus_write(bus
, i
, MII_CTRL1000
, ADVERTISE_1000FULL
);
1181 mdiobus_write(bus
, i
, MII_BMCR
, BMCR_RESET
| BMCR_ANENABLE
);
1190 ar8327_init_globals(struct ar8xxx_priv
*priv
)
1194 /* enable CPU port and disable mirror port */
1195 t
= AR8327_FWD_CTRL0_CPU_PORT_EN
|
1196 AR8327_FWD_CTRL0_MIRROR_PORT
;
1197 priv
->write(priv
, AR8327_REG_FWD_CTRL0
, t
);
1199 /* forward multicast and broadcast frames to CPU */
1200 t
= (AR8327_PORTS_ALL
<< AR8327_FWD_CTRL1_UC_FLOOD_S
) |
1201 (AR8327_PORTS_ALL
<< AR8327_FWD_CTRL1_MC_FLOOD_S
) |
1202 (AR8327_PORTS_ALL
<< AR8327_FWD_CTRL1_BC_FLOOD_S
);
1203 priv
->write(priv
, AR8327_REG_FWD_CTRL1
, t
);
1206 ar8xxx_rmw(priv
, AR8327_REG_MAX_FRAME_SIZE
,
1207 AR8327_MAX_FRAME_SIZE_MTU
, 1518 + 8 + 2);
1209 /* Enable MIB counters */
1210 ar8xxx_reg_set(priv
, AR8327_REG_MODULE_EN
,
1211 AR8327_MODULE_EN_MIB
);
1215 ar8327_init_port(struct ar8xxx_priv
*priv
, int port
)
1219 if (port
== AR8216_PORT_CPU
)
1220 t
= priv
->chip_data
.ar8327
.port0_status
;
1222 t
= priv
->chip_data
.ar8327
.port6_status
;
1224 t
= AR8216_PORT_STATUS_LINK_AUTO
;
1226 priv
->write(priv
, AR8327_REG_PORT_STATUS(port
), t
);
1227 priv
->write(priv
, AR8327_REG_PORT_HEADER(port
), 0);
1229 t
= 1 << AR8327_PORT_VLAN0_DEF_SVID_S
;
1230 t
|= 1 << AR8327_PORT_VLAN0_DEF_CVID_S
;
1231 priv
->write(priv
, AR8327_REG_PORT_VLAN0(port
), t
);
1233 t
= AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH
<< AR8327_PORT_VLAN1_OUT_MODE_S
;
1234 priv
->write(priv
, AR8327_REG_PORT_VLAN1(port
), t
);
1236 t
= AR8327_PORT_LOOKUP_LEARN
;
1237 t
|= AR8216_PORT_STATE_FORWARD
<< AR8327_PORT_LOOKUP_STATE_S
;
1238 priv
->write(priv
, AR8327_REG_PORT_LOOKUP(port
), t
);
1242 ar8327_read_port_status(struct ar8xxx_priv
*priv
, int port
)
1244 return priv
->read(priv
, AR8327_REG_PORT_STATUS(port
));
1248 ar8327_atu_flush(struct ar8xxx_priv
*priv
)
1252 ret
= ar8216_wait_bit(priv
, AR8327_REG_ATU_FUNC
,
1253 AR8327_ATU_FUNC_BUSY
, 0);
1255 priv
->write(priv
, AR8327_REG_ATU_FUNC
,
1256 AR8327_ATU_FUNC_OP_FLUSH
);
1262 ar8327_vtu_op(struct ar8xxx_priv
*priv
, u32 op
, u32 val
)
1264 if (ar8216_wait_bit(priv
, AR8327_REG_VTU_FUNC1
,
1265 AR8327_VTU_FUNC1_BUSY
, 0))
1268 if ((op
& AR8327_VTU_FUNC1_OP
) == AR8327_VTU_FUNC1_OP_LOAD
)
1269 priv
->write(priv
, AR8327_REG_VTU_FUNC0
, val
);
1271 op
|= AR8327_VTU_FUNC1_BUSY
;
1272 priv
->write(priv
, AR8327_REG_VTU_FUNC1
, op
);
1276 ar8327_vtu_flush(struct ar8xxx_priv
*priv
)
1278 ar8327_vtu_op(priv
, AR8327_VTU_FUNC1_OP_FLUSH
, 0);
1282 ar8327_vtu_load_vlan(struct ar8xxx_priv
*priv
, u32 vid
, u32 port_mask
)
1288 op
= AR8327_VTU_FUNC1_OP_LOAD
| (vid
<< AR8327_VTU_FUNC1_VID_S
);
1289 val
= AR8327_VTU_FUNC0_VALID
| AR8327_VTU_FUNC0_IVL
;
1290 for (i
= 0; i
< AR8327_NUM_PORTS
; i
++) {
1293 if ((port_mask
& BIT(i
)) == 0)
1294 mode
= AR8327_VTU_FUNC0_EG_MODE_NOT
;
1295 else if (priv
->vlan
== 0)
1296 mode
= AR8327_VTU_FUNC0_EG_MODE_KEEP
;
1297 else if (priv
->vlan_tagged
& BIT(i
))
1298 mode
= AR8327_VTU_FUNC0_EG_MODE_TAG
;
1300 mode
= AR8327_VTU_FUNC0_EG_MODE_UNTAG
;
1302 val
|= mode
<< AR8327_VTU_FUNC0_EG_MODE_S(i
);
1304 ar8327_vtu_op(priv
, op
, val
);
1308 ar8327_setup_port(struct ar8xxx_priv
*priv
, int port
, u32 egress
, u32 ingress
,
1309 u32 members
, u32 pvid
)
1314 t
= pvid
<< AR8327_PORT_VLAN0_DEF_SVID_S
;
1315 t
|= pvid
<< AR8327_PORT_VLAN0_DEF_CVID_S
;
1316 priv
->write(priv
, AR8327_REG_PORT_VLAN0(port
), t
);
1318 mode
= AR8327_PORT_VLAN1_OUT_MODE_UNMOD
;
1320 case AR8216_OUT_KEEP
:
1321 mode
= AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH
;
1323 case AR8216_OUT_STRIP_VLAN
:
1324 mode
= AR8327_PORT_VLAN1_OUT_MODE_UNTAG
;
1326 case AR8216_OUT_ADD_VLAN
:
1327 mode
= AR8327_PORT_VLAN1_OUT_MODE_TAG
;
1331 t
= AR8327_PORT_VLAN1_PORT_VLAN_PROP
;
1332 t
|= mode
<< AR8327_PORT_VLAN1_OUT_MODE_S
;
1333 priv
->write(priv
, AR8327_REG_PORT_VLAN1(port
), t
);
1336 t
|= AR8327_PORT_LOOKUP_LEARN
;
1337 t
|= ingress
<< AR8327_PORT_LOOKUP_IN_MODE_S
;
1338 t
|= AR8216_PORT_STATE_FORWARD
<< AR8327_PORT_LOOKUP_STATE_S
;
1339 priv
->write(priv
, AR8327_REG_PORT_LOOKUP(port
), t
);
1342 static const struct ar8xxx_chip ar8327_chip
= {
1343 .caps
= AR8XXX_CAP_GIGE
| AR8XXX_CAP_MIB_COUNTERS
,
1344 .hw_init
= ar8327_hw_init
,
1345 .init_globals
= ar8327_init_globals
,
1346 .init_port
= ar8327_init_port
,
1347 .setup_port
= ar8327_setup_port
,
1348 .read_port_status
= ar8327_read_port_status
,
1349 .atu_flush
= ar8327_atu_flush
,
1350 .vtu_flush
= ar8327_vtu_flush
,
1351 .vtu_load_vlan
= ar8327_vtu_load_vlan
,
1353 .num_mibs
= ARRAY_SIZE(ar8236_mibs
),
1354 .mib_decs
= ar8236_mibs
,
1358 ar8xxx_sw_set_vlan(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1359 struct switch_val
*val
)
1361 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1362 priv
->vlan
= !!val
->value
.i
;
1367 ar8xxx_sw_get_vlan(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1368 struct switch_val
*val
)
1370 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1371 val
->value
.i
= priv
->vlan
;
1377 ar8xxx_sw_set_pvid(struct switch_dev
*dev
, int port
, int vlan
)
1379 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1381 /* make sure no invalid PVIDs get set */
1383 if (vlan
>= dev
->vlans
)
1386 priv
->pvid
[port
] = vlan
;
1391 ar8xxx_sw_get_pvid(struct switch_dev
*dev
, int port
, int *vlan
)
1393 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1394 *vlan
= priv
->pvid
[port
];
1399 ar8xxx_sw_set_vid(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1400 struct switch_val
*val
)
1402 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1403 priv
->vlan_id
[val
->port_vlan
] = val
->value
.i
;
1408 ar8xxx_sw_get_vid(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1409 struct switch_val
*val
)
1411 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1412 val
->value
.i
= priv
->vlan_id
[val
->port_vlan
];
1417 ar8xxx_sw_get_port_link(struct switch_dev
*dev
, int port
,
1418 struct switch_port_link
*link
)
1420 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1422 ar8216_read_port_link(priv
, port
, link
);
1427 ar8xxx_sw_get_ports(struct switch_dev
*dev
, struct switch_val
*val
)
1429 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1430 u8 ports
= priv
->vlan_table
[val
->port_vlan
];
1434 for (i
= 0; i
< dev
->ports
; i
++) {
1435 struct switch_port
*p
;
1437 if (!(ports
& (1 << i
)))
1440 p
= &val
->value
.ports
[val
->len
++];
1442 if (priv
->vlan_tagged
& (1 << i
))
1443 p
->flags
= (1 << SWITCH_PORT_FLAG_TAGGED
);
1451 ar8xxx_sw_set_ports(struct switch_dev
*dev
, struct switch_val
*val
)
1453 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1454 u8
*vt
= &priv
->vlan_table
[val
->port_vlan
];
1458 for (i
= 0; i
< val
->len
; i
++) {
1459 struct switch_port
*p
= &val
->value
.ports
[i
];
1461 if (p
->flags
& (1 << SWITCH_PORT_FLAG_TAGGED
)) {
1462 priv
->vlan_tagged
|= (1 << p
->id
);
1464 priv
->vlan_tagged
&= ~(1 << p
->id
);
1465 priv
->pvid
[p
->id
] = val
->port_vlan
;
1467 /* make sure that an untagged port does not
1468 * appear in other vlans */
1469 for (j
= 0; j
< AR8X16_MAX_VLANS
; j
++) {
1470 if (j
== val
->port_vlan
)
1472 priv
->vlan_table
[j
] &= ~(1 << p
->id
);
1482 ar8327_set_mirror_regs(struct ar8xxx_priv
*priv
)
1486 /* reset all mirror registers */
1487 ar8xxx_rmw(priv
, AR8327_REG_FWD_CTRL0
,
1488 AR8327_FWD_CTRL0_MIRROR_PORT
,
1489 (0xF << AR8327_FWD_CTRL0_MIRROR_PORT_S
));
1490 for (port
= 0; port
< AR8327_NUM_PORTS
; port
++) {
1491 ar8xxx_rmw(priv
, AR8327_REG_PORT_LOOKUP(port
),
1492 AR8327_PORT_LOOKUP_ING_MIRROR_EN
,
1495 ar8xxx_rmw(priv
, AR8327_REG_PORT_HOL_CTRL1(port
),
1496 AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN
,
1500 /* now enable mirroring if necessary */
1501 if (priv
->source_port
>= AR8327_NUM_PORTS
||
1502 priv
->monitor_port
>= AR8327_NUM_PORTS
||
1503 priv
->source_port
== priv
->monitor_port
) {
1507 ar8xxx_rmw(priv
, AR8327_REG_FWD_CTRL0
,
1508 AR8327_FWD_CTRL0_MIRROR_PORT
,
1509 (priv
->monitor_port
<< AR8327_FWD_CTRL0_MIRROR_PORT_S
));
1511 if (priv
->mirror_rx
)
1512 ar8xxx_rmw(priv
, AR8327_REG_PORT_LOOKUP(priv
->source_port
),
1513 AR8327_PORT_LOOKUP_ING_MIRROR_EN
,
1514 AR8327_PORT_LOOKUP_ING_MIRROR_EN
);
1516 if (priv
->mirror_tx
)
1517 ar8xxx_rmw(priv
, AR8327_REG_PORT_HOL_CTRL1(priv
->source_port
),
1518 AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN
,
1519 AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN
);
1523 ar8216_set_mirror_regs(struct ar8xxx_priv
*priv
)
1527 /* reset all mirror registers */
1528 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CPUPORT
,
1529 AR8216_GLOBAL_CPUPORT_MIRROR_PORT
,
1530 (0xF << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S
));
1531 for (port
= 0; port
< AR8216_NUM_PORTS
; port
++) {
1532 ar8xxx_rmw(priv
, AR8216_REG_PORT_CTRL(port
),
1533 AR8216_PORT_CTRL_MIRROR_RX
,
1536 ar8xxx_rmw(priv
, AR8216_REG_PORT_CTRL(port
),
1537 AR8216_PORT_CTRL_MIRROR_TX
,
1541 /* now enable mirroring if necessary */
1542 if (priv
->source_port
>= AR8216_NUM_PORTS
||
1543 priv
->monitor_port
>= AR8216_NUM_PORTS
||
1544 priv
->source_port
== priv
->monitor_port
) {
1548 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CPUPORT
,
1549 AR8216_GLOBAL_CPUPORT_MIRROR_PORT
,
1550 (priv
->monitor_port
<< AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S
));
1552 if (priv
->mirror_rx
)
1553 ar8xxx_rmw(priv
, AR8216_REG_PORT_CTRL(priv
->source_port
),
1554 AR8216_PORT_CTRL_MIRROR_RX
,
1555 AR8216_PORT_CTRL_MIRROR_RX
);
1557 if (priv
->mirror_tx
)
1558 ar8xxx_rmw(priv
, AR8216_REG_PORT_CTRL(priv
->source_port
),
1559 AR8216_PORT_CTRL_MIRROR_TX
,
1560 AR8216_PORT_CTRL_MIRROR_TX
);
1564 ar8xxx_set_mirror_regs(struct ar8xxx_priv
*priv
)
1566 if (chip_is_ar8327(priv
)) {
1567 ar8327_set_mirror_regs(priv
);
1569 ar8216_set_mirror_regs(priv
);
1574 ar8xxx_sw_hw_apply(struct switch_dev
*dev
)
1576 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1577 u8 portmask
[AR8X16_MAX_PORTS
];
1580 mutex_lock(&priv
->reg_mutex
);
1581 /* flush all vlan translation unit entries */
1582 priv
->chip
->vtu_flush(priv
);
1584 memset(portmask
, 0, sizeof(portmask
));
1586 /* calculate the port destination masks and load vlans
1587 * into the vlan translation unit */
1588 for (j
= 0; j
< AR8X16_MAX_VLANS
; j
++) {
1589 u8 vp
= priv
->vlan_table
[j
];
1594 for (i
= 0; i
< dev
->ports
; i
++) {
1597 portmask
[i
] |= vp
& ~mask
;
1600 priv
->chip
->vtu_load_vlan(priv
, priv
->vlan_id
[j
],
1601 priv
->vlan_table
[j
]);
1605 * isolate all ports, but connect them to the cpu port */
1606 for (i
= 0; i
< dev
->ports
; i
++) {
1607 if (i
== AR8216_PORT_CPU
)
1610 portmask
[i
] = 1 << AR8216_PORT_CPU
;
1611 portmask
[AR8216_PORT_CPU
] |= (1 << i
);
1615 /* update the port destination mask registers and tag settings */
1616 for (i
= 0; i
< dev
->ports
; i
++) {
1617 int egress
, ingress
;
1621 pvid
= priv
->vlan_id
[priv
->pvid
[i
]];
1622 if (priv
->vlan_tagged
& (1 << i
))
1623 egress
= AR8216_OUT_ADD_VLAN
;
1625 egress
= AR8216_OUT_STRIP_VLAN
;
1626 ingress
= AR8216_IN_SECURE
;
1629 egress
= AR8216_OUT_KEEP
;
1630 ingress
= AR8216_IN_PORT_ONLY
;
1633 priv
->chip
->setup_port(priv
, i
, egress
, ingress
, portmask
[i
],
1637 ar8xxx_set_mirror_regs(priv
);
1639 mutex_unlock(&priv
->reg_mutex
);
1644 ar8xxx_sw_reset_switch(struct switch_dev
*dev
)
1646 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1649 mutex_lock(&priv
->reg_mutex
);
1650 memset(&priv
->vlan
, 0, sizeof(struct ar8xxx_priv
) -
1651 offsetof(struct ar8xxx_priv
, vlan
));
1653 for (i
= 0; i
< AR8X16_MAX_VLANS
; i
++)
1654 priv
->vlan_id
[i
] = i
;
1656 /* Configure all ports */
1657 for (i
= 0; i
< dev
->ports
; i
++)
1658 priv
->chip
->init_port(priv
, i
);
1660 priv
->mirror_rx
= false;
1661 priv
->mirror_tx
= false;
1662 priv
->source_port
= 0;
1663 priv
->monitor_port
= 0;
1665 priv
->chip
->init_globals(priv
);
1667 mutex_unlock(&priv
->reg_mutex
);
1669 return ar8xxx_sw_hw_apply(dev
);
1673 ar8xxx_sw_set_reset_mibs(struct switch_dev
*dev
,
1674 const struct switch_attr
*attr
,
1675 struct switch_val
*val
)
1677 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1681 if (!ar8xxx_has_mib_counters(priv
))
1684 mutex_lock(&priv
->mib_lock
);
1686 len
= priv
->dev
.ports
* priv
->chip
->num_mibs
*
1687 sizeof(*priv
->mib_stats
);
1688 memset(priv
->mib_stats
, '\0', len
);
1689 ret
= ar8xxx_mib_flush(priv
);
1696 mutex_unlock(&priv
->mib_lock
);
1701 ar8xxx_sw_set_mirror_rx_enable(struct switch_dev
*dev
,
1702 const struct switch_attr
*attr
,
1703 struct switch_val
*val
)
1705 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1707 mutex_lock(&priv
->reg_mutex
);
1708 priv
->mirror_rx
= !!val
->value
.i
;
1709 ar8xxx_set_mirror_regs(priv
);
1710 mutex_unlock(&priv
->reg_mutex
);
1716 ar8xxx_sw_get_mirror_rx_enable(struct switch_dev
*dev
,
1717 const struct switch_attr
*attr
,
1718 struct switch_val
*val
)
1720 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1721 val
->value
.i
= priv
->mirror_rx
;
1726 ar8xxx_sw_set_mirror_tx_enable(struct switch_dev
*dev
,
1727 const struct switch_attr
*attr
,
1728 struct switch_val
*val
)
1730 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1732 mutex_lock(&priv
->reg_mutex
);
1733 priv
->mirror_tx
= !!val
->value
.i
;
1734 ar8xxx_set_mirror_regs(priv
);
1735 mutex_unlock(&priv
->reg_mutex
);
1741 ar8xxx_sw_get_mirror_tx_enable(struct switch_dev
*dev
,
1742 const struct switch_attr
*attr
,
1743 struct switch_val
*val
)
1745 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1746 val
->value
.i
= priv
->mirror_tx
;
1751 ar8xxx_sw_set_mirror_monitor_port(struct switch_dev
*dev
,
1752 const struct switch_attr
*attr
,
1753 struct switch_val
*val
)
1755 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1757 mutex_lock(&priv
->reg_mutex
);
1758 priv
->monitor_port
= val
->value
.i
;
1759 ar8xxx_set_mirror_regs(priv
);
1760 mutex_unlock(&priv
->reg_mutex
);
1766 ar8xxx_sw_get_mirror_monitor_port(struct switch_dev
*dev
,
1767 const struct switch_attr
*attr
,
1768 struct switch_val
*val
)
1770 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1771 val
->value
.i
= priv
->monitor_port
;
1776 ar8xxx_sw_set_mirror_source_port(struct switch_dev
*dev
,
1777 const struct switch_attr
*attr
,
1778 struct switch_val
*val
)
1780 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1782 mutex_lock(&priv
->reg_mutex
);
1783 priv
->source_port
= val
->value
.i
;
1784 ar8xxx_set_mirror_regs(priv
);
1785 mutex_unlock(&priv
->reg_mutex
);
1791 ar8xxx_sw_get_mirror_source_port(struct switch_dev
*dev
,
1792 const struct switch_attr
*attr
,
1793 struct switch_val
*val
)
1795 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1796 val
->value
.i
= priv
->source_port
;
1801 ar8xxx_sw_set_port_reset_mib(struct switch_dev
*dev
,
1802 const struct switch_attr
*attr
,
1803 struct switch_val
*val
)
1805 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1809 if (!ar8xxx_has_mib_counters(priv
))
1812 port
= val
->port_vlan
;
1813 if (port
>= dev
->ports
)
1816 mutex_lock(&priv
->mib_lock
);
1817 ret
= ar8xxx_mib_capture(priv
);
1821 ar8xxx_mib_fetch_port_stat(priv
, port
, true);
1826 mutex_unlock(&priv
->mib_lock
);
1831 ar8xxx_sw_get_port_mib(struct switch_dev
*dev
,
1832 const struct switch_attr
*attr
,
1833 struct switch_val
*val
)
1835 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1836 const struct ar8xxx_chip
*chip
= priv
->chip
;
1840 char *buf
= priv
->buf
;
1843 if (!ar8xxx_has_mib_counters(priv
))
1846 port
= val
->port_vlan
;
1847 if (port
>= dev
->ports
)
1850 mutex_lock(&priv
->mib_lock
);
1851 ret
= ar8xxx_mib_capture(priv
);
1855 ar8xxx_mib_fetch_port_stat(priv
, port
, false);
1857 len
+= snprintf(buf
+ len
, sizeof(priv
->buf
) - len
,
1858 "Port %d MIB counters\n",
1861 mib_stats
= &priv
->mib_stats
[port
* chip
->num_mibs
];
1862 for (i
= 0; i
< chip
->num_mibs
; i
++)
1863 len
+= snprintf(buf
+ len
, sizeof(priv
->buf
) - len
,
1865 chip
->mib_decs
[i
].name
,
1874 mutex_unlock(&priv
->mib_lock
);
1878 static struct switch_attr ar8xxx_sw_attr_globals
[] = {
1880 .type
= SWITCH_TYPE_INT
,
1881 .name
= "enable_vlan",
1882 .description
= "Enable VLAN mode",
1883 .set
= ar8xxx_sw_set_vlan
,
1884 .get
= ar8xxx_sw_get_vlan
,
1888 .type
= SWITCH_TYPE_NOVAL
,
1889 .name
= "reset_mibs",
1890 .description
= "Reset all MIB counters",
1891 .set
= ar8xxx_sw_set_reset_mibs
,
1894 .type
= SWITCH_TYPE_INT
,
1895 .name
= "enable_mirror_rx",
1896 .description
= "Enable mirroring of RX packets",
1897 .set
= ar8xxx_sw_set_mirror_rx_enable
,
1898 .get
= ar8xxx_sw_get_mirror_rx_enable
,
1902 .type
= SWITCH_TYPE_INT
,
1903 .name
= "enable_mirror_tx",
1904 .description
= "Enable mirroring of TX packets",
1905 .set
= ar8xxx_sw_set_mirror_tx_enable
,
1906 .get
= ar8xxx_sw_get_mirror_tx_enable
,
1910 .type
= SWITCH_TYPE_INT
,
1911 .name
= "mirror_monitor_port",
1912 .description
= "Mirror monitor port",
1913 .set
= ar8xxx_sw_set_mirror_monitor_port
,
1914 .get
= ar8xxx_sw_get_mirror_monitor_port
,
1915 .max
= AR8216_NUM_PORTS
- 1
1918 .type
= SWITCH_TYPE_INT
,
1919 .name
= "mirror_source_port",
1920 .description
= "Mirror source port",
1921 .set
= ar8xxx_sw_set_mirror_source_port
,
1922 .get
= ar8xxx_sw_get_mirror_source_port
,
1923 .max
= AR8216_NUM_PORTS
- 1
1927 static struct switch_attr ar8327_sw_attr_globals
[] = {
1929 .type
= SWITCH_TYPE_INT
,
1930 .name
= "enable_vlan",
1931 .description
= "Enable VLAN mode",
1932 .set
= ar8xxx_sw_set_vlan
,
1933 .get
= ar8xxx_sw_get_vlan
,
1937 .type
= SWITCH_TYPE_NOVAL
,
1938 .name
= "reset_mibs",
1939 .description
= "Reset all MIB counters",
1940 .set
= ar8xxx_sw_set_reset_mibs
,
1943 .type
= SWITCH_TYPE_INT
,
1944 .name
= "enable_mirror_rx",
1945 .description
= "Enable mirroring of RX packets",
1946 .set
= ar8xxx_sw_set_mirror_rx_enable
,
1947 .get
= ar8xxx_sw_get_mirror_rx_enable
,
1951 .type
= SWITCH_TYPE_INT
,
1952 .name
= "enable_mirror_tx",
1953 .description
= "Enable mirroring of TX packets",
1954 .set
= ar8xxx_sw_set_mirror_tx_enable
,
1955 .get
= ar8xxx_sw_get_mirror_tx_enable
,
1959 .type
= SWITCH_TYPE_INT
,
1960 .name
= "mirror_monitor_port",
1961 .description
= "Mirror monitor port",
1962 .set
= ar8xxx_sw_set_mirror_monitor_port
,
1963 .get
= ar8xxx_sw_get_mirror_monitor_port
,
1964 .max
= AR8327_NUM_PORTS
- 1
1967 .type
= SWITCH_TYPE_INT
,
1968 .name
= "mirror_source_port",
1969 .description
= "Mirror source port",
1970 .set
= ar8xxx_sw_set_mirror_source_port
,
1971 .get
= ar8xxx_sw_get_mirror_source_port
,
1972 .max
= AR8327_NUM_PORTS
- 1
1976 static struct switch_attr ar8xxx_sw_attr_port
[] = {
1978 .type
= SWITCH_TYPE_NOVAL
,
1979 .name
= "reset_mib",
1980 .description
= "Reset single port MIB counters",
1981 .set
= ar8xxx_sw_set_port_reset_mib
,
1984 .type
= SWITCH_TYPE_STRING
,
1986 .description
= "Get port's MIB counters",
1988 .get
= ar8xxx_sw_get_port_mib
,
1992 static struct switch_attr ar8xxx_sw_attr_vlan
[] = {
1994 .type
= SWITCH_TYPE_INT
,
1996 .description
= "VLAN ID (0-4094)",
1997 .set
= ar8xxx_sw_set_vid
,
1998 .get
= ar8xxx_sw_get_vid
,
2003 static const struct switch_dev_ops ar8xxx_sw_ops
= {
2005 .attr
= ar8xxx_sw_attr_globals
,
2006 .n_attr
= ARRAY_SIZE(ar8xxx_sw_attr_globals
),
2009 .attr
= ar8xxx_sw_attr_port
,
2010 .n_attr
= ARRAY_SIZE(ar8xxx_sw_attr_port
),
2013 .attr
= ar8xxx_sw_attr_vlan
,
2014 .n_attr
= ARRAY_SIZE(ar8xxx_sw_attr_vlan
),
2016 .get_port_pvid
= ar8xxx_sw_get_pvid
,
2017 .set_port_pvid
= ar8xxx_sw_set_pvid
,
2018 .get_vlan_ports
= ar8xxx_sw_get_ports
,
2019 .set_vlan_ports
= ar8xxx_sw_set_ports
,
2020 .apply_config
= ar8xxx_sw_hw_apply
,
2021 .reset_switch
= ar8xxx_sw_reset_switch
,
2022 .get_port_link
= ar8xxx_sw_get_port_link
,
2025 static const struct switch_dev_ops ar8327_sw_ops
= {
2027 .attr
= ar8327_sw_attr_globals
,
2028 .n_attr
= ARRAY_SIZE(ar8327_sw_attr_globals
),
2031 .attr
= ar8xxx_sw_attr_port
,
2032 .n_attr
= ARRAY_SIZE(ar8xxx_sw_attr_port
),
2035 .attr
= ar8xxx_sw_attr_vlan
,
2036 .n_attr
= ARRAY_SIZE(ar8xxx_sw_attr_vlan
),
2038 .get_port_pvid
= ar8xxx_sw_get_pvid
,
2039 .set_port_pvid
= ar8xxx_sw_set_pvid
,
2040 .get_vlan_ports
= ar8xxx_sw_get_ports
,
2041 .set_vlan_ports
= ar8xxx_sw_set_ports
,
2042 .apply_config
= ar8xxx_sw_hw_apply
,
2043 .reset_switch
= ar8xxx_sw_reset_switch
,
2044 .get_port_link
= ar8xxx_sw_get_port_link
,
2048 ar8xxx_id_chip(struct ar8xxx_priv
*priv
)
2054 val
= priv
->read(priv
, AR8216_REG_CTRL
);
2058 id
= val
& (AR8216_CTRL_REVISION
| AR8216_CTRL_VERSION
);
2059 for (i
= 0; i
< AR8X16_PROBE_RETRIES
; i
++) {
2062 val
= priv
->read(priv
, AR8216_REG_CTRL
);
2066 t
= val
& (AR8216_CTRL_REVISION
| AR8216_CTRL_VERSION
);
2071 priv
->chip_ver
= (id
& AR8216_CTRL_VERSION
) >> AR8216_CTRL_VERSION_S
;
2072 priv
->chip_rev
= (id
& AR8216_CTRL_REVISION
);
2074 switch (priv
->chip_ver
) {
2075 case AR8XXX_VER_AR8216
:
2076 priv
->chip
= &ar8216_chip
;
2078 case AR8XXX_VER_AR8236
:
2079 priv
->chip
= &ar8236_chip
;
2081 case AR8XXX_VER_AR8316
:
2082 priv
->chip
= &ar8316_chip
;
2084 case AR8XXX_VER_AR8327
:
2085 priv
->mii_lo_first
= true;
2086 priv
->chip
= &ar8327_chip
;
2089 pr_err("ar8216: Unknown Atheros device [ver=%d, rev=%d]\n",
2090 priv
->chip_ver
, priv
->chip_rev
);
2099 ar8xxx_mib_work_func(struct work_struct
*work
)
2101 struct ar8xxx_priv
*priv
;
2104 priv
= container_of(work
, struct ar8xxx_priv
, mib_work
.work
);
2106 mutex_lock(&priv
->mib_lock
);
2108 err
= ar8xxx_mib_capture(priv
);
2112 ar8xxx_mib_fetch_port_stat(priv
, priv
->mib_next_port
, false);
2115 priv
->mib_next_port
++;
2116 if (priv
->mib_next_port
>= priv
->dev
.ports
)
2117 priv
->mib_next_port
= 0;
2119 mutex_unlock(&priv
->mib_lock
);
2120 schedule_delayed_work(&priv
->mib_work
,
2121 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY
));
2125 ar8xxx_mib_init(struct ar8xxx_priv
*priv
)
2129 if (!ar8xxx_has_mib_counters(priv
))
2132 BUG_ON(!priv
->chip
->mib_decs
|| !priv
->chip
->num_mibs
);
2134 len
= priv
->dev
.ports
* priv
->chip
->num_mibs
*
2135 sizeof(*priv
->mib_stats
);
2136 priv
->mib_stats
= kzalloc(len
, GFP_KERNEL
);
2138 if (!priv
->mib_stats
)
2145 ar8xxx_mib_start(struct ar8xxx_priv
*priv
)
2147 if (!ar8xxx_has_mib_counters(priv
))
2150 schedule_delayed_work(&priv
->mib_work
,
2151 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY
));
2155 ar8xxx_mib_stop(struct ar8xxx_priv
*priv
)
2157 if (!ar8xxx_has_mib_counters(priv
))
2160 cancel_delayed_work(&priv
->mib_work
);
2163 static struct ar8xxx_priv
*
2166 struct ar8xxx_priv
*priv
;
2168 priv
= kzalloc(sizeof(struct ar8xxx_priv
), GFP_KERNEL
);
2172 mutex_init(&priv
->reg_mutex
);
2173 mutex_init(&priv
->mib_lock
);
2174 INIT_DELAYED_WORK(&priv
->mib_work
, ar8xxx_mib_work_func
);
2180 ar8xxx_free(struct ar8xxx_priv
*priv
)
2182 kfree(priv
->mib_stats
);
2186 static struct ar8xxx_priv
*
2187 ar8xxx_create_mii(struct mii_bus
*bus
)
2189 struct ar8xxx_priv
*priv
;
2191 priv
= ar8xxx_create();
2193 priv
->mii_bus
= bus
;
2194 priv
->read
= ar8xxx_mii_read
;
2195 priv
->write
= ar8xxx_mii_write
;
2202 ar8xxx_probe_switch(struct ar8xxx_priv
*priv
)
2204 struct switch_dev
*swdev
;
2207 ret
= ar8xxx_id_chip(priv
);
2212 swdev
->cpu_port
= AR8216_PORT_CPU
;
2213 swdev
->ops
= &ar8xxx_sw_ops
;
2215 if (chip_is_ar8316(priv
)) {
2216 swdev
->name
= "Atheros AR8316";
2217 swdev
->vlans
= AR8X16_MAX_VLANS
;
2218 swdev
->ports
= AR8216_NUM_PORTS
;
2219 } else if (chip_is_ar8236(priv
)) {
2220 swdev
->name
= "Atheros AR8236";
2221 swdev
->vlans
= AR8216_NUM_VLANS
;
2222 swdev
->ports
= AR8216_NUM_PORTS
;
2223 } else if (chip_is_ar8327(priv
)) {
2224 swdev
->name
= "Atheros AR8327";
2225 swdev
->vlans
= AR8X16_MAX_VLANS
;
2226 swdev
->ports
= AR8327_NUM_PORTS
;
2227 swdev
->ops
= &ar8327_sw_ops
;
2229 swdev
->name
= "Atheros AR8216";
2230 swdev
->vlans
= AR8216_NUM_VLANS
;
2231 swdev
->ports
= AR8216_NUM_PORTS
;
2234 ret
= ar8xxx_mib_init(priv
);
2242 ar8xxx_start(struct ar8xxx_priv
*priv
)
2248 ret
= priv
->chip
->hw_init(priv
);
2252 ret
= ar8xxx_sw_reset_switch(&priv
->dev
);
2258 ar8xxx_mib_start(priv
);
2264 ar8xxx_phy_config_init(struct phy_device
*phydev
)
2266 struct ar8xxx_priv
*priv
= phydev
->priv
;
2267 struct net_device
*dev
= phydev
->attached_dev
;
2273 if (chip_is_ar8327(priv
))
2278 if (phydev
->addr
!= 0) {
2279 if (chip_is_ar8316(priv
)) {
2280 /* switch device has been initialized, reinit */
2281 priv
->dev
.ports
= (AR8216_NUM_PORTS
- 1);
2282 priv
->initialized
= false;
2283 priv
->port4_phy
= true;
2284 ar8316_hw_init(priv
);
2291 ret
= ar8xxx_start(priv
);
2295 /* VID fixup only needed on ar8216 */
2296 if (chip_is_ar8216(priv
)) {
2297 dev
->phy_ptr
= priv
;
2298 dev
->priv_flags
|= IFF_NO_IP_ALIGN
;
2299 dev
->eth_mangle_rx
= ar8216_mangle_rx
;
2300 dev
->eth_mangle_tx
= ar8216_mangle_tx
;
2307 ar8xxx_phy_read_status(struct phy_device
*phydev
)
2309 struct ar8xxx_priv
*priv
= phydev
->priv
;
2310 struct switch_port_link link
;
2313 if (phydev
->addr
!= 0)
2314 return genphy_read_status(phydev
);
2316 ar8216_read_port_link(priv
, phydev
->addr
, &link
);
2317 phydev
->link
= !!link
.link
;
2321 switch (link
.speed
) {
2322 case SWITCH_PORT_SPEED_10
:
2323 phydev
->speed
= SPEED_10
;
2325 case SWITCH_PORT_SPEED_100
:
2326 phydev
->speed
= SPEED_100
;
2328 case SWITCH_PORT_SPEED_1000
:
2329 phydev
->speed
= SPEED_1000
;
2334 phydev
->duplex
= link
.duplex
? DUPLEX_FULL
: DUPLEX_HALF
;
2336 /* flush the address translation unit */
2337 mutex_lock(&priv
->reg_mutex
);
2338 ret
= priv
->chip
->atu_flush(priv
);
2339 mutex_unlock(&priv
->reg_mutex
);
2341 phydev
->state
= PHY_RUNNING
;
2342 netif_carrier_on(phydev
->attached_dev
);
2343 phydev
->adjust_link(phydev
->attached_dev
);
2349 ar8xxx_phy_config_aneg(struct phy_device
*phydev
)
2351 if (phydev
->addr
== 0)
2354 return genphy_config_aneg(phydev
);
2357 static const u32 ar8xxx_phy_ids
[] = {
2365 ar8xxx_phy_match(u32 phy_id
)
2369 for (i
= 0; i
< ARRAY_SIZE(ar8xxx_phy_ids
); i
++)
2370 if (phy_id
== ar8xxx_phy_ids
[i
])
2377 ar8xxx_is_possible(struct mii_bus
*bus
)
2381 for (i
= 0; i
< 4; i
++) {
2384 phy_id
= mdiobus_read(bus
, i
, MII_PHYSID1
) << 16;
2385 phy_id
|= mdiobus_read(bus
, i
, MII_PHYSID2
);
2386 if (!ar8xxx_phy_match(phy_id
)) {
2387 pr_debug("ar8xxx: unknown PHY at %s:%02x id:%08x\n",
2388 dev_name(&bus
->dev
), i
, phy_id
);
2397 ar8xxx_phy_probe(struct phy_device
*phydev
)
2399 struct ar8xxx_priv
*priv
;
2400 struct switch_dev
*swdev
;
2403 /* skip PHYs at unused adresses */
2404 if (phydev
->addr
!= 0 && phydev
->addr
!= 4)
2407 if (!ar8xxx_is_possible(phydev
->bus
))
2410 mutex_lock(&ar8xxx_dev_list_lock
);
2411 list_for_each_entry(priv
, &ar8xxx_dev_list
, list
)
2412 if (priv
->mii_bus
== phydev
->bus
)
2415 priv
= ar8xxx_create_mii(phydev
->bus
);
2421 ret
= ar8xxx_probe_switch(priv
);
2426 swdev
->alias
= dev_name(&priv
->mii_bus
->dev
);
2427 ret
= register_switch(swdev
, NULL
);
2431 pr_info("%s: %s rev. %u switch registered on %s\n",
2432 swdev
->devname
, swdev
->name
, priv
->chip_rev
,
2433 dev_name(&priv
->mii_bus
->dev
));
2438 if (phydev
->addr
== 0) {
2439 if (ar8xxx_has_gige(priv
)) {
2440 phydev
->supported
= SUPPORTED_1000baseT_Full
;
2441 phydev
->advertising
= ADVERTISED_1000baseT_Full
;
2443 phydev
->supported
= SUPPORTED_100baseT_Full
;
2444 phydev
->advertising
= ADVERTISED_100baseT_Full
;
2447 if (chip_is_ar8327(priv
)) {
2450 ret
= ar8xxx_start(priv
);
2452 goto err_unregister_switch
;
2455 if (ar8xxx_has_gige(priv
)) {
2456 phydev
->supported
|= SUPPORTED_1000baseT_Full
;
2457 phydev
->advertising
|= ADVERTISED_1000baseT_Full
;
2461 phydev
->priv
= priv
;
2463 list_add(&priv
->list
, &ar8xxx_dev_list
);
2465 mutex_unlock(&ar8xxx_dev_list_lock
);
2469 err_unregister_switch
:
2470 if (--priv
->use_count
)
2473 unregister_switch(&priv
->dev
);
2478 mutex_unlock(&ar8xxx_dev_list_lock
);
2483 ar8xxx_phy_detach(struct phy_device
*phydev
)
2485 struct net_device
*dev
= phydev
->attached_dev
;
2490 dev
->phy_ptr
= NULL
;
2491 dev
->priv_flags
&= ~IFF_NO_IP_ALIGN
;
2492 dev
->eth_mangle_rx
= NULL
;
2493 dev
->eth_mangle_tx
= NULL
;
2497 ar8xxx_phy_remove(struct phy_device
*phydev
)
2499 struct ar8xxx_priv
*priv
= phydev
->priv
;
2504 phydev
->priv
= NULL
;
2505 if (--priv
->use_count
> 0)
2508 mutex_lock(&ar8xxx_dev_list_lock
);
2509 list_del(&priv
->list
);
2510 mutex_unlock(&ar8xxx_dev_list_lock
);
2512 unregister_switch(&priv
->dev
);
2513 ar8xxx_mib_stop(priv
);
2517 static struct phy_driver ar8xxx_phy_driver
= {
2518 .phy_id
= 0x004d0000,
2519 .name
= "Atheros AR8216/AR8236/AR8316",
2520 .phy_id_mask
= 0xffff0000,
2521 .features
= PHY_BASIC_FEATURES
,
2522 .probe
= ar8xxx_phy_probe
,
2523 .remove
= ar8xxx_phy_remove
,
2524 .detach
= ar8xxx_phy_detach
,
2525 .config_init
= ar8xxx_phy_config_init
,
2526 .config_aneg
= ar8xxx_phy_config_aneg
,
2527 .read_status
= ar8xxx_phy_read_status
,
2528 .driver
= { .owner
= THIS_MODULE
},
2534 return phy_driver_register(&ar8xxx_phy_driver
);
2540 phy_driver_unregister(&ar8xxx_phy_driver
);
2543 module_init(ar8xxx_init
);
2544 module_exit(ar8xxx_exit
);
2545 MODULE_LICENSE("GPL");