2 * ar8216.c: AR8216 switch driver
4 * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>
5 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/list.h>
22 #include <linux/if_ether.h>
23 #include <linux/skbuff.h>
24 #include <linux/netdevice.h>
25 #include <linux/netlink.h>
26 #include <linux/of_device.h>
27 #include <linux/of_mdio.h>
28 #include <linux/of_net.h>
29 #include <linux/bitops.h>
30 #include <net/genetlink.h>
31 #include <linux/switch.h>
32 #include <linux/delay.h>
33 #include <linux/phy.h>
34 #include <linux/etherdevice.h>
35 #include <linux/lockdep.h>
36 #include <linux/ar8216_platform.h>
37 #include <linux/workqueue.h>
38 #include <linux/version.h>
42 extern const struct ar8xxx_chip ar8327_chip
;
43 extern const struct ar8xxx_chip ar8337_chip
;
45 #define AR8XXX_MIB_WORK_DELAY 2000 /* msecs */
47 #define MIB_DESC(_s , _o, _n) \
54 static const struct ar8xxx_mib_desc ar8216_mibs
[] = {
55 MIB_DESC(1, AR8216_STATS_RXBROAD
, "RxBroad"),
56 MIB_DESC(1, AR8216_STATS_RXPAUSE
, "RxPause"),
57 MIB_DESC(1, AR8216_STATS_RXMULTI
, "RxMulti"),
58 MIB_DESC(1, AR8216_STATS_RXFCSERR
, "RxFcsErr"),
59 MIB_DESC(1, AR8216_STATS_RXALIGNERR
, "RxAlignErr"),
60 MIB_DESC(1, AR8216_STATS_RXRUNT
, "RxRunt"),
61 MIB_DESC(1, AR8216_STATS_RXFRAGMENT
, "RxFragment"),
62 MIB_DESC(1, AR8216_STATS_RX64BYTE
, "Rx64Byte"),
63 MIB_DESC(1, AR8216_STATS_RX128BYTE
, "Rx128Byte"),
64 MIB_DESC(1, AR8216_STATS_RX256BYTE
, "Rx256Byte"),
65 MIB_DESC(1, AR8216_STATS_RX512BYTE
, "Rx512Byte"),
66 MIB_DESC(1, AR8216_STATS_RX1024BYTE
, "Rx1024Byte"),
67 MIB_DESC(1, AR8216_STATS_RXMAXBYTE
, "RxMaxByte"),
68 MIB_DESC(1, AR8216_STATS_RXTOOLONG
, "RxTooLong"),
69 MIB_DESC(2, AR8216_STATS_RXGOODBYTE
, "RxGoodByte"),
70 MIB_DESC(2, AR8216_STATS_RXBADBYTE
, "RxBadByte"),
71 MIB_DESC(1, AR8216_STATS_RXOVERFLOW
, "RxOverFlow"),
72 MIB_DESC(1, AR8216_STATS_FILTERED
, "Filtered"),
73 MIB_DESC(1, AR8216_STATS_TXBROAD
, "TxBroad"),
74 MIB_DESC(1, AR8216_STATS_TXPAUSE
, "TxPause"),
75 MIB_DESC(1, AR8216_STATS_TXMULTI
, "TxMulti"),
76 MIB_DESC(1, AR8216_STATS_TXUNDERRUN
, "TxUnderRun"),
77 MIB_DESC(1, AR8216_STATS_TX64BYTE
, "Tx64Byte"),
78 MIB_DESC(1, AR8216_STATS_TX128BYTE
, "Tx128Byte"),
79 MIB_DESC(1, AR8216_STATS_TX256BYTE
, "Tx256Byte"),
80 MIB_DESC(1, AR8216_STATS_TX512BYTE
, "Tx512Byte"),
81 MIB_DESC(1, AR8216_STATS_TX1024BYTE
, "Tx1024Byte"),
82 MIB_DESC(1, AR8216_STATS_TXMAXBYTE
, "TxMaxByte"),
83 MIB_DESC(1, AR8216_STATS_TXOVERSIZE
, "TxOverSize"),
84 MIB_DESC(2, AR8216_STATS_TXBYTE
, "TxByte"),
85 MIB_DESC(1, AR8216_STATS_TXCOLLISION
, "TxCollision"),
86 MIB_DESC(1, AR8216_STATS_TXABORTCOL
, "TxAbortCol"),
87 MIB_DESC(1, AR8216_STATS_TXMULTICOL
, "TxMultiCol"),
88 MIB_DESC(1, AR8216_STATS_TXSINGLECOL
, "TxSingleCol"),
89 MIB_DESC(1, AR8216_STATS_TXEXCDEFER
, "TxExcDefer"),
90 MIB_DESC(1, AR8216_STATS_TXDEFER
, "TxDefer"),
91 MIB_DESC(1, AR8216_STATS_TXLATECOL
, "TxLateCol"),
94 const struct ar8xxx_mib_desc ar8236_mibs
[39] = {
95 MIB_DESC(1, AR8236_STATS_RXBROAD
, "RxBroad"),
96 MIB_DESC(1, AR8236_STATS_RXPAUSE
, "RxPause"),
97 MIB_DESC(1, AR8236_STATS_RXMULTI
, "RxMulti"),
98 MIB_DESC(1, AR8236_STATS_RXFCSERR
, "RxFcsErr"),
99 MIB_DESC(1, AR8236_STATS_RXALIGNERR
, "RxAlignErr"),
100 MIB_DESC(1, AR8236_STATS_RXRUNT
, "RxRunt"),
101 MIB_DESC(1, AR8236_STATS_RXFRAGMENT
, "RxFragment"),
102 MIB_DESC(1, AR8236_STATS_RX64BYTE
, "Rx64Byte"),
103 MIB_DESC(1, AR8236_STATS_RX128BYTE
, "Rx128Byte"),
104 MIB_DESC(1, AR8236_STATS_RX256BYTE
, "Rx256Byte"),
105 MIB_DESC(1, AR8236_STATS_RX512BYTE
, "Rx512Byte"),
106 MIB_DESC(1, AR8236_STATS_RX1024BYTE
, "Rx1024Byte"),
107 MIB_DESC(1, AR8236_STATS_RX1518BYTE
, "Rx1518Byte"),
108 MIB_DESC(1, AR8236_STATS_RXMAXBYTE
, "RxMaxByte"),
109 MIB_DESC(1, AR8236_STATS_RXTOOLONG
, "RxTooLong"),
110 MIB_DESC(2, AR8236_STATS_RXGOODBYTE
, "RxGoodByte"),
111 MIB_DESC(2, AR8236_STATS_RXBADBYTE
, "RxBadByte"),
112 MIB_DESC(1, AR8236_STATS_RXOVERFLOW
, "RxOverFlow"),
113 MIB_DESC(1, AR8236_STATS_FILTERED
, "Filtered"),
114 MIB_DESC(1, AR8236_STATS_TXBROAD
, "TxBroad"),
115 MIB_DESC(1, AR8236_STATS_TXPAUSE
, "TxPause"),
116 MIB_DESC(1, AR8236_STATS_TXMULTI
, "TxMulti"),
117 MIB_DESC(1, AR8236_STATS_TXUNDERRUN
, "TxUnderRun"),
118 MIB_DESC(1, AR8236_STATS_TX64BYTE
, "Tx64Byte"),
119 MIB_DESC(1, AR8236_STATS_TX128BYTE
, "Tx128Byte"),
120 MIB_DESC(1, AR8236_STATS_TX256BYTE
, "Tx256Byte"),
121 MIB_DESC(1, AR8236_STATS_TX512BYTE
, "Tx512Byte"),
122 MIB_DESC(1, AR8236_STATS_TX1024BYTE
, "Tx1024Byte"),
123 MIB_DESC(1, AR8236_STATS_TX1518BYTE
, "Tx1518Byte"),
124 MIB_DESC(1, AR8236_STATS_TXMAXBYTE
, "TxMaxByte"),
125 MIB_DESC(1, AR8236_STATS_TXOVERSIZE
, "TxOverSize"),
126 MIB_DESC(2, AR8236_STATS_TXBYTE
, "TxByte"),
127 MIB_DESC(1, AR8236_STATS_TXCOLLISION
, "TxCollision"),
128 MIB_DESC(1, AR8236_STATS_TXABORTCOL
, "TxAbortCol"),
129 MIB_DESC(1, AR8236_STATS_TXMULTICOL
, "TxMultiCol"),
130 MIB_DESC(1, AR8236_STATS_TXSINGLECOL
, "TxSingleCol"),
131 MIB_DESC(1, AR8236_STATS_TXEXCDEFER
, "TxExcDefer"),
132 MIB_DESC(1, AR8236_STATS_TXDEFER
, "TxDefer"),
133 MIB_DESC(1, AR8236_STATS_TXLATECOL
, "TxLateCol"),
136 static DEFINE_MUTEX(ar8xxx_dev_list_lock
);
137 static LIST_HEAD(ar8xxx_dev_list
);
139 /* inspired by phy_poll_reset in drivers/net/phy/phy_device.c */
141 ar8xxx_phy_poll_reset(struct mii_bus
*bus
)
143 unsigned int sleep_msecs
= 20;
146 for (elapsed
= sleep_msecs
; elapsed
<= 600;
147 elapsed
+= sleep_msecs
) {
149 for (i
= 0; i
< AR8XXX_NUM_PHYS
; i
++) {
150 ret
= mdiobus_read(bus
, i
, MII_BMCR
);
153 if (ret
& BMCR_RESET
)
155 if (i
== AR8XXX_NUM_PHYS
- 1) {
156 usleep_range(1000, 2000);
165 ar8xxx_phy_check_aneg(struct phy_device
*phydev
)
169 if (phydev
->autoneg
!= AUTONEG_ENABLE
)
172 * BMCR_ANENABLE might have been cleared
173 * by phy_init_hw in certain kernel versions
174 * therefore check for it
176 ret
= phy_read(phydev
, MII_BMCR
);
179 if (ret
& BMCR_ANENABLE
)
182 dev_info(&phydev
->mdio
.dev
, "ANEG disabled, re-enabling ...\n");
183 ret
|= BMCR_ANENABLE
| BMCR_ANRESTART
;
184 return phy_write(phydev
, MII_BMCR
, ret
);
188 ar8xxx_phy_init(struct ar8xxx_priv
*priv
)
193 bus
= priv
->sw_mii_bus
?: priv
->mii_bus
;
194 for (i
= 0; i
< AR8XXX_NUM_PHYS
; i
++) {
195 if (priv
->chip
->phy_fixup
)
196 priv
->chip
->phy_fixup(priv
, i
);
198 /* initialize the port itself */
199 mdiobus_write(bus
, i
, MII_ADVERTISE
,
200 ADVERTISE_ALL
| ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
);
201 if (ar8xxx_has_gige(priv
))
202 mdiobus_write(bus
, i
, MII_CTRL1000
, ADVERTISE_1000FULL
);
203 mdiobus_write(bus
, i
, MII_BMCR
, BMCR_RESET
| BMCR_ANENABLE
);
206 ar8xxx_phy_poll_reset(bus
);
210 ar8xxx_mii_read32(struct ar8xxx_priv
*priv
, int phy_id
, int regnum
)
212 struct mii_bus
*bus
= priv
->mii_bus
;
215 lo
= bus
->read(bus
, phy_id
, regnum
);
216 hi
= bus
->read(bus
, phy_id
, regnum
+ 1);
218 return (hi
<< 16) | lo
;
222 ar8xxx_mii_write32(struct ar8xxx_priv
*priv
, int phy_id
, int regnum
, u32 val
)
224 struct mii_bus
*bus
= priv
->mii_bus
;
228 hi
= (u16
) (val
>> 16);
230 if (priv
->chip
->mii_lo_first
)
232 bus
->write(bus
, phy_id
, regnum
, lo
);
233 bus
->write(bus
, phy_id
, regnum
+ 1, hi
);
235 bus
->write(bus
, phy_id
, regnum
+ 1, hi
);
236 bus
->write(bus
, phy_id
, regnum
, lo
);
241 ar8xxx_read(struct ar8xxx_priv
*priv
, int reg
)
243 struct mii_bus
*bus
= priv
->mii_bus
;
247 split_addr((u32
) reg
, &r1
, &r2
, &page
);
249 mutex_lock(&bus
->mdio_lock
);
251 bus
->write(bus
, 0x18, 0, page
);
252 wait_for_page_switch();
253 val
= ar8xxx_mii_read32(priv
, 0x10 | r2
, r1
);
255 mutex_unlock(&bus
->mdio_lock
);
261 ar8xxx_write(struct ar8xxx_priv
*priv
, int reg
, u32 val
)
263 struct mii_bus
*bus
= priv
->mii_bus
;
266 split_addr((u32
) reg
, &r1
, &r2
, &page
);
268 mutex_lock(&bus
->mdio_lock
);
270 bus
->write(bus
, 0x18, 0, page
);
271 wait_for_page_switch();
272 ar8xxx_mii_write32(priv
, 0x10 | r2
, r1
, val
);
274 mutex_unlock(&bus
->mdio_lock
);
278 ar8xxx_rmw(struct ar8xxx_priv
*priv
, int reg
, u32 mask
, u32 val
)
280 struct mii_bus
*bus
= priv
->mii_bus
;
284 split_addr((u32
) reg
, &r1
, &r2
, &page
);
286 mutex_lock(&bus
->mdio_lock
);
288 bus
->write(bus
, 0x18, 0, page
);
289 wait_for_page_switch();
291 ret
= ar8xxx_mii_read32(priv
, 0x10 | r2
, r1
);
294 ar8xxx_mii_write32(priv
, 0x10 | r2
, r1
, ret
);
296 mutex_unlock(&bus
->mdio_lock
);
301 ar8xxx_phy_dbg_read(struct ar8xxx_priv
*priv
, int phy_addr
,
302 u16 dbg_addr
, u16
*dbg_data
)
304 struct mii_bus
*bus
= priv
->mii_bus
;
306 mutex_lock(&bus
->mdio_lock
);
307 bus
->write(bus
, phy_addr
, MII_ATH_DBG_ADDR
, dbg_addr
);
308 *dbg_data
= bus
->read(bus
, phy_addr
, MII_ATH_DBG_DATA
);
309 mutex_unlock(&bus
->mdio_lock
);
313 ar8xxx_phy_dbg_write(struct ar8xxx_priv
*priv
, int phy_addr
,
314 u16 dbg_addr
, u16 dbg_data
)
316 struct mii_bus
*bus
= priv
->mii_bus
;
318 mutex_lock(&bus
->mdio_lock
);
319 bus
->write(bus
, phy_addr
, MII_ATH_DBG_ADDR
, dbg_addr
);
320 bus
->write(bus
, phy_addr
, MII_ATH_DBG_DATA
, dbg_data
);
321 mutex_unlock(&bus
->mdio_lock
);
325 ar8xxx_phy_mmd_prep(struct mii_bus
*bus
, int phy_addr
, u16 addr
, u16 reg
)
327 bus
->write(bus
, phy_addr
, MII_ATH_MMD_ADDR
, addr
);
328 bus
->write(bus
, phy_addr
, MII_ATH_MMD_DATA
, reg
);
329 bus
->write(bus
, phy_addr
, MII_ATH_MMD_ADDR
, addr
| 0x4000);
333 ar8xxx_phy_mmd_write(struct ar8xxx_priv
*priv
, int phy_addr
, u16 addr
, u16 reg
, u16 data
)
335 struct mii_bus
*bus
= priv
->mii_bus
;
337 mutex_lock(&bus
->mdio_lock
);
338 ar8xxx_phy_mmd_prep(bus
, phy_addr
, addr
, reg
);
339 bus
->write(bus
, phy_addr
, MII_ATH_MMD_DATA
, data
);
340 mutex_unlock(&bus
->mdio_lock
);
344 ar8xxx_phy_mmd_read(struct ar8xxx_priv
*priv
, int phy_addr
, u16 addr
, u16 reg
)
346 struct mii_bus
*bus
= priv
->mii_bus
;
349 mutex_lock(&bus
->mdio_lock
);
350 ar8xxx_phy_mmd_prep(bus
, phy_addr
, addr
, reg
);
351 data
= bus
->read(bus
, phy_addr
, MII_ATH_MMD_DATA
);
352 mutex_unlock(&bus
->mdio_lock
);
358 ar8xxx_reg_wait(struct ar8xxx_priv
*priv
, u32 reg
, u32 mask
, u32 val
,
363 for (i
= 0; i
< timeout
; i
++) {
366 t
= ar8xxx_read(priv
, reg
);
367 if ((t
& mask
) == val
)
370 usleep_range(1000, 2000);
378 ar8xxx_mib_op(struct ar8xxx_priv
*priv
, u32 op
)
380 unsigned mib_func
= priv
->chip
->mib_func
;
383 lockdep_assert_held(&priv
->mib_lock
);
385 /* Capture the hardware statistics for all ports */
386 ar8xxx_rmw(priv
, mib_func
, AR8216_MIB_FUNC
, (op
<< AR8216_MIB_FUNC_S
));
388 /* Wait for the capturing to complete. */
389 ret
= ar8xxx_reg_wait(priv
, mib_func
, AR8216_MIB_BUSY
, 0, 10);
400 ar8xxx_mib_capture(struct ar8xxx_priv
*priv
)
402 return ar8xxx_mib_op(priv
, AR8216_MIB_FUNC_CAPTURE
);
406 ar8xxx_mib_flush(struct ar8xxx_priv
*priv
)
408 return ar8xxx_mib_op(priv
, AR8216_MIB_FUNC_FLUSH
);
412 ar8xxx_mib_fetch_port_stat(struct ar8xxx_priv
*priv
, int port
, bool flush
)
418 WARN_ON(port
>= priv
->dev
.ports
);
420 lockdep_assert_held(&priv
->mib_lock
);
422 base
= priv
->chip
->reg_port_stats_start
+
423 priv
->chip
->reg_port_stats_length
* port
;
425 mib_stats
= &priv
->mib_stats
[port
* priv
->chip
->num_mibs
];
426 for (i
= 0; i
< priv
->chip
->num_mibs
; i
++) {
427 const struct ar8xxx_mib_desc
*mib
;
430 mib
= &priv
->chip
->mib_decs
[i
];
431 t
= ar8xxx_read(priv
, base
+ mib
->offset
);
432 if (mib
->size
== 2) {
435 hi
= ar8xxx_read(priv
, base
+ mib
->offset
+ 4);
448 ar8216_read_port_link(struct ar8xxx_priv
*priv
, int port
,
449 struct switch_port_link
*link
)
454 memset(link
, '\0', sizeof(*link
));
456 status
= priv
->chip
->read_port_status(priv
, port
);
458 link
->aneg
= !!(status
& AR8216_PORT_STATUS_LINK_AUTO
);
460 link
->link
= !!(status
& AR8216_PORT_STATUS_LINK_UP
);
464 if (priv
->get_port_link
) {
467 err
= priv
->get_port_link(port
);
476 link
->duplex
= !!(status
& AR8216_PORT_STATUS_DUPLEX
);
477 link
->tx_flow
= !!(status
& AR8216_PORT_STATUS_TXFLOW
);
478 link
->rx_flow
= !!(status
& AR8216_PORT_STATUS_RXFLOW
);
480 if (link
->aneg
&& link
->duplex
&& priv
->chip
->read_port_eee_status
)
481 link
->eee
= priv
->chip
->read_port_eee_status(priv
, port
);
483 speed
= (status
& AR8216_PORT_STATUS_SPEED
) >>
484 AR8216_PORT_STATUS_SPEED_S
;
487 case AR8216_PORT_SPEED_10M
:
488 link
->speed
= SWITCH_PORT_SPEED_10
;
490 case AR8216_PORT_SPEED_100M
:
491 link
->speed
= SWITCH_PORT_SPEED_100
;
493 case AR8216_PORT_SPEED_1000M
:
494 link
->speed
= SWITCH_PORT_SPEED_1000
;
497 link
->speed
= SWITCH_PORT_SPEED_UNKNOWN
;
502 static struct sk_buff
*
503 ar8216_mangle_tx(struct net_device
*dev
, struct sk_buff
*skb
)
505 struct ar8xxx_priv
*priv
= dev
->phy_ptr
;
514 if (unlikely(skb_headroom(skb
) < 2)) {
515 if (pskb_expand_head(skb
, 2, 0, GFP_ATOMIC
) < 0)
519 buf
= skb_push(skb
, 2);
527 dev_kfree_skb_any(skb
);
532 ar8216_mangle_rx(struct net_device
*dev
, struct sk_buff
*skb
)
534 struct ar8xxx_priv
*priv
;
542 /* don't strip the header if vlan mode is disabled */
546 /* strip header, get vlan id */
550 /* check for vlan header presence */
551 if ((buf
[12 + 2] != 0x81) || (buf
[13 + 2] != 0x00))
556 /* no need to fix up packets coming from a tagged source */
557 if (priv
->vlan_tagged
& (1 << port
))
560 /* lookup port vid from local table, the switch passes an invalid vlan id */
561 vlan
= priv
->vlan_id
[priv
->pvid
[port
]];
564 buf
[14 + 2] |= vlan
>> 8;
565 buf
[15 + 2] = vlan
& 0xff;
569 ar8216_wait_bit(struct ar8xxx_priv
*priv
, int reg
, u32 mask
, u32 val
)
575 t
= ar8xxx_read(priv
, reg
);
576 if ((t
& mask
) == val
)
586 pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
587 (unsigned int) reg
, t
, mask
, val
);
592 ar8216_vtu_op(struct ar8xxx_priv
*priv
, u32 op
, u32 val
)
594 if (ar8216_wait_bit(priv
, AR8216_REG_VTU
, AR8216_VTU_ACTIVE
, 0))
596 if ((op
& AR8216_VTU_OP
) == AR8216_VTU_OP_LOAD
) {
597 val
&= AR8216_VTUDATA_MEMBER
;
598 val
|= AR8216_VTUDATA_VALID
;
599 ar8xxx_write(priv
, AR8216_REG_VTU_DATA
, val
);
601 op
|= AR8216_VTU_ACTIVE
;
602 ar8xxx_write(priv
, AR8216_REG_VTU
, op
);
606 ar8216_vtu_flush(struct ar8xxx_priv
*priv
)
608 ar8216_vtu_op(priv
, AR8216_VTU_OP_FLUSH
, 0);
612 ar8216_vtu_load_vlan(struct ar8xxx_priv
*priv
, u32 vid
, u32 port_mask
)
616 op
= AR8216_VTU_OP_LOAD
| (vid
<< AR8216_VTU_VID_S
);
617 ar8216_vtu_op(priv
, op
, port_mask
);
621 ar8216_atu_flush(struct ar8xxx_priv
*priv
)
625 ret
= ar8216_wait_bit(priv
, AR8216_REG_ATU_FUNC0
, AR8216_ATU_ACTIVE
, 0);
627 ar8xxx_write(priv
, AR8216_REG_ATU_FUNC0
, AR8216_ATU_OP_FLUSH
|
634 ar8216_atu_flush_port(struct ar8xxx_priv
*priv
, int port
)
639 ret
= ar8216_wait_bit(priv
, AR8216_REG_ATU_FUNC0
, AR8216_ATU_ACTIVE
, 0);
641 t
= (port
<< AR8216_ATU_PORT_NUM_S
) | AR8216_ATU_OP_FLUSH_PORT
;
642 t
|= AR8216_ATU_ACTIVE
;
643 ar8xxx_write(priv
, AR8216_REG_ATU_FUNC0
, t
);
650 ar8216_read_port_status(struct ar8xxx_priv
*priv
, int port
)
652 return ar8xxx_read(priv
, AR8216_REG_PORT_STATUS(port
));
656 __ar8216_setup_port(struct ar8xxx_priv
*priv
, int port
, u32 members
,
664 pvid
= priv
->vlan_id
[priv
->pvid
[port
]];
665 if (priv
->vlan_tagged
& (1 << port
))
666 egress
= AR8216_OUT_ADD_VLAN
;
668 egress
= AR8216_OUT_STRIP_VLAN
;
669 ingress
= AR8216_IN_SECURE
;
672 egress
= AR8216_OUT_KEEP
;
673 ingress
= AR8216_IN_PORT_ONLY
;
676 header
= ath_hdr_en
? AR8216_PORT_CTRL_HEADER
: 0;
678 ar8xxx_rmw(priv
, AR8216_REG_PORT_CTRL(port
),
679 AR8216_PORT_CTRL_LEARN
| AR8216_PORT_CTRL_VLAN_MODE
|
680 AR8216_PORT_CTRL_SINGLE_VLAN
| AR8216_PORT_CTRL_STATE
|
681 AR8216_PORT_CTRL_HEADER
| AR8216_PORT_CTRL_LEARN_LOCK
,
682 AR8216_PORT_CTRL_LEARN
| header
|
683 (egress
<< AR8216_PORT_CTRL_VLAN_MODE_S
) |
684 (AR8216_PORT_STATE_FORWARD
<< AR8216_PORT_CTRL_STATE_S
));
686 ar8xxx_rmw(priv
, AR8216_REG_PORT_VLAN(port
),
687 AR8216_PORT_VLAN_DEST_PORTS
| AR8216_PORT_VLAN_MODE
|
688 AR8216_PORT_VLAN_DEFAULT_ID
,
689 (members
<< AR8216_PORT_VLAN_DEST_PORTS_S
) |
690 (ingress
<< AR8216_PORT_VLAN_MODE_S
) |
691 (pvid
<< AR8216_PORT_VLAN_DEFAULT_ID_S
));
695 ar8216_setup_port(struct ar8xxx_priv
*priv
, int port
, u32 members
)
697 return __ar8216_setup_port(priv
, port
, members
,
698 chip_is_ar8216(priv
) && priv
->vlan
&&
699 port
== AR8216_PORT_CPU
);
703 ar8216_hw_init(struct ar8xxx_priv
*priv
)
705 if (priv
->initialized
)
708 ar8xxx_phy_init(priv
);
710 priv
->initialized
= true;
715 ar8216_init_globals(struct ar8xxx_priv
*priv
)
717 /* standard atheros magic */
718 ar8xxx_write(priv
, 0x38, 0xc000050e);
720 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
721 AR8216_GCTRL_MTU
, 1518 + 8 + 2);
725 __ar8216_init_port(struct ar8xxx_priv
*priv
, int port
,
726 bool cpu_ge
, bool flow_en
)
728 /* Enable port learning and tx */
729 ar8xxx_write(priv
, AR8216_REG_PORT_CTRL(port
),
730 AR8216_PORT_CTRL_LEARN
|
731 (4 << AR8216_PORT_CTRL_STATE_S
));
733 ar8xxx_write(priv
, AR8216_REG_PORT_VLAN(port
), 0);
735 if (port
== AR8216_PORT_CPU
) {
736 ar8xxx_write(priv
, AR8216_REG_PORT_STATUS(port
),
737 AR8216_PORT_STATUS_LINK_UP
|
738 (cpu_ge
? AR8216_PORT_SPEED_1000M
: AR8216_PORT_SPEED_100M
) |
739 AR8216_PORT_STATUS_TXMAC
|
740 AR8216_PORT_STATUS_RXMAC
|
741 (flow_en
? AR8216_PORT_STATUS_RXFLOW
: 0) |
742 (flow_en
? AR8216_PORT_STATUS_TXFLOW
: 0) |
743 AR8216_PORT_STATUS_DUPLEX
);
745 ar8xxx_write(priv
, AR8216_REG_PORT_STATUS(port
),
746 AR8216_PORT_STATUS_LINK_AUTO
);
751 ar8216_init_port(struct ar8xxx_priv
*priv
, int port
)
753 __ar8216_init_port(priv
, port
, ar8xxx_has_gige(priv
),
754 chip_is_ar8316(priv
));
758 ar8216_wait_atu_ready(struct ar8xxx_priv
*priv
, u16 r2
, u16 r1
)
762 while (ar8xxx_mii_read32(priv
, r2
, r1
) & AR8216_ATU_ACTIVE
&& --timeout
) {
768 pr_err("ar8216: timeout waiting for atu to become ready\n");
771 static void ar8216_get_arl_entry(struct ar8xxx_priv
*priv
,
772 struct arl_entry
*a
, u32
*status
, enum arl_op op
)
774 struct mii_bus
*bus
= priv
->mii_bus
;
776 u16 r1_func0
, r1_func1
, r1_func2
;
777 u32 t
, val0
, val1
, val2
;
779 split_addr(AR8216_REG_ATU_FUNC0
, &r1_func0
, &r2
, &page
);
782 r1_func1
= (AR8216_REG_ATU_FUNC1
>> 1) & 0x1e;
783 r1_func2
= (AR8216_REG_ATU_FUNC2
>> 1) & 0x1e;
786 case AR8XXX_ARL_INITIALIZE
:
787 /* all ATU registers are on the same page
788 * therefore set page only once
790 bus
->write(bus
, 0x18, 0, page
);
791 wait_for_page_switch();
793 ar8216_wait_atu_ready(priv
, r2
, r1_func0
);
795 ar8xxx_mii_write32(priv
, r2
, r1_func0
, AR8216_ATU_OP_GET_NEXT
);
796 ar8xxx_mii_write32(priv
, r2
, r1_func1
, 0);
797 ar8xxx_mii_write32(priv
, r2
, r1_func2
, 0);
799 case AR8XXX_ARL_GET_NEXT
:
800 t
= ar8xxx_mii_read32(priv
, r2
, r1_func0
);
801 t
|= AR8216_ATU_ACTIVE
;
802 ar8xxx_mii_write32(priv
, r2
, r1_func0
, t
);
803 ar8216_wait_atu_ready(priv
, r2
, r1_func0
);
805 val0
= ar8xxx_mii_read32(priv
, r2
, r1_func0
);
806 val1
= ar8xxx_mii_read32(priv
, r2
, r1_func1
);
807 val2
= ar8xxx_mii_read32(priv
, r2
, r1_func2
);
809 *status
= (val2
& AR8216_ATU_STATUS
) >> AR8216_ATU_STATUS_S
;
813 a
->portmap
= (val2
& AR8216_ATU_PORTS
) >> AR8216_ATU_PORTS_S
;
814 a
->mac
[0] = (val0
& AR8216_ATU_ADDR5
) >> AR8216_ATU_ADDR5_S
;
815 a
->mac
[1] = (val0
& AR8216_ATU_ADDR4
) >> AR8216_ATU_ADDR4_S
;
816 a
->mac
[2] = (val1
& AR8216_ATU_ADDR3
) >> AR8216_ATU_ADDR3_S
;
817 a
->mac
[3] = (val1
& AR8216_ATU_ADDR2
) >> AR8216_ATU_ADDR2_S
;
818 a
->mac
[4] = (val1
& AR8216_ATU_ADDR1
) >> AR8216_ATU_ADDR1_S
;
819 a
->mac
[5] = (val1
& AR8216_ATU_ADDR0
) >> AR8216_ATU_ADDR0_S
;
825 ar8216_phy_read(struct ar8xxx_priv
*priv
, int addr
, int regnum
)
830 if (addr
>= AR8216_NUM_PORTS
)
832 t
= (regnum
<< AR8216_MDIO_CTRL_REG_ADDR_S
) |
833 (addr
<< AR8216_MDIO_CTRL_PHY_ADDR_S
) |
834 AR8216_MDIO_CTRL_MASTER_EN
|
835 AR8216_MDIO_CTRL_BUSY
|
836 AR8216_MDIO_CTRL_CMD_READ
;
838 ar8xxx_write(priv
, AR8216_REG_MDIO_CTRL
, t
);
839 err
= ar8xxx_reg_wait(priv
, AR8216_REG_MDIO_CTRL
,
840 AR8216_MDIO_CTRL_BUSY
, 0, 5);
842 val
= ar8xxx_read(priv
, AR8216_REG_MDIO_CTRL
);
844 return val
& AR8216_MDIO_CTRL_DATA_M
;
848 ar8216_phy_write(struct ar8xxx_priv
*priv
, int addr
, int regnum
, u16 val
)
853 if (addr
>= AR8216_NUM_PORTS
)
856 t
= (addr
<< AR8216_MDIO_CTRL_PHY_ADDR_S
) |
857 (regnum
<< AR8216_MDIO_CTRL_REG_ADDR_S
) |
858 AR8216_MDIO_CTRL_MASTER_EN
|
859 AR8216_MDIO_CTRL_BUSY
|
860 AR8216_MDIO_CTRL_CMD_WRITE
|
863 ar8xxx_write(priv
, AR8216_REG_MDIO_CTRL
, t
);
864 ret
= ar8xxx_reg_wait(priv
, AR8216_REG_MDIO_CTRL
,
865 AR8216_MDIO_CTRL_BUSY
, 0, 5);
871 ar8229_hw_init(struct ar8xxx_priv
*priv
)
875 if (priv
->initialized
)
878 ar8xxx_write(priv
, AR8216_REG_CTRL
, AR8216_CTRL_RESET
);
879 ar8xxx_reg_wait(priv
, AR8216_REG_CTRL
, AR8216_CTRL_RESET
, 0, 1000);
881 phy_if_mode
= of_get_phy_mode(priv
->pdev
->of_node
);
883 if (phy_if_mode
== PHY_INTERFACE_MODE_GMII
) {
884 ar8xxx_write(priv
, AR8229_REG_OPER_MODE0
,
885 AR8229_OPER_MODE0_MAC_GMII_EN
);
886 } else if (phy_if_mode
== PHY_INTERFACE_MODE_MII
) {
887 ar8xxx_write(priv
, AR8229_REG_OPER_MODE0
,
888 AR8229_OPER_MODE0_PHY_MII_EN
);
890 pr_err("ar8229: unsupported mii mode\n");
894 if (priv
->port4_phy
) {
895 ar8xxx_write(priv
, AR8229_REG_OPER_MODE1
,
896 AR8229_REG_OPER_MODE1_PHY4_MII_EN
);
897 /* disable port5 to prevent mii conflict */
898 ar8xxx_write(priv
, AR8216_REG_PORT_STATUS(5), 0);
901 ar8xxx_phy_init(priv
);
903 priv
->initialized
= true;
908 ar8229_init_globals(struct ar8xxx_priv
*priv
)
911 /* Enable CPU port, and disable mirror port */
912 ar8xxx_write(priv
, AR8216_REG_GLOBAL_CPUPORT
,
913 AR8216_GLOBAL_CPUPORT_EN
|
914 (15 << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S
));
916 /* Setup TAG priority mapping */
917 ar8xxx_write(priv
, AR8216_REG_TAG_PRIORITY
, 0xfa50);
919 /* Enable aging, MAC replacing */
920 ar8xxx_write(priv
, AR8216_REG_ATU_CTRL
,
921 0x2b /* 5 min age time */ |
922 AR8216_ATU_CTRL_AGE_EN
|
923 AR8216_ATU_CTRL_LEARN_CHANGE
);
925 /* Enable ARP frame acknowledge */
926 ar8xxx_reg_set(priv
, AR8229_REG_QM_CTRL
,
927 AR8229_QM_CTRL_ARP_EN
);
929 /* Enable Broadcast/Multicast frames transmitted to the CPU */
930 ar8xxx_reg_set(priv
, AR8216_REG_FLOOD_MASK
,
931 AR8229_FLOOD_MASK_BC_DP(0) |
932 AR8229_FLOOD_MASK_MC_DP(0));
935 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
936 AR8236_GCTRL_MTU
, AR8236_GCTRL_MTU
);
938 /* Enable MIB counters */
939 ar8xxx_reg_set(priv
, AR8216_REG_MIB_FUNC
,
942 /* setup Service TAG */
943 ar8xxx_rmw(priv
, AR8216_REG_SERVICE_TAG
, AR8216_SERVICE_TAG_M
, 0);
947 ar8229_init_port(struct ar8xxx_priv
*priv
, int port
)
949 __ar8216_init_port(priv
, port
, true, true);
954 ar7240sw_hw_init(struct ar8xxx_priv
*priv
)
956 if (priv
->initialized
)
959 ar8xxx_write(priv
, AR8216_REG_CTRL
, AR8216_CTRL_RESET
);
960 ar8xxx_reg_wait(priv
, AR8216_REG_CTRL
, AR8216_CTRL_RESET
, 0, 1000);
963 /* disable port5 to prevent mii conflict */
964 ar8xxx_write(priv
, AR8216_REG_PORT_STATUS(5), 0);
966 ar8xxx_phy_init(priv
);
968 priv
->initialized
= true;
973 ar7240sw_init_globals(struct ar8xxx_priv
*priv
)
976 /* Enable CPU port, and disable mirror port */
977 ar8xxx_write(priv
, AR8216_REG_GLOBAL_CPUPORT
,
978 AR8216_GLOBAL_CPUPORT_EN
|
979 (15 << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S
));
981 /* Setup TAG priority mapping */
982 ar8xxx_write(priv
, AR8216_REG_TAG_PRIORITY
, 0xfa50);
984 /* Enable ARP frame acknowledge, aging, MAC replacing */
985 ar8xxx_write(priv
, AR8216_REG_ATU_CTRL
,
986 AR8216_ATU_CTRL_RESERVED
|
987 0x2b /* 5 min age time */ |
988 AR8216_ATU_CTRL_AGE_EN
|
989 AR8216_ATU_CTRL_ARP_EN
|
990 AR8216_ATU_CTRL_LEARN_CHANGE
);
992 /* Enable Broadcast frames transmitted to the CPU */
993 ar8xxx_reg_set(priv
, AR8216_REG_FLOOD_MASK
,
994 AR8236_FM_CPU_BROADCAST_EN
);
997 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
1001 /* setup Service TAG */
1002 ar8xxx_rmw(priv
, AR8216_REG_SERVICE_TAG
, AR8216_SERVICE_TAG_M
, 0);
1006 ar7240sw_setup_port(struct ar8xxx_priv
*priv
, int port
, u32 members
)
1008 return __ar8216_setup_port(priv
, port
, members
, false);
1012 ar8236_setup_port(struct ar8xxx_priv
*priv
, int port
, u32 members
)
1014 u32 egress
, ingress
;
1018 pvid
= priv
->vlan_id
[priv
->pvid
[port
]];
1019 if (priv
->vlan_tagged
& (1 << port
))
1020 egress
= AR8216_OUT_ADD_VLAN
;
1022 egress
= AR8216_OUT_STRIP_VLAN
;
1023 ingress
= AR8216_IN_SECURE
;
1026 egress
= AR8216_OUT_KEEP
;
1027 ingress
= AR8216_IN_PORT_ONLY
;
1030 ar8xxx_rmw(priv
, AR8216_REG_PORT_CTRL(port
),
1031 AR8216_PORT_CTRL_LEARN
| AR8216_PORT_CTRL_VLAN_MODE
|
1032 AR8216_PORT_CTRL_SINGLE_VLAN
| AR8216_PORT_CTRL_STATE
|
1033 AR8216_PORT_CTRL_HEADER
| AR8216_PORT_CTRL_LEARN_LOCK
,
1034 AR8216_PORT_CTRL_LEARN
|
1035 (egress
<< AR8216_PORT_CTRL_VLAN_MODE_S
) |
1036 (AR8216_PORT_STATE_FORWARD
<< AR8216_PORT_CTRL_STATE_S
));
1038 ar8xxx_rmw(priv
, AR8236_REG_PORT_VLAN(port
),
1039 AR8236_PORT_VLAN_DEFAULT_ID
,
1040 (pvid
<< AR8236_PORT_VLAN_DEFAULT_ID_S
));
1042 ar8xxx_rmw(priv
, AR8236_REG_PORT_VLAN2(port
),
1043 AR8236_PORT_VLAN2_VLAN_MODE
|
1044 AR8236_PORT_VLAN2_MEMBER
,
1045 (ingress
<< AR8236_PORT_VLAN2_VLAN_MODE_S
) |
1046 (members
<< AR8236_PORT_VLAN2_MEMBER_S
));
1050 ar8236_init_globals(struct ar8xxx_priv
*priv
)
1052 /* enable jumbo frames */
1053 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
1054 AR8316_GCTRL_MTU
, 9018 + 8 + 2);
1056 /* enable cpu port to receive arp frames */
1057 ar8xxx_reg_set(priv
, AR8216_REG_ATU_CTRL
,
1058 AR8236_ATU_CTRL_RES
);
1060 /* enable cpu port to receive multicast and broadcast frames */
1061 ar8xxx_reg_set(priv
, AR8216_REG_FLOOD_MASK
,
1062 AR8236_FM_CPU_BROADCAST_EN
| AR8236_FM_CPU_BCAST_FWD_EN
);
1064 /* Enable MIB counters */
1065 ar8xxx_rmw(priv
, AR8216_REG_MIB_FUNC
, AR8216_MIB_FUNC
| AR8236_MIB_EN
,
1066 (AR8216_MIB_FUNC_NO_OP
<< AR8216_MIB_FUNC_S
) |
1071 ar8316_hw_init(struct ar8xxx_priv
*priv
)
1075 val
= ar8xxx_read(priv
, AR8316_REG_POSTRIP
);
1077 if (priv
->phy
->interface
== PHY_INTERFACE_MODE_RGMII
) {
1078 if (priv
->port4_phy
) {
1079 /* value taken from Ubiquiti RouterStation Pro */
1080 newval
= 0x81461bea;
1081 pr_info("ar8316: Using port 4 as PHY\n");
1083 newval
= 0x01261be2;
1084 pr_info("ar8316: Using port 4 as switch port\n");
1086 } else if (priv
->phy
->interface
== PHY_INTERFACE_MODE_GMII
) {
1087 /* value taken from AVM Fritz!Box 7390 sources */
1088 newval
= 0x010e5b71;
1090 /* no known value for phy interface */
1091 pr_err("ar8316: unsupported mii mode: %d.\n",
1092 priv
->phy
->interface
);
1099 ar8xxx_write(priv
, AR8316_REG_POSTRIP
, newval
);
1101 if (priv
->port4_phy
&&
1102 priv
->phy
->interface
== PHY_INTERFACE_MODE_RGMII
) {
1103 /* work around for phy4 rgmii mode */
1104 ar8xxx_phy_dbg_write(priv
, 4, 0x12, 0x480c);
1106 ar8xxx_phy_dbg_write(priv
, 4, 0x0, 0x824e);
1108 ar8xxx_phy_dbg_write(priv
, 4, 0x5, 0x3d47);
1112 ar8xxx_phy_init(priv
);
1115 priv
->initialized
= true;
1120 ar8316_init_globals(struct ar8xxx_priv
*priv
)
1122 /* standard atheros magic */
1123 ar8xxx_write(priv
, 0x38, 0xc000050e);
1125 /* enable cpu port to receive multicast and broadcast frames */
1126 ar8xxx_write(priv
, AR8216_REG_FLOOD_MASK
, 0x003f003f);
1128 /* enable jumbo frames */
1129 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
1130 AR8316_GCTRL_MTU
, 9018 + 8 + 2);
1132 /* Enable MIB counters */
1133 ar8xxx_rmw(priv
, AR8216_REG_MIB_FUNC
, AR8216_MIB_FUNC
| AR8236_MIB_EN
,
1134 (AR8216_MIB_FUNC_NO_OP
<< AR8216_MIB_FUNC_S
) |
1139 ar8xxx_sw_set_vlan(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1140 struct switch_val
*val
)
1142 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1143 priv
->vlan
= !!val
->value
.i
;
1148 ar8xxx_sw_get_vlan(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1149 struct switch_val
*val
)
1151 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1152 val
->value
.i
= priv
->vlan
;
1158 ar8xxx_sw_set_pvid(struct switch_dev
*dev
, int port
, int vlan
)
1160 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1162 /* make sure no invalid PVIDs get set */
1164 if (vlan
< 0 || vlan
>= dev
->vlans
||
1165 port
< 0 || port
>= AR8X16_MAX_PORTS
)
1168 priv
->pvid
[port
] = vlan
;
1173 ar8xxx_sw_get_pvid(struct switch_dev
*dev
, int port
, int *vlan
)
1175 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1177 if (port
< 0 || port
>= AR8X16_MAX_PORTS
)
1180 *vlan
= priv
->pvid
[port
];
1185 ar8xxx_sw_set_vid(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1186 struct switch_val
*val
)
1188 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1190 if (val
->port_vlan
>= AR8X16_MAX_VLANS
)
1193 priv
->vlan_id
[val
->port_vlan
] = val
->value
.i
;
1198 ar8xxx_sw_get_vid(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1199 struct switch_val
*val
)
1201 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1202 val
->value
.i
= priv
->vlan_id
[val
->port_vlan
];
1207 ar8xxx_sw_get_port_link(struct switch_dev
*dev
, int port
,
1208 struct switch_port_link
*link
)
1210 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1212 ar8216_read_port_link(priv
, port
, link
);
1217 ar8xxx_sw_get_ports(struct switch_dev
*dev
, struct switch_val
*val
)
1219 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1223 if (val
->port_vlan
>= AR8X16_MAX_VLANS
)
1226 ports
= priv
->vlan_table
[val
->port_vlan
];
1228 for (i
= 0; i
< dev
->ports
; i
++) {
1229 struct switch_port
*p
;
1231 if (!(ports
& (1 << i
)))
1234 p
= &val
->value
.ports
[val
->len
++];
1236 if (priv
->vlan_tagged
& (1 << i
))
1237 p
->flags
= (1 << SWITCH_PORT_FLAG_TAGGED
);
1245 ar8xxx_sw_set_ports(struct switch_dev
*dev
, struct switch_val
*val
)
1247 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1248 u8
*vt
= &priv
->vlan_table
[val
->port_vlan
];
1252 for (i
= 0; i
< val
->len
; i
++) {
1253 struct switch_port
*p
= &val
->value
.ports
[i
];
1255 if (p
->flags
& (1 << SWITCH_PORT_FLAG_TAGGED
)) {
1256 priv
->vlan_tagged
|= (1 << p
->id
);
1258 priv
->vlan_tagged
&= ~(1 << p
->id
);
1259 priv
->pvid
[p
->id
] = val
->port_vlan
;
1261 /* make sure that an untagged port does not
1262 * appear in other vlans */
1263 for (j
= 0; j
< AR8X16_MAX_VLANS
; j
++) {
1264 if (j
== val
->port_vlan
)
1266 priv
->vlan_table
[j
] &= ~(1 << p
->id
);
1276 ar8216_set_mirror_regs(struct ar8xxx_priv
*priv
)
1280 /* reset all mirror registers */
1281 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CPUPORT
,
1282 AR8216_GLOBAL_CPUPORT_MIRROR_PORT
,
1283 (0xF << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S
));
1284 for (port
= 0; port
< AR8216_NUM_PORTS
; port
++) {
1285 ar8xxx_reg_clear(priv
, AR8216_REG_PORT_CTRL(port
),
1286 AR8216_PORT_CTRL_MIRROR_RX
);
1288 ar8xxx_reg_clear(priv
, AR8216_REG_PORT_CTRL(port
),
1289 AR8216_PORT_CTRL_MIRROR_TX
);
1292 /* now enable mirroring if necessary */
1293 if (priv
->source_port
>= AR8216_NUM_PORTS
||
1294 priv
->monitor_port
>= AR8216_NUM_PORTS
||
1295 priv
->source_port
== priv
->monitor_port
) {
1299 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CPUPORT
,
1300 AR8216_GLOBAL_CPUPORT_MIRROR_PORT
,
1301 (priv
->monitor_port
<< AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S
));
1303 if (priv
->mirror_rx
)
1304 ar8xxx_reg_set(priv
, AR8216_REG_PORT_CTRL(priv
->source_port
),
1305 AR8216_PORT_CTRL_MIRROR_RX
);
1307 if (priv
->mirror_tx
)
1308 ar8xxx_reg_set(priv
, AR8216_REG_PORT_CTRL(priv
->source_port
),
1309 AR8216_PORT_CTRL_MIRROR_TX
);
1313 ar8xxx_age_time_val(int age_time
)
1315 return (age_time
+ AR8XXX_REG_ARL_CTRL_AGE_TIME_SECS
/ 2) /
1316 AR8XXX_REG_ARL_CTRL_AGE_TIME_SECS
;
1320 ar8xxx_set_age_time(struct ar8xxx_priv
*priv
, int reg
)
1322 u32 age_time
= ar8xxx_age_time_val(priv
->arl_age_time
);
1323 ar8xxx_rmw(priv
, reg
, AR8216_ATU_CTRL_AGE_TIME
, age_time
<< AR8216_ATU_CTRL_AGE_TIME_S
);
1327 ar8xxx_sw_hw_apply(struct switch_dev
*dev
)
1329 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1330 const struct ar8xxx_chip
*chip
= priv
->chip
;
1331 u8 portmask
[AR8X16_MAX_PORTS
];
1334 mutex_lock(&priv
->reg_mutex
);
1335 /* flush all vlan translation unit entries */
1336 priv
->chip
->vtu_flush(priv
);
1338 memset(portmask
, 0, sizeof(portmask
));
1340 /* calculate the port destination masks and load vlans
1341 * into the vlan translation unit */
1342 for (j
= 0; j
< AR8X16_MAX_VLANS
; j
++) {
1343 u8 vp
= priv
->vlan_table
[j
];
1348 for (i
= 0; i
< dev
->ports
; i
++) {
1351 portmask
[i
] |= vp
& ~mask
;
1354 chip
->vtu_load_vlan(priv
, priv
->vlan_id
[j
],
1355 priv
->vlan_table
[j
]);
1359 * isolate all ports, but connect them to the cpu port */
1360 for (i
= 0; i
< dev
->ports
; i
++) {
1361 if (i
== AR8216_PORT_CPU
)
1364 portmask
[i
] = 1 << AR8216_PORT_CPU
;
1365 portmask
[AR8216_PORT_CPU
] |= (1 << i
);
1369 /* update the port destination mask registers and tag settings */
1370 for (i
= 0; i
< dev
->ports
; i
++) {
1371 chip
->setup_port(priv
, i
, portmask
[i
]);
1374 chip
->set_mirror_regs(priv
);
1377 if (chip
->reg_arl_ctrl
)
1378 ar8xxx_set_age_time(priv
, chip
->reg_arl_ctrl
);
1380 mutex_unlock(&priv
->reg_mutex
);
1385 ar8xxx_sw_reset_switch(struct switch_dev
*dev
)
1387 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1388 const struct ar8xxx_chip
*chip
= priv
->chip
;
1391 mutex_lock(&priv
->reg_mutex
);
1392 memset(&priv
->vlan
, 0, sizeof(struct ar8xxx_priv
) -
1393 offsetof(struct ar8xxx_priv
, vlan
));
1395 for (i
= 0; i
< AR8X16_MAX_VLANS
; i
++)
1396 priv
->vlan_id
[i
] = i
;
1398 /* Configure all ports */
1399 for (i
= 0; i
< dev
->ports
; i
++)
1400 chip
->init_port(priv
, i
);
1402 priv
->mirror_rx
= false;
1403 priv
->mirror_tx
= false;
1404 priv
->source_port
= 0;
1405 priv
->monitor_port
= 0;
1406 priv
->arl_age_time
= AR8XXX_DEFAULT_ARL_AGE_TIME
;
1408 chip
->init_globals(priv
);
1409 chip
->atu_flush(priv
);
1411 mutex_unlock(&priv
->reg_mutex
);
1413 return chip
->sw_hw_apply(dev
);
1417 ar8xxx_sw_set_reset_mibs(struct switch_dev
*dev
,
1418 const struct switch_attr
*attr
,
1419 struct switch_val
*val
)
1421 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1425 if (!ar8xxx_has_mib_counters(priv
))
1428 mutex_lock(&priv
->mib_lock
);
1430 len
= priv
->dev
.ports
* priv
->chip
->num_mibs
*
1431 sizeof(*priv
->mib_stats
);
1432 memset(priv
->mib_stats
, '\0', len
);
1433 ret
= ar8xxx_mib_flush(priv
);
1440 mutex_unlock(&priv
->mib_lock
);
1445 ar8xxx_sw_set_mirror_rx_enable(struct switch_dev
*dev
,
1446 const struct switch_attr
*attr
,
1447 struct switch_val
*val
)
1449 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1451 mutex_lock(&priv
->reg_mutex
);
1452 priv
->mirror_rx
= !!val
->value
.i
;
1453 priv
->chip
->set_mirror_regs(priv
);
1454 mutex_unlock(&priv
->reg_mutex
);
1460 ar8xxx_sw_get_mirror_rx_enable(struct switch_dev
*dev
,
1461 const struct switch_attr
*attr
,
1462 struct switch_val
*val
)
1464 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1465 val
->value
.i
= priv
->mirror_rx
;
1470 ar8xxx_sw_set_mirror_tx_enable(struct switch_dev
*dev
,
1471 const struct switch_attr
*attr
,
1472 struct switch_val
*val
)
1474 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1476 mutex_lock(&priv
->reg_mutex
);
1477 priv
->mirror_tx
= !!val
->value
.i
;
1478 priv
->chip
->set_mirror_regs(priv
);
1479 mutex_unlock(&priv
->reg_mutex
);
1485 ar8xxx_sw_get_mirror_tx_enable(struct switch_dev
*dev
,
1486 const struct switch_attr
*attr
,
1487 struct switch_val
*val
)
1489 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1490 val
->value
.i
= priv
->mirror_tx
;
1495 ar8xxx_sw_set_mirror_monitor_port(struct switch_dev
*dev
,
1496 const struct switch_attr
*attr
,
1497 struct switch_val
*val
)
1499 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1501 mutex_lock(&priv
->reg_mutex
);
1502 priv
->monitor_port
= val
->value
.i
;
1503 priv
->chip
->set_mirror_regs(priv
);
1504 mutex_unlock(&priv
->reg_mutex
);
1510 ar8xxx_sw_get_mirror_monitor_port(struct switch_dev
*dev
,
1511 const struct switch_attr
*attr
,
1512 struct switch_val
*val
)
1514 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1515 val
->value
.i
= priv
->monitor_port
;
1520 ar8xxx_sw_set_mirror_source_port(struct switch_dev
*dev
,
1521 const struct switch_attr
*attr
,
1522 struct switch_val
*val
)
1524 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1526 mutex_lock(&priv
->reg_mutex
);
1527 priv
->source_port
= val
->value
.i
;
1528 priv
->chip
->set_mirror_regs(priv
);
1529 mutex_unlock(&priv
->reg_mutex
);
1535 ar8xxx_sw_get_mirror_source_port(struct switch_dev
*dev
,
1536 const struct switch_attr
*attr
,
1537 struct switch_val
*val
)
1539 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1540 val
->value
.i
= priv
->source_port
;
1545 ar8xxx_sw_set_port_reset_mib(struct switch_dev
*dev
,
1546 const struct switch_attr
*attr
,
1547 struct switch_val
*val
)
1549 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1553 if (!ar8xxx_has_mib_counters(priv
))
1556 port
= val
->port_vlan
;
1557 if (port
>= dev
->ports
)
1560 mutex_lock(&priv
->mib_lock
);
1561 ret
= ar8xxx_mib_capture(priv
);
1565 ar8xxx_mib_fetch_port_stat(priv
, port
, true);
1570 mutex_unlock(&priv
->mib_lock
);
1575 ar8xxx_byte_to_str(char *buf
, int len
, u64 byte
)
1580 if (byte
>= 0x40000000) { /* 1 GiB */
1581 b
= byte
* 10 / 0x40000000;
1583 } else if (byte
>= 0x100000) { /* 1 MiB */
1584 b
= byte
* 10 / 0x100000;
1586 } else if (byte
>= 0x400) { /* 1 KiB */
1587 b
= byte
* 10 / 0x400;
1593 if (strcmp(unit
, "Byte"))
1594 snprintf(buf
, len
, "%lu.%lu %s", b
/ 10, b
% 10, unit
);
1596 snprintf(buf
, len
, "%lu %s", b
, unit
);
1600 ar8xxx_sw_get_port_mib(struct switch_dev
*dev
,
1601 const struct switch_attr
*attr
,
1602 struct switch_val
*val
)
1604 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1605 const struct ar8xxx_chip
*chip
= priv
->chip
;
1606 u64
*mib_stats
, mib_data
;
1609 char *buf
= priv
->buf
;
1611 const char *mib_name
;
1613 bool mib_stats_empty
= true;
1615 if (!ar8xxx_has_mib_counters(priv
))
1618 port
= val
->port_vlan
;
1619 if (port
>= dev
->ports
)
1622 mutex_lock(&priv
->mib_lock
);
1623 ret
= ar8xxx_mib_capture(priv
);
1627 ar8xxx_mib_fetch_port_stat(priv
, port
, false);
1629 len
+= snprintf(buf
+ len
, sizeof(priv
->buf
) - len
,
1632 mib_stats
= &priv
->mib_stats
[port
* chip
->num_mibs
];
1633 for (i
= 0; i
< chip
->num_mibs
; i
++) {
1634 mib_name
= chip
->mib_decs
[i
].name
;
1635 mib_data
= mib_stats
[i
];
1636 len
+= snprintf(buf
+ len
, sizeof(priv
->buf
) - len
,
1637 "%-12s: %llu\n", mib_name
, mib_data
);
1638 if ((!strcmp(mib_name
, "TxByte") ||
1639 !strcmp(mib_name
, "RxGoodByte")) &&
1641 ar8xxx_byte_to_str(buf1
, sizeof(buf1
), mib_data
);
1642 --len
; /* discard newline at the end of buf */
1643 len
+= snprintf(buf
+ len
, sizeof(priv
->buf
) - len
,
1646 if (mib_stats_empty
&& mib_data
)
1647 mib_stats_empty
= false;
1650 if (mib_stats_empty
)
1651 len
= snprintf(buf
, sizeof(priv
->buf
), "No MIB data");
1659 mutex_unlock(&priv
->mib_lock
);
1664 ar8xxx_sw_set_arl_age_time(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1665 struct switch_val
*val
)
1667 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1668 int age_time
= val
->value
.i
;
1674 age_time_val
= ar8xxx_age_time_val(age_time
);
1675 if (age_time_val
== 0 || age_time_val
> 0xffff)
1678 priv
->arl_age_time
= age_time
;
1683 ar8xxx_sw_get_arl_age_time(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1684 struct switch_val
*val
)
1686 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1687 val
->value
.i
= priv
->arl_age_time
;
1692 ar8xxx_sw_get_arl_table(struct switch_dev
*dev
,
1693 const struct switch_attr
*attr
,
1694 struct switch_val
*val
)
1696 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1697 struct mii_bus
*bus
= priv
->mii_bus
;
1698 const struct ar8xxx_chip
*chip
= priv
->chip
;
1699 char *buf
= priv
->arl_buf
;
1700 int i
, j
, k
, len
= 0;
1701 struct arl_entry
*a
, *a1
;
1704 if (!chip
->get_arl_entry
)
1707 mutex_lock(&priv
->reg_mutex
);
1708 mutex_lock(&bus
->mdio_lock
);
1710 chip
->get_arl_entry(priv
, NULL
, NULL
, AR8XXX_ARL_INITIALIZE
);
1712 for(i
= 0; i
< AR8XXX_NUM_ARL_RECORDS
; ++i
) {
1713 a
= &priv
->arl_table
[i
];
1715 chip
->get_arl_entry(priv
, a
, &status
, AR8XXX_ARL_GET_NEXT
);
1721 * ARL table can include multiple valid entries
1722 * per MAC, just with differing status codes
1724 for (j
= 0; j
< i
; ++j
) {
1725 a1
= &priv
->arl_table
[j
];
1726 if (!memcmp(a
->mac
, a1
->mac
, sizeof(a
->mac
))) {
1727 /* ignore ports already seen in former entry */
1728 a
->portmap
&= ~a1
->portmap
;
1735 mutex_unlock(&bus
->mdio_lock
);
1737 len
+= snprintf(buf
+ len
, sizeof(priv
->arl_buf
) - len
,
1738 "address resolution table\n");
1740 if (i
== AR8XXX_NUM_ARL_RECORDS
)
1741 len
+= snprintf(buf
+ len
, sizeof(priv
->arl_buf
) - len
,
1742 "Too many entries found, displaying the first %d only!\n",
1743 AR8XXX_NUM_ARL_RECORDS
);
1745 for (j
= 0; j
< priv
->dev
.ports
; ++j
) {
1746 for (k
= 0; k
< i
; ++k
) {
1747 a
= &priv
->arl_table
[k
];
1748 if (!(a
->portmap
& BIT(j
)))
1750 len
+= snprintf(buf
+ len
, sizeof(priv
->arl_buf
) - len
,
1751 "Port %d: MAC %02x:%02x:%02x:%02x:%02x:%02x\n",
1753 a
->mac
[5], a
->mac
[4], a
->mac
[3],
1754 a
->mac
[2], a
->mac
[1], a
->mac
[0]);
1761 mutex_unlock(&priv
->reg_mutex
);
1767 ar8xxx_sw_set_flush_arl_table(struct switch_dev
*dev
,
1768 const struct switch_attr
*attr
,
1769 struct switch_val
*val
)
1771 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1774 mutex_lock(&priv
->reg_mutex
);
1775 ret
= priv
->chip
->atu_flush(priv
);
1776 mutex_unlock(&priv
->reg_mutex
);
1782 ar8xxx_sw_set_flush_port_arl_table(struct switch_dev
*dev
,
1783 const struct switch_attr
*attr
,
1784 struct switch_val
*val
)
1786 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1789 port
= val
->port_vlan
;
1790 if (port
>= dev
->ports
)
1793 mutex_lock(&priv
->reg_mutex
);
1794 ret
= priv
->chip
->atu_flush_port(priv
, port
);
1795 mutex_unlock(&priv
->reg_mutex
);
1801 ar8xxx_sw_get_port_stats(struct switch_dev
*dev
, int port
,
1802 struct switch_port_stats
*stats
)
1804 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1807 if (!ar8xxx_has_mib_counters(priv
))
1810 if (!(priv
->chip
->mib_rxb_id
|| priv
->chip
->mib_txb_id
))
1813 if (port
>= dev
->ports
)
1816 mutex_lock(&priv
->mib_lock
);
1818 mib_stats
= &priv
->mib_stats
[port
* priv
->chip
->num_mibs
];
1820 stats
->tx_bytes
= mib_stats
[priv
->chip
->mib_txb_id
];
1821 stats
->rx_bytes
= mib_stats
[priv
->chip
->mib_rxb_id
];
1823 mutex_unlock(&priv
->mib_lock
);
1828 ar8xxx_phy_read(struct mii_bus
*bus
, int phy_addr
, int reg_addr
)
1830 struct ar8xxx_priv
*priv
= bus
->priv
;
1831 return priv
->chip
->phy_read(priv
, phy_addr
, reg_addr
);
1835 ar8xxx_phy_write(struct mii_bus
*bus
, int phy_addr
, int reg_addr
,
1838 struct ar8xxx_priv
*priv
= bus
->priv
;
1839 return priv
->chip
->phy_write(priv
, phy_addr
, reg_addr
, reg_val
);
1842 static const struct switch_attr ar8xxx_sw_attr_globals
[] = {
1844 .type
= SWITCH_TYPE_INT
,
1845 .name
= "enable_vlan",
1846 .description
= "Enable VLAN mode",
1847 .set
= ar8xxx_sw_set_vlan
,
1848 .get
= ar8xxx_sw_get_vlan
,
1852 .type
= SWITCH_TYPE_NOVAL
,
1853 .name
= "reset_mibs",
1854 .description
= "Reset all MIB counters",
1855 .set
= ar8xxx_sw_set_reset_mibs
,
1858 .type
= SWITCH_TYPE_INT
,
1859 .name
= "enable_mirror_rx",
1860 .description
= "Enable mirroring of RX packets",
1861 .set
= ar8xxx_sw_set_mirror_rx_enable
,
1862 .get
= ar8xxx_sw_get_mirror_rx_enable
,
1866 .type
= SWITCH_TYPE_INT
,
1867 .name
= "enable_mirror_tx",
1868 .description
= "Enable mirroring of TX packets",
1869 .set
= ar8xxx_sw_set_mirror_tx_enable
,
1870 .get
= ar8xxx_sw_get_mirror_tx_enable
,
1874 .type
= SWITCH_TYPE_INT
,
1875 .name
= "mirror_monitor_port",
1876 .description
= "Mirror monitor port",
1877 .set
= ar8xxx_sw_set_mirror_monitor_port
,
1878 .get
= ar8xxx_sw_get_mirror_monitor_port
,
1879 .max
= AR8216_NUM_PORTS
- 1
1882 .type
= SWITCH_TYPE_INT
,
1883 .name
= "mirror_source_port",
1884 .description
= "Mirror source port",
1885 .set
= ar8xxx_sw_set_mirror_source_port
,
1886 .get
= ar8xxx_sw_get_mirror_source_port
,
1887 .max
= AR8216_NUM_PORTS
- 1
1890 .type
= SWITCH_TYPE_STRING
,
1891 .name
= "arl_table",
1892 .description
= "Get ARL table",
1894 .get
= ar8xxx_sw_get_arl_table
,
1897 .type
= SWITCH_TYPE_NOVAL
,
1898 .name
= "flush_arl_table",
1899 .description
= "Flush ARL table",
1900 .set
= ar8xxx_sw_set_flush_arl_table
,
1904 const struct switch_attr ar8xxx_sw_attr_port
[] = {
1906 .type
= SWITCH_TYPE_NOVAL
,
1907 .name
= "reset_mib",
1908 .description
= "Reset single port MIB counters",
1909 .set
= ar8xxx_sw_set_port_reset_mib
,
1912 .type
= SWITCH_TYPE_STRING
,
1914 .description
= "Get port's MIB counters",
1916 .get
= ar8xxx_sw_get_port_mib
,
1919 .type
= SWITCH_TYPE_NOVAL
,
1920 .name
= "flush_arl_table",
1921 .description
= "Flush port's ARL table entries",
1922 .set
= ar8xxx_sw_set_flush_port_arl_table
,
1926 const struct switch_attr ar8xxx_sw_attr_vlan
[1] = {
1928 .type
= SWITCH_TYPE_INT
,
1930 .description
= "VLAN ID (0-4094)",
1931 .set
= ar8xxx_sw_set_vid
,
1932 .get
= ar8xxx_sw_get_vid
,
1937 static const struct switch_dev_ops ar8xxx_sw_ops
= {
1939 .attr
= ar8xxx_sw_attr_globals
,
1940 .n_attr
= ARRAY_SIZE(ar8xxx_sw_attr_globals
),
1943 .attr
= ar8xxx_sw_attr_port
,
1944 .n_attr
= ARRAY_SIZE(ar8xxx_sw_attr_port
),
1947 .attr
= ar8xxx_sw_attr_vlan
,
1948 .n_attr
= ARRAY_SIZE(ar8xxx_sw_attr_vlan
),
1950 .get_port_pvid
= ar8xxx_sw_get_pvid
,
1951 .set_port_pvid
= ar8xxx_sw_set_pvid
,
1952 .get_vlan_ports
= ar8xxx_sw_get_ports
,
1953 .set_vlan_ports
= ar8xxx_sw_set_ports
,
1954 .apply_config
= ar8xxx_sw_hw_apply
,
1955 .reset_switch
= ar8xxx_sw_reset_switch
,
1956 .get_port_link
= ar8xxx_sw_get_port_link
,
1957 .get_port_stats
= ar8xxx_sw_get_port_stats
,
1960 static const struct ar8xxx_chip ar7240sw_chip
= {
1961 .caps
= AR8XXX_CAP_MIB_COUNTERS
,
1963 .reg_port_stats_start
= 0x20000,
1964 .reg_port_stats_length
= 0x100,
1965 .reg_arl_ctrl
= AR8216_REG_ATU_CTRL
,
1967 .name
= "Atheros AR724X/AR933X built-in",
1968 .ports
= AR7240SW_NUM_PORTS
,
1969 .vlans
= AR8216_NUM_VLANS
,
1970 .swops
= &ar8xxx_sw_ops
,
1972 .hw_init
= ar7240sw_hw_init
,
1973 .init_globals
= ar7240sw_init_globals
,
1974 .init_port
= ar8229_init_port
,
1975 .phy_read
= ar8216_phy_read
,
1976 .phy_write
= ar8216_phy_write
,
1977 .setup_port
= ar7240sw_setup_port
,
1978 .read_port_status
= ar8216_read_port_status
,
1979 .atu_flush
= ar8216_atu_flush
,
1980 .atu_flush_port
= ar8216_atu_flush_port
,
1981 .vtu_flush
= ar8216_vtu_flush
,
1982 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
1983 .set_mirror_regs
= ar8216_set_mirror_regs
,
1984 .get_arl_entry
= ar8216_get_arl_entry
,
1985 .sw_hw_apply
= ar8xxx_sw_hw_apply
,
1987 .num_mibs
= ARRAY_SIZE(ar8236_mibs
),
1988 .mib_decs
= ar8236_mibs
,
1989 .mib_func
= AR8216_REG_MIB_FUNC
,
1990 .mib_rxb_id
= AR8236_MIB_RXB_ID
,
1991 .mib_txb_id
= AR8236_MIB_TXB_ID
,
1994 static const struct ar8xxx_chip ar8216_chip
= {
1995 .caps
= AR8XXX_CAP_MIB_COUNTERS
,
1997 .reg_port_stats_start
= 0x19000,
1998 .reg_port_stats_length
= 0xa0,
1999 .reg_arl_ctrl
= AR8216_REG_ATU_CTRL
,
2001 .name
= "Atheros AR8216",
2002 .ports
= AR8216_NUM_PORTS
,
2003 .vlans
= AR8216_NUM_VLANS
,
2004 .swops
= &ar8xxx_sw_ops
,
2006 .hw_init
= ar8216_hw_init
,
2007 .init_globals
= ar8216_init_globals
,
2008 .init_port
= ar8216_init_port
,
2009 .setup_port
= ar8216_setup_port
,
2010 .read_port_status
= ar8216_read_port_status
,
2011 .atu_flush
= ar8216_atu_flush
,
2012 .atu_flush_port
= ar8216_atu_flush_port
,
2013 .vtu_flush
= ar8216_vtu_flush
,
2014 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
2015 .set_mirror_regs
= ar8216_set_mirror_regs
,
2016 .get_arl_entry
= ar8216_get_arl_entry
,
2017 .sw_hw_apply
= ar8xxx_sw_hw_apply
,
2019 .num_mibs
= ARRAY_SIZE(ar8216_mibs
),
2020 .mib_decs
= ar8216_mibs
,
2021 .mib_func
= AR8216_REG_MIB_FUNC
,
2022 .mib_rxb_id
= AR8216_MIB_RXB_ID
,
2023 .mib_txb_id
= AR8216_MIB_TXB_ID
,
2026 static const struct ar8xxx_chip ar8229_chip
= {
2027 .caps
= AR8XXX_CAP_MIB_COUNTERS
,
2029 .reg_port_stats_start
= 0x20000,
2030 .reg_port_stats_length
= 0x100,
2031 .reg_arl_ctrl
= AR8216_REG_ATU_CTRL
,
2033 .name
= "Atheros AR8229",
2034 .ports
= AR8216_NUM_PORTS
,
2035 .vlans
= AR8216_NUM_VLANS
,
2036 .swops
= &ar8xxx_sw_ops
,
2038 .hw_init
= ar8229_hw_init
,
2039 .init_globals
= ar8229_init_globals
,
2040 .init_port
= ar8229_init_port
,
2041 .phy_read
= ar8216_phy_read
,
2042 .phy_write
= ar8216_phy_write
,
2043 .setup_port
= ar8236_setup_port
,
2044 .read_port_status
= ar8216_read_port_status
,
2045 .atu_flush
= ar8216_atu_flush
,
2046 .atu_flush_port
= ar8216_atu_flush_port
,
2047 .vtu_flush
= ar8216_vtu_flush
,
2048 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
2049 .set_mirror_regs
= ar8216_set_mirror_regs
,
2050 .get_arl_entry
= ar8216_get_arl_entry
,
2051 .sw_hw_apply
= ar8xxx_sw_hw_apply
,
2053 .num_mibs
= ARRAY_SIZE(ar8236_mibs
),
2054 .mib_decs
= ar8236_mibs
,
2055 .mib_func
= AR8216_REG_MIB_FUNC
,
2056 .mib_rxb_id
= AR8236_MIB_RXB_ID
,
2057 .mib_txb_id
= AR8236_MIB_TXB_ID
,
2060 static const struct ar8xxx_chip ar8236_chip
= {
2061 .caps
= AR8XXX_CAP_MIB_COUNTERS
,
2063 .reg_port_stats_start
= 0x20000,
2064 .reg_port_stats_length
= 0x100,
2065 .reg_arl_ctrl
= AR8216_REG_ATU_CTRL
,
2067 .name
= "Atheros AR8236",
2068 .ports
= AR8216_NUM_PORTS
,
2069 .vlans
= AR8216_NUM_VLANS
,
2070 .swops
= &ar8xxx_sw_ops
,
2072 .hw_init
= ar8216_hw_init
,
2073 .init_globals
= ar8236_init_globals
,
2074 .init_port
= ar8216_init_port
,
2075 .setup_port
= ar8236_setup_port
,
2076 .read_port_status
= ar8216_read_port_status
,
2077 .atu_flush
= ar8216_atu_flush
,
2078 .atu_flush_port
= ar8216_atu_flush_port
,
2079 .vtu_flush
= ar8216_vtu_flush
,
2080 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
2081 .set_mirror_regs
= ar8216_set_mirror_regs
,
2082 .get_arl_entry
= ar8216_get_arl_entry
,
2083 .sw_hw_apply
= ar8xxx_sw_hw_apply
,
2085 .num_mibs
= ARRAY_SIZE(ar8236_mibs
),
2086 .mib_decs
= ar8236_mibs
,
2087 .mib_func
= AR8216_REG_MIB_FUNC
,
2088 .mib_rxb_id
= AR8236_MIB_RXB_ID
,
2089 .mib_txb_id
= AR8236_MIB_TXB_ID
,
2092 static const struct ar8xxx_chip ar8316_chip
= {
2093 .caps
= AR8XXX_CAP_GIGE
| AR8XXX_CAP_MIB_COUNTERS
,
2095 .reg_port_stats_start
= 0x20000,
2096 .reg_port_stats_length
= 0x100,
2097 .reg_arl_ctrl
= AR8216_REG_ATU_CTRL
,
2099 .name
= "Atheros AR8316",
2100 .ports
= AR8216_NUM_PORTS
,
2101 .vlans
= AR8X16_MAX_VLANS
,
2102 .swops
= &ar8xxx_sw_ops
,
2104 .hw_init
= ar8316_hw_init
,
2105 .init_globals
= ar8316_init_globals
,
2106 .init_port
= ar8216_init_port
,
2107 .setup_port
= ar8216_setup_port
,
2108 .read_port_status
= ar8216_read_port_status
,
2109 .atu_flush
= ar8216_atu_flush
,
2110 .atu_flush_port
= ar8216_atu_flush_port
,
2111 .vtu_flush
= ar8216_vtu_flush
,
2112 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
2113 .set_mirror_regs
= ar8216_set_mirror_regs
,
2114 .get_arl_entry
= ar8216_get_arl_entry
,
2115 .sw_hw_apply
= ar8xxx_sw_hw_apply
,
2117 .num_mibs
= ARRAY_SIZE(ar8236_mibs
),
2118 .mib_decs
= ar8236_mibs
,
2119 .mib_func
= AR8216_REG_MIB_FUNC
,
2120 .mib_rxb_id
= AR8236_MIB_RXB_ID
,
2121 .mib_txb_id
= AR8236_MIB_TXB_ID
,
2125 ar8xxx_read_id(struct ar8xxx_priv
*priv
)
2131 val
= ar8xxx_read(priv
, AR8216_REG_CTRL
);
2135 id
= val
& (AR8216_CTRL_REVISION
| AR8216_CTRL_VERSION
);
2136 for (i
= 0; i
< AR8X16_PROBE_RETRIES
; i
++) {
2139 val
= ar8xxx_read(priv
, AR8216_REG_CTRL
);
2143 t
= val
& (AR8216_CTRL_REVISION
| AR8216_CTRL_VERSION
);
2148 priv
->chip_ver
= (id
& AR8216_CTRL_VERSION
) >> AR8216_CTRL_VERSION_S
;
2149 priv
->chip_rev
= (id
& AR8216_CTRL_REVISION
);
2154 ar8xxx_id_chip(struct ar8xxx_priv
*priv
)
2158 ret
= ar8xxx_read_id(priv
);
2162 switch (priv
->chip_ver
) {
2163 case AR8XXX_VER_AR8216
:
2164 priv
->chip
= &ar8216_chip
;
2166 case AR8XXX_VER_AR8236
:
2167 priv
->chip
= &ar8236_chip
;
2169 case AR8XXX_VER_AR8316
:
2170 priv
->chip
= &ar8316_chip
;
2172 case AR8XXX_VER_AR8327
:
2173 priv
->chip
= &ar8327_chip
;
2175 case AR8XXX_VER_AR8337
:
2176 priv
->chip
= &ar8337_chip
;
2179 pr_err("ar8216: Unknown Atheros device [ver=%d, rev=%d]\n",
2180 priv
->chip_ver
, priv
->chip_rev
);
2189 ar8xxx_mib_work_func(struct work_struct
*work
)
2191 struct ar8xxx_priv
*priv
;
2194 priv
= container_of(work
, struct ar8xxx_priv
, mib_work
.work
);
2196 mutex_lock(&priv
->mib_lock
);
2198 err
= ar8xxx_mib_capture(priv
);
2202 ar8xxx_mib_fetch_port_stat(priv
, priv
->mib_next_port
, false);
2205 priv
->mib_next_port
++;
2206 if (priv
->mib_next_port
>= priv
->dev
.ports
)
2207 priv
->mib_next_port
= 0;
2209 mutex_unlock(&priv
->mib_lock
);
2210 schedule_delayed_work(&priv
->mib_work
,
2211 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY
));
2215 ar8xxx_mib_init(struct ar8xxx_priv
*priv
)
2219 if (!ar8xxx_has_mib_counters(priv
))
2222 BUG_ON(!priv
->chip
->mib_decs
|| !priv
->chip
->num_mibs
);
2224 len
= priv
->dev
.ports
* priv
->chip
->num_mibs
*
2225 sizeof(*priv
->mib_stats
);
2226 priv
->mib_stats
= kzalloc(len
, GFP_KERNEL
);
2228 if (!priv
->mib_stats
)
2235 ar8xxx_mib_start(struct ar8xxx_priv
*priv
)
2237 if (!ar8xxx_has_mib_counters(priv
))
2240 schedule_delayed_work(&priv
->mib_work
,
2241 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY
));
2245 ar8xxx_mib_stop(struct ar8xxx_priv
*priv
)
2247 if (!ar8xxx_has_mib_counters(priv
))
2250 cancel_delayed_work_sync(&priv
->mib_work
);
2253 static struct ar8xxx_priv
*
2256 struct ar8xxx_priv
*priv
;
2258 priv
= kzalloc(sizeof(struct ar8xxx_priv
), GFP_KERNEL
);
2262 mutex_init(&priv
->reg_mutex
);
2263 mutex_init(&priv
->mib_lock
);
2264 INIT_DELAYED_WORK(&priv
->mib_work
, ar8xxx_mib_work_func
);
2270 ar8xxx_free(struct ar8xxx_priv
*priv
)
2272 if (priv
->chip
&& priv
->chip
->cleanup
)
2273 priv
->chip
->cleanup(priv
);
2275 kfree(priv
->chip_data
);
2276 kfree(priv
->mib_stats
);
2281 ar8xxx_probe_switch(struct ar8xxx_priv
*priv
)
2283 const struct ar8xxx_chip
*chip
;
2284 struct switch_dev
*swdev
;
2290 swdev
->cpu_port
= AR8216_PORT_CPU
;
2291 swdev
->name
= chip
->name
;
2292 swdev
->vlans
= chip
->vlans
;
2293 swdev
->ports
= chip
->ports
;
2294 swdev
->ops
= chip
->swops
;
2296 ret
= ar8xxx_mib_init(priv
);
2304 ar8xxx_start(struct ar8xxx_priv
*priv
)
2310 ret
= priv
->chip
->hw_init(priv
);
2314 ret
= ar8xxx_sw_reset_switch(&priv
->dev
);
2320 ar8xxx_mib_start(priv
);
2326 ar8xxx_phy_config_init(struct phy_device
*phydev
)
2328 struct ar8xxx_priv
*priv
= phydev
->priv
;
2329 struct net_device
*dev
= phydev
->attached_dev
;
2335 if (priv
->chip
->config_at_probe
)
2336 return ar8xxx_phy_check_aneg(phydev
);
2340 if (phydev
->mdio
.addr
!= 0) {
2341 if (chip_is_ar8316(priv
)) {
2342 /* switch device has been initialized, reinit */
2343 priv
->dev
.ports
= (AR8216_NUM_PORTS
- 1);
2344 priv
->initialized
= false;
2345 priv
->port4_phy
= true;
2346 ar8316_hw_init(priv
);
2353 ret
= ar8xxx_start(priv
);
2357 /* VID fixup only needed on ar8216 */
2358 if (chip_is_ar8216(priv
)) {
2359 dev
->phy_ptr
= priv
;
2360 dev
->priv_flags
|= IFF_NO_IP_ALIGN
;
2361 dev
->eth_mangle_rx
= ar8216_mangle_rx
;
2362 dev
->eth_mangle_tx
= ar8216_mangle_tx
;
2369 ar8xxx_check_link_states(struct ar8xxx_priv
*priv
)
2371 bool link_new
, changed
= false;
2375 mutex_lock(&priv
->reg_mutex
);
2377 for (i
= 0; i
< priv
->dev
.ports
; i
++) {
2378 status
= priv
->chip
->read_port_status(priv
, i
);
2379 link_new
= !!(status
& AR8216_PORT_STATUS_LINK_UP
);
2380 if (link_new
== priv
->link_up
[i
])
2383 priv
->link_up
[i
] = link_new
;
2385 /* flush ARL entries for this port if it went down*/
2387 priv
->chip
->atu_flush_port(priv
, i
);
2388 dev_info(&priv
->phy
->mdio
.dev
, "Port %d is %s\n",
2389 i
, link_new
? "up" : "down");
2392 mutex_unlock(&priv
->reg_mutex
);
2398 ar8xxx_phy_read_status(struct phy_device
*phydev
)
2400 struct ar8xxx_priv
*priv
= phydev
->priv
;
2401 struct switch_port_link link
;
2403 /* check for switch port link changes */
2404 if (phydev
->state
== PHY_CHANGELINK
)
2405 ar8xxx_check_link_states(priv
);
2407 if (phydev
->mdio
.addr
!= 0)
2408 return genphy_read_status(phydev
);
2410 ar8216_read_port_link(priv
, phydev
->mdio
.addr
, &link
);
2411 phydev
->link
= !!link
.link
;
2415 switch (link
.speed
) {
2416 case SWITCH_PORT_SPEED_10
:
2417 phydev
->speed
= SPEED_10
;
2419 case SWITCH_PORT_SPEED_100
:
2420 phydev
->speed
= SPEED_100
;
2422 case SWITCH_PORT_SPEED_1000
:
2423 phydev
->speed
= SPEED_1000
;
2428 phydev
->duplex
= link
.duplex
? DUPLEX_FULL
: DUPLEX_HALF
;
2430 phydev
->state
= PHY_RUNNING
;
2431 netif_carrier_on(phydev
->attached_dev
);
2432 if (phydev
->adjust_link
)
2433 phydev
->adjust_link(phydev
->attached_dev
);
2439 ar8xxx_phy_config_aneg(struct phy_device
*phydev
)
2441 if (phydev
->mdio
.addr
== 0)
2444 return genphy_config_aneg(phydev
);
2447 static const u32 ar8xxx_phy_ids
[] = {
2449 0x004dd034, /* AR8327 */
2450 0x004dd036, /* AR8337 */
2453 0x004dd043, /* AR8236 */
2457 ar8xxx_phy_match(u32 phy_id
)
2461 for (i
= 0; i
< ARRAY_SIZE(ar8xxx_phy_ids
); i
++)
2462 if (phy_id
== ar8xxx_phy_ids
[i
])
2469 ar8xxx_is_possible(struct mii_bus
*bus
)
2471 unsigned int i
, found_phys
= 0;
2473 for (i
= 0; i
< 5; i
++) {
2476 phy_id
= mdiobus_read(bus
, i
, MII_PHYSID1
) << 16;
2477 phy_id
|= mdiobus_read(bus
, i
, MII_PHYSID2
);
2478 if (ar8xxx_phy_match(phy_id
)) {
2480 } else if (phy_id
) {
2481 pr_debug("ar8xxx: unknown PHY at %s:%02x id:%08x\n",
2482 dev_name(&bus
->dev
), i
, phy_id
);
2485 return !!found_phys
;
2489 ar8xxx_phy_probe(struct phy_device
*phydev
)
2491 struct ar8xxx_priv
*priv
;
2492 struct switch_dev
*swdev
;
2495 /* skip PHYs at unused adresses */
2496 if (phydev
->mdio
.addr
!= 0 && phydev
->mdio
.addr
!= 3 && phydev
->mdio
.addr
!= 4)
2499 if (!ar8xxx_is_possible(phydev
->mdio
.bus
))
2502 mutex_lock(&ar8xxx_dev_list_lock
);
2503 list_for_each_entry(priv
, &ar8xxx_dev_list
, list
)
2504 if (priv
->mii_bus
== phydev
->mdio
.bus
)
2507 priv
= ar8xxx_create();
2513 priv
->mii_bus
= phydev
->mdio
.bus
;
2514 priv
->pdev
= &phydev
->mdio
.dev
;
2516 ret
= ar8xxx_id_chip(priv
);
2520 ret
= ar8xxx_probe_switch(priv
);
2525 swdev
->alias
= dev_name(&priv
->mii_bus
->dev
);
2526 ret
= register_switch(swdev
, NULL
);
2530 pr_info("%s: %s rev. %u switch registered on %s\n",
2531 swdev
->devname
, swdev
->name
, priv
->chip_rev
,
2532 dev_name(&priv
->mii_bus
->dev
));
2534 list_add(&priv
->list
, &ar8xxx_dev_list
);
2539 if (phydev
->mdio
.addr
== 0) {
2540 if (ar8xxx_has_gige(priv
)) {
2541 phydev
->supported
= SUPPORTED_1000baseT_Full
;
2542 phydev
->advertising
= ADVERTISED_1000baseT_Full
;
2544 phydev
->supported
= SUPPORTED_100baseT_Full
;
2545 phydev
->advertising
= ADVERTISED_100baseT_Full
;
2548 if (priv
->chip
->config_at_probe
) {
2551 ret
= ar8xxx_start(priv
);
2553 goto err_unregister_switch
;
2556 if (ar8xxx_has_gige(priv
)) {
2557 phydev
->supported
|= SUPPORTED_1000baseT_Full
;
2558 phydev
->advertising
|= ADVERTISED_1000baseT_Full
;
2560 if (priv
->chip
->phy_rgmii_set
)
2561 priv
->chip
->phy_rgmii_set(priv
, phydev
);
2564 phydev
->priv
= priv
;
2566 mutex_unlock(&ar8xxx_dev_list_lock
);
2570 err_unregister_switch
:
2571 if (--priv
->use_count
)
2574 unregister_switch(&priv
->dev
);
2579 mutex_unlock(&ar8xxx_dev_list_lock
);
2584 ar8xxx_phy_detach(struct phy_device
*phydev
)
2586 struct net_device
*dev
= phydev
->attached_dev
;
2591 dev
->phy_ptr
= NULL
;
2592 dev
->priv_flags
&= ~IFF_NO_IP_ALIGN
;
2593 dev
->eth_mangle_rx
= NULL
;
2594 dev
->eth_mangle_tx
= NULL
;
2598 ar8xxx_phy_remove(struct phy_device
*phydev
)
2600 struct ar8xxx_priv
*priv
= phydev
->priv
;
2605 phydev
->priv
= NULL
;
2607 mutex_lock(&ar8xxx_dev_list_lock
);
2609 if (--priv
->use_count
> 0) {
2610 mutex_unlock(&ar8xxx_dev_list_lock
);
2614 list_del(&priv
->list
);
2615 mutex_unlock(&ar8xxx_dev_list_lock
);
2617 unregister_switch(&priv
->dev
);
2618 ar8xxx_mib_stop(priv
);
2623 ar8xxx_phy_soft_reset(struct phy_device
*phydev
)
2625 /* we don't need an extra reset */
2629 static struct phy_driver ar8xxx_phy_driver
[] = {
2631 .phy_id
= 0x004d0000,
2632 .name
= "Atheros AR8216/AR8236/AR8316",
2633 .phy_id_mask
= 0xffff0000,
2634 .features
= PHY_BASIC_FEATURES
,
2635 .probe
= ar8xxx_phy_probe
,
2636 .remove
= ar8xxx_phy_remove
,
2637 .detach
= ar8xxx_phy_detach
,
2638 .config_init
= ar8xxx_phy_config_init
,
2639 .config_aneg
= ar8xxx_phy_config_aneg
,
2640 .read_status
= ar8xxx_phy_read_status
,
2641 .soft_reset
= ar8xxx_phy_soft_reset
,
2645 static const struct of_device_id ar8xxx_mdiodev_of_match
[] = {
2647 .compatible
= "qca,ar7240sw",
2648 .data
= &ar7240sw_chip
,
2650 .compatible
= "qca,ar8229",
2651 .data
= &ar8229_chip
,
2653 .compatible
= "qca,ar8236",
2654 .data
= &ar8236_chip
,
2656 .compatible
= "qca,ar8327",
2657 .data
= &ar8327_chip
,
2663 ar8xxx_mdiodev_probe(struct mdio_device
*mdiodev
)
2665 const struct of_device_id
*match
;
2666 struct ar8xxx_priv
*priv
;
2667 struct switch_dev
*swdev
;
2668 struct device_node
*mdio_node
;
2671 match
= of_match_device(ar8xxx_mdiodev_of_match
, &mdiodev
->dev
);
2675 priv
= ar8xxx_create();
2679 priv
->mii_bus
= mdiodev
->bus
;
2680 priv
->pdev
= &mdiodev
->dev
;
2681 priv
->chip
= (const struct ar8xxx_chip
*) match
->data
;
2683 ret
= ar8xxx_read_id(priv
);
2687 ret
= ar8xxx_probe_switch(priv
);
2691 if (priv
->chip
->phy_read
&& priv
->chip
->phy_write
) {
2692 priv
->sw_mii_bus
= devm_mdiobus_alloc(&mdiodev
->dev
);
2693 priv
->sw_mii_bus
->name
= "ar8xxx-mdio";
2694 priv
->sw_mii_bus
->read
= ar8xxx_phy_read
;
2695 priv
->sw_mii_bus
->write
= ar8xxx_phy_write
;
2696 priv
->sw_mii_bus
->priv
= priv
;
2697 priv
->sw_mii_bus
->parent
= &mdiodev
->dev
;
2698 snprintf(priv
->sw_mii_bus
->id
, MII_BUS_ID_SIZE
, "%s",
2699 dev_name(&mdiodev
->dev
));
2700 mdio_node
= of_get_child_by_name(priv
->pdev
->of_node
, "mdio-bus");
2701 ret
= of_mdiobus_register(priv
->sw_mii_bus
, mdio_node
);
2707 swdev
->alias
= dev_name(&mdiodev
->dev
);
2709 if (of_property_read_bool(priv
->pdev
->of_node
, "qca,phy4-mii-enable")) {
2710 priv
->port4_phy
= true;
2714 ret
= register_switch(swdev
, NULL
);
2718 pr_info("%s: %s rev. %u switch registered on %s\n",
2719 swdev
->devname
, swdev
->name
, priv
->chip_rev
,
2720 dev_name(&priv
->mii_bus
->dev
));
2722 mutex_lock(&ar8xxx_dev_list_lock
);
2723 list_add(&priv
->list
, &ar8xxx_dev_list
);
2724 mutex_unlock(&ar8xxx_dev_list_lock
);
2728 ret
= ar8xxx_start(priv
);
2730 goto err_unregister_switch
;
2732 dev_set_drvdata(&mdiodev
->dev
, priv
);
2736 err_unregister_switch
:
2737 if (--priv
->use_count
)
2740 unregister_switch(&priv
->dev
);
2748 ar8xxx_mdiodev_remove(struct mdio_device
*mdiodev
)
2750 struct ar8xxx_priv
*priv
= dev_get_drvdata(&mdiodev
->dev
);
2755 mutex_lock(&ar8xxx_dev_list_lock
);
2757 if (--priv
->use_count
> 0) {
2758 mutex_unlock(&ar8xxx_dev_list_lock
);
2762 list_del(&priv
->list
);
2763 mutex_unlock(&ar8xxx_dev_list_lock
);
2765 unregister_switch(&priv
->dev
);
2766 ar8xxx_mib_stop(priv
);
2767 if(priv
->sw_mii_bus
)
2768 mdiobus_unregister(priv
->sw_mii_bus
);
2772 static struct mdio_driver ar8xxx_mdio_driver
= {
2773 .probe
= ar8xxx_mdiodev_probe
,
2774 .remove
= ar8xxx_mdiodev_remove
,
2776 .name
= "ar8xxx-switch",
2777 .of_match_table
= ar8xxx_mdiodev_of_match
,
2781 static int __init
ar8216_init(void)
2785 ret
= phy_drivers_register(ar8xxx_phy_driver
,
2786 ARRAY_SIZE(ar8xxx_phy_driver
),
2791 ret
= mdio_driver_register(&ar8xxx_mdio_driver
);
2793 phy_drivers_unregister(ar8xxx_phy_driver
,
2794 ARRAY_SIZE(ar8xxx_phy_driver
));
2798 module_init(ar8216_init
);
2800 static void __exit
ar8216_exit(void)
2802 mdio_driver_unregister(&ar8xxx_mdio_driver
);
2803 phy_drivers_unregister(ar8xxx_phy_driver
,
2804 ARRAY_SIZE(ar8xxx_phy_driver
));
2806 module_exit(ar8216_exit
);
2808 MODULE_LICENSE("GPL");