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generic: ar8216: add mdio-device probing support
[openwrt/staging/stintel.git] / target / linux / generic / files / drivers / net / phy / ar8216.c
1 /*
2 * ar8216.c: AR8216 switch driver
3 *
4 * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>
5 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18 #include <linux/if.h>
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/list.h>
22 #include <linux/if_ether.h>
23 #include <linux/skbuff.h>
24 #include <linux/netdevice.h>
25 #include <linux/netlink.h>
26 #include <linux/of_device.h>
27 #include <linux/of_mdio.h>
28 #include <linux/bitops.h>
29 #include <net/genetlink.h>
30 #include <linux/switch.h>
31 #include <linux/delay.h>
32 #include <linux/phy.h>
33 #include <linux/etherdevice.h>
34 #include <linux/lockdep.h>
35 #include <linux/ar8216_platform.h>
36 #include <linux/workqueue.h>
37 #include <linux/version.h>
38
39 #include "ar8216.h"
40
41 extern const struct ar8xxx_chip ar8327_chip;
42 extern const struct ar8xxx_chip ar8337_chip;
43
44 #define AR8XXX_MIB_WORK_DELAY 2000 /* msecs */
45
46 #define MIB_DESC(_s , _o, _n) \
47 { \
48 .size = (_s), \
49 .offset = (_o), \
50 .name = (_n), \
51 }
52
53 static const struct ar8xxx_mib_desc ar8216_mibs[] = {
54 MIB_DESC(1, AR8216_STATS_RXBROAD, "RxBroad"),
55 MIB_DESC(1, AR8216_STATS_RXPAUSE, "RxPause"),
56 MIB_DESC(1, AR8216_STATS_RXMULTI, "RxMulti"),
57 MIB_DESC(1, AR8216_STATS_RXFCSERR, "RxFcsErr"),
58 MIB_DESC(1, AR8216_STATS_RXALIGNERR, "RxAlignErr"),
59 MIB_DESC(1, AR8216_STATS_RXRUNT, "RxRunt"),
60 MIB_DESC(1, AR8216_STATS_RXFRAGMENT, "RxFragment"),
61 MIB_DESC(1, AR8216_STATS_RX64BYTE, "Rx64Byte"),
62 MIB_DESC(1, AR8216_STATS_RX128BYTE, "Rx128Byte"),
63 MIB_DESC(1, AR8216_STATS_RX256BYTE, "Rx256Byte"),
64 MIB_DESC(1, AR8216_STATS_RX512BYTE, "Rx512Byte"),
65 MIB_DESC(1, AR8216_STATS_RX1024BYTE, "Rx1024Byte"),
66 MIB_DESC(1, AR8216_STATS_RXMAXBYTE, "RxMaxByte"),
67 MIB_DESC(1, AR8216_STATS_RXTOOLONG, "RxTooLong"),
68 MIB_DESC(2, AR8216_STATS_RXGOODBYTE, "RxGoodByte"),
69 MIB_DESC(2, AR8216_STATS_RXBADBYTE, "RxBadByte"),
70 MIB_DESC(1, AR8216_STATS_RXOVERFLOW, "RxOverFlow"),
71 MIB_DESC(1, AR8216_STATS_FILTERED, "Filtered"),
72 MIB_DESC(1, AR8216_STATS_TXBROAD, "TxBroad"),
73 MIB_DESC(1, AR8216_STATS_TXPAUSE, "TxPause"),
74 MIB_DESC(1, AR8216_STATS_TXMULTI, "TxMulti"),
75 MIB_DESC(1, AR8216_STATS_TXUNDERRUN, "TxUnderRun"),
76 MIB_DESC(1, AR8216_STATS_TX64BYTE, "Tx64Byte"),
77 MIB_DESC(1, AR8216_STATS_TX128BYTE, "Tx128Byte"),
78 MIB_DESC(1, AR8216_STATS_TX256BYTE, "Tx256Byte"),
79 MIB_DESC(1, AR8216_STATS_TX512BYTE, "Tx512Byte"),
80 MIB_DESC(1, AR8216_STATS_TX1024BYTE, "Tx1024Byte"),
81 MIB_DESC(1, AR8216_STATS_TXMAXBYTE, "TxMaxByte"),
82 MIB_DESC(1, AR8216_STATS_TXOVERSIZE, "TxOverSize"),
83 MIB_DESC(2, AR8216_STATS_TXBYTE, "TxByte"),
84 MIB_DESC(1, AR8216_STATS_TXCOLLISION, "TxCollision"),
85 MIB_DESC(1, AR8216_STATS_TXABORTCOL, "TxAbortCol"),
86 MIB_DESC(1, AR8216_STATS_TXMULTICOL, "TxMultiCol"),
87 MIB_DESC(1, AR8216_STATS_TXSINGLECOL, "TxSingleCol"),
88 MIB_DESC(1, AR8216_STATS_TXEXCDEFER, "TxExcDefer"),
89 MIB_DESC(1, AR8216_STATS_TXDEFER, "TxDefer"),
90 MIB_DESC(1, AR8216_STATS_TXLATECOL, "TxLateCol"),
91 };
92
93 const struct ar8xxx_mib_desc ar8236_mibs[39] = {
94 MIB_DESC(1, AR8236_STATS_RXBROAD, "RxBroad"),
95 MIB_DESC(1, AR8236_STATS_RXPAUSE, "RxPause"),
96 MIB_DESC(1, AR8236_STATS_RXMULTI, "RxMulti"),
97 MIB_DESC(1, AR8236_STATS_RXFCSERR, "RxFcsErr"),
98 MIB_DESC(1, AR8236_STATS_RXALIGNERR, "RxAlignErr"),
99 MIB_DESC(1, AR8236_STATS_RXRUNT, "RxRunt"),
100 MIB_DESC(1, AR8236_STATS_RXFRAGMENT, "RxFragment"),
101 MIB_DESC(1, AR8236_STATS_RX64BYTE, "Rx64Byte"),
102 MIB_DESC(1, AR8236_STATS_RX128BYTE, "Rx128Byte"),
103 MIB_DESC(1, AR8236_STATS_RX256BYTE, "Rx256Byte"),
104 MIB_DESC(1, AR8236_STATS_RX512BYTE, "Rx512Byte"),
105 MIB_DESC(1, AR8236_STATS_RX1024BYTE, "Rx1024Byte"),
106 MIB_DESC(1, AR8236_STATS_RX1518BYTE, "Rx1518Byte"),
107 MIB_DESC(1, AR8236_STATS_RXMAXBYTE, "RxMaxByte"),
108 MIB_DESC(1, AR8236_STATS_RXTOOLONG, "RxTooLong"),
109 MIB_DESC(2, AR8236_STATS_RXGOODBYTE, "RxGoodByte"),
110 MIB_DESC(2, AR8236_STATS_RXBADBYTE, "RxBadByte"),
111 MIB_DESC(1, AR8236_STATS_RXOVERFLOW, "RxOverFlow"),
112 MIB_DESC(1, AR8236_STATS_FILTERED, "Filtered"),
113 MIB_DESC(1, AR8236_STATS_TXBROAD, "TxBroad"),
114 MIB_DESC(1, AR8236_STATS_TXPAUSE, "TxPause"),
115 MIB_DESC(1, AR8236_STATS_TXMULTI, "TxMulti"),
116 MIB_DESC(1, AR8236_STATS_TXUNDERRUN, "TxUnderRun"),
117 MIB_DESC(1, AR8236_STATS_TX64BYTE, "Tx64Byte"),
118 MIB_DESC(1, AR8236_STATS_TX128BYTE, "Tx128Byte"),
119 MIB_DESC(1, AR8236_STATS_TX256BYTE, "Tx256Byte"),
120 MIB_DESC(1, AR8236_STATS_TX512BYTE, "Tx512Byte"),
121 MIB_DESC(1, AR8236_STATS_TX1024BYTE, "Tx1024Byte"),
122 MIB_DESC(1, AR8236_STATS_TX1518BYTE, "Tx1518Byte"),
123 MIB_DESC(1, AR8236_STATS_TXMAXBYTE, "TxMaxByte"),
124 MIB_DESC(1, AR8236_STATS_TXOVERSIZE, "TxOverSize"),
125 MIB_DESC(2, AR8236_STATS_TXBYTE, "TxByte"),
126 MIB_DESC(1, AR8236_STATS_TXCOLLISION, "TxCollision"),
127 MIB_DESC(1, AR8236_STATS_TXABORTCOL, "TxAbortCol"),
128 MIB_DESC(1, AR8236_STATS_TXMULTICOL, "TxMultiCol"),
129 MIB_DESC(1, AR8236_STATS_TXSINGLECOL, "TxSingleCol"),
130 MIB_DESC(1, AR8236_STATS_TXEXCDEFER, "TxExcDefer"),
131 MIB_DESC(1, AR8236_STATS_TXDEFER, "TxDefer"),
132 MIB_DESC(1, AR8236_STATS_TXLATECOL, "TxLateCol"),
133 };
134
135 static DEFINE_MUTEX(ar8xxx_dev_list_lock);
136 static LIST_HEAD(ar8xxx_dev_list);
137
138 /* inspired by phy_poll_reset in drivers/net/phy/phy_device.c */
139 static int
140 ar8xxx_phy_poll_reset(struct mii_bus *bus)
141 {
142 unsigned int sleep_msecs = 20;
143 int ret, elapsed, i;
144
145 for (elapsed = sleep_msecs; elapsed <= 600;
146 elapsed += sleep_msecs) {
147 msleep(sleep_msecs);
148 for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
149 ret = mdiobus_read(bus, i, MII_BMCR);
150 if (ret < 0)
151 return ret;
152 if (ret & BMCR_RESET)
153 break;
154 if (i == AR8XXX_NUM_PHYS - 1) {
155 usleep_range(1000, 2000);
156 return 0;
157 }
158 }
159 }
160 return -ETIMEDOUT;
161 }
162
163 static int
164 ar8xxx_phy_check_aneg(struct phy_device *phydev)
165 {
166 int ret;
167
168 if (phydev->autoneg != AUTONEG_ENABLE)
169 return 0;
170 /*
171 * BMCR_ANENABLE might have been cleared
172 * by phy_init_hw in certain kernel versions
173 * therefore check for it
174 */
175 ret = phy_read(phydev, MII_BMCR);
176 if (ret < 0)
177 return ret;
178 if (ret & BMCR_ANENABLE)
179 return 0;
180
181 dev_info(&phydev->mdio.dev, "ANEG disabled, re-enabling ...\n");
182 ret |= BMCR_ANENABLE | BMCR_ANRESTART;
183 return phy_write(phydev, MII_BMCR, ret);
184 }
185
186 void
187 ar8xxx_phy_init(struct ar8xxx_priv *priv)
188 {
189 int i;
190 struct mii_bus *bus;
191
192 bus = priv->mii_bus;
193 for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
194 if (priv->chip->phy_fixup)
195 priv->chip->phy_fixup(priv, i);
196
197 /* initialize the port itself */
198 mdiobus_write(bus, i, MII_ADVERTISE,
199 ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
200 if (ar8xxx_has_gige(priv))
201 mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
202 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
203 }
204
205 ar8xxx_phy_poll_reset(bus);
206 }
207
208 u32
209 ar8xxx_mii_read32(struct ar8xxx_priv *priv, int phy_id, int regnum)
210 {
211 struct mii_bus *bus = priv->mii_bus;
212 u16 lo, hi;
213
214 lo = bus->read(bus, phy_id, regnum);
215 hi = bus->read(bus, phy_id, regnum + 1);
216
217 return (hi << 16) | lo;
218 }
219
220 void
221 ar8xxx_mii_write32(struct ar8xxx_priv *priv, int phy_id, int regnum, u32 val)
222 {
223 struct mii_bus *bus = priv->mii_bus;
224 u16 lo, hi;
225
226 lo = val & 0xffff;
227 hi = (u16) (val >> 16);
228
229 if (priv->chip->mii_lo_first)
230 {
231 bus->write(bus, phy_id, regnum, lo);
232 bus->write(bus, phy_id, regnum + 1, hi);
233 } else {
234 bus->write(bus, phy_id, regnum + 1, hi);
235 bus->write(bus, phy_id, regnum, lo);
236 }
237 }
238
239 u32
240 ar8xxx_read(struct ar8xxx_priv *priv, int reg)
241 {
242 struct mii_bus *bus = priv->mii_bus;
243 u16 r1, r2, page;
244 u32 val;
245
246 split_addr((u32) reg, &r1, &r2, &page);
247
248 mutex_lock(&bus->mdio_lock);
249
250 bus->write(bus, 0x18, 0, page);
251 wait_for_page_switch();
252 val = ar8xxx_mii_read32(priv, 0x10 | r2, r1);
253
254 mutex_unlock(&bus->mdio_lock);
255
256 return val;
257 }
258
259 void
260 ar8xxx_write(struct ar8xxx_priv *priv, int reg, u32 val)
261 {
262 struct mii_bus *bus = priv->mii_bus;
263 u16 r1, r2, page;
264
265 split_addr((u32) reg, &r1, &r2, &page);
266
267 mutex_lock(&bus->mdio_lock);
268
269 bus->write(bus, 0x18, 0, page);
270 wait_for_page_switch();
271 ar8xxx_mii_write32(priv, 0x10 | r2, r1, val);
272
273 mutex_unlock(&bus->mdio_lock);
274 }
275
276 u32
277 ar8xxx_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
278 {
279 struct mii_bus *bus = priv->mii_bus;
280 u16 r1, r2, page;
281 u32 ret;
282
283 split_addr((u32) reg, &r1, &r2, &page);
284
285 mutex_lock(&bus->mdio_lock);
286
287 bus->write(bus, 0x18, 0, page);
288 wait_for_page_switch();
289
290 ret = ar8xxx_mii_read32(priv, 0x10 | r2, r1);
291 ret &= ~mask;
292 ret |= val;
293 ar8xxx_mii_write32(priv, 0x10 | r2, r1, ret);
294
295 mutex_unlock(&bus->mdio_lock);
296
297 return ret;
298 }
299 void
300 ar8xxx_phy_dbg_read(struct ar8xxx_priv *priv, int phy_addr,
301 u16 dbg_addr, u16 *dbg_data)
302 {
303 struct mii_bus *bus = priv->mii_bus;
304
305 mutex_lock(&bus->mdio_lock);
306 bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr);
307 *dbg_data = bus->read(bus, phy_addr, MII_ATH_DBG_DATA);
308 mutex_unlock(&bus->mdio_lock);
309 }
310
311 void
312 ar8xxx_phy_dbg_write(struct ar8xxx_priv *priv, int phy_addr,
313 u16 dbg_addr, u16 dbg_data)
314 {
315 struct mii_bus *bus = priv->mii_bus;
316
317 mutex_lock(&bus->mdio_lock);
318 bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr);
319 bus->write(bus, phy_addr, MII_ATH_DBG_DATA, dbg_data);
320 mutex_unlock(&bus->mdio_lock);
321 }
322
323 static inline void
324 ar8xxx_phy_mmd_prep(struct mii_bus *bus, int phy_addr, u16 addr, u16 reg)
325 {
326 bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr);
327 bus->write(bus, phy_addr, MII_ATH_MMD_DATA, reg);
328 bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr | 0x4000);
329 }
330
331 void
332 ar8xxx_phy_mmd_write(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 reg, u16 data)
333 {
334 struct mii_bus *bus = priv->mii_bus;
335
336 mutex_lock(&bus->mdio_lock);
337 ar8xxx_phy_mmd_prep(bus, phy_addr, addr, reg);
338 bus->write(bus, phy_addr, MII_ATH_MMD_DATA, data);
339 mutex_unlock(&bus->mdio_lock);
340 }
341
342 u16
343 ar8xxx_phy_mmd_read(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 reg)
344 {
345 struct mii_bus *bus = priv->mii_bus;
346 u16 data;
347
348 mutex_lock(&bus->mdio_lock);
349 ar8xxx_phy_mmd_prep(bus, phy_addr, addr, reg);
350 data = bus->read(bus, phy_addr, MII_ATH_MMD_DATA);
351 mutex_unlock(&bus->mdio_lock);
352
353 return data;
354 }
355
356 static int
357 ar8xxx_reg_wait(struct ar8xxx_priv *priv, u32 reg, u32 mask, u32 val,
358 unsigned timeout)
359 {
360 int i;
361
362 for (i = 0; i < timeout; i++) {
363 u32 t;
364
365 t = ar8xxx_read(priv, reg);
366 if ((t & mask) == val)
367 return 0;
368
369 usleep_range(1000, 2000);
370 cond_resched();
371 }
372
373 return -ETIMEDOUT;
374 }
375
376 static int
377 ar8xxx_mib_op(struct ar8xxx_priv *priv, u32 op)
378 {
379 unsigned mib_func = priv->chip->mib_func;
380 int ret;
381
382 lockdep_assert_held(&priv->mib_lock);
383
384 /* Capture the hardware statistics for all ports */
385 ar8xxx_rmw(priv, mib_func, AR8216_MIB_FUNC, (op << AR8216_MIB_FUNC_S));
386
387 /* Wait for the capturing to complete. */
388 ret = ar8xxx_reg_wait(priv, mib_func, AR8216_MIB_BUSY, 0, 10);
389 if (ret)
390 goto out;
391
392 ret = 0;
393
394 out:
395 return ret;
396 }
397
398 static int
399 ar8xxx_mib_capture(struct ar8xxx_priv *priv)
400 {
401 return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_CAPTURE);
402 }
403
404 static int
405 ar8xxx_mib_flush(struct ar8xxx_priv *priv)
406 {
407 return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_FLUSH);
408 }
409
410 static void
411 ar8xxx_mib_fetch_port_stat(struct ar8xxx_priv *priv, int port, bool flush)
412 {
413 unsigned int base;
414 u64 *mib_stats;
415 int i;
416
417 WARN_ON(port >= priv->dev.ports);
418
419 lockdep_assert_held(&priv->mib_lock);
420
421 base = priv->chip->reg_port_stats_start +
422 priv->chip->reg_port_stats_length * port;
423
424 mib_stats = &priv->mib_stats[port * priv->chip->num_mibs];
425 for (i = 0; i < priv->chip->num_mibs; i++) {
426 const struct ar8xxx_mib_desc *mib;
427 u64 t;
428
429 mib = &priv->chip->mib_decs[i];
430 t = ar8xxx_read(priv, base + mib->offset);
431 if (mib->size == 2) {
432 u64 hi;
433
434 hi = ar8xxx_read(priv, base + mib->offset + 4);
435 t |= hi << 32;
436 }
437
438 if (flush)
439 mib_stats[i] = 0;
440 else
441 mib_stats[i] += t;
442 cond_resched();
443 }
444 }
445
446 static void
447 ar8216_read_port_link(struct ar8xxx_priv *priv, int port,
448 struct switch_port_link *link)
449 {
450 u32 status;
451 u32 speed;
452
453 memset(link, '\0', sizeof(*link));
454
455 status = priv->chip->read_port_status(priv, port);
456
457 link->aneg = !!(status & AR8216_PORT_STATUS_LINK_AUTO);
458 if (link->aneg) {
459 link->link = !!(status & AR8216_PORT_STATUS_LINK_UP);
460 } else {
461 link->link = true;
462
463 if (priv->get_port_link) {
464 int err;
465
466 err = priv->get_port_link(port);
467 if (err >= 0)
468 link->link = !!err;
469 }
470 }
471
472 if (!link->link)
473 return;
474
475 link->duplex = !!(status & AR8216_PORT_STATUS_DUPLEX);
476 link->tx_flow = !!(status & AR8216_PORT_STATUS_TXFLOW);
477 link->rx_flow = !!(status & AR8216_PORT_STATUS_RXFLOW);
478
479 if (link->aneg && link->duplex && priv->chip->read_port_eee_status)
480 link->eee = priv->chip->read_port_eee_status(priv, port);
481
482 speed = (status & AR8216_PORT_STATUS_SPEED) >>
483 AR8216_PORT_STATUS_SPEED_S;
484
485 switch (speed) {
486 case AR8216_PORT_SPEED_10M:
487 link->speed = SWITCH_PORT_SPEED_10;
488 break;
489 case AR8216_PORT_SPEED_100M:
490 link->speed = SWITCH_PORT_SPEED_100;
491 break;
492 case AR8216_PORT_SPEED_1000M:
493 link->speed = SWITCH_PORT_SPEED_1000;
494 break;
495 default:
496 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
497 break;
498 }
499 }
500
501 static struct sk_buff *
502 ar8216_mangle_tx(struct net_device *dev, struct sk_buff *skb)
503 {
504 struct ar8xxx_priv *priv = dev->phy_ptr;
505 unsigned char *buf;
506
507 if (unlikely(!priv))
508 goto error;
509
510 if (!priv->vlan)
511 goto send;
512
513 if (unlikely(skb_headroom(skb) < 2)) {
514 if (pskb_expand_head(skb, 2, 0, GFP_ATOMIC) < 0)
515 goto error;
516 }
517
518 buf = skb_push(skb, 2);
519 buf[0] = 0x10;
520 buf[1] = 0x80;
521
522 send:
523 return skb;
524
525 error:
526 dev_kfree_skb_any(skb);
527 return NULL;
528 }
529
530 static void
531 ar8216_mangle_rx(struct net_device *dev, struct sk_buff *skb)
532 {
533 struct ar8xxx_priv *priv;
534 unsigned char *buf;
535 int port, vlan;
536
537 priv = dev->phy_ptr;
538 if (!priv)
539 return;
540
541 /* don't strip the header if vlan mode is disabled */
542 if (!priv->vlan)
543 return;
544
545 /* strip header, get vlan id */
546 buf = skb->data;
547 skb_pull(skb, 2);
548
549 /* check for vlan header presence */
550 if ((buf[12 + 2] != 0x81) || (buf[13 + 2] != 0x00))
551 return;
552
553 port = buf[0] & 0x7;
554
555 /* no need to fix up packets coming from a tagged source */
556 if (priv->vlan_tagged & (1 << port))
557 return;
558
559 /* lookup port vid from local table, the switch passes an invalid vlan id */
560 vlan = priv->vlan_id[priv->pvid[port]];
561
562 buf[14 + 2] &= 0xf0;
563 buf[14 + 2] |= vlan >> 8;
564 buf[15 + 2] = vlan & 0xff;
565 }
566
567 int
568 ar8216_wait_bit(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
569 {
570 int timeout = 20;
571 u32 t = 0;
572
573 while (1) {
574 t = ar8xxx_read(priv, reg);
575 if ((t & mask) == val)
576 return 0;
577
578 if (timeout-- <= 0)
579 break;
580
581 udelay(10);
582 cond_resched();
583 }
584
585 pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
586 (unsigned int) reg, t, mask, val);
587 return -ETIMEDOUT;
588 }
589
590 static void
591 ar8216_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
592 {
593 if (ar8216_wait_bit(priv, AR8216_REG_VTU, AR8216_VTU_ACTIVE, 0))
594 return;
595 if ((op & AR8216_VTU_OP) == AR8216_VTU_OP_LOAD) {
596 val &= AR8216_VTUDATA_MEMBER;
597 val |= AR8216_VTUDATA_VALID;
598 ar8xxx_write(priv, AR8216_REG_VTU_DATA, val);
599 }
600 op |= AR8216_VTU_ACTIVE;
601 ar8xxx_write(priv, AR8216_REG_VTU, op);
602 }
603
604 static void
605 ar8216_vtu_flush(struct ar8xxx_priv *priv)
606 {
607 ar8216_vtu_op(priv, AR8216_VTU_OP_FLUSH, 0);
608 }
609
610 static void
611 ar8216_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)
612 {
613 u32 op;
614
615 op = AR8216_VTU_OP_LOAD | (vid << AR8216_VTU_VID_S);
616 ar8216_vtu_op(priv, op, port_mask);
617 }
618
619 static int
620 ar8216_atu_flush(struct ar8xxx_priv *priv)
621 {
622 int ret;
623
624 ret = ar8216_wait_bit(priv, AR8216_REG_ATU_FUNC0, AR8216_ATU_ACTIVE, 0);
625 if (!ret)
626 ar8xxx_write(priv, AR8216_REG_ATU_FUNC0, AR8216_ATU_OP_FLUSH |
627 AR8216_ATU_ACTIVE);
628
629 return ret;
630 }
631
632 static int
633 ar8216_atu_flush_port(struct ar8xxx_priv *priv, int port)
634 {
635 u32 t;
636 int ret;
637
638 ret = ar8216_wait_bit(priv, AR8216_REG_ATU_FUNC0, AR8216_ATU_ACTIVE, 0);
639 if (!ret) {
640 t = (port << AR8216_ATU_PORT_NUM_S) | AR8216_ATU_OP_FLUSH_PORT;
641 t |= AR8216_ATU_ACTIVE;
642 ar8xxx_write(priv, AR8216_REG_ATU_FUNC0, t);
643 }
644
645 return ret;
646 }
647
648 static u32
649 ar8216_read_port_status(struct ar8xxx_priv *priv, int port)
650 {
651 return ar8xxx_read(priv, AR8216_REG_PORT_STATUS(port));
652 }
653
654 static void
655 ar8216_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
656 {
657 u32 header;
658 u32 egress, ingress;
659 u32 pvid;
660
661 if (priv->vlan) {
662 pvid = priv->vlan_id[priv->pvid[port]];
663 if (priv->vlan_tagged & (1 << port))
664 egress = AR8216_OUT_ADD_VLAN;
665 else
666 egress = AR8216_OUT_STRIP_VLAN;
667 ingress = AR8216_IN_SECURE;
668 } else {
669 pvid = port;
670 egress = AR8216_OUT_KEEP;
671 ingress = AR8216_IN_PORT_ONLY;
672 }
673
674 if (chip_is_ar8216(priv) && priv->vlan && port == AR8216_PORT_CPU)
675 header = AR8216_PORT_CTRL_HEADER;
676 else
677 header = 0;
678
679 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
680 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
681 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
682 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
683 AR8216_PORT_CTRL_LEARN | header |
684 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
685 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
686
687 ar8xxx_rmw(priv, AR8216_REG_PORT_VLAN(port),
688 AR8216_PORT_VLAN_DEST_PORTS | AR8216_PORT_VLAN_MODE |
689 AR8216_PORT_VLAN_DEFAULT_ID,
690 (members << AR8216_PORT_VLAN_DEST_PORTS_S) |
691 (ingress << AR8216_PORT_VLAN_MODE_S) |
692 (pvid << AR8216_PORT_VLAN_DEFAULT_ID_S));
693 }
694
695 static int
696 ar8216_hw_init(struct ar8xxx_priv *priv)
697 {
698 if (priv->initialized)
699 return 0;
700
701 ar8xxx_phy_init(priv);
702
703 priv->initialized = true;
704 return 0;
705 }
706
707 static void
708 ar8216_init_globals(struct ar8xxx_priv *priv)
709 {
710 /* standard atheros magic */
711 ar8xxx_write(priv, 0x38, 0xc000050e);
712
713 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
714 AR8216_GCTRL_MTU, 1518 + 8 + 2);
715 }
716
717 static void
718 ar8216_init_port(struct ar8xxx_priv *priv, int port)
719 {
720 /* Enable port learning and tx */
721 ar8xxx_write(priv, AR8216_REG_PORT_CTRL(port),
722 AR8216_PORT_CTRL_LEARN |
723 (4 << AR8216_PORT_CTRL_STATE_S));
724
725 ar8xxx_write(priv, AR8216_REG_PORT_VLAN(port), 0);
726
727 if (port == AR8216_PORT_CPU) {
728 ar8xxx_write(priv, AR8216_REG_PORT_STATUS(port),
729 AR8216_PORT_STATUS_LINK_UP |
730 (ar8xxx_has_gige(priv) ?
731 AR8216_PORT_SPEED_1000M : AR8216_PORT_SPEED_100M) |
732 AR8216_PORT_STATUS_TXMAC |
733 AR8216_PORT_STATUS_RXMAC |
734 (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_RXFLOW : 0) |
735 (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_TXFLOW : 0) |
736 AR8216_PORT_STATUS_DUPLEX);
737 } else {
738 ar8xxx_write(priv, AR8216_REG_PORT_STATUS(port),
739 AR8216_PORT_STATUS_LINK_AUTO);
740 }
741 }
742
743 static void
744 ar8216_wait_atu_ready(struct ar8xxx_priv *priv, u16 r2, u16 r1)
745 {
746 int timeout = 20;
747
748 while (ar8xxx_mii_read32(priv, r2, r1) & AR8216_ATU_ACTIVE && --timeout) {
749 udelay(10);
750 cond_resched();
751 }
752
753 if (!timeout)
754 pr_err("ar8216: timeout waiting for atu to become ready\n");
755 }
756
757 static void ar8216_get_arl_entry(struct ar8xxx_priv *priv,
758 struct arl_entry *a, u32 *status, enum arl_op op)
759 {
760 struct mii_bus *bus = priv->mii_bus;
761 u16 r2, page;
762 u16 r1_func0, r1_func1, r1_func2;
763 u32 t, val0, val1, val2;
764
765 split_addr(AR8216_REG_ATU_FUNC0, &r1_func0, &r2, &page);
766 r2 |= 0x10;
767
768 r1_func1 = (AR8216_REG_ATU_FUNC1 >> 1) & 0x1e;
769 r1_func2 = (AR8216_REG_ATU_FUNC2 >> 1) & 0x1e;
770
771 switch (op) {
772 case AR8XXX_ARL_INITIALIZE:
773 /* all ATU registers are on the same page
774 * therefore set page only once
775 */
776 bus->write(bus, 0x18, 0, page);
777 wait_for_page_switch();
778
779 ar8216_wait_atu_ready(priv, r2, r1_func0);
780
781 ar8xxx_mii_write32(priv, r2, r1_func0, AR8216_ATU_OP_GET_NEXT);
782 ar8xxx_mii_write32(priv, r2, r1_func1, 0);
783 ar8xxx_mii_write32(priv, r2, r1_func2, 0);
784 break;
785 case AR8XXX_ARL_GET_NEXT:
786 t = ar8xxx_mii_read32(priv, r2, r1_func0);
787 t |= AR8216_ATU_ACTIVE;
788 ar8xxx_mii_write32(priv, r2, r1_func0, t);
789 ar8216_wait_atu_ready(priv, r2, r1_func0);
790
791 val0 = ar8xxx_mii_read32(priv, r2, r1_func0);
792 val1 = ar8xxx_mii_read32(priv, r2, r1_func1);
793 val2 = ar8xxx_mii_read32(priv, r2, r1_func2);
794
795 *status = (val2 & AR8216_ATU_STATUS) >> AR8216_ATU_STATUS_S;
796 if (!*status)
797 break;
798
799 a->portmap = (val2 & AR8216_ATU_PORTS) >> AR8216_ATU_PORTS_S;
800 a->mac[0] = (val0 & AR8216_ATU_ADDR5) >> AR8216_ATU_ADDR5_S;
801 a->mac[1] = (val0 & AR8216_ATU_ADDR4) >> AR8216_ATU_ADDR4_S;
802 a->mac[2] = (val1 & AR8216_ATU_ADDR3) >> AR8216_ATU_ADDR3_S;
803 a->mac[3] = (val1 & AR8216_ATU_ADDR2) >> AR8216_ATU_ADDR2_S;
804 a->mac[4] = (val1 & AR8216_ATU_ADDR1) >> AR8216_ATU_ADDR1_S;
805 a->mac[5] = (val1 & AR8216_ATU_ADDR0) >> AR8216_ATU_ADDR0_S;
806 break;
807 }
808 }
809
810 static void
811 ar8236_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
812 {
813 u32 egress, ingress;
814 u32 pvid;
815
816 if (priv->vlan) {
817 pvid = priv->vlan_id[priv->pvid[port]];
818 if (priv->vlan_tagged & (1 << port))
819 egress = AR8216_OUT_ADD_VLAN;
820 else
821 egress = AR8216_OUT_STRIP_VLAN;
822 ingress = AR8216_IN_SECURE;
823 } else {
824 pvid = port;
825 egress = AR8216_OUT_KEEP;
826 ingress = AR8216_IN_PORT_ONLY;
827 }
828
829 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
830 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
831 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
832 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
833 AR8216_PORT_CTRL_LEARN |
834 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
835 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
836
837 ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN(port),
838 AR8236_PORT_VLAN_DEFAULT_ID,
839 (pvid << AR8236_PORT_VLAN_DEFAULT_ID_S));
840
841 ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN2(port),
842 AR8236_PORT_VLAN2_VLAN_MODE |
843 AR8236_PORT_VLAN2_MEMBER,
844 (ingress << AR8236_PORT_VLAN2_VLAN_MODE_S) |
845 (members << AR8236_PORT_VLAN2_MEMBER_S));
846 }
847
848 static void
849 ar8236_init_globals(struct ar8xxx_priv *priv)
850 {
851 /* enable jumbo frames */
852 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
853 AR8316_GCTRL_MTU, 9018 + 8 + 2);
854
855 /* enable cpu port to receive arp frames */
856 ar8xxx_reg_set(priv, AR8216_REG_ATU_CTRL,
857 AR8236_ATU_CTRL_RES);
858
859 /* enable cpu port to receive multicast and broadcast frames */
860 ar8xxx_reg_set(priv, AR8216_REG_FLOOD_MASK,
861 AR8236_FM_CPU_BROADCAST_EN | AR8236_FM_CPU_BCAST_FWD_EN);
862
863 /* Enable MIB counters */
864 ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
865 (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
866 AR8236_MIB_EN);
867 }
868
869 static int
870 ar8316_hw_init(struct ar8xxx_priv *priv)
871 {
872 u32 val, newval;
873
874 val = ar8xxx_read(priv, AR8316_REG_POSTRIP);
875
876 if (priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
877 if (priv->port4_phy) {
878 /* value taken from Ubiquiti RouterStation Pro */
879 newval = 0x81461bea;
880 pr_info("ar8316: Using port 4 as PHY\n");
881 } else {
882 newval = 0x01261be2;
883 pr_info("ar8316: Using port 4 as switch port\n");
884 }
885 } else if (priv->phy->interface == PHY_INTERFACE_MODE_GMII) {
886 /* value taken from AVM Fritz!Box 7390 sources */
887 newval = 0x010e5b71;
888 } else {
889 /* no known value for phy interface */
890 pr_err("ar8316: unsupported mii mode: %d.\n",
891 priv->phy->interface);
892 return -EINVAL;
893 }
894
895 if (val == newval)
896 goto out;
897
898 ar8xxx_write(priv, AR8316_REG_POSTRIP, newval);
899
900 if (priv->port4_phy &&
901 priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
902 /* work around for phy4 rgmii mode */
903 ar8xxx_phy_dbg_write(priv, 4, 0x12, 0x480c);
904 /* rx delay */
905 ar8xxx_phy_dbg_write(priv, 4, 0x0, 0x824e);
906 /* tx delay */
907 ar8xxx_phy_dbg_write(priv, 4, 0x5, 0x3d47);
908 msleep(1000);
909 }
910
911 ar8xxx_phy_init(priv);
912
913 out:
914 priv->initialized = true;
915 return 0;
916 }
917
918 static void
919 ar8316_init_globals(struct ar8xxx_priv *priv)
920 {
921 /* standard atheros magic */
922 ar8xxx_write(priv, 0x38, 0xc000050e);
923
924 /* enable cpu port to receive multicast and broadcast frames */
925 ar8xxx_write(priv, AR8216_REG_FLOOD_MASK, 0x003f003f);
926
927 /* enable jumbo frames */
928 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
929 AR8316_GCTRL_MTU, 9018 + 8 + 2);
930
931 /* Enable MIB counters */
932 ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
933 (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
934 AR8236_MIB_EN);
935 }
936
937 int
938 ar8xxx_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
939 struct switch_val *val)
940 {
941 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
942 priv->vlan = !!val->value.i;
943 return 0;
944 }
945
946 int
947 ar8xxx_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
948 struct switch_val *val)
949 {
950 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
951 val->value.i = priv->vlan;
952 return 0;
953 }
954
955
956 int
957 ar8xxx_sw_set_pvid(struct switch_dev *dev, int port, int vlan)
958 {
959 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
960
961 /* make sure no invalid PVIDs get set */
962
963 if (vlan < 0 || vlan >= dev->vlans ||
964 port < 0 || port >= AR8X16_MAX_PORTS)
965 return -EINVAL;
966
967 priv->pvid[port] = vlan;
968 return 0;
969 }
970
971 int
972 ar8xxx_sw_get_pvid(struct switch_dev *dev, int port, int *vlan)
973 {
974 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
975
976 if (port < 0 || port >= AR8X16_MAX_PORTS)
977 return -EINVAL;
978
979 *vlan = priv->pvid[port];
980 return 0;
981 }
982
983 static int
984 ar8xxx_sw_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
985 struct switch_val *val)
986 {
987 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
988
989 if (val->port_vlan >= AR8X16_MAX_VLANS)
990 return -EINVAL;
991
992 priv->vlan_id[val->port_vlan] = val->value.i;
993 return 0;
994 }
995
996 static int
997 ar8xxx_sw_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
998 struct switch_val *val)
999 {
1000 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1001 val->value.i = priv->vlan_id[val->port_vlan];
1002 return 0;
1003 }
1004
1005 int
1006 ar8xxx_sw_get_port_link(struct switch_dev *dev, int port,
1007 struct switch_port_link *link)
1008 {
1009 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1010
1011 ar8216_read_port_link(priv, port, link);
1012 return 0;
1013 }
1014
1015 static int
1016 ar8xxx_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
1017 {
1018 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1019 u8 ports;
1020 int i;
1021
1022 if (val->port_vlan >= AR8X16_MAX_VLANS)
1023 return -EINVAL;
1024
1025 ports = priv->vlan_table[val->port_vlan];
1026 val->len = 0;
1027 for (i = 0; i < dev->ports; i++) {
1028 struct switch_port *p;
1029
1030 if (!(ports & (1 << i)))
1031 continue;
1032
1033 p = &val->value.ports[val->len++];
1034 p->id = i;
1035 if (priv->vlan_tagged & (1 << i))
1036 p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
1037 else
1038 p->flags = 0;
1039 }
1040 return 0;
1041 }
1042
1043 static int
1044 ar8xxx_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
1045 {
1046 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1047 u8 *vt = &priv->vlan_table[val->port_vlan];
1048 int i, j;
1049
1050 *vt = 0;
1051 for (i = 0; i < val->len; i++) {
1052 struct switch_port *p = &val->value.ports[i];
1053
1054 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
1055 priv->vlan_tagged |= (1 << p->id);
1056 } else {
1057 priv->vlan_tagged &= ~(1 << p->id);
1058 priv->pvid[p->id] = val->port_vlan;
1059
1060 /* make sure that an untagged port does not
1061 * appear in other vlans */
1062 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1063 if (j == val->port_vlan)
1064 continue;
1065 priv->vlan_table[j] &= ~(1 << p->id);
1066 }
1067 }
1068
1069 *vt |= 1 << p->id;
1070 }
1071 return 0;
1072 }
1073
1074 static void
1075 ar8216_set_mirror_regs(struct ar8xxx_priv *priv)
1076 {
1077 int port;
1078
1079 /* reset all mirror registers */
1080 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
1081 AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
1082 (0xF << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
1083 for (port = 0; port < AR8216_NUM_PORTS; port++) {
1084 ar8xxx_reg_clear(priv, AR8216_REG_PORT_CTRL(port),
1085 AR8216_PORT_CTRL_MIRROR_RX);
1086
1087 ar8xxx_reg_clear(priv, AR8216_REG_PORT_CTRL(port),
1088 AR8216_PORT_CTRL_MIRROR_TX);
1089 }
1090
1091 /* now enable mirroring if necessary */
1092 if (priv->source_port >= AR8216_NUM_PORTS ||
1093 priv->monitor_port >= AR8216_NUM_PORTS ||
1094 priv->source_port == priv->monitor_port) {
1095 return;
1096 }
1097
1098 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
1099 AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
1100 (priv->monitor_port << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
1101
1102 if (priv->mirror_rx)
1103 ar8xxx_reg_set(priv, AR8216_REG_PORT_CTRL(priv->source_port),
1104 AR8216_PORT_CTRL_MIRROR_RX);
1105
1106 if (priv->mirror_tx)
1107 ar8xxx_reg_set(priv, AR8216_REG_PORT_CTRL(priv->source_port),
1108 AR8216_PORT_CTRL_MIRROR_TX);
1109 }
1110
1111 static inline u32
1112 ar8xxx_age_time_val(int age_time)
1113 {
1114 return (age_time + AR8XXX_REG_ARL_CTRL_AGE_TIME_SECS / 2) /
1115 AR8XXX_REG_ARL_CTRL_AGE_TIME_SECS;
1116 }
1117
1118 static inline void
1119 ar8xxx_set_age_time(struct ar8xxx_priv *priv, int reg)
1120 {
1121 u32 age_time = ar8xxx_age_time_val(priv->arl_age_time);
1122 ar8xxx_rmw(priv, reg, AR8216_ATU_CTRL_AGE_TIME, age_time << AR8216_ATU_CTRL_AGE_TIME_S);
1123 }
1124
1125 int
1126 ar8xxx_sw_hw_apply(struct switch_dev *dev)
1127 {
1128 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1129 const struct ar8xxx_chip *chip = priv->chip;
1130 u8 portmask[AR8X16_MAX_PORTS];
1131 int i, j;
1132
1133 mutex_lock(&priv->reg_mutex);
1134 /* flush all vlan translation unit entries */
1135 priv->chip->vtu_flush(priv);
1136
1137 memset(portmask, 0, sizeof(portmask));
1138 if (!priv->init) {
1139 /* calculate the port destination masks and load vlans
1140 * into the vlan translation unit */
1141 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1142 u8 vp = priv->vlan_table[j];
1143
1144 if (!vp)
1145 continue;
1146
1147 for (i = 0; i < dev->ports; i++) {
1148 u8 mask = (1 << i);
1149 if (vp & mask)
1150 portmask[i] |= vp & ~mask;
1151 }
1152
1153 chip->vtu_load_vlan(priv, priv->vlan_id[j],
1154 priv->vlan_table[j]);
1155 }
1156 } else {
1157 /* vlan disabled:
1158 * isolate all ports, but connect them to the cpu port */
1159 for (i = 0; i < dev->ports; i++) {
1160 if (i == AR8216_PORT_CPU)
1161 continue;
1162
1163 portmask[i] = 1 << AR8216_PORT_CPU;
1164 portmask[AR8216_PORT_CPU] |= (1 << i);
1165 }
1166 }
1167
1168 /* update the port destination mask registers and tag settings */
1169 for (i = 0; i < dev->ports; i++) {
1170 chip->setup_port(priv, i, portmask[i]);
1171 }
1172
1173 chip->set_mirror_regs(priv);
1174
1175 /* set age time */
1176 if (chip->reg_arl_ctrl)
1177 ar8xxx_set_age_time(priv, chip->reg_arl_ctrl);
1178
1179 mutex_unlock(&priv->reg_mutex);
1180 return 0;
1181 }
1182
1183 int
1184 ar8xxx_sw_reset_switch(struct switch_dev *dev)
1185 {
1186 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1187 const struct ar8xxx_chip *chip = priv->chip;
1188 int i;
1189
1190 mutex_lock(&priv->reg_mutex);
1191 memset(&priv->vlan, 0, sizeof(struct ar8xxx_priv) -
1192 offsetof(struct ar8xxx_priv, vlan));
1193
1194 for (i = 0; i < AR8X16_MAX_VLANS; i++)
1195 priv->vlan_id[i] = i;
1196
1197 /* Configure all ports */
1198 for (i = 0; i < dev->ports; i++)
1199 chip->init_port(priv, i);
1200
1201 priv->mirror_rx = false;
1202 priv->mirror_tx = false;
1203 priv->source_port = 0;
1204 priv->monitor_port = 0;
1205 priv->arl_age_time = AR8XXX_DEFAULT_ARL_AGE_TIME;
1206
1207 chip->init_globals(priv);
1208 chip->atu_flush(priv);
1209
1210 mutex_unlock(&priv->reg_mutex);
1211
1212 return chip->sw_hw_apply(dev);
1213 }
1214
1215 int
1216 ar8xxx_sw_set_reset_mibs(struct switch_dev *dev,
1217 const struct switch_attr *attr,
1218 struct switch_val *val)
1219 {
1220 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1221 unsigned int len;
1222 int ret;
1223
1224 if (!ar8xxx_has_mib_counters(priv))
1225 return -EOPNOTSUPP;
1226
1227 mutex_lock(&priv->mib_lock);
1228
1229 len = priv->dev.ports * priv->chip->num_mibs *
1230 sizeof(*priv->mib_stats);
1231 memset(priv->mib_stats, '\0', len);
1232 ret = ar8xxx_mib_flush(priv);
1233 if (ret)
1234 goto unlock;
1235
1236 ret = 0;
1237
1238 unlock:
1239 mutex_unlock(&priv->mib_lock);
1240 return ret;
1241 }
1242
1243 int
1244 ar8xxx_sw_set_mirror_rx_enable(struct switch_dev *dev,
1245 const struct switch_attr *attr,
1246 struct switch_val *val)
1247 {
1248 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1249
1250 mutex_lock(&priv->reg_mutex);
1251 priv->mirror_rx = !!val->value.i;
1252 priv->chip->set_mirror_regs(priv);
1253 mutex_unlock(&priv->reg_mutex);
1254
1255 return 0;
1256 }
1257
1258 int
1259 ar8xxx_sw_get_mirror_rx_enable(struct switch_dev *dev,
1260 const struct switch_attr *attr,
1261 struct switch_val *val)
1262 {
1263 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1264 val->value.i = priv->mirror_rx;
1265 return 0;
1266 }
1267
1268 int
1269 ar8xxx_sw_set_mirror_tx_enable(struct switch_dev *dev,
1270 const struct switch_attr *attr,
1271 struct switch_val *val)
1272 {
1273 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1274
1275 mutex_lock(&priv->reg_mutex);
1276 priv->mirror_tx = !!val->value.i;
1277 priv->chip->set_mirror_regs(priv);
1278 mutex_unlock(&priv->reg_mutex);
1279
1280 return 0;
1281 }
1282
1283 int
1284 ar8xxx_sw_get_mirror_tx_enable(struct switch_dev *dev,
1285 const struct switch_attr *attr,
1286 struct switch_val *val)
1287 {
1288 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1289 val->value.i = priv->mirror_tx;
1290 return 0;
1291 }
1292
1293 int
1294 ar8xxx_sw_set_mirror_monitor_port(struct switch_dev *dev,
1295 const struct switch_attr *attr,
1296 struct switch_val *val)
1297 {
1298 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1299
1300 mutex_lock(&priv->reg_mutex);
1301 priv->monitor_port = val->value.i;
1302 priv->chip->set_mirror_regs(priv);
1303 mutex_unlock(&priv->reg_mutex);
1304
1305 return 0;
1306 }
1307
1308 int
1309 ar8xxx_sw_get_mirror_monitor_port(struct switch_dev *dev,
1310 const struct switch_attr *attr,
1311 struct switch_val *val)
1312 {
1313 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1314 val->value.i = priv->monitor_port;
1315 return 0;
1316 }
1317
1318 int
1319 ar8xxx_sw_set_mirror_source_port(struct switch_dev *dev,
1320 const struct switch_attr *attr,
1321 struct switch_val *val)
1322 {
1323 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1324
1325 mutex_lock(&priv->reg_mutex);
1326 priv->source_port = val->value.i;
1327 priv->chip->set_mirror_regs(priv);
1328 mutex_unlock(&priv->reg_mutex);
1329
1330 return 0;
1331 }
1332
1333 int
1334 ar8xxx_sw_get_mirror_source_port(struct switch_dev *dev,
1335 const struct switch_attr *attr,
1336 struct switch_val *val)
1337 {
1338 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1339 val->value.i = priv->source_port;
1340 return 0;
1341 }
1342
1343 int
1344 ar8xxx_sw_set_port_reset_mib(struct switch_dev *dev,
1345 const struct switch_attr *attr,
1346 struct switch_val *val)
1347 {
1348 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1349 int port;
1350 int ret;
1351
1352 if (!ar8xxx_has_mib_counters(priv))
1353 return -EOPNOTSUPP;
1354
1355 port = val->port_vlan;
1356 if (port >= dev->ports)
1357 return -EINVAL;
1358
1359 mutex_lock(&priv->mib_lock);
1360 ret = ar8xxx_mib_capture(priv);
1361 if (ret)
1362 goto unlock;
1363
1364 ar8xxx_mib_fetch_port_stat(priv, port, true);
1365
1366 ret = 0;
1367
1368 unlock:
1369 mutex_unlock(&priv->mib_lock);
1370 return ret;
1371 }
1372
1373 static void
1374 ar8xxx_byte_to_str(char *buf, int len, u64 byte)
1375 {
1376 unsigned long b;
1377 const char *unit;
1378
1379 if (byte >= 0x40000000) { /* 1 GiB */
1380 b = byte * 10 / 0x40000000;
1381 unit = "GiB";
1382 } else if (byte >= 0x100000) { /* 1 MiB */
1383 b = byte * 10 / 0x100000;
1384 unit = "MiB";
1385 } else if (byte >= 0x400) { /* 1 KiB */
1386 b = byte * 10 / 0x400;
1387 unit = "KiB";
1388 } else {
1389 b = byte;
1390 unit = "Byte";
1391 }
1392 if (strcmp(unit, "Byte"))
1393 snprintf(buf, len, "%lu.%lu %s", b / 10, b % 10, unit);
1394 else
1395 snprintf(buf, len, "%lu %s", b, unit);
1396 }
1397
1398 int
1399 ar8xxx_sw_get_port_mib(struct switch_dev *dev,
1400 const struct switch_attr *attr,
1401 struct switch_val *val)
1402 {
1403 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1404 const struct ar8xxx_chip *chip = priv->chip;
1405 u64 *mib_stats, mib_data;
1406 unsigned int port;
1407 int ret;
1408 char *buf = priv->buf;
1409 char buf1[64];
1410 const char *mib_name;
1411 int i, len = 0;
1412 bool mib_stats_empty = true;
1413
1414 if (!ar8xxx_has_mib_counters(priv))
1415 return -EOPNOTSUPP;
1416
1417 port = val->port_vlan;
1418 if (port >= dev->ports)
1419 return -EINVAL;
1420
1421 mutex_lock(&priv->mib_lock);
1422 ret = ar8xxx_mib_capture(priv);
1423 if (ret)
1424 goto unlock;
1425
1426 ar8xxx_mib_fetch_port_stat(priv, port, false);
1427
1428 len += snprintf(buf + len, sizeof(priv->buf) - len,
1429 "MIB counters\n");
1430
1431 mib_stats = &priv->mib_stats[port * chip->num_mibs];
1432 for (i = 0; i < chip->num_mibs; i++) {
1433 mib_name = chip->mib_decs[i].name;
1434 mib_data = mib_stats[i];
1435 len += snprintf(buf + len, sizeof(priv->buf) - len,
1436 "%-12s: %llu\n", mib_name, mib_data);
1437 if ((!strcmp(mib_name, "TxByte") ||
1438 !strcmp(mib_name, "RxGoodByte")) &&
1439 mib_data >= 1024) {
1440 ar8xxx_byte_to_str(buf1, sizeof(buf1), mib_data);
1441 --len; /* discard newline at the end of buf */
1442 len += snprintf(buf + len, sizeof(priv->buf) - len,
1443 " (%s)\n", buf1);
1444 }
1445 if (mib_stats_empty && mib_data)
1446 mib_stats_empty = false;
1447 }
1448
1449 if (mib_stats_empty)
1450 len = snprintf(buf, sizeof(priv->buf), "No MIB data");
1451
1452 val->value.s = buf;
1453 val->len = len;
1454
1455 ret = 0;
1456
1457 unlock:
1458 mutex_unlock(&priv->mib_lock);
1459 return ret;
1460 }
1461
1462 int
1463 ar8xxx_sw_set_arl_age_time(struct switch_dev *dev, const struct switch_attr *attr,
1464 struct switch_val *val)
1465 {
1466 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1467 int age_time = val->value.i;
1468 u32 age_time_val;
1469
1470 if (age_time < 0)
1471 return -EINVAL;
1472
1473 age_time_val = ar8xxx_age_time_val(age_time);
1474 if (age_time_val == 0 || age_time_val > 0xffff)
1475 return -EINVAL;
1476
1477 priv->arl_age_time = age_time;
1478 return 0;
1479 }
1480
1481 int
1482 ar8xxx_sw_get_arl_age_time(struct switch_dev *dev, const struct switch_attr *attr,
1483 struct switch_val *val)
1484 {
1485 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1486 val->value.i = priv->arl_age_time;
1487 return 0;
1488 }
1489
1490 int
1491 ar8xxx_sw_get_arl_table(struct switch_dev *dev,
1492 const struct switch_attr *attr,
1493 struct switch_val *val)
1494 {
1495 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1496 struct mii_bus *bus = priv->mii_bus;
1497 const struct ar8xxx_chip *chip = priv->chip;
1498 char *buf = priv->arl_buf;
1499 int i, j, k, len = 0;
1500 struct arl_entry *a, *a1;
1501 u32 status;
1502
1503 if (!chip->get_arl_entry)
1504 return -EOPNOTSUPP;
1505
1506 mutex_lock(&priv->reg_mutex);
1507 mutex_lock(&bus->mdio_lock);
1508
1509 chip->get_arl_entry(priv, NULL, NULL, AR8XXX_ARL_INITIALIZE);
1510
1511 for(i = 0; i < AR8XXX_NUM_ARL_RECORDS; ++i) {
1512 a = &priv->arl_table[i];
1513 duplicate:
1514 chip->get_arl_entry(priv, a, &status, AR8XXX_ARL_GET_NEXT);
1515
1516 if (!status)
1517 break;
1518
1519 /* avoid duplicates
1520 * ARL table can include multiple valid entries
1521 * per MAC, just with differing status codes
1522 */
1523 for (j = 0; j < i; ++j) {
1524 a1 = &priv->arl_table[j];
1525 if (!memcmp(a->mac, a1->mac, sizeof(a->mac))) {
1526 /* ignore ports already seen in former entry */
1527 a->portmap &= ~a1->portmap;
1528 if (!a->portmap)
1529 goto duplicate;
1530 }
1531 }
1532 }
1533
1534 mutex_unlock(&bus->mdio_lock);
1535
1536 len += snprintf(buf + len, sizeof(priv->arl_buf) - len,
1537 "address resolution table\n");
1538
1539 if (i == AR8XXX_NUM_ARL_RECORDS)
1540 len += snprintf(buf + len, sizeof(priv->arl_buf) - len,
1541 "Too many entries found, displaying the first %d only!\n",
1542 AR8XXX_NUM_ARL_RECORDS);
1543
1544 for (j = 0; j < priv->dev.ports; ++j) {
1545 for (k = 0; k < i; ++k) {
1546 a = &priv->arl_table[k];
1547 if (!(a->portmap & BIT(j)))
1548 continue;
1549 len += snprintf(buf + len, sizeof(priv->arl_buf) - len,
1550 "Port %d: MAC %02x:%02x:%02x:%02x:%02x:%02x\n",
1551 j,
1552 a->mac[5], a->mac[4], a->mac[3],
1553 a->mac[2], a->mac[1], a->mac[0]);
1554 }
1555 }
1556
1557 val->value.s = buf;
1558 val->len = len;
1559
1560 mutex_unlock(&priv->reg_mutex);
1561
1562 return 0;
1563 }
1564
1565 int
1566 ar8xxx_sw_set_flush_arl_table(struct switch_dev *dev,
1567 const struct switch_attr *attr,
1568 struct switch_val *val)
1569 {
1570 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1571 int ret;
1572
1573 mutex_lock(&priv->reg_mutex);
1574 ret = priv->chip->atu_flush(priv);
1575 mutex_unlock(&priv->reg_mutex);
1576
1577 return ret;
1578 }
1579
1580 int
1581 ar8xxx_sw_set_flush_port_arl_table(struct switch_dev *dev,
1582 const struct switch_attr *attr,
1583 struct switch_val *val)
1584 {
1585 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1586 int port, ret;
1587
1588 port = val->port_vlan;
1589 if (port >= dev->ports)
1590 return -EINVAL;
1591
1592 mutex_lock(&priv->reg_mutex);
1593 ret = priv->chip->atu_flush_port(priv, port);
1594 mutex_unlock(&priv->reg_mutex);
1595
1596 return ret;
1597 }
1598
1599 static const struct switch_attr ar8xxx_sw_attr_globals[] = {
1600 {
1601 .type = SWITCH_TYPE_INT,
1602 .name = "enable_vlan",
1603 .description = "Enable VLAN mode",
1604 .set = ar8xxx_sw_set_vlan,
1605 .get = ar8xxx_sw_get_vlan,
1606 .max = 1
1607 },
1608 {
1609 .type = SWITCH_TYPE_NOVAL,
1610 .name = "reset_mibs",
1611 .description = "Reset all MIB counters",
1612 .set = ar8xxx_sw_set_reset_mibs,
1613 },
1614 {
1615 .type = SWITCH_TYPE_INT,
1616 .name = "enable_mirror_rx",
1617 .description = "Enable mirroring of RX packets",
1618 .set = ar8xxx_sw_set_mirror_rx_enable,
1619 .get = ar8xxx_sw_get_mirror_rx_enable,
1620 .max = 1
1621 },
1622 {
1623 .type = SWITCH_TYPE_INT,
1624 .name = "enable_mirror_tx",
1625 .description = "Enable mirroring of TX packets",
1626 .set = ar8xxx_sw_set_mirror_tx_enable,
1627 .get = ar8xxx_sw_get_mirror_tx_enable,
1628 .max = 1
1629 },
1630 {
1631 .type = SWITCH_TYPE_INT,
1632 .name = "mirror_monitor_port",
1633 .description = "Mirror monitor port",
1634 .set = ar8xxx_sw_set_mirror_monitor_port,
1635 .get = ar8xxx_sw_get_mirror_monitor_port,
1636 .max = AR8216_NUM_PORTS - 1
1637 },
1638 {
1639 .type = SWITCH_TYPE_INT,
1640 .name = "mirror_source_port",
1641 .description = "Mirror source port",
1642 .set = ar8xxx_sw_set_mirror_source_port,
1643 .get = ar8xxx_sw_get_mirror_source_port,
1644 .max = AR8216_NUM_PORTS - 1
1645 },
1646 {
1647 .type = SWITCH_TYPE_STRING,
1648 .name = "arl_table",
1649 .description = "Get ARL table",
1650 .set = NULL,
1651 .get = ar8xxx_sw_get_arl_table,
1652 },
1653 {
1654 .type = SWITCH_TYPE_NOVAL,
1655 .name = "flush_arl_table",
1656 .description = "Flush ARL table",
1657 .set = ar8xxx_sw_set_flush_arl_table,
1658 },
1659 };
1660
1661 const struct switch_attr ar8xxx_sw_attr_port[] = {
1662 {
1663 .type = SWITCH_TYPE_NOVAL,
1664 .name = "reset_mib",
1665 .description = "Reset single port MIB counters",
1666 .set = ar8xxx_sw_set_port_reset_mib,
1667 },
1668 {
1669 .type = SWITCH_TYPE_STRING,
1670 .name = "mib",
1671 .description = "Get port's MIB counters",
1672 .set = NULL,
1673 .get = ar8xxx_sw_get_port_mib,
1674 },
1675 {
1676 .type = SWITCH_TYPE_NOVAL,
1677 .name = "flush_arl_table",
1678 .description = "Flush port's ARL table entries",
1679 .set = ar8xxx_sw_set_flush_port_arl_table,
1680 },
1681 };
1682
1683 const struct switch_attr ar8xxx_sw_attr_vlan[1] = {
1684 {
1685 .type = SWITCH_TYPE_INT,
1686 .name = "vid",
1687 .description = "VLAN ID (0-4094)",
1688 .set = ar8xxx_sw_set_vid,
1689 .get = ar8xxx_sw_get_vid,
1690 .max = 4094,
1691 },
1692 };
1693
1694 static const struct switch_dev_ops ar8xxx_sw_ops = {
1695 .attr_global = {
1696 .attr = ar8xxx_sw_attr_globals,
1697 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_globals),
1698 },
1699 .attr_port = {
1700 .attr = ar8xxx_sw_attr_port,
1701 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_port),
1702 },
1703 .attr_vlan = {
1704 .attr = ar8xxx_sw_attr_vlan,
1705 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan),
1706 },
1707 .get_port_pvid = ar8xxx_sw_get_pvid,
1708 .set_port_pvid = ar8xxx_sw_set_pvid,
1709 .get_vlan_ports = ar8xxx_sw_get_ports,
1710 .set_vlan_ports = ar8xxx_sw_set_ports,
1711 .apply_config = ar8xxx_sw_hw_apply,
1712 .reset_switch = ar8xxx_sw_reset_switch,
1713 .get_port_link = ar8xxx_sw_get_port_link,
1714 /* The following op is disabled as it hogs the CPU and degrades performance.
1715 An implementation has been attempted in 4d8a66d but reading MIB data is slow
1716 on ar8xxx switches.
1717
1718 The high CPU load has been traced down to the ar8xxx_reg_wait() call in
1719 ar8xxx_mib_op(), which has to usleep_range() till the MIB busy flag set by
1720 the request to update the MIB counter is cleared. */
1721 #if 0
1722 .get_port_stats = ar8xxx_sw_get_port_stats,
1723 #endif
1724 };
1725
1726 static const struct ar8xxx_chip ar8216_chip = {
1727 .caps = AR8XXX_CAP_MIB_COUNTERS,
1728
1729 .reg_port_stats_start = 0x19000,
1730 .reg_port_stats_length = 0xa0,
1731 .reg_arl_ctrl = AR8216_REG_ATU_CTRL,
1732
1733 .name = "Atheros AR8216",
1734 .ports = AR8216_NUM_PORTS,
1735 .vlans = AR8216_NUM_VLANS,
1736 .swops = &ar8xxx_sw_ops,
1737
1738 .hw_init = ar8216_hw_init,
1739 .init_globals = ar8216_init_globals,
1740 .init_port = ar8216_init_port,
1741 .setup_port = ar8216_setup_port,
1742 .read_port_status = ar8216_read_port_status,
1743 .atu_flush = ar8216_atu_flush,
1744 .atu_flush_port = ar8216_atu_flush_port,
1745 .vtu_flush = ar8216_vtu_flush,
1746 .vtu_load_vlan = ar8216_vtu_load_vlan,
1747 .set_mirror_regs = ar8216_set_mirror_regs,
1748 .get_arl_entry = ar8216_get_arl_entry,
1749 .sw_hw_apply = ar8xxx_sw_hw_apply,
1750
1751 .num_mibs = ARRAY_SIZE(ar8216_mibs),
1752 .mib_decs = ar8216_mibs,
1753 .mib_func = AR8216_REG_MIB_FUNC
1754 };
1755
1756 static const struct ar8xxx_chip ar8236_chip = {
1757 .caps = AR8XXX_CAP_MIB_COUNTERS,
1758
1759 .reg_port_stats_start = 0x20000,
1760 .reg_port_stats_length = 0x100,
1761 .reg_arl_ctrl = AR8216_REG_ATU_CTRL,
1762
1763 .name = "Atheros AR8236",
1764 .ports = AR8216_NUM_PORTS,
1765 .vlans = AR8216_NUM_VLANS,
1766 .swops = &ar8xxx_sw_ops,
1767
1768 .hw_init = ar8216_hw_init,
1769 .init_globals = ar8236_init_globals,
1770 .init_port = ar8216_init_port,
1771 .setup_port = ar8236_setup_port,
1772 .read_port_status = ar8216_read_port_status,
1773 .atu_flush = ar8216_atu_flush,
1774 .atu_flush_port = ar8216_atu_flush_port,
1775 .vtu_flush = ar8216_vtu_flush,
1776 .vtu_load_vlan = ar8216_vtu_load_vlan,
1777 .set_mirror_regs = ar8216_set_mirror_regs,
1778 .get_arl_entry = ar8216_get_arl_entry,
1779 .sw_hw_apply = ar8xxx_sw_hw_apply,
1780
1781 .num_mibs = ARRAY_SIZE(ar8236_mibs),
1782 .mib_decs = ar8236_mibs,
1783 .mib_func = AR8216_REG_MIB_FUNC
1784 };
1785
1786 static const struct ar8xxx_chip ar8316_chip = {
1787 .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
1788
1789 .reg_port_stats_start = 0x20000,
1790 .reg_port_stats_length = 0x100,
1791 .reg_arl_ctrl = AR8216_REG_ATU_CTRL,
1792
1793 .name = "Atheros AR8316",
1794 .ports = AR8216_NUM_PORTS,
1795 .vlans = AR8X16_MAX_VLANS,
1796 .swops = &ar8xxx_sw_ops,
1797
1798 .hw_init = ar8316_hw_init,
1799 .init_globals = ar8316_init_globals,
1800 .init_port = ar8216_init_port,
1801 .setup_port = ar8216_setup_port,
1802 .read_port_status = ar8216_read_port_status,
1803 .atu_flush = ar8216_atu_flush,
1804 .atu_flush_port = ar8216_atu_flush_port,
1805 .vtu_flush = ar8216_vtu_flush,
1806 .vtu_load_vlan = ar8216_vtu_load_vlan,
1807 .set_mirror_regs = ar8216_set_mirror_regs,
1808 .get_arl_entry = ar8216_get_arl_entry,
1809 .sw_hw_apply = ar8xxx_sw_hw_apply,
1810
1811 .num_mibs = ARRAY_SIZE(ar8236_mibs),
1812 .mib_decs = ar8236_mibs,
1813 .mib_func = AR8216_REG_MIB_FUNC
1814 };
1815
1816 static int
1817 ar8xxx_read_id(struct ar8xxx_priv *priv)
1818 {
1819 u32 val;
1820 u16 id;
1821 int i;
1822
1823 val = ar8xxx_read(priv, AR8216_REG_CTRL);
1824 if (val == ~0)
1825 return -ENODEV;
1826
1827 id = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
1828 for (i = 0; i < AR8X16_PROBE_RETRIES; i++) {
1829 u16 t;
1830
1831 val = ar8xxx_read(priv, AR8216_REG_CTRL);
1832 if (val == ~0)
1833 return -ENODEV;
1834
1835 t = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
1836 if (t != id)
1837 return -ENODEV;
1838 }
1839
1840 priv->chip_ver = (id & AR8216_CTRL_VERSION) >> AR8216_CTRL_VERSION_S;
1841 priv->chip_rev = (id & AR8216_CTRL_REVISION);
1842 return 0;
1843 }
1844
1845 static int
1846 ar8xxx_id_chip(struct ar8xxx_priv *priv)
1847 {
1848 int ret;
1849
1850 ret = ar8xxx_read_id(priv);
1851 if(ret)
1852 return ret;
1853
1854 switch (priv->chip_ver) {
1855 case AR8XXX_VER_AR8216:
1856 priv->chip = &ar8216_chip;
1857 break;
1858 case AR8XXX_VER_AR8236:
1859 priv->chip = &ar8236_chip;
1860 break;
1861 case AR8XXX_VER_AR8316:
1862 priv->chip = &ar8316_chip;
1863 break;
1864 case AR8XXX_VER_AR8327:
1865 priv->chip = &ar8327_chip;
1866 break;
1867 case AR8XXX_VER_AR8337:
1868 priv->chip = &ar8337_chip;
1869 break;
1870 default:
1871 pr_err("ar8216: Unknown Atheros device [ver=%d, rev=%d]\n",
1872 priv->chip_ver, priv->chip_rev);
1873
1874 return -ENODEV;
1875 }
1876
1877 return 0;
1878 }
1879
1880 static void
1881 ar8xxx_mib_work_func(struct work_struct *work)
1882 {
1883 struct ar8xxx_priv *priv;
1884 int err;
1885
1886 priv = container_of(work, struct ar8xxx_priv, mib_work.work);
1887
1888 mutex_lock(&priv->mib_lock);
1889
1890 err = ar8xxx_mib_capture(priv);
1891 if (err)
1892 goto next_port;
1893
1894 ar8xxx_mib_fetch_port_stat(priv, priv->mib_next_port, false);
1895
1896 next_port:
1897 priv->mib_next_port++;
1898 if (priv->mib_next_port >= priv->dev.ports)
1899 priv->mib_next_port = 0;
1900
1901 mutex_unlock(&priv->mib_lock);
1902 schedule_delayed_work(&priv->mib_work,
1903 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
1904 }
1905
1906 static int
1907 ar8xxx_mib_init(struct ar8xxx_priv *priv)
1908 {
1909 unsigned int len;
1910
1911 if (!ar8xxx_has_mib_counters(priv))
1912 return 0;
1913
1914 BUG_ON(!priv->chip->mib_decs || !priv->chip->num_mibs);
1915
1916 len = priv->dev.ports * priv->chip->num_mibs *
1917 sizeof(*priv->mib_stats);
1918 priv->mib_stats = kzalloc(len, GFP_KERNEL);
1919
1920 if (!priv->mib_stats)
1921 return -ENOMEM;
1922
1923 return 0;
1924 }
1925
1926 static void
1927 ar8xxx_mib_start(struct ar8xxx_priv *priv)
1928 {
1929 if (!ar8xxx_has_mib_counters(priv))
1930 return;
1931
1932 schedule_delayed_work(&priv->mib_work,
1933 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
1934 }
1935
1936 static void
1937 ar8xxx_mib_stop(struct ar8xxx_priv *priv)
1938 {
1939 if (!ar8xxx_has_mib_counters(priv))
1940 return;
1941
1942 cancel_delayed_work_sync(&priv->mib_work);
1943 }
1944
1945 static struct ar8xxx_priv *
1946 ar8xxx_create(void)
1947 {
1948 struct ar8xxx_priv *priv;
1949
1950 priv = kzalloc(sizeof(struct ar8xxx_priv), GFP_KERNEL);
1951 if (priv == NULL)
1952 return NULL;
1953
1954 mutex_init(&priv->reg_mutex);
1955 mutex_init(&priv->mib_lock);
1956 INIT_DELAYED_WORK(&priv->mib_work, ar8xxx_mib_work_func);
1957
1958 return priv;
1959 }
1960
1961 static void
1962 ar8xxx_free(struct ar8xxx_priv *priv)
1963 {
1964 if (priv->chip && priv->chip->cleanup)
1965 priv->chip->cleanup(priv);
1966
1967 kfree(priv->chip_data);
1968 kfree(priv->mib_stats);
1969 kfree(priv);
1970 }
1971
1972 static int
1973 ar8xxx_probe_switch(struct ar8xxx_priv *priv)
1974 {
1975 const struct ar8xxx_chip *chip;
1976 struct switch_dev *swdev;
1977 int ret;
1978
1979 chip = priv->chip;
1980
1981 swdev = &priv->dev;
1982 swdev->cpu_port = AR8216_PORT_CPU;
1983 swdev->name = chip->name;
1984 swdev->vlans = chip->vlans;
1985 swdev->ports = chip->ports;
1986 swdev->ops = chip->swops;
1987
1988 ret = ar8xxx_mib_init(priv);
1989 if (ret)
1990 return ret;
1991
1992 return 0;
1993 }
1994
1995 static int
1996 ar8xxx_start(struct ar8xxx_priv *priv)
1997 {
1998 int ret;
1999
2000 priv->init = true;
2001
2002 ret = priv->chip->hw_init(priv);
2003 if (ret)
2004 return ret;
2005
2006 ret = ar8xxx_sw_reset_switch(&priv->dev);
2007 if (ret)
2008 return ret;
2009
2010 priv->init = false;
2011
2012 ar8xxx_mib_start(priv);
2013
2014 return 0;
2015 }
2016
2017 static int
2018 ar8xxx_phy_config_init(struct phy_device *phydev)
2019 {
2020 struct ar8xxx_priv *priv = phydev->priv;
2021 struct net_device *dev = phydev->attached_dev;
2022 int ret;
2023
2024 if (WARN_ON(!priv))
2025 return -ENODEV;
2026
2027 if (priv->chip->config_at_probe)
2028 return ar8xxx_phy_check_aneg(phydev);
2029
2030 priv->phy = phydev;
2031
2032 if (phydev->mdio.addr != 0) {
2033 if (chip_is_ar8316(priv)) {
2034 /* switch device has been initialized, reinit */
2035 priv->dev.ports = (AR8216_NUM_PORTS - 1);
2036 priv->initialized = false;
2037 priv->port4_phy = true;
2038 ar8316_hw_init(priv);
2039 return 0;
2040 }
2041
2042 return 0;
2043 }
2044
2045 ret = ar8xxx_start(priv);
2046 if (ret)
2047 return ret;
2048
2049 /* VID fixup only needed on ar8216 */
2050 if (chip_is_ar8216(priv)) {
2051 dev->phy_ptr = priv;
2052 dev->priv_flags |= IFF_NO_IP_ALIGN;
2053 dev->eth_mangle_rx = ar8216_mangle_rx;
2054 dev->eth_mangle_tx = ar8216_mangle_tx;
2055 }
2056
2057 return 0;
2058 }
2059
2060 static bool
2061 ar8xxx_check_link_states(struct ar8xxx_priv *priv)
2062 {
2063 bool link_new, changed = false;
2064 u32 status;
2065 int i;
2066
2067 mutex_lock(&priv->reg_mutex);
2068
2069 for (i = 0; i < priv->dev.ports; i++) {
2070 status = priv->chip->read_port_status(priv, i);
2071 link_new = !!(status & AR8216_PORT_STATUS_LINK_UP);
2072 if (link_new == priv->link_up[i])
2073 continue;
2074
2075 priv->link_up[i] = link_new;
2076 changed = true;
2077 /* flush ARL entries for this port if it went down*/
2078 if (!link_new)
2079 priv->chip->atu_flush_port(priv, i);
2080 dev_info(&priv->phy->mdio.dev, "Port %d is %s\n",
2081 i, link_new ? "up" : "down");
2082 }
2083
2084 mutex_unlock(&priv->reg_mutex);
2085
2086 return changed;
2087 }
2088
2089 static int
2090 ar8xxx_phy_read_status(struct phy_device *phydev)
2091 {
2092 struct ar8xxx_priv *priv = phydev->priv;
2093 struct switch_port_link link;
2094
2095 /* check for switch port link changes */
2096 if (phydev->state == PHY_CHANGELINK)
2097 ar8xxx_check_link_states(priv);
2098
2099 if (phydev->mdio.addr != 0)
2100 return genphy_read_status(phydev);
2101
2102 ar8216_read_port_link(priv, phydev->mdio.addr, &link);
2103 phydev->link = !!link.link;
2104 if (!phydev->link)
2105 return 0;
2106
2107 switch (link.speed) {
2108 case SWITCH_PORT_SPEED_10:
2109 phydev->speed = SPEED_10;
2110 break;
2111 case SWITCH_PORT_SPEED_100:
2112 phydev->speed = SPEED_100;
2113 break;
2114 case SWITCH_PORT_SPEED_1000:
2115 phydev->speed = SPEED_1000;
2116 break;
2117 default:
2118 phydev->speed = 0;
2119 }
2120 phydev->duplex = link.duplex ? DUPLEX_FULL : DUPLEX_HALF;
2121
2122 phydev->state = PHY_RUNNING;
2123 netif_carrier_on(phydev->attached_dev);
2124 if (phydev->adjust_link)
2125 phydev->adjust_link(phydev->attached_dev);
2126
2127 return 0;
2128 }
2129
2130 static int
2131 ar8xxx_phy_config_aneg(struct phy_device *phydev)
2132 {
2133 if (phydev->mdio.addr == 0)
2134 return 0;
2135
2136 return genphy_config_aneg(phydev);
2137 }
2138
2139 static const u32 ar8xxx_phy_ids[] = {
2140 0x004dd033,
2141 0x004dd034, /* AR8327 */
2142 0x004dd036, /* AR8337 */
2143 0x004dd041,
2144 0x004dd042,
2145 0x004dd043, /* AR8236 */
2146 };
2147
2148 static bool
2149 ar8xxx_phy_match(u32 phy_id)
2150 {
2151 int i;
2152
2153 for (i = 0; i < ARRAY_SIZE(ar8xxx_phy_ids); i++)
2154 if (phy_id == ar8xxx_phy_ids[i])
2155 return true;
2156
2157 return false;
2158 }
2159
2160 static bool
2161 ar8xxx_is_possible(struct mii_bus *bus)
2162 {
2163 unsigned int i, found_phys = 0;
2164
2165 for (i = 0; i < 5; i++) {
2166 u32 phy_id;
2167
2168 phy_id = mdiobus_read(bus, i, MII_PHYSID1) << 16;
2169 phy_id |= mdiobus_read(bus, i, MII_PHYSID2);
2170 if (ar8xxx_phy_match(phy_id)) {
2171 found_phys++;
2172 } else if (phy_id) {
2173 pr_debug("ar8xxx: unknown PHY at %s:%02x id:%08x\n",
2174 dev_name(&bus->dev), i, phy_id);
2175 }
2176 }
2177 return !!found_phys;
2178 }
2179
2180 static int
2181 ar8xxx_phy_probe(struct phy_device *phydev)
2182 {
2183 struct ar8xxx_priv *priv;
2184 struct switch_dev *swdev;
2185 int ret;
2186
2187 /* skip PHYs at unused adresses */
2188 if (phydev->mdio.addr != 0 && phydev->mdio.addr != 3 && phydev->mdio.addr != 4)
2189 return -ENODEV;
2190
2191 if (!ar8xxx_is_possible(phydev->mdio.bus))
2192 return -ENODEV;
2193
2194 mutex_lock(&ar8xxx_dev_list_lock);
2195 list_for_each_entry(priv, &ar8xxx_dev_list, list)
2196 if (priv->mii_bus == phydev->mdio.bus)
2197 goto found;
2198
2199 priv = ar8xxx_create();
2200 if (priv == NULL) {
2201 ret = -ENOMEM;
2202 goto unlock;
2203 }
2204
2205 priv->mii_bus = phydev->mdio.bus;
2206 priv->pdev = &phydev->mdio.dev;
2207
2208 ret = ar8xxx_id_chip(priv);
2209 if (ret)
2210 goto free_priv;
2211
2212 ret = ar8xxx_probe_switch(priv);
2213 if (ret)
2214 goto free_priv;
2215
2216 swdev = &priv->dev;
2217 swdev->alias = dev_name(&priv->mii_bus->dev);
2218 ret = register_switch(swdev, NULL);
2219 if (ret)
2220 goto free_priv;
2221
2222 pr_info("%s: %s rev. %u switch registered on %s\n",
2223 swdev->devname, swdev->name, priv->chip_rev,
2224 dev_name(&priv->mii_bus->dev));
2225
2226 list_add(&priv->list, &ar8xxx_dev_list);
2227
2228 found:
2229 priv->use_count++;
2230
2231 if (phydev->mdio.addr == 0) {
2232 if (ar8xxx_has_gige(priv)) {
2233 phydev->supported = SUPPORTED_1000baseT_Full;
2234 phydev->advertising = ADVERTISED_1000baseT_Full;
2235 } else {
2236 phydev->supported = SUPPORTED_100baseT_Full;
2237 phydev->advertising = ADVERTISED_100baseT_Full;
2238 }
2239
2240 if (priv->chip->config_at_probe) {
2241 priv->phy = phydev;
2242
2243 ret = ar8xxx_start(priv);
2244 if (ret)
2245 goto err_unregister_switch;
2246 }
2247 } else {
2248 if (ar8xxx_has_gige(priv)) {
2249 phydev->supported |= SUPPORTED_1000baseT_Full;
2250 phydev->advertising |= ADVERTISED_1000baseT_Full;
2251 }
2252 if (priv->chip->phy_rgmii_set)
2253 priv->chip->phy_rgmii_set(priv, phydev);
2254 }
2255
2256 phydev->priv = priv;
2257
2258 mutex_unlock(&ar8xxx_dev_list_lock);
2259
2260 return 0;
2261
2262 err_unregister_switch:
2263 if (--priv->use_count)
2264 goto unlock;
2265
2266 unregister_switch(&priv->dev);
2267
2268 free_priv:
2269 ar8xxx_free(priv);
2270 unlock:
2271 mutex_unlock(&ar8xxx_dev_list_lock);
2272 return ret;
2273 }
2274
2275 static void
2276 ar8xxx_phy_detach(struct phy_device *phydev)
2277 {
2278 struct net_device *dev = phydev->attached_dev;
2279
2280 if (!dev)
2281 return;
2282
2283 dev->phy_ptr = NULL;
2284 dev->priv_flags &= ~IFF_NO_IP_ALIGN;
2285 dev->eth_mangle_rx = NULL;
2286 dev->eth_mangle_tx = NULL;
2287 }
2288
2289 static void
2290 ar8xxx_phy_remove(struct phy_device *phydev)
2291 {
2292 struct ar8xxx_priv *priv = phydev->priv;
2293
2294 if (WARN_ON(!priv))
2295 return;
2296
2297 phydev->priv = NULL;
2298
2299 mutex_lock(&ar8xxx_dev_list_lock);
2300
2301 if (--priv->use_count > 0) {
2302 mutex_unlock(&ar8xxx_dev_list_lock);
2303 return;
2304 }
2305
2306 list_del(&priv->list);
2307 mutex_unlock(&ar8xxx_dev_list_lock);
2308
2309 unregister_switch(&priv->dev);
2310 ar8xxx_mib_stop(priv);
2311 ar8xxx_free(priv);
2312 }
2313
2314 static int
2315 ar8xxx_phy_soft_reset(struct phy_device *phydev)
2316 {
2317 /* we don't need an extra reset */
2318 return 0;
2319 }
2320
2321 static struct phy_driver ar8xxx_phy_driver[] = {
2322 {
2323 .phy_id = 0x004d0000,
2324 .name = "Atheros AR8216/AR8236/AR8316",
2325 .phy_id_mask = 0xffff0000,
2326 .features = PHY_BASIC_FEATURES,
2327 .probe = ar8xxx_phy_probe,
2328 .remove = ar8xxx_phy_remove,
2329 .detach = ar8xxx_phy_detach,
2330 .config_init = ar8xxx_phy_config_init,
2331 .config_aneg = ar8xxx_phy_config_aneg,
2332 .read_status = ar8xxx_phy_read_status,
2333 .soft_reset = ar8xxx_phy_soft_reset,
2334 }
2335 };
2336
2337 static const struct of_device_id ar8xxx_mdiodev_of_match[] = {
2338 {
2339 .compatible = "qca,ar8236",
2340 .data = &ar8236_chip,
2341 }, {
2342 .compatible = "qca,ar8327",
2343 .data = &ar8327_chip,
2344 },
2345 { /* sentinel */ },
2346 };
2347
2348 static int
2349 ar8xxx_mdiodev_probe(struct mdio_device *mdiodev)
2350 {
2351 const struct of_device_id *match;
2352 struct ar8xxx_priv *priv;
2353 struct switch_dev *swdev;
2354 int ret;
2355
2356 match = of_match_device(ar8xxx_mdiodev_of_match, &mdiodev->dev);
2357 if (!match)
2358 return -EINVAL;
2359
2360 priv = ar8xxx_create();
2361 if (priv == NULL)
2362 return -ENOMEM;
2363
2364 priv->mii_bus = mdiodev->bus;
2365 priv->pdev = &mdiodev->dev;
2366 priv->chip = (const struct ar8xxx_chip *) match->data;
2367
2368 ret = ar8xxx_read_id(priv);
2369 if (ret)
2370 goto free_priv;
2371
2372 ret = ar8xxx_probe_switch(priv);
2373 if (ret)
2374 goto free_priv;
2375
2376 swdev = &priv->dev;
2377 swdev->alias = dev_name(&mdiodev->dev);
2378 ret = register_switch(swdev, NULL);
2379 if (ret)
2380 goto free_priv;
2381
2382 pr_info("%s: %s rev. %u switch registered on %s\n",
2383 swdev->devname, swdev->name, priv->chip_rev,
2384 dev_name(&priv->mii_bus->dev));
2385
2386 mutex_lock(&ar8xxx_dev_list_lock);
2387 list_add(&priv->list, &ar8xxx_dev_list);
2388 mutex_unlock(&ar8xxx_dev_list_lock);
2389
2390 priv->use_count++;
2391
2392 ret = ar8xxx_start(priv);
2393 if (ret)
2394 goto err_unregister_switch;
2395
2396 dev_set_drvdata(&mdiodev->dev, priv);
2397
2398 return 0;
2399
2400 err_unregister_switch:
2401 if (--priv->use_count)
2402 return ret;
2403
2404 unregister_switch(&priv->dev);
2405
2406 free_priv:
2407 ar8xxx_free(priv);
2408 return ret;
2409 }
2410
2411 static void
2412 ar8xxx_mdiodev_remove(struct mdio_device *mdiodev)
2413 {
2414 struct ar8xxx_priv *priv = dev_get_drvdata(&mdiodev->dev);
2415
2416 if (WARN_ON(!priv))
2417 return;
2418
2419 mutex_lock(&ar8xxx_dev_list_lock);
2420
2421 if (--priv->use_count > 0) {
2422 mutex_unlock(&ar8xxx_dev_list_lock);
2423 return;
2424 }
2425
2426 list_del(&priv->list);
2427 mutex_unlock(&ar8xxx_dev_list_lock);
2428
2429 unregister_switch(&priv->dev);
2430 ar8xxx_mib_stop(priv);
2431 ar8xxx_free(priv);
2432 }
2433
2434 static struct mdio_driver ar8xxx_mdio_driver = {
2435 .probe = ar8xxx_mdiodev_probe,
2436 .remove = ar8xxx_mdiodev_remove,
2437 .mdiodrv.driver = {
2438 .name = "ar8xxx-switch",
2439 .of_match_table = ar8xxx_mdiodev_of_match,
2440 },
2441 };
2442
2443 static int __init ar8216_init(void)
2444 {
2445 int ret;
2446
2447 ret = phy_drivers_register(ar8xxx_phy_driver,
2448 ARRAY_SIZE(ar8xxx_phy_driver),
2449 THIS_MODULE);
2450 if (ret)
2451 return ret;
2452
2453 ret = mdio_driver_register(&ar8xxx_mdio_driver);
2454 if (ret)
2455 phy_drivers_unregister(ar8xxx_phy_driver,
2456 ARRAY_SIZE(ar8xxx_phy_driver));
2457
2458 return ret;
2459 }
2460 module_init(ar8216_init);
2461
2462 static void __exit ar8216_exit(void)
2463 {
2464 mdio_driver_unregister(&ar8xxx_mdio_driver);
2465 phy_drivers_unregister(ar8xxx_phy_driver,
2466 ARRAY_SIZE(ar8xxx_phy_driver));
2467 }
2468 module_exit(ar8216_exit);
2469
2470 MODULE_LICENSE("GPL");
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