2 * ar8216.c: AR8216 switch driver
4 * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>
5 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/list.h>
22 #include <linux/if_ether.h>
23 #include <linux/skbuff.h>
24 #include <linux/netdevice.h>
25 #include <linux/netlink.h>
26 #include <linux/of_device.h>
27 #include <linux/of_mdio.h>
28 #include <linux/of_net.h>
29 #include <linux/bitops.h>
30 #include <net/genetlink.h>
31 #include <linux/switch.h>
32 #include <linux/delay.h>
33 #include <linux/phy.h>
34 #include <linux/etherdevice.h>
35 #include <linux/lockdep.h>
36 #include <linux/ar8216_platform.h>
37 #include <linux/workqueue.h>
38 #include <linux/version.h>
42 extern const struct ar8xxx_chip ar8327_chip
;
43 extern const struct ar8xxx_chip ar8337_chip
;
45 #define AR8XXX_MIB_WORK_DELAY 2000 /* msecs */
47 #define MIB_DESC(_s , _o, _n) \
54 static const struct ar8xxx_mib_desc ar8216_mibs
[] = {
55 MIB_DESC(1, AR8216_STATS_RXBROAD
, "RxBroad"),
56 MIB_DESC(1, AR8216_STATS_RXPAUSE
, "RxPause"),
57 MIB_DESC(1, AR8216_STATS_RXMULTI
, "RxMulti"),
58 MIB_DESC(1, AR8216_STATS_RXFCSERR
, "RxFcsErr"),
59 MIB_DESC(1, AR8216_STATS_RXALIGNERR
, "RxAlignErr"),
60 MIB_DESC(1, AR8216_STATS_RXRUNT
, "RxRunt"),
61 MIB_DESC(1, AR8216_STATS_RXFRAGMENT
, "RxFragment"),
62 MIB_DESC(1, AR8216_STATS_RX64BYTE
, "Rx64Byte"),
63 MIB_DESC(1, AR8216_STATS_RX128BYTE
, "Rx128Byte"),
64 MIB_DESC(1, AR8216_STATS_RX256BYTE
, "Rx256Byte"),
65 MIB_DESC(1, AR8216_STATS_RX512BYTE
, "Rx512Byte"),
66 MIB_DESC(1, AR8216_STATS_RX1024BYTE
, "Rx1024Byte"),
67 MIB_DESC(1, AR8216_STATS_RXMAXBYTE
, "RxMaxByte"),
68 MIB_DESC(1, AR8216_STATS_RXTOOLONG
, "RxTooLong"),
69 MIB_DESC(2, AR8216_STATS_RXGOODBYTE
, "RxGoodByte"),
70 MIB_DESC(2, AR8216_STATS_RXBADBYTE
, "RxBadByte"),
71 MIB_DESC(1, AR8216_STATS_RXOVERFLOW
, "RxOverFlow"),
72 MIB_DESC(1, AR8216_STATS_FILTERED
, "Filtered"),
73 MIB_DESC(1, AR8216_STATS_TXBROAD
, "TxBroad"),
74 MIB_DESC(1, AR8216_STATS_TXPAUSE
, "TxPause"),
75 MIB_DESC(1, AR8216_STATS_TXMULTI
, "TxMulti"),
76 MIB_DESC(1, AR8216_STATS_TXUNDERRUN
, "TxUnderRun"),
77 MIB_DESC(1, AR8216_STATS_TX64BYTE
, "Tx64Byte"),
78 MIB_DESC(1, AR8216_STATS_TX128BYTE
, "Tx128Byte"),
79 MIB_DESC(1, AR8216_STATS_TX256BYTE
, "Tx256Byte"),
80 MIB_DESC(1, AR8216_STATS_TX512BYTE
, "Tx512Byte"),
81 MIB_DESC(1, AR8216_STATS_TX1024BYTE
, "Tx1024Byte"),
82 MIB_DESC(1, AR8216_STATS_TXMAXBYTE
, "TxMaxByte"),
83 MIB_DESC(1, AR8216_STATS_TXOVERSIZE
, "TxOverSize"),
84 MIB_DESC(2, AR8216_STATS_TXBYTE
, "TxByte"),
85 MIB_DESC(1, AR8216_STATS_TXCOLLISION
, "TxCollision"),
86 MIB_DESC(1, AR8216_STATS_TXABORTCOL
, "TxAbortCol"),
87 MIB_DESC(1, AR8216_STATS_TXMULTICOL
, "TxMultiCol"),
88 MIB_DESC(1, AR8216_STATS_TXSINGLECOL
, "TxSingleCol"),
89 MIB_DESC(1, AR8216_STATS_TXEXCDEFER
, "TxExcDefer"),
90 MIB_DESC(1, AR8216_STATS_TXDEFER
, "TxDefer"),
91 MIB_DESC(1, AR8216_STATS_TXLATECOL
, "TxLateCol"),
94 const struct ar8xxx_mib_desc ar8236_mibs
[39] = {
95 MIB_DESC(1, AR8236_STATS_RXBROAD
, "RxBroad"),
96 MIB_DESC(1, AR8236_STATS_RXPAUSE
, "RxPause"),
97 MIB_DESC(1, AR8236_STATS_RXMULTI
, "RxMulti"),
98 MIB_DESC(1, AR8236_STATS_RXFCSERR
, "RxFcsErr"),
99 MIB_DESC(1, AR8236_STATS_RXALIGNERR
, "RxAlignErr"),
100 MIB_DESC(1, AR8236_STATS_RXRUNT
, "RxRunt"),
101 MIB_DESC(1, AR8236_STATS_RXFRAGMENT
, "RxFragment"),
102 MIB_DESC(1, AR8236_STATS_RX64BYTE
, "Rx64Byte"),
103 MIB_DESC(1, AR8236_STATS_RX128BYTE
, "Rx128Byte"),
104 MIB_DESC(1, AR8236_STATS_RX256BYTE
, "Rx256Byte"),
105 MIB_DESC(1, AR8236_STATS_RX512BYTE
, "Rx512Byte"),
106 MIB_DESC(1, AR8236_STATS_RX1024BYTE
, "Rx1024Byte"),
107 MIB_DESC(1, AR8236_STATS_RX1518BYTE
, "Rx1518Byte"),
108 MIB_DESC(1, AR8236_STATS_RXMAXBYTE
, "RxMaxByte"),
109 MIB_DESC(1, AR8236_STATS_RXTOOLONG
, "RxTooLong"),
110 MIB_DESC(2, AR8236_STATS_RXGOODBYTE
, "RxGoodByte"),
111 MIB_DESC(2, AR8236_STATS_RXBADBYTE
, "RxBadByte"),
112 MIB_DESC(1, AR8236_STATS_RXOVERFLOW
, "RxOverFlow"),
113 MIB_DESC(1, AR8236_STATS_FILTERED
, "Filtered"),
114 MIB_DESC(1, AR8236_STATS_TXBROAD
, "TxBroad"),
115 MIB_DESC(1, AR8236_STATS_TXPAUSE
, "TxPause"),
116 MIB_DESC(1, AR8236_STATS_TXMULTI
, "TxMulti"),
117 MIB_DESC(1, AR8236_STATS_TXUNDERRUN
, "TxUnderRun"),
118 MIB_DESC(1, AR8236_STATS_TX64BYTE
, "Tx64Byte"),
119 MIB_DESC(1, AR8236_STATS_TX128BYTE
, "Tx128Byte"),
120 MIB_DESC(1, AR8236_STATS_TX256BYTE
, "Tx256Byte"),
121 MIB_DESC(1, AR8236_STATS_TX512BYTE
, "Tx512Byte"),
122 MIB_DESC(1, AR8236_STATS_TX1024BYTE
, "Tx1024Byte"),
123 MIB_DESC(1, AR8236_STATS_TX1518BYTE
, "Tx1518Byte"),
124 MIB_DESC(1, AR8236_STATS_TXMAXBYTE
, "TxMaxByte"),
125 MIB_DESC(1, AR8236_STATS_TXOVERSIZE
, "TxOverSize"),
126 MIB_DESC(2, AR8236_STATS_TXBYTE
, "TxByte"),
127 MIB_DESC(1, AR8236_STATS_TXCOLLISION
, "TxCollision"),
128 MIB_DESC(1, AR8236_STATS_TXABORTCOL
, "TxAbortCol"),
129 MIB_DESC(1, AR8236_STATS_TXMULTICOL
, "TxMultiCol"),
130 MIB_DESC(1, AR8236_STATS_TXSINGLECOL
, "TxSingleCol"),
131 MIB_DESC(1, AR8236_STATS_TXEXCDEFER
, "TxExcDefer"),
132 MIB_DESC(1, AR8236_STATS_TXDEFER
, "TxDefer"),
133 MIB_DESC(1, AR8236_STATS_TXLATECOL
, "TxLateCol"),
136 static DEFINE_MUTEX(ar8xxx_dev_list_lock
);
137 static LIST_HEAD(ar8xxx_dev_list
);
139 /* inspired by phy_poll_reset in drivers/net/phy/phy_device.c */
141 ar8xxx_phy_poll_reset(struct mii_bus
*bus
)
143 unsigned int sleep_msecs
= 20;
146 for (elapsed
= sleep_msecs
; elapsed
<= 600;
147 elapsed
+= sleep_msecs
) {
149 for (i
= 0; i
< AR8XXX_NUM_PHYS
; i
++) {
150 ret
= mdiobus_read(bus
, i
, MII_BMCR
);
153 if (ret
& BMCR_RESET
)
155 if (i
== AR8XXX_NUM_PHYS
- 1) {
156 usleep_range(1000, 2000);
165 ar8xxx_phy_check_aneg(struct phy_device
*phydev
)
169 if (phydev
->autoneg
!= AUTONEG_ENABLE
)
172 * BMCR_ANENABLE might have been cleared
173 * by phy_init_hw in certain kernel versions
174 * therefore check for it
176 ret
= phy_read(phydev
, MII_BMCR
);
179 if (ret
& BMCR_ANENABLE
)
182 dev_info(&phydev
->mdio
.dev
, "ANEG disabled, re-enabling ...\n");
183 ret
|= BMCR_ANENABLE
| BMCR_ANRESTART
;
184 return phy_write(phydev
, MII_BMCR
, ret
);
188 ar8xxx_phy_init(struct ar8xxx_priv
*priv
)
193 bus
= priv
->sw_mii_bus
?: priv
->mii_bus
;
194 for (i
= 0; i
< AR8XXX_NUM_PHYS
; i
++) {
195 if (priv
->chip
->phy_fixup
)
196 priv
->chip
->phy_fixup(priv
, i
);
198 /* initialize the port itself */
199 mdiobus_write(bus
, i
, MII_ADVERTISE
,
200 ADVERTISE_ALL
| ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
);
201 if (ar8xxx_has_gige(priv
))
202 mdiobus_write(bus
, i
, MII_CTRL1000
, ADVERTISE_1000FULL
);
203 mdiobus_write(bus
, i
, MII_BMCR
, BMCR_RESET
| BMCR_ANENABLE
);
206 ar8xxx_phy_poll_reset(bus
);
210 ar8xxx_mii_read32(struct ar8xxx_priv
*priv
, int phy_id
, int regnum
)
212 struct mii_bus
*bus
= priv
->mii_bus
;
215 lo
= bus
->read(bus
, phy_id
, regnum
);
216 hi
= bus
->read(bus
, phy_id
, regnum
+ 1);
218 return (hi
<< 16) | lo
;
222 ar8xxx_mii_write32(struct ar8xxx_priv
*priv
, int phy_id
, int regnum
, u32 val
)
224 struct mii_bus
*bus
= priv
->mii_bus
;
228 hi
= (u16
) (val
>> 16);
230 if (priv
->chip
->mii_lo_first
)
232 bus
->write(bus
, phy_id
, regnum
, lo
);
233 bus
->write(bus
, phy_id
, regnum
+ 1, hi
);
235 bus
->write(bus
, phy_id
, regnum
+ 1, hi
);
236 bus
->write(bus
, phy_id
, regnum
, lo
);
241 ar8xxx_read(struct ar8xxx_priv
*priv
, int reg
)
243 struct mii_bus
*bus
= priv
->mii_bus
;
247 split_addr((u32
) reg
, &r1
, &r2
, &page
);
249 mutex_lock(&bus
->mdio_lock
);
251 bus
->write(bus
, 0x18, 0, page
);
252 wait_for_page_switch();
253 val
= ar8xxx_mii_read32(priv
, 0x10 | r2
, r1
);
255 mutex_unlock(&bus
->mdio_lock
);
261 ar8xxx_write(struct ar8xxx_priv
*priv
, int reg
, u32 val
)
263 struct mii_bus
*bus
= priv
->mii_bus
;
266 split_addr((u32
) reg
, &r1
, &r2
, &page
);
268 mutex_lock(&bus
->mdio_lock
);
270 bus
->write(bus
, 0x18, 0, page
);
271 wait_for_page_switch();
272 ar8xxx_mii_write32(priv
, 0x10 | r2
, r1
, val
);
274 mutex_unlock(&bus
->mdio_lock
);
278 ar8xxx_rmw(struct ar8xxx_priv
*priv
, int reg
, u32 mask
, u32 val
)
280 struct mii_bus
*bus
= priv
->mii_bus
;
284 split_addr((u32
) reg
, &r1
, &r2
, &page
);
286 mutex_lock(&bus
->mdio_lock
);
288 bus
->write(bus
, 0x18, 0, page
);
289 wait_for_page_switch();
291 ret
= ar8xxx_mii_read32(priv
, 0x10 | r2
, r1
);
294 ar8xxx_mii_write32(priv
, 0x10 | r2
, r1
, ret
);
296 mutex_unlock(&bus
->mdio_lock
);
301 ar8xxx_phy_dbg_read(struct ar8xxx_priv
*priv
, int phy_addr
,
302 u16 dbg_addr
, u16
*dbg_data
)
304 struct mii_bus
*bus
= priv
->mii_bus
;
306 mutex_lock(&bus
->mdio_lock
);
307 bus
->write(bus
, phy_addr
, MII_ATH_DBG_ADDR
, dbg_addr
);
308 *dbg_data
= bus
->read(bus
, phy_addr
, MII_ATH_DBG_DATA
);
309 mutex_unlock(&bus
->mdio_lock
);
313 ar8xxx_phy_dbg_write(struct ar8xxx_priv
*priv
, int phy_addr
,
314 u16 dbg_addr
, u16 dbg_data
)
316 struct mii_bus
*bus
= priv
->mii_bus
;
318 mutex_lock(&bus
->mdio_lock
);
319 bus
->write(bus
, phy_addr
, MII_ATH_DBG_ADDR
, dbg_addr
);
320 bus
->write(bus
, phy_addr
, MII_ATH_DBG_DATA
, dbg_data
);
321 mutex_unlock(&bus
->mdio_lock
);
325 ar8xxx_phy_mmd_prep(struct mii_bus
*bus
, int phy_addr
, u16 addr
, u16 reg
)
327 bus
->write(bus
, phy_addr
, MII_ATH_MMD_ADDR
, addr
);
328 bus
->write(bus
, phy_addr
, MII_ATH_MMD_DATA
, reg
);
329 bus
->write(bus
, phy_addr
, MII_ATH_MMD_ADDR
, addr
| 0x4000);
333 ar8xxx_phy_mmd_write(struct ar8xxx_priv
*priv
, int phy_addr
, u16 addr
, u16 reg
, u16 data
)
335 struct mii_bus
*bus
= priv
->mii_bus
;
337 mutex_lock(&bus
->mdio_lock
);
338 ar8xxx_phy_mmd_prep(bus
, phy_addr
, addr
, reg
);
339 bus
->write(bus
, phy_addr
, MII_ATH_MMD_DATA
, data
);
340 mutex_unlock(&bus
->mdio_lock
);
344 ar8xxx_phy_mmd_read(struct ar8xxx_priv
*priv
, int phy_addr
, u16 addr
, u16 reg
)
346 struct mii_bus
*bus
= priv
->mii_bus
;
349 mutex_lock(&bus
->mdio_lock
);
350 ar8xxx_phy_mmd_prep(bus
, phy_addr
, addr
, reg
);
351 data
= bus
->read(bus
, phy_addr
, MII_ATH_MMD_DATA
);
352 mutex_unlock(&bus
->mdio_lock
);
358 ar8xxx_reg_wait(struct ar8xxx_priv
*priv
, u32 reg
, u32 mask
, u32 val
,
363 for (i
= 0; i
< timeout
; i
++) {
366 t
= ar8xxx_read(priv
, reg
);
367 if ((t
& mask
) == val
)
370 usleep_range(1000, 2000);
378 ar8xxx_mib_op(struct ar8xxx_priv
*priv
, u32 op
)
380 unsigned mib_func
= priv
->chip
->mib_func
;
383 lockdep_assert_held(&priv
->mib_lock
);
385 /* Capture the hardware statistics for all ports */
386 ar8xxx_rmw(priv
, mib_func
, AR8216_MIB_FUNC
, (op
<< AR8216_MIB_FUNC_S
));
388 /* Wait for the capturing to complete. */
389 ret
= ar8xxx_reg_wait(priv
, mib_func
, AR8216_MIB_BUSY
, 0, 10);
400 ar8xxx_mib_capture(struct ar8xxx_priv
*priv
)
402 return ar8xxx_mib_op(priv
, AR8216_MIB_FUNC_CAPTURE
);
406 ar8xxx_mib_flush(struct ar8xxx_priv
*priv
)
408 return ar8xxx_mib_op(priv
, AR8216_MIB_FUNC_FLUSH
);
412 ar8xxx_mib_fetch_port_stat(struct ar8xxx_priv
*priv
, int port
, bool flush
)
418 WARN_ON(port
>= priv
->dev
.ports
);
420 lockdep_assert_held(&priv
->mib_lock
);
422 base
= priv
->chip
->reg_port_stats_start
+
423 priv
->chip
->reg_port_stats_length
* port
;
425 mib_stats
= &priv
->mib_stats
[port
* priv
->chip
->num_mibs
];
426 for (i
= 0; i
< priv
->chip
->num_mibs
; i
++) {
427 const struct ar8xxx_mib_desc
*mib
;
430 mib
= &priv
->chip
->mib_decs
[i
];
431 t
= ar8xxx_read(priv
, base
+ mib
->offset
);
432 if (mib
->size
== 2) {
435 hi
= ar8xxx_read(priv
, base
+ mib
->offset
+ 4);
448 ar8216_read_port_link(struct ar8xxx_priv
*priv
, int port
,
449 struct switch_port_link
*link
)
454 memset(link
, '\0', sizeof(*link
));
456 status
= priv
->chip
->read_port_status(priv
, port
);
458 link
->aneg
= !!(status
& AR8216_PORT_STATUS_LINK_AUTO
);
460 link
->link
= !!(status
& AR8216_PORT_STATUS_LINK_UP
);
464 if (priv
->get_port_link
) {
467 err
= priv
->get_port_link(port
);
476 link
->duplex
= !!(status
& AR8216_PORT_STATUS_DUPLEX
);
477 link
->tx_flow
= !!(status
& AR8216_PORT_STATUS_TXFLOW
);
478 link
->rx_flow
= !!(status
& AR8216_PORT_STATUS_RXFLOW
);
480 if (link
->aneg
&& link
->duplex
&& priv
->chip
->read_port_eee_status
)
481 link
->eee
= priv
->chip
->read_port_eee_status(priv
, port
);
483 speed
= (status
& AR8216_PORT_STATUS_SPEED
) >>
484 AR8216_PORT_STATUS_SPEED_S
;
487 case AR8216_PORT_SPEED_10M
:
488 link
->speed
= SWITCH_PORT_SPEED_10
;
490 case AR8216_PORT_SPEED_100M
:
491 link
->speed
= SWITCH_PORT_SPEED_100
;
493 case AR8216_PORT_SPEED_1000M
:
494 link
->speed
= SWITCH_PORT_SPEED_1000
;
497 link
->speed
= SWITCH_PORT_SPEED_UNKNOWN
;
502 static struct sk_buff
*
503 ar8216_mangle_tx(struct net_device
*dev
, struct sk_buff
*skb
)
505 struct ar8xxx_priv
*priv
= dev
->phy_ptr
;
514 if (unlikely(skb_headroom(skb
) < 2)) {
515 if (pskb_expand_head(skb
, 2, 0, GFP_ATOMIC
) < 0)
519 buf
= skb_push(skb
, 2);
527 dev_kfree_skb_any(skb
);
532 ar8216_mangle_rx(struct net_device
*dev
, struct sk_buff
*skb
)
534 struct ar8xxx_priv
*priv
;
542 /* don't strip the header if vlan mode is disabled */
546 /* strip header, get vlan id */
550 /* check for vlan header presence */
551 if ((buf
[12 + 2] != 0x81) || (buf
[13 + 2] != 0x00))
556 /* no need to fix up packets coming from a tagged source */
557 if (priv
->vlan_tagged
& (1 << port
))
560 /* lookup port vid from local table, the switch passes an invalid vlan id */
561 vlan
= priv
->vlan_id
[priv
->pvid
[port
]];
564 buf
[14 + 2] |= vlan
>> 8;
565 buf
[15 + 2] = vlan
& 0xff;
569 ar8216_wait_bit(struct ar8xxx_priv
*priv
, int reg
, u32 mask
, u32 val
)
575 t
= ar8xxx_read(priv
, reg
);
576 if ((t
& mask
) == val
)
586 pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
587 (unsigned int) reg
, t
, mask
, val
);
592 ar8216_vtu_op(struct ar8xxx_priv
*priv
, u32 op
, u32 val
)
594 if (ar8216_wait_bit(priv
, AR8216_REG_VTU
, AR8216_VTU_ACTIVE
, 0))
596 if ((op
& AR8216_VTU_OP
) == AR8216_VTU_OP_LOAD
) {
597 val
&= AR8216_VTUDATA_MEMBER
;
598 val
|= AR8216_VTUDATA_VALID
;
599 ar8xxx_write(priv
, AR8216_REG_VTU_DATA
, val
);
601 op
|= AR8216_VTU_ACTIVE
;
602 ar8xxx_write(priv
, AR8216_REG_VTU
, op
);
606 ar8216_vtu_flush(struct ar8xxx_priv
*priv
)
608 ar8216_vtu_op(priv
, AR8216_VTU_OP_FLUSH
, 0);
612 ar8216_vtu_load_vlan(struct ar8xxx_priv
*priv
, u32 vid
, u32 port_mask
)
616 op
= AR8216_VTU_OP_LOAD
| (vid
<< AR8216_VTU_VID_S
);
617 ar8216_vtu_op(priv
, op
, port_mask
);
621 ar8216_atu_flush(struct ar8xxx_priv
*priv
)
625 ret
= ar8216_wait_bit(priv
, AR8216_REG_ATU_FUNC0
, AR8216_ATU_ACTIVE
, 0);
627 ar8xxx_write(priv
, AR8216_REG_ATU_FUNC0
, AR8216_ATU_OP_FLUSH
|
634 ar8216_atu_flush_port(struct ar8xxx_priv
*priv
, int port
)
639 ret
= ar8216_wait_bit(priv
, AR8216_REG_ATU_FUNC0
, AR8216_ATU_ACTIVE
, 0);
641 t
= (port
<< AR8216_ATU_PORT_NUM_S
) | AR8216_ATU_OP_FLUSH_PORT
;
642 t
|= AR8216_ATU_ACTIVE
;
643 ar8xxx_write(priv
, AR8216_REG_ATU_FUNC0
, t
);
650 ar8216_read_port_status(struct ar8xxx_priv
*priv
, int port
)
652 return ar8xxx_read(priv
, AR8216_REG_PORT_STATUS(port
));
656 ar8216_setup_port(struct ar8xxx_priv
*priv
, int port
, u32 members
)
663 pvid
= priv
->vlan_id
[priv
->pvid
[port
]];
664 if (priv
->vlan_tagged
& (1 << port
))
665 egress
= AR8216_OUT_ADD_VLAN
;
667 egress
= AR8216_OUT_STRIP_VLAN
;
668 ingress
= AR8216_IN_SECURE
;
671 egress
= AR8216_OUT_KEEP
;
672 ingress
= AR8216_IN_PORT_ONLY
;
675 if (chip_is_ar8216(priv
) && priv
->vlan
&& port
== AR8216_PORT_CPU
)
676 header
= AR8216_PORT_CTRL_HEADER
;
680 ar8xxx_rmw(priv
, AR8216_REG_PORT_CTRL(port
),
681 AR8216_PORT_CTRL_LEARN
| AR8216_PORT_CTRL_VLAN_MODE
|
682 AR8216_PORT_CTRL_SINGLE_VLAN
| AR8216_PORT_CTRL_STATE
|
683 AR8216_PORT_CTRL_HEADER
| AR8216_PORT_CTRL_LEARN_LOCK
,
684 AR8216_PORT_CTRL_LEARN
| header
|
685 (egress
<< AR8216_PORT_CTRL_VLAN_MODE_S
) |
686 (AR8216_PORT_STATE_FORWARD
<< AR8216_PORT_CTRL_STATE_S
));
688 ar8xxx_rmw(priv
, AR8216_REG_PORT_VLAN(port
),
689 AR8216_PORT_VLAN_DEST_PORTS
| AR8216_PORT_VLAN_MODE
|
690 AR8216_PORT_VLAN_DEFAULT_ID
,
691 (members
<< AR8216_PORT_VLAN_DEST_PORTS_S
) |
692 (ingress
<< AR8216_PORT_VLAN_MODE_S
) |
693 (pvid
<< AR8216_PORT_VLAN_DEFAULT_ID_S
));
697 ar8216_hw_init(struct ar8xxx_priv
*priv
)
699 if (priv
->initialized
)
702 ar8xxx_phy_init(priv
);
704 priv
->initialized
= true;
709 ar8216_init_globals(struct ar8xxx_priv
*priv
)
711 /* standard atheros magic */
712 ar8xxx_write(priv
, 0x38, 0xc000050e);
714 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
715 AR8216_GCTRL_MTU
, 1518 + 8 + 2);
719 __ar8216_init_port(struct ar8xxx_priv
*priv
, int port
,
720 bool cpu_ge
, bool flow_en
)
722 /* Enable port learning and tx */
723 ar8xxx_write(priv
, AR8216_REG_PORT_CTRL(port
),
724 AR8216_PORT_CTRL_LEARN
|
725 (4 << AR8216_PORT_CTRL_STATE_S
));
727 ar8xxx_write(priv
, AR8216_REG_PORT_VLAN(port
), 0);
729 if (port
== AR8216_PORT_CPU
) {
730 ar8xxx_write(priv
, AR8216_REG_PORT_STATUS(port
),
731 AR8216_PORT_STATUS_LINK_UP
|
732 (cpu_ge
? AR8216_PORT_SPEED_1000M
: AR8216_PORT_SPEED_100M
) |
733 AR8216_PORT_STATUS_TXMAC
|
734 AR8216_PORT_STATUS_RXMAC
|
735 (flow_en
? AR8216_PORT_STATUS_RXFLOW
: 0) |
736 (flow_en
? AR8216_PORT_STATUS_TXFLOW
: 0) |
737 AR8216_PORT_STATUS_DUPLEX
);
739 ar8xxx_write(priv
, AR8216_REG_PORT_STATUS(port
),
740 AR8216_PORT_STATUS_LINK_AUTO
);
745 ar8216_init_port(struct ar8xxx_priv
*priv
, int port
)
747 __ar8216_init_port(priv
, port
, ar8xxx_has_gige(priv
),
748 chip_is_ar8316(priv
));
752 ar8216_wait_atu_ready(struct ar8xxx_priv
*priv
, u16 r2
, u16 r1
)
756 while (ar8xxx_mii_read32(priv
, r2
, r1
) & AR8216_ATU_ACTIVE
&& --timeout
) {
762 pr_err("ar8216: timeout waiting for atu to become ready\n");
765 static void ar8216_get_arl_entry(struct ar8xxx_priv
*priv
,
766 struct arl_entry
*a
, u32
*status
, enum arl_op op
)
768 struct mii_bus
*bus
= priv
->mii_bus
;
770 u16 r1_func0
, r1_func1
, r1_func2
;
771 u32 t
, val0
, val1
, val2
;
773 split_addr(AR8216_REG_ATU_FUNC0
, &r1_func0
, &r2
, &page
);
776 r1_func1
= (AR8216_REG_ATU_FUNC1
>> 1) & 0x1e;
777 r1_func2
= (AR8216_REG_ATU_FUNC2
>> 1) & 0x1e;
780 case AR8XXX_ARL_INITIALIZE
:
781 /* all ATU registers are on the same page
782 * therefore set page only once
784 bus
->write(bus
, 0x18, 0, page
);
785 wait_for_page_switch();
787 ar8216_wait_atu_ready(priv
, r2
, r1_func0
);
789 ar8xxx_mii_write32(priv
, r2
, r1_func0
, AR8216_ATU_OP_GET_NEXT
);
790 ar8xxx_mii_write32(priv
, r2
, r1_func1
, 0);
791 ar8xxx_mii_write32(priv
, r2
, r1_func2
, 0);
793 case AR8XXX_ARL_GET_NEXT
:
794 t
= ar8xxx_mii_read32(priv
, r2
, r1_func0
);
795 t
|= AR8216_ATU_ACTIVE
;
796 ar8xxx_mii_write32(priv
, r2
, r1_func0
, t
);
797 ar8216_wait_atu_ready(priv
, r2
, r1_func0
);
799 val0
= ar8xxx_mii_read32(priv
, r2
, r1_func0
);
800 val1
= ar8xxx_mii_read32(priv
, r2
, r1_func1
);
801 val2
= ar8xxx_mii_read32(priv
, r2
, r1_func2
);
803 *status
= (val2
& AR8216_ATU_STATUS
) >> AR8216_ATU_STATUS_S
;
807 a
->portmap
= (val2
& AR8216_ATU_PORTS
) >> AR8216_ATU_PORTS_S
;
808 a
->mac
[0] = (val0
& AR8216_ATU_ADDR5
) >> AR8216_ATU_ADDR5_S
;
809 a
->mac
[1] = (val0
& AR8216_ATU_ADDR4
) >> AR8216_ATU_ADDR4_S
;
810 a
->mac
[2] = (val1
& AR8216_ATU_ADDR3
) >> AR8216_ATU_ADDR3_S
;
811 a
->mac
[3] = (val1
& AR8216_ATU_ADDR2
) >> AR8216_ATU_ADDR2_S
;
812 a
->mac
[4] = (val1
& AR8216_ATU_ADDR1
) >> AR8216_ATU_ADDR1_S
;
813 a
->mac
[5] = (val1
& AR8216_ATU_ADDR0
) >> AR8216_ATU_ADDR0_S
;
819 ar8229_hw_init(struct ar8xxx_priv
*priv
)
823 if (priv
->initialized
)
826 ar8xxx_write(priv
, AR8216_REG_CTRL
, AR8216_CTRL_RESET
);
827 ar8xxx_reg_wait(priv
, AR8216_REG_CTRL
, AR8216_CTRL_RESET
, 0, 1000);
829 phy_if_mode
= of_get_phy_mode(priv
->pdev
->of_node
);
831 if (phy_if_mode
== PHY_INTERFACE_MODE_GMII
) {
832 ar8xxx_write(priv
, AR8229_REG_OPER_MODE0
,
833 AR8229_OPER_MODE0_MAC_GMII_EN
);
834 } else if (phy_if_mode
== PHY_INTERFACE_MODE_MII
) {
835 ar8xxx_write(priv
, AR8229_REG_OPER_MODE0
,
836 AR8229_OPER_MODE0_PHY_MII_EN
);
838 pr_err("ar8229: unsupported mii mode\n");
843 ar8xxx_write(priv
, AR8229_REG_OPER_MODE1
,
844 AR8229_REG_OPER_MODE1_PHY4_MII_EN
);
846 ar8xxx_phy_init(priv
);
848 priv
->initialized
= true;
853 ar8229_init_globals(struct ar8xxx_priv
*priv
)
856 /* Enable CPU port, and disable mirror port */
857 ar8xxx_write(priv
, AR8216_REG_GLOBAL_CPUPORT
,
858 AR8216_GLOBAL_CPUPORT_EN
|
859 (15 << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S
));
861 /* Setup TAG priority mapping */
862 ar8xxx_write(priv
, AR8216_REG_TAG_PRIORITY
, 0xfa50);
864 /* Enable aging, MAC replacing */
865 ar8xxx_write(priv
, AR8216_REG_ATU_CTRL
,
866 0x2b /* 5 min age time */ |
867 AR8216_ATU_CTRL_AGE_EN
|
868 AR8216_ATU_CTRL_LEARN_CHANGE
);
870 /* Enable ARP frame acknowledge */
871 ar8xxx_reg_set(priv
, AR8229_REG_QM_CTRL
,
872 AR8229_QM_CTRL_ARP_EN
);
874 /* Enable Broadcast/Multicast frames transmitted to the CPU */
875 ar8xxx_reg_set(priv
, AR8216_REG_FLOOD_MASK
,
876 AR8229_FLOOD_MASK_BC_DP(0) |
877 AR8229_FLOOD_MASK_MC_DP(0));
880 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
881 AR8236_GCTRL_MTU
, AR8236_GCTRL_MTU
);
883 /* Enable MIB counters */
884 ar8xxx_reg_set(priv
, AR8216_REG_MIB_FUNC
,
887 /* setup Service TAG */
888 ar8xxx_rmw(priv
, AR8216_REG_SERVICE_TAG
, AR8216_SERVICE_TAG_M
, 0);
892 ar8229_init_port(struct ar8xxx_priv
*priv
, int port
)
894 __ar8216_init_port(priv
, port
, true, true);
898 ar8236_setup_port(struct ar8xxx_priv
*priv
, int port
, u32 members
)
904 pvid
= priv
->vlan_id
[priv
->pvid
[port
]];
905 if (priv
->vlan_tagged
& (1 << port
))
906 egress
= AR8216_OUT_ADD_VLAN
;
908 egress
= AR8216_OUT_STRIP_VLAN
;
909 ingress
= AR8216_IN_SECURE
;
912 egress
= AR8216_OUT_KEEP
;
913 ingress
= AR8216_IN_PORT_ONLY
;
916 ar8xxx_rmw(priv
, AR8216_REG_PORT_CTRL(port
),
917 AR8216_PORT_CTRL_LEARN
| AR8216_PORT_CTRL_VLAN_MODE
|
918 AR8216_PORT_CTRL_SINGLE_VLAN
| AR8216_PORT_CTRL_STATE
|
919 AR8216_PORT_CTRL_HEADER
| AR8216_PORT_CTRL_LEARN_LOCK
,
920 AR8216_PORT_CTRL_LEARN
|
921 (egress
<< AR8216_PORT_CTRL_VLAN_MODE_S
) |
922 (AR8216_PORT_STATE_FORWARD
<< AR8216_PORT_CTRL_STATE_S
));
924 ar8xxx_rmw(priv
, AR8236_REG_PORT_VLAN(port
),
925 AR8236_PORT_VLAN_DEFAULT_ID
,
926 (pvid
<< AR8236_PORT_VLAN_DEFAULT_ID_S
));
928 ar8xxx_rmw(priv
, AR8236_REG_PORT_VLAN2(port
),
929 AR8236_PORT_VLAN2_VLAN_MODE
|
930 AR8236_PORT_VLAN2_MEMBER
,
931 (ingress
<< AR8236_PORT_VLAN2_VLAN_MODE_S
) |
932 (members
<< AR8236_PORT_VLAN2_MEMBER_S
));
936 ar8236_init_globals(struct ar8xxx_priv
*priv
)
938 /* enable jumbo frames */
939 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
940 AR8316_GCTRL_MTU
, 9018 + 8 + 2);
942 /* enable cpu port to receive arp frames */
943 ar8xxx_reg_set(priv
, AR8216_REG_ATU_CTRL
,
944 AR8236_ATU_CTRL_RES
);
946 /* enable cpu port to receive multicast and broadcast frames */
947 ar8xxx_reg_set(priv
, AR8216_REG_FLOOD_MASK
,
948 AR8236_FM_CPU_BROADCAST_EN
| AR8236_FM_CPU_BCAST_FWD_EN
);
950 /* Enable MIB counters */
951 ar8xxx_rmw(priv
, AR8216_REG_MIB_FUNC
, AR8216_MIB_FUNC
| AR8236_MIB_EN
,
952 (AR8216_MIB_FUNC_NO_OP
<< AR8216_MIB_FUNC_S
) |
957 ar8316_hw_init(struct ar8xxx_priv
*priv
)
961 val
= ar8xxx_read(priv
, AR8316_REG_POSTRIP
);
963 if (priv
->phy
->interface
== PHY_INTERFACE_MODE_RGMII
) {
964 if (priv
->port4_phy
) {
965 /* value taken from Ubiquiti RouterStation Pro */
967 pr_info("ar8316: Using port 4 as PHY\n");
970 pr_info("ar8316: Using port 4 as switch port\n");
972 } else if (priv
->phy
->interface
== PHY_INTERFACE_MODE_GMII
) {
973 /* value taken from AVM Fritz!Box 7390 sources */
976 /* no known value for phy interface */
977 pr_err("ar8316: unsupported mii mode: %d.\n",
978 priv
->phy
->interface
);
985 ar8xxx_write(priv
, AR8316_REG_POSTRIP
, newval
);
987 if (priv
->port4_phy
&&
988 priv
->phy
->interface
== PHY_INTERFACE_MODE_RGMII
) {
989 /* work around for phy4 rgmii mode */
990 ar8xxx_phy_dbg_write(priv
, 4, 0x12, 0x480c);
992 ar8xxx_phy_dbg_write(priv
, 4, 0x0, 0x824e);
994 ar8xxx_phy_dbg_write(priv
, 4, 0x5, 0x3d47);
998 ar8xxx_phy_init(priv
);
1001 priv
->initialized
= true;
1006 ar8316_init_globals(struct ar8xxx_priv
*priv
)
1008 /* standard atheros magic */
1009 ar8xxx_write(priv
, 0x38, 0xc000050e);
1011 /* enable cpu port to receive multicast and broadcast frames */
1012 ar8xxx_write(priv
, AR8216_REG_FLOOD_MASK
, 0x003f003f);
1014 /* enable jumbo frames */
1015 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
1016 AR8316_GCTRL_MTU
, 9018 + 8 + 2);
1018 /* Enable MIB counters */
1019 ar8xxx_rmw(priv
, AR8216_REG_MIB_FUNC
, AR8216_MIB_FUNC
| AR8236_MIB_EN
,
1020 (AR8216_MIB_FUNC_NO_OP
<< AR8216_MIB_FUNC_S
) |
1025 ar8xxx_sw_set_vlan(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1026 struct switch_val
*val
)
1028 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1029 priv
->vlan
= !!val
->value
.i
;
1034 ar8xxx_sw_get_vlan(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1035 struct switch_val
*val
)
1037 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1038 val
->value
.i
= priv
->vlan
;
1044 ar8xxx_sw_set_pvid(struct switch_dev
*dev
, int port
, int vlan
)
1046 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1048 /* make sure no invalid PVIDs get set */
1050 if (vlan
< 0 || vlan
>= dev
->vlans
||
1051 port
< 0 || port
>= AR8X16_MAX_PORTS
)
1054 priv
->pvid
[port
] = vlan
;
1059 ar8xxx_sw_get_pvid(struct switch_dev
*dev
, int port
, int *vlan
)
1061 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1063 if (port
< 0 || port
>= AR8X16_MAX_PORTS
)
1066 *vlan
= priv
->pvid
[port
];
1071 ar8xxx_sw_set_vid(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1072 struct switch_val
*val
)
1074 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1076 if (val
->port_vlan
>= AR8X16_MAX_VLANS
)
1079 priv
->vlan_id
[val
->port_vlan
] = val
->value
.i
;
1084 ar8xxx_sw_get_vid(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1085 struct switch_val
*val
)
1087 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1088 val
->value
.i
= priv
->vlan_id
[val
->port_vlan
];
1093 ar8xxx_sw_get_port_link(struct switch_dev
*dev
, int port
,
1094 struct switch_port_link
*link
)
1096 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1098 ar8216_read_port_link(priv
, port
, link
);
1103 ar8xxx_sw_get_ports(struct switch_dev
*dev
, struct switch_val
*val
)
1105 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1109 if (val
->port_vlan
>= AR8X16_MAX_VLANS
)
1112 ports
= priv
->vlan_table
[val
->port_vlan
];
1114 for (i
= 0; i
< dev
->ports
; i
++) {
1115 struct switch_port
*p
;
1117 if (!(ports
& (1 << i
)))
1120 p
= &val
->value
.ports
[val
->len
++];
1122 if (priv
->vlan_tagged
& (1 << i
))
1123 p
->flags
= (1 << SWITCH_PORT_FLAG_TAGGED
);
1131 ar8xxx_sw_set_ports(struct switch_dev
*dev
, struct switch_val
*val
)
1133 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1134 u8
*vt
= &priv
->vlan_table
[val
->port_vlan
];
1138 for (i
= 0; i
< val
->len
; i
++) {
1139 struct switch_port
*p
= &val
->value
.ports
[i
];
1141 if (p
->flags
& (1 << SWITCH_PORT_FLAG_TAGGED
)) {
1142 priv
->vlan_tagged
|= (1 << p
->id
);
1144 priv
->vlan_tagged
&= ~(1 << p
->id
);
1145 priv
->pvid
[p
->id
] = val
->port_vlan
;
1147 /* make sure that an untagged port does not
1148 * appear in other vlans */
1149 for (j
= 0; j
< AR8X16_MAX_VLANS
; j
++) {
1150 if (j
== val
->port_vlan
)
1152 priv
->vlan_table
[j
] &= ~(1 << p
->id
);
1162 ar8216_set_mirror_regs(struct ar8xxx_priv
*priv
)
1166 /* reset all mirror registers */
1167 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CPUPORT
,
1168 AR8216_GLOBAL_CPUPORT_MIRROR_PORT
,
1169 (0xF << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S
));
1170 for (port
= 0; port
< AR8216_NUM_PORTS
; port
++) {
1171 ar8xxx_reg_clear(priv
, AR8216_REG_PORT_CTRL(port
),
1172 AR8216_PORT_CTRL_MIRROR_RX
);
1174 ar8xxx_reg_clear(priv
, AR8216_REG_PORT_CTRL(port
),
1175 AR8216_PORT_CTRL_MIRROR_TX
);
1178 /* now enable mirroring if necessary */
1179 if (priv
->source_port
>= AR8216_NUM_PORTS
||
1180 priv
->monitor_port
>= AR8216_NUM_PORTS
||
1181 priv
->source_port
== priv
->monitor_port
) {
1185 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CPUPORT
,
1186 AR8216_GLOBAL_CPUPORT_MIRROR_PORT
,
1187 (priv
->monitor_port
<< AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S
));
1189 if (priv
->mirror_rx
)
1190 ar8xxx_reg_set(priv
, AR8216_REG_PORT_CTRL(priv
->source_port
),
1191 AR8216_PORT_CTRL_MIRROR_RX
);
1193 if (priv
->mirror_tx
)
1194 ar8xxx_reg_set(priv
, AR8216_REG_PORT_CTRL(priv
->source_port
),
1195 AR8216_PORT_CTRL_MIRROR_TX
);
1199 ar8xxx_age_time_val(int age_time
)
1201 return (age_time
+ AR8XXX_REG_ARL_CTRL_AGE_TIME_SECS
/ 2) /
1202 AR8XXX_REG_ARL_CTRL_AGE_TIME_SECS
;
1206 ar8xxx_set_age_time(struct ar8xxx_priv
*priv
, int reg
)
1208 u32 age_time
= ar8xxx_age_time_val(priv
->arl_age_time
);
1209 ar8xxx_rmw(priv
, reg
, AR8216_ATU_CTRL_AGE_TIME
, age_time
<< AR8216_ATU_CTRL_AGE_TIME_S
);
1213 ar8xxx_sw_hw_apply(struct switch_dev
*dev
)
1215 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1216 const struct ar8xxx_chip
*chip
= priv
->chip
;
1217 u8 portmask
[AR8X16_MAX_PORTS
];
1220 mutex_lock(&priv
->reg_mutex
);
1221 /* flush all vlan translation unit entries */
1222 priv
->chip
->vtu_flush(priv
);
1224 memset(portmask
, 0, sizeof(portmask
));
1226 /* calculate the port destination masks and load vlans
1227 * into the vlan translation unit */
1228 for (j
= 0; j
< AR8X16_MAX_VLANS
; j
++) {
1229 u8 vp
= priv
->vlan_table
[j
];
1234 for (i
= 0; i
< dev
->ports
; i
++) {
1237 portmask
[i
] |= vp
& ~mask
;
1240 chip
->vtu_load_vlan(priv
, priv
->vlan_id
[j
],
1241 priv
->vlan_table
[j
]);
1245 * isolate all ports, but connect them to the cpu port */
1246 for (i
= 0; i
< dev
->ports
; i
++) {
1247 if (i
== AR8216_PORT_CPU
)
1250 portmask
[i
] = 1 << AR8216_PORT_CPU
;
1251 portmask
[AR8216_PORT_CPU
] |= (1 << i
);
1255 /* update the port destination mask registers and tag settings */
1256 for (i
= 0; i
< dev
->ports
; i
++) {
1257 chip
->setup_port(priv
, i
, portmask
[i
]);
1260 chip
->set_mirror_regs(priv
);
1263 if (chip
->reg_arl_ctrl
)
1264 ar8xxx_set_age_time(priv
, chip
->reg_arl_ctrl
);
1266 mutex_unlock(&priv
->reg_mutex
);
1271 ar8xxx_sw_reset_switch(struct switch_dev
*dev
)
1273 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1274 const struct ar8xxx_chip
*chip
= priv
->chip
;
1277 mutex_lock(&priv
->reg_mutex
);
1278 memset(&priv
->vlan
, 0, sizeof(struct ar8xxx_priv
) -
1279 offsetof(struct ar8xxx_priv
, vlan
));
1281 for (i
= 0; i
< AR8X16_MAX_VLANS
; i
++)
1282 priv
->vlan_id
[i
] = i
;
1284 /* Configure all ports */
1285 for (i
= 0; i
< dev
->ports
; i
++)
1286 chip
->init_port(priv
, i
);
1288 priv
->mirror_rx
= false;
1289 priv
->mirror_tx
= false;
1290 priv
->source_port
= 0;
1291 priv
->monitor_port
= 0;
1292 priv
->arl_age_time
= AR8XXX_DEFAULT_ARL_AGE_TIME
;
1294 chip
->init_globals(priv
);
1295 chip
->atu_flush(priv
);
1297 mutex_unlock(&priv
->reg_mutex
);
1299 return chip
->sw_hw_apply(dev
);
1303 ar8xxx_sw_set_reset_mibs(struct switch_dev
*dev
,
1304 const struct switch_attr
*attr
,
1305 struct switch_val
*val
)
1307 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1311 if (!ar8xxx_has_mib_counters(priv
))
1314 mutex_lock(&priv
->mib_lock
);
1316 len
= priv
->dev
.ports
* priv
->chip
->num_mibs
*
1317 sizeof(*priv
->mib_stats
);
1318 memset(priv
->mib_stats
, '\0', len
);
1319 ret
= ar8xxx_mib_flush(priv
);
1326 mutex_unlock(&priv
->mib_lock
);
1331 ar8xxx_sw_set_mirror_rx_enable(struct switch_dev
*dev
,
1332 const struct switch_attr
*attr
,
1333 struct switch_val
*val
)
1335 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1337 mutex_lock(&priv
->reg_mutex
);
1338 priv
->mirror_rx
= !!val
->value
.i
;
1339 priv
->chip
->set_mirror_regs(priv
);
1340 mutex_unlock(&priv
->reg_mutex
);
1346 ar8xxx_sw_get_mirror_rx_enable(struct switch_dev
*dev
,
1347 const struct switch_attr
*attr
,
1348 struct switch_val
*val
)
1350 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1351 val
->value
.i
= priv
->mirror_rx
;
1356 ar8xxx_sw_set_mirror_tx_enable(struct switch_dev
*dev
,
1357 const struct switch_attr
*attr
,
1358 struct switch_val
*val
)
1360 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1362 mutex_lock(&priv
->reg_mutex
);
1363 priv
->mirror_tx
= !!val
->value
.i
;
1364 priv
->chip
->set_mirror_regs(priv
);
1365 mutex_unlock(&priv
->reg_mutex
);
1371 ar8xxx_sw_get_mirror_tx_enable(struct switch_dev
*dev
,
1372 const struct switch_attr
*attr
,
1373 struct switch_val
*val
)
1375 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1376 val
->value
.i
= priv
->mirror_tx
;
1381 ar8xxx_sw_set_mirror_monitor_port(struct switch_dev
*dev
,
1382 const struct switch_attr
*attr
,
1383 struct switch_val
*val
)
1385 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1387 mutex_lock(&priv
->reg_mutex
);
1388 priv
->monitor_port
= val
->value
.i
;
1389 priv
->chip
->set_mirror_regs(priv
);
1390 mutex_unlock(&priv
->reg_mutex
);
1396 ar8xxx_sw_get_mirror_monitor_port(struct switch_dev
*dev
,
1397 const struct switch_attr
*attr
,
1398 struct switch_val
*val
)
1400 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1401 val
->value
.i
= priv
->monitor_port
;
1406 ar8xxx_sw_set_mirror_source_port(struct switch_dev
*dev
,
1407 const struct switch_attr
*attr
,
1408 struct switch_val
*val
)
1410 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1412 mutex_lock(&priv
->reg_mutex
);
1413 priv
->source_port
= val
->value
.i
;
1414 priv
->chip
->set_mirror_regs(priv
);
1415 mutex_unlock(&priv
->reg_mutex
);
1421 ar8xxx_sw_get_mirror_source_port(struct switch_dev
*dev
,
1422 const struct switch_attr
*attr
,
1423 struct switch_val
*val
)
1425 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1426 val
->value
.i
= priv
->source_port
;
1431 ar8xxx_sw_set_port_reset_mib(struct switch_dev
*dev
,
1432 const struct switch_attr
*attr
,
1433 struct switch_val
*val
)
1435 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1439 if (!ar8xxx_has_mib_counters(priv
))
1442 port
= val
->port_vlan
;
1443 if (port
>= dev
->ports
)
1446 mutex_lock(&priv
->mib_lock
);
1447 ret
= ar8xxx_mib_capture(priv
);
1451 ar8xxx_mib_fetch_port_stat(priv
, port
, true);
1456 mutex_unlock(&priv
->mib_lock
);
1461 ar8xxx_byte_to_str(char *buf
, int len
, u64 byte
)
1466 if (byte
>= 0x40000000) { /* 1 GiB */
1467 b
= byte
* 10 / 0x40000000;
1469 } else if (byte
>= 0x100000) { /* 1 MiB */
1470 b
= byte
* 10 / 0x100000;
1472 } else if (byte
>= 0x400) { /* 1 KiB */
1473 b
= byte
* 10 / 0x400;
1479 if (strcmp(unit
, "Byte"))
1480 snprintf(buf
, len
, "%lu.%lu %s", b
/ 10, b
% 10, unit
);
1482 snprintf(buf
, len
, "%lu %s", b
, unit
);
1486 ar8xxx_sw_get_port_mib(struct switch_dev
*dev
,
1487 const struct switch_attr
*attr
,
1488 struct switch_val
*val
)
1490 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1491 const struct ar8xxx_chip
*chip
= priv
->chip
;
1492 u64
*mib_stats
, mib_data
;
1495 char *buf
= priv
->buf
;
1497 const char *mib_name
;
1499 bool mib_stats_empty
= true;
1501 if (!ar8xxx_has_mib_counters(priv
))
1504 port
= val
->port_vlan
;
1505 if (port
>= dev
->ports
)
1508 mutex_lock(&priv
->mib_lock
);
1509 ret
= ar8xxx_mib_capture(priv
);
1513 ar8xxx_mib_fetch_port_stat(priv
, port
, false);
1515 len
+= snprintf(buf
+ len
, sizeof(priv
->buf
) - len
,
1518 mib_stats
= &priv
->mib_stats
[port
* chip
->num_mibs
];
1519 for (i
= 0; i
< chip
->num_mibs
; i
++) {
1520 mib_name
= chip
->mib_decs
[i
].name
;
1521 mib_data
= mib_stats
[i
];
1522 len
+= snprintf(buf
+ len
, sizeof(priv
->buf
) - len
,
1523 "%-12s: %llu\n", mib_name
, mib_data
);
1524 if ((!strcmp(mib_name
, "TxByte") ||
1525 !strcmp(mib_name
, "RxGoodByte")) &&
1527 ar8xxx_byte_to_str(buf1
, sizeof(buf1
), mib_data
);
1528 --len
; /* discard newline at the end of buf */
1529 len
+= snprintf(buf
+ len
, sizeof(priv
->buf
) - len
,
1532 if (mib_stats_empty
&& mib_data
)
1533 mib_stats_empty
= false;
1536 if (mib_stats_empty
)
1537 len
= snprintf(buf
, sizeof(priv
->buf
), "No MIB data");
1545 mutex_unlock(&priv
->mib_lock
);
1550 ar8xxx_sw_set_arl_age_time(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1551 struct switch_val
*val
)
1553 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1554 int age_time
= val
->value
.i
;
1560 age_time_val
= ar8xxx_age_time_val(age_time
);
1561 if (age_time_val
== 0 || age_time_val
> 0xffff)
1564 priv
->arl_age_time
= age_time
;
1569 ar8xxx_sw_get_arl_age_time(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1570 struct switch_val
*val
)
1572 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1573 val
->value
.i
= priv
->arl_age_time
;
1578 ar8xxx_sw_get_arl_table(struct switch_dev
*dev
,
1579 const struct switch_attr
*attr
,
1580 struct switch_val
*val
)
1582 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1583 struct mii_bus
*bus
= priv
->mii_bus
;
1584 const struct ar8xxx_chip
*chip
= priv
->chip
;
1585 char *buf
= priv
->arl_buf
;
1586 int i
, j
, k
, len
= 0;
1587 struct arl_entry
*a
, *a1
;
1590 if (!chip
->get_arl_entry
)
1593 mutex_lock(&priv
->reg_mutex
);
1594 mutex_lock(&bus
->mdio_lock
);
1596 chip
->get_arl_entry(priv
, NULL
, NULL
, AR8XXX_ARL_INITIALIZE
);
1598 for(i
= 0; i
< AR8XXX_NUM_ARL_RECORDS
; ++i
) {
1599 a
= &priv
->arl_table
[i
];
1601 chip
->get_arl_entry(priv
, a
, &status
, AR8XXX_ARL_GET_NEXT
);
1607 * ARL table can include multiple valid entries
1608 * per MAC, just with differing status codes
1610 for (j
= 0; j
< i
; ++j
) {
1611 a1
= &priv
->arl_table
[j
];
1612 if (!memcmp(a
->mac
, a1
->mac
, sizeof(a
->mac
))) {
1613 /* ignore ports already seen in former entry */
1614 a
->portmap
&= ~a1
->portmap
;
1621 mutex_unlock(&bus
->mdio_lock
);
1623 len
+= snprintf(buf
+ len
, sizeof(priv
->arl_buf
) - len
,
1624 "address resolution table\n");
1626 if (i
== AR8XXX_NUM_ARL_RECORDS
)
1627 len
+= snprintf(buf
+ len
, sizeof(priv
->arl_buf
) - len
,
1628 "Too many entries found, displaying the first %d only!\n",
1629 AR8XXX_NUM_ARL_RECORDS
);
1631 for (j
= 0; j
< priv
->dev
.ports
; ++j
) {
1632 for (k
= 0; k
< i
; ++k
) {
1633 a
= &priv
->arl_table
[k
];
1634 if (!(a
->portmap
& BIT(j
)))
1636 len
+= snprintf(buf
+ len
, sizeof(priv
->arl_buf
) - len
,
1637 "Port %d: MAC %02x:%02x:%02x:%02x:%02x:%02x\n",
1639 a
->mac
[5], a
->mac
[4], a
->mac
[3],
1640 a
->mac
[2], a
->mac
[1], a
->mac
[0]);
1647 mutex_unlock(&priv
->reg_mutex
);
1653 ar8xxx_sw_set_flush_arl_table(struct switch_dev
*dev
,
1654 const struct switch_attr
*attr
,
1655 struct switch_val
*val
)
1657 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1660 mutex_lock(&priv
->reg_mutex
);
1661 ret
= priv
->chip
->atu_flush(priv
);
1662 mutex_unlock(&priv
->reg_mutex
);
1668 ar8xxx_sw_set_flush_port_arl_table(struct switch_dev
*dev
,
1669 const struct switch_attr
*attr
,
1670 struct switch_val
*val
)
1672 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1675 port
= val
->port_vlan
;
1676 if (port
>= dev
->ports
)
1679 mutex_lock(&priv
->reg_mutex
);
1680 ret
= priv
->chip
->atu_flush_port(priv
, port
);
1681 mutex_unlock(&priv
->reg_mutex
);
1687 ar8xxx_phy_read(struct mii_bus
*bus
, int phy_addr
, int reg_addr
)
1689 struct ar8xxx_priv
*priv
= bus
->priv
;
1690 return priv
->chip
->phy_read(priv
, phy_addr
, reg_addr
);
1694 ar8xxx_phy_write(struct mii_bus
*bus
, int phy_addr
, int reg_addr
,
1697 struct ar8xxx_priv
*priv
= bus
->priv
;
1698 return priv
->chip
->phy_write(priv
, phy_addr
, reg_addr
, reg_val
);
1701 static const struct switch_attr ar8xxx_sw_attr_globals
[] = {
1703 .type
= SWITCH_TYPE_INT
,
1704 .name
= "enable_vlan",
1705 .description
= "Enable VLAN mode",
1706 .set
= ar8xxx_sw_set_vlan
,
1707 .get
= ar8xxx_sw_get_vlan
,
1711 .type
= SWITCH_TYPE_NOVAL
,
1712 .name
= "reset_mibs",
1713 .description
= "Reset all MIB counters",
1714 .set
= ar8xxx_sw_set_reset_mibs
,
1717 .type
= SWITCH_TYPE_INT
,
1718 .name
= "enable_mirror_rx",
1719 .description
= "Enable mirroring of RX packets",
1720 .set
= ar8xxx_sw_set_mirror_rx_enable
,
1721 .get
= ar8xxx_sw_get_mirror_rx_enable
,
1725 .type
= SWITCH_TYPE_INT
,
1726 .name
= "enable_mirror_tx",
1727 .description
= "Enable mirroring of TX packets",
1728 .set
= ar8xxx_sw_set_mirror_tx_enable
,
1729 .get
= ar8xxx_sw_get_mirror_tx_enable
,
1733 .type
= SWITCH_TYPE_INT
,
1734 .name
= "mirror_monitor_port",
1735 .description
= "Mirror monitor port",
1736 .set
= ar8xxx_sw_set_mirror_monitor_port
,
1737 .get
= ar8xxx_sw_get_mirror_monitor_port
,
1738 .max
= AR8216_NUM_PORTS
- 1
1741 .type
= SWITCH_TYPE_INT
,
1742 .name
= "mirror_source_port",
1743 .description
= "Mirror source port",
1744 .set
= ar8xxx_sw_set_mirror_source_port
,
1745 .get
= ar8xxx_sw_get_mirror_source_port
,
1746 .max
= AR8216_NUM_PORTS
- 1
1749 .type
= SWITCH_TYPE_STRING
,
1750 .name
= "arl_table",
1751 .description
= "Get ARL table",
1753 .get
= ar8xxx_sw_get_arl_table
,
1756 .type
= SWITCH_TYPE_NOVAL
,
1757 .name
= "flush_arl_table",
1758 .description
= "Flush ARL table",
1759 .set
= ar8xxx_sw_set_flush_arl_table
,
1763 const struct switch_attr ar8xxx_sw_attr_port
[] = {
1765 .type
= SWITCH_TYPE_NOVAL
,
1766 .name
= "reset_mib",
1767 .description
= "Reset single port MIB counters",
1768 .set
= ar8xxx_sw_set_port_reset_mib
,
1771 .type
= SWITCH_TYPE_STRING
,
1773 .description
= "Get port's MIB counters",
1775 .get
= ar8xxx_sw_get_port_mib
,
1778 .type
= SWITCH_TYPE_NOVAL
,
1779 .name
= "flush_arl_table",
1780 .description
= "Flush port's ARL table entries",
1781 .set
= ar8xxx_sw_set_flush_port_arl_table
,
1785 const struct switch_attr ar8xxx_sw_attr_vlan
[1] = {
1787 .type
= SWITCH_TYPE_INT
,
1789 .description
= "VLAN ID (0-4094)",
1790 .set
= ar8xxx_sw_set_vid
,
1791 .get
= ar8xxx_sw_get_vid
,
1796 static const struct switch_dev_ops ar8xxx_sw_ops
= {
1798 .attr
= ar8xxx_sw_attr_globals
,
1799 .n_attr
= ARRAY_SIZE(ar8xxx_sw_attr_globals
),
1802 .attr
= ar8xxx_sw_attr_port
,
1803 .n_attr
= ARRAY_SIZE(ar8xxx_sw_attr_port
),
1806 .attr
= ar8xxx_sw_attr_vlan
,
1807 .n_attr
= ARRAY_SIZE(ar8xxx_sw_attr_vlan
),
1809 .get_port_pvid
= ar8xxx_sw_get_pvid
,
1810 .set_port_pvid
= ar8xxx_sw_set_pvid
,
1811 .get_vlan_ports
= ar8xxx_sw_get_ports
,
1812 .set_vlan_ports
= ar8xxx_sw_set_ports
,
1813 .apply_config
= ar8xxx_sw_hw_apply
,
1814 .reset_switch
= ar8xxx_sw_reset_switch
,
1815 .get_port_link
= ar8xxx_sw_get_port_link
,
1816 /* The following op is disabled as it hogs the CPU and degrades performance.
1817 An implementation has been attempted in 4d8a66d but reading MIB data is slow
1820 The high CPU load has been traced down to the ar8xxx_reg_wait() call in
1821 ar8xxx_mib_op(), which has to usleep_range() till the MIB busy flag set by
1822 the request to update the MIB counter is cleared. */
1824 .get_port_stats
= ar8xxx_sw_get_port_stats
,
1828 static const struct ar8xxx_chip ar8216_chip
= {
1829 .caps
= AR8XXX_CAP_MIB_COUNTERS
,
1831 .reg_port_stats_start
= 0x19000,
1832 .reg_port_stats_length
= 0xa0,
1833 .reg_arl_ctrl
= AR8216_REG_ATU_CTRL
,
1835 .name
= "Atheros AR8216",
1836 .ports
= AR8216_NUM_PORTS
,
1837 .vlans
= AR8216_NUM_VLANS
,
1838 .swops
= &ar8xxx_sw_ops
,
1840 .hw_init
= ar8216_hw_init
,
1841 .init_globals
= ar8216_init_globals
,
1842 .init_port
= ar8216_init_port
,
1843 .setup_port
= ar8216_setup_port
,
1844 .read_port_status
= ar8216_read_port_status
,
1845 .atu_flush
= ar8216_atu_flush
,
1846 .atu_flush_port
= ar8216_atu_flush_port
,
1847 .vtu_flush
= ar8216_vtu_flush
,
1848 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
1849 .set_mirror_regs
= ar8216_set_mirror_regs
,
1850 .get_arl_entry
= ar8216_get_arl_entry
,
1851 .sw_hw_apply
= ar8xxx_sw_hw_apply
,
1853 .num_mibs
= ARRAY_SIZE(ar8216_mibs
),
1854 .mib_decs
= ar8216_mibs
,
1855 .mib_func
= AR8216_REG_MIB_FUNC
1858 static const struct ar8xxx_chip ar8229_chip
= {
1859 .caps
= AR8XXX_CAP_MIB_COUNTERS
,
1861 .reg_port_stats_start
= 0x20000,
1862 .reg_port_stats_length
= 0x100,
1863 .reg_arl_ctrl
= AR8216_REG_ATU_CTRL
,
1865 .name
= "Atheros AR8229",
1866 .ports
= AR8216_NUM_PORTS
,
1867 .vlans
= AR8216_NUM_VLANS
,
1868 .swops
= &ar8xxx_sw_ops
,
1870 .hw_init
= ar8229_hw_init
,
1871 .init_globals
= ar8229_init_globals
,
1872 .init_port
= ar8229_init_port
,
1873 .setup_port
= ar8236_setup_port
,
1874 .read_port_status
= ar8216_read_port_status
,
1875 .atu_flush
= ar8216_atu_flush
,
1876 .atu_flush_port
= ar8216_atu_flush_port
,
1877 .vtu_flush
= ar8216_vtu_flush
,
1878 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
1879 .set_mirror_regs
= ar8216_set_mirror_regs
,
1880 .get_arl_entry
= ar8216_get_arl_entry
,
1881 .sw_hw_apply
= ar8xxx_sw_hw_apply
,
1883 .num_mibs
= ARRAY_SIZE(ar8236_mibs
),
1884 .mib_decs
= ar8236_mibs
,
1885 .mib_func
= AR8216_REG_MIB_FUNC
1888 static const struct ar8xxx_chip ar8236_chip
= {
1889 .caps
= AR8XXX_CAP_MIB_COUNTERS
,
1891 .reg_port_stats_start
= 0x20000,
1892 .reg_port_stats_length
= 0x100,
1893 .reg_arl_ctrl
= AR8216_REG_ATU_CTRL
,
1895 .name
= "Atheros AR8236",
1896 .ports
= AR8216_NUM_PORTS
,
1897 .vlans
= AR8216_NUM_VLANS
,
1898 .swops
= &ar8xxx_sw_ops
,
1900 .hw_init
= ar8216_hw_init
,
1901 .init_globals
= ar8236_init_globals
,
1902 .init_port
= ar8216_init_port
,
1903 .setup_port
= ar8236_setup_port
,
1904 .read_port_status
= ar8216_read_port_status
,
1905 .atu_flush
= ar8216_atu_flush
,
1906 .atu_flush_port
= ar8216_atu_flush_port
,
1907 .vtu_flush
= ar8216_vtu_flush
,
1908 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
1909 .set_mirror_regs
= ar8216_set_mirror_regs
,
1910 .get_arl_entry
= ar8216_get_arl_entry
,
1911 .sw_hw_apply
= ar8xxx_sw_hw_apply
,
1913 .num_mibs
= ARRAY_SIZE(ar8236_mibs
),
1914 .mib_decs
= ar8236_mibs
,
1915 .mib_func
= AR8216_REG_MIB_FUNC
1918 static const struct ar8xxx_chip ar8316_chip
= {
1919 .caps
= AR8XXX_CAP_GIGE
| AR8XXX_CAP_MIB_COUNTERS
,
1921 .reg_port_stats_start
= 0x20000,
1922 .reg_port_stats_length
= 0x100,
1923 .reg_arl_ctrl
= AR8216_REG_ATU_CTRL
,
1925 .name
= "Atheros AR8316",
1926 .ports
= AR8216_NUM_PORTS
,
1927 .vlans
= AR8X16_MAX_VLANS
,
1928 .swops
= &ar8xxx_sw_ops
,
1930 .hw_init
= ar8316_hw_init
,
1931 .init_globals
= ar8316_init_globals
,
1932 .init_port
= ar8216_init_port
,
1933 .setup_port
= ar8216_setup_port
,
1934 .read_port_status
= ar8216_read_port_status
,
1935 .atu_flush
= ar8216_atu_flush
,
1936 .atu_flush_port
= ar8216_atu_flush_port
,
1937 .vtu_flush
= ar8216_vtu_flush
,
1938 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
1939 .set_mirror_regs
= ar8216_set_mirror_regs
,
1940 .get_arl_entry
= ar8216_get_arl_entry
,
1941 .sw_hw_apply
= ar8xxx_sw_hw_apply
,
1943 .num_mibs
= ARRAY_SIZE(ar8236_mibs
),
1944 .mib_decs
= ar8236_mibs
,
1945 .mib_func
= AR8216_REG_MIB_FUNC
1949 ar8xxx_read_id(struct ar8xxx_priv
*priv
)
1955 val
= ar8xxx_read(priv
, AR8216_REG_CTRL
);
1959 id
= val
& (AR8216_CTRL_REVISION
| AR8216_CTRL_VERSION
);
1960 for (i
= 0; i
< AR8X16_PROBE_RETRIES
; i
++) {
1963 val
= ar8xxx_read(priv
, AR8216_REG_CTRL
);
1967 t
= val
& (AR8216_CTRL_REVISION
| AR8216_CTRL_VERSION
);
1972 priv
->chip_ver
= (id
& AR8216_CTRL_VERSION
) >> AR8216_CTRL_VERSION_S
;
1973 priv
->chip_rev
= (id
& AR8216_CTRL_REVISION
);
1978 ar8xxx_id_chip(struct ar8xxx_priv
*priv
)
1982 ret
= ar8xxx_read_id(priv
);
1986 switch (priv
->chip_ver
) {
1987 case AR8XXX_VER_AR8216
:
1988 priv
->chip
= &ar8216_chip
;
1990 case AR8XXX_VER_AR8236
:
1991 priv
->chip
= &ar8236_chip
;
1993 case AR8XXX_VER_AR8316
:
1994 priv
->chip
= &ar8316_chip
;
1996 case AR8XXX_VER_AR8327
:
1997 priv
->chip
= &ar8327_chip
;
1999 case AR8XXX_VER_AR8337
:
2000 priv
->chip
= &ar8337_chip
;
2003 pr_err("ar8216: Unknown Atheros device [ver=%d, rev=%d]\n",
2004 priv
->chip_ver
, priv
->chip_rev
);
2013 ar8xxx_mib_work_func(struct work_struct
*work
)
2015 struct ar8xxx_priv
*priv
;
2018 priv
= container_of(work
, struct ar8xxx_priv
, mib_work
.work
);
2020 mutex_lock(&priv
->mib_lock
);
2022 err
= ar8xxx_mib_capture(priv
);
2026 ar8xxx_mib_fetch_port_stat(priv
, priv
->mib_next_port
, false);
2029 priv
->mib_next_port
++;
2030 if (priv
->mib_next_port
>= priv
->dev
.ports
)
2031 priv
->mib_next_port
= 0;
2033 mutex_unlock(&priv
->mib_lock
);
2034 schedule_delayed_work(&priv
->mib_work
,
2035 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY
));
2039 ar8xxx_mib_init(struct ar8xxx_priv
*priv
)
2043 if (!ar8xxx_has_mib_counters(priv
))
2046 BUG_ON(!priv
->chip
->mib_decs
|| !priv
->chip
->num_mibs
);
2048 len
= priv
->dev
.ports
* priv
->chip
->num_mibs
*
2049 sizeof(*priv
->mib_stats
);
2050 priv
->mib_stats
= kzalloc(len
, GFP_KERNEL
);
2052 if (!priv
->mib_stats
)
2059 ar8xxx_mib_start(struct ar8xxx_priv
*priv
)
2061 if (!ar8xxx_has_mib_counters(priv
))
2064 schedule_delayed_work(&priv
->mib_work
,
2065 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY
));
2069 ar8xxx_mib_stop(struct ar8xxx_priv
*priv
)
2071 if (!ar8xxx_has_mib_counters(priv
))
2074 cancel_delayed_work_sync(&priv
->mib_work
);
2077 static struct ar8xxx_priv
*
2080 struct ar8xxx_priv
*priv
;
2082 priv
= kzalloc(sizeof(struct ar8xxx_priv
), GFP_KERNEL
);
2086 mutex_init(&priv
->reg_mutex
);
2087 mutex_init(&priv
->mib_lock
);
2088 INIT_DELAYED_WORK(&priv
->mib_work
, ar8xxx_mib_work_func
);
2094 ar8xxx_free(struct ar8xxx_priv
*priv
)
2096 if (priv
->chip
&& priv
->chip
->cleanup
)
2097 priv
->chip
->cleanup(priv
);
2099 kfree(priv
->chip_data
);
2100 kfree(priv
->mib_stats
);
2105 ar8xxx_probe_switch(struct ar8xxx_priv
*priv
)
2107 const struct ar8xxx_chip
*chip
;
2108 struct switch_dev
*swdev
;
2114 swdev
->cpu_port
= AR8216_PORT_CPU
;
2115 swdev
->name
= chip
->name
;
2116 swdev
->vlans
= chip
->vlans
;
2117 swdev
->ports
= chip
->ports
;
2118 swdev
->ops
= chip
->swops
;
2120 ret
= ar8xxx_mib_init(priv
);
2128 ar8xxx_start(struct ar8xxx_priv
*priv
)
2134 ret
= priv
->chip
->hw_init(priv
);
2138 ret
= ar8xxx_sw_reset_switch(&priv
->dev
);
2144 ar8xxx_mib_start(priv
);
2150 ar8xxx_phy_config_init(struct phy_device
*phydev
)
2152 struct ar8xxx_priv
*priv
= phydev
->priv
;
2153 struct net_device
*dev
= phydev
->attached_dev
;
2159 if (priv
->chip
->config_at_probe
)
2160 return ar8xxx_phy_check_aneg(phydev
);
2164 if (phydev
->mdio
.addr
!= 0) {
2165 if (chip_is_ar8316(priv
)) {
2166 /* switch device has been initialized, reinit */
2167 priv
->dev
.ports
= (AR8216_NUM_PORTS
- 1);
2168 priv
->initialized
= false;
2169 priv
->port4_phy
= true;
2170 ar8316_hw_init(priv
);
2177 ret
= ar8xxx_start(priv
);
2181 /* VID fixup only needed on ar8216 */
2182 if (chip_is_ar8216(priv
)) {
2183 dev
->phy_ptr
= priv
;
2184 dev
->priv_flags
|= IFF_NO_IP_ALIGN
;
2185 dev
->eth_mangle_rx
= ar8216_mangle_rx
;
2186 dev
->eth_mangle_tx
= ar8216_mangle_tx
;
2193 ar8xxx_check_link_states(struct ar8xxx_priv
*priv
)
2195 bool link_new
, changed
= false;
2199 mutex_lock(&priv
->reg_mutex
);
2201 for (i
= 0; i
< priv
->dev
.ports
; i
++) {
2202 status
= priv
->chip
->read_port_status(priv
, i
);
2203 link_new
= !!(status
& AR8216_PORT_STATUS_LINK_UP
);
2204 if (link_new
== priv
->link_up
[i
])
2207 priv
->link_up
[i
] = link_new
;
2209 /* flush ARL entries for this port if it went down*/
2211 priv
->chip
->atu_flush_port(priv
, i
);
2212 dev_info(&priv
->phy
->mdio
.dev
, "Port %d is %s\n",
2213 i
, link_new
? "up" : "down");
2216 mutex_unlock(&priv
->reg_mutex
);
2222 ar8xxx_phy_read_status(struct phy_device
*phydev
)
2224 struct ar8xxx_priv
*priv
= phydev
->priv
;
2225 struct switch_port_link link
;
2227 /* check for switch port link changes */
2228 if (phydev
->state
== PHY_CHANGELINK
)
2229 ar8xxx_check_link_states(priv
);
2231 if (phydev
->mdio
.addr
!= 0)
2232 return genphy_read_status(phydev
);
2234 ar8216_read_port_link(priv
, phydev
->mdio
.addr
, &link
);
2235 phydev
->link
= !!link
.link
;
2239 switch (link
.speed
) {
2240 case SWITCH_PORT_SPEED_10
:
2241 phydev
->speed
= SPEED_10
;
2243 case SWITCH_PORT_SPEED_100
:
2244 phydev
->speed
= SPEED_100
;
2246 case SWITCH_PORT_SPEED_1000
:
2247 phydev
->speed
= SPEED_1000
;
2252 phydev
->duplex
= link
.duplex
? DUPLEX_FULL
: DUPLEX_HALF
;
2254 phydev
->state
= PHY_RUNNING
;
2255 netif_carrier_on(phydev
->attached_dev
);
2256 if (phydev
->adjust_link
)
2257 phydev
->adjust_link(phydev
->attached_dev
);
2263 ar8xxx_phy_config_aneg(struct phy_device
*phydev
)
2265 if (phydev
->mdio
.addr
== 0)
2268 return genphy_config_aneg(phydev
);
2271 static const u32 ar8xxx_phy_ids
[] = {
2273 0x004dd034, /* AR8327 */
2274 0x004dd036, /* AR8337 */
2277 0x004dd043, /* AR8236 */
2281 ar8xxx_phy_match(u32 phy_id
)
2285 for (i
= 0; i
< ARRAY_SIZE(ar8xxx_phy_ids
); i
++)
2286 if (phy_id
== ar8xxx_phy_ids
[i
])
2293 ar8xxx_is_possible(struct mii_bus
*bus
)
2295 unsigned int i
, found_phys
= 0;
2297 for (i
= 0; i
< 5; i
++) {
2300 phy_id
= mdiobus_read(bus
, i
, MII_PHYSID1
) << 16;
2301 phy_id
|= mdiobus_read(bus
, i
, MII_PHYSID2
);
2302 if (ar8xxx_phy_match(phy_id
)) {
2304 } else if (phy_id
) {
2305 pr_debug("ar8xxx: unknown PHY at %s:%02x id:%08x\n",
2306 dev_name(&bus
->dev
), i
, phy_id
);
2309 return !!found_phys
;
2313 ar8xxx_phy_probe(struct phy_device
*phydev
)
2315 struct ar8xxx_priv
*priv
;
2316 struct switch_dev
*swdev
;
2319 /* skip PHYs at unused adresses */
2320 if (phydev
->mdio
.addr
!= 0 && phydev
->mdio
.addr
!= 3 && phydev
->mdio
.addr
!= 4)
2323 if (!ar8xxx_is_possible(phydev
->mdio
.bus
))
2326 mutex_lock(&ar8xxx_dev_list_lock
);
2327 list_for_each_entry(priv
, &ar8xxx_dev_list
, list
)
2328 if (priv
->mii_bus
== phydev
->mdio
.bus
)
2331 priv
= ar8xxx_create();
2337 priv
->mii_bus
= phydev
->mdio
.bus
;
2338 priv
->pdev
= &phydev
->mdio
.dev
;
2340 ret
= ar8xxx_id_chip(priv
);
2344 ret
= ar8xxx_probe_switch(priv
);
2349 swdev
->alias
= dev_name(&priv
->mii_bus
->dev
);
2350 ret
= register_switch(swdev
, NULL
);
2354 pr_info("%s: %s rev. %u switch registered on %s\n",
2355 swdev
->devname
, swdev
->name
, priv
->chip_rev
,
2356 dev_name(&priv
->mii_bus
->dev
));
2358 list_add(&priv
->list
, &ar8xxx_dev_list
);
2363 if (phydev
->mdio
.addr
== 0) {
2364 if (ar8xxx_has_gige(priv
)) {
2365 phydev
->supported
= SUPPORTED_1000baseT_Full
;
2366 phydev
->advertising
= ADVERTISED_1000baseT_Full
;
2368 phydev
->supported
= SUPPORTED_100baseT_Full
;
2369 phydev
->advertising
= ADVERTISED_100baseT_Full
;
2372 if (priv
->chip
->config_at_probe
) {
2375 ret
= ar8xxx_start(priv
);
2377 goto err_unregister_switch
;
2380 if (ar8xxx_has_gige(priv
)) {
2381 phydev
->supported
|= SUPPORTED_1000baseT_Full
;
2382 phydev
->advertising
|= ADVERTISED_1000baseT_Full
;
2384 if (priv
->chip
->phy_rgmii_set
)
2385 priv
->chip
->phy_rgmii_set(priv
, phydev
);
2388 phydev
->priv
= priv
;
2390 mutex_unlock(&ar8xxx_dev_list_lock
);
2394 err_unregister_switch
:
2395 if (--priv
->use_count
)
2398 unregister_switch(&priv
->dev
);
2403 mutex_unlock(&ar8xxx_dev_list_lock
);
2408 ar8xxx_phy_detach(struct phy_device
*phydev
)
2410 struct net_device
*dev
= phydev
->attached_dev
;
2415 dev
->phy_ptr
= NULL
;
2416 dev
->priv_flags
&= ~IFF_NO_IP_ALIGN
;
2417 dev
->eth_mangle_rx
= NULL
;
2418 dev
->eth_mangle_tx
= NULL
;
2422 ar8xxx_phy_remove(struct phy_device
*phydev
)
2424 struct ar8xxx_priv
*priv
= phydev
->priv
;
2429 phydev
->priv
= NULL
;
2431 mutex_lock(&ar8xxx_dev_list_lock
);
2433 if (--priv
->use_count
> 0) {
2434 mutex_unlock(&ar8xxx_dev_list_lock
);
2438 list_del(&priv
->list
);
2439 mutex_unlock(&ar8xxx_dev_list_lock
);
2441 unregister_switch(&priv
->dev
);
2442 ar8xxx_mib_stop(priv
);
2447 ar8xxx_phy_soft_reset(struct phy_device
*phydev
)
2449 /* we don't need an extra reset */
2453 static struct phy_driver ar8xxx_phy_driver
[] = {
2455 .phy_id
= 0x004d0000,
2456 .name
= "Atheros AR8216/AR8236/AR8316",
2457 .phy_id_mask
= 0xffff0000,
2458 .features
= PHY_BASIC_FEATURES
,
2459 .probe
= ar8xxx_phy_probe
,
2460 .remove
= ar8xxx_phy_remove
,
2461 .detach
= ar8xxx_phy_detach
,
2462 .config_init
= ar8xxx_phy_config_init
,
2463 .config_aneg
= ar8xxx_phy_config_aneg
,
2464 .read_status
= ar8xxx_phy_read_status
,
2465 .soft_reset
= ar8xxx_phy_soft_reset
,
2469 static const struct of_device_id ar8xxx_mdiodev_of_match
[] = {
2471 .compatible
= "qca,ar8229",
2472 .data
= &ar8229_chip
,
2474 .compatible
= "qca,ar8236",
2475 .data
= &ar8236_chip
,
2477 .compatible
= "qca,ar8327",
2478 .data
= &ar8327_chip
,
2484 ar8xxx_mdiodev_probe(struct mdio_device
*mdiodev
)
2486 const struct of_device_id
*match
;
2487 struct ar8xxx_priv
*priv
;
2488 struct switch_dev
*swdev
;
2489 struct device_node
*mdio_node
;
2492 match
= of_match_device(ar8xxx_mdiodev_of_match
, &mdiodev
->dev
);
2496 priv
= ar8xxx_create();
2500 priv
->mii_bus
= mdiodev
->bus
;
2501 priv
->pdev
= &mdiodev
->dev
;
2502 priv
->chip
= (const struct ar8xxx_chip
*) match
->data
;
2504 ret
= ar8xxx_read_id(priv
);
2508 ret
= ar8xxx_probe_switch(priv
);
2512 if (priv
->chip
->phy_read
&& priv
->chip
->phy_write
) {
2513 priv
->sw_mii_bus
= devm_mdiobus_alloc(&mdiodev
->dev
);
2514 priv
->sw_mii_bus
->name
= "ar8xxx-mdio";
2515 priv
->sw_mii_bus
->read
= ar8xxx_phy_read
;
2516 priv
->sw_mii_bus
->write
= ar8xxx_phy_write
;
2517 priv
->sw_mii_bus
->priv
= priv
;
2518 priv
->sw_mii_bus
->parent
= &mdiodev
->dev
;
2519 snprintf(priv
->sw_mii_bus
->id
, MII_BUS_ID_SIZE
, "%s",
2520 dev_name(&mdiodev
->dev
));
2521 mdio_node
= of_get_child_by_name(priv
->pdev
->of_node
, "mdio-bus");
2522 ret
= of_mdiobus_register(priv
->sw_mii_bus
, mdio_node
);
2528 swdev
->alias
= dev_name(&mdiodev
->dev
);
2529 ret
= register_switch(swdev
, NULL
);
2533 pr_info("%s: %s rev. %u switch registered on %s\n",
2534 swdev
->devname
, swdev
->name
, priv
->chip_rev
,
2535 dev_name(&priv
->mii_bus
->dev
));
2537 mutex_lock(&ar8xxx_dev_list_lock
);
2538 list_add(&priv
->list
, &ar8xxx_dev_list
);
2539 mutex_unlock(&ar8xxx_dev_list_lock
);
2543 ret
= ar8xxx_start(priv
);
2545 goto err_unregister_switch
;
2547 dev_set_drvdata(&mdiodev
->dev
, priv
);
2551 err_unregister_switch
:
2552 if (--priv
->use_count
)
2555 unregister_switch(&priv
->dev
);
2563 ar8xxx_mdiodev_remove(struct mdio_device
*mdiodev
)
2565 struct ar8xxx_priv
*priv
= dev_get_drvdata(&mdiodev
->dev
);
2570 mutex_lock(&ar8xxx_dev_list_lock
);
2572 if (--priv
->use_count
> 0) {
2573 mutex_unlock(&ar8xxx_dev_list_lock
);
2577 list_del(&priv
->list
);
2578 mutex_unlock(&ar8xxx_dev_list_lock
);
2580 unregister_switch(&priv
->dev
);
2581 ar8xxx_mib_stop(priv
);
2582 if(priv
->sw_mii_bus
)
2583 mdiobus_unregister(priv
->sw_mii_bus
);
2587 static struct mdio_driver ar8xxx_mdio_driver
= {
2588 .probe
= ar8xxx_mdiodev_probe
,
2589 .remove
= ar8xxx_mdiodev_remove
,
2591 .name
= "ar8xxx-switch",
2592 .of_match_table
= ar8xxx_mdiodev_of_match
,
2596 static int __init
ar8216_init(void)
2600 ret
= phy_drivers_register(ar8xxx_phy_driver
,
2601 ARRAY_SIZE(ar8xxx_phy_driver
),
2606 ret
= mdio_driver_register(&ar8xxx_mdio_driver
);
2608 phy_drivers_unregister(ar8xxx_phy_driver
,
2609 ARRAY_SIZE(ar8xxx_phy_driver
));
2613 module_init(ar8216_init
);
2615 static void __exit
ar8216_exit(void)
2617 mdio_driver_unregister(&ar8xxx_mdio_driver
);
2618 phy_drivers_unregister(ar8xxx_phy_driver
,
2619 ARRAY_SIZE(ar8xxx_phy_driver
));
2621 module_exit(ar8216_exit
);
2623 MODULE_LICENSE("GPL");