2 * ar8216.c: AR8216 switch driver
4 * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/list.h>
22 #include <linux/if_ether.h>
23 #include <linux/skbuff.h>
24 #include <linux/netdevice.h>
25 #include <linux/netlink.h>
26 #include <linux/bitops.h>
27 #include <net/genetlink.h>
28 #include <linux/switch.h>
29 #include <linux/delay.h>
30 #include <linux/phy.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/lockdep.h>
34 #include <linux/ar8216_platform.h>
35 #include <linux/workqueue.h>
36 #include <linux/of_device.h>
37 #include <linux/leds.h>
38 #include <linux/gpio.h>
42 /* size of the vlan table */
43 #define AR8X16_MAX_VLANS 128
44 #define AR8X16_PROBE_RETRIES 10
45 #define AR8X16_MAX_PORTS 8
47 #define AR8XXX_MIB_WORK_DELAY 2000 /* msecs */
51 #define AR8XXX_CAP_GIGE BIT(0)
52 #define AR8XXX_CAP_MIB_COUNTERS BIT(1)
54 #define AR8XXX_NUM_PHYS 5
57 AR8XXX_VER_AR8216
= 0x01,
58 AR8XXX_VER_AR8236
= 0x03,
59 AR8XXX_VER_AR8316
= 0x10,
60 AR8XXX_VER_AR8327
= 0x12,
61 AR8XXX_VER_AR8337
= 0x13,
64 struct ar8xxx_mib_desc
{
73 int (*hw_init
)(struct ar8xxx_priv
*priv
);
74 void (*cleanup
)(struct ar8xxx_priv
*priv
);
76 void (*init_globals
)(struct ar8xxx_priv
*priv
);
77 void (*init_port
)(struct ar8xxx_priv
*priv
, int port
);
78 void (*setup_port
)(struct ar8xxx_priv
*priv
, int port
, u32 members
);
79 u32 (*read_port_status
)(struct ar8xxx_priv
*priv
, int port
);
80 int (*atu_flush
)(struct ar8xxx_priv
*priv
);
81 void (*vtu_flush
)(struct ar8xxx_priv
*priv
);
82 void (*vtu_load_vlan
)(struct ar8xxx_priv
*priv
, u32 vid
, u32 port_mask
);
84 const struct ar8xxx_mib_desc
*mib_decs
;
88 enum ar8327_led_pattern
{
89 AR8327_LED_PATTERN_OFF
= 0,
90 AR8327_LED_PATTERN_BLINK
,
91 AR8327_LED_PATTERN_ON
,
92 AR8327_LED_PATTERN_RULE
,
95 struct ar8327_led_entry
{
101 struct led_classdev cdev
;
102 struct ar8xxx_priv
*sw_priv
;
107 enum ar8327_led_mode mode
;
111 struct work_struct led_work
;
113 enum ar8327_led_pattern pattern
;
120 struct ar8327_led
**leds
;
121 unsigned int num_leds
;
125 struct switch_dev dev
;
126 struct mii_bus
*mii_bus
;
127 struct phy_device
*phy
;
129 u32 (*read
)(struct ar8xxx_priv
*priv
, int reg
);
130 void (*write
)(struct ar8xxx_priv
*priv
, int reg
, u32 val
);
131 u32 (*rmw
)(struct ar8xxx_priv
*priv
, int reg
, u32 mask
, u32 val
);
133 int (*get_port_link
)(unsigned port
);
135 const struct net_device_ops
*ndo_old
;
136 struct net_device_ops ndo
;
137 struct mutex reg_mutex
;
140 const struct ar8xxx_chip
*chip
;
142 struct ar8327_data ar8327
;
151 struct mutex mib_lock
;
152 struct delayed_work mib_work
;
156 struct list_head list
;
157 unsigned int use_count
;
159 /* all fields below are cleared on reset */
161 u16 vlan_id
[AR8X16_MAX_VLANS
];
162 u8 vlan_table
[AR8X16_MAX_VLANS
];
164 u16 pvid
[AR8X16_MAX_PORTS
];
173 #define MIB_DESC(_s , _o, _n) \
180 static const struct ar8xxx_mib_desc ar8216_mibs
[] = {
181 MIB_DESC(1, AR8216_STATS_RXBROAD
, "RxBroad"),
182 MIB_DESC(1, AR8216_STATS_RXPAUSE
, "RxPause"),
183 MIB_DESC(1, AR8216_STATS_RXMULTI
, "RxMulti"),
184 MIB_DESC(1, AR8216_STATS_RXFCSERR
, "RxFcsErr"),
185 MIB_DESC(1, AR8216_STATS_RXALIGNERR
, "RxAlignErr"),
186 MIB_DESC(1, AR8216_STATS_RXRUNT
, "RxRunt"),
187 MIB_DESC(1, AR8216_STATS_RXFRAGMENT
, "RxFragment"),
188 MIB_DESC(1, AR8216_STATS_RX64BYTE
, "Rx64Byte"),
189 MIB_DESC(1, AR8216_STATS_RX128BYTE
, "Rx128Byte"),
190 MIB_DESC(1, AR8216_STATS_RX256BYTE
, "Rx256Byte"),
191 MIB_DESC(1, AR8216_STATS_RX512BYTE
, "Rx512Byte"),
192 MIB_DESC(1, AR8216_STATS_RX1024BYTE
, "Rx1024Byte"),
193 MIB_DESC(1, AR8216_STATS_RXMAXBYTE
, "RxMaxByte"),
194 MIB_DESC(1, AR8216_STATS_RXTOOLONG
, "RxTooLong"),
195 MIB_DESC(2, AR8216_STATS_RXGOODBYTE
, "RxGoodByte"),
196 MIB_DESC(2, AR8216_STATS_RXBADBYTE
, "RxBadByte"),
197 MIB_DESC(1, AR8216_STATS_RXOVERFLOW
, "RxOverFlow"),
198 MIB_DESC(1, AR8216_STATS_FILTERED
, "Filtered"),
199 MIB_DESC(1, AR8216_STATS_TXBROAD
, "TxBroad"),
200 MIB_DESC(1, AR8216_STATS_TXPAUSE
, "TxPause"),
201 MIB_DESC(1, AR8216_STATS_TXMULTI
, "TxMulti"),
202 MIB_DESC(1, AR8216_STATS_TXUNDERRUN
, "TxUnderRun"),
203 MIB_DESC(1, AR8216_STATS_TX64BYTE
, "Tx64Byte"),
204 MIB_DESC(1, AR8216_STATS_TX128BYTE
, "Tx128Byte"),
205 MIB_DESC(1, AR8216_STATS_TX256BYTE
, "Tx256Byte"),
206 MIB_DESC(1, AR8216_STATS_TX512BYTE
, "Tx512Byte"),
207 MIB_DESC(1, AR8216_STATS_TX1024BYTE
, "Tx1024Byte"),
208 MIB_DESC(1, AR8216_STATS_TXMAXBYTE
, "TxMaxByte"),
209 MIB_DESC(1, AR8216_STATS_TXOVERSIZE
, "TxOverSize"),
210 MIB_DESC(2, AR8216_STATS_TXBYTE
, "TxByte"),
211 MIB_DESC(1, AR8216_STATS_TXCOLLISION
, "TxCollision"),
212 MIB_DESC(1, AR8216_STATS_TXABORTCOL
, "TxAbortCol"),
213 MIB_DESC(1, AR8216_STATS_TXMULTICOL
, "TxMultiCol"),
214 MIB_DESC(1, AR8216_STATS_TXSINGLECOL
, "TxSingleCol"),
215 MIB_DESC(1, AR8216_STATS_TXEXCDEFER
, "TxExcDefer"),
216 MIB_DESC(1, AR8216_STATS_TXDEFER
, "TxDefer"),
217 MIB_DESC(1, AR8216_STATS_TXLATECOL
, "TxLateCol"),
220 static const struct ar8xxx_mib_desc ar8236_mibs
[] = {
221 MIB_DESC(1, AR8236_STATS_RXBROAD
, "RxBroad"),
222 MIB_DESC(1, AR8236_STATS_RXPAUSE
, "RxPause"),
223 MIB_DESC(1, AR8236_STATS_RXMULTI
, "RxMulti"),
224 MIB_DESC(1, AR8236_STATS_RXFCSERR
, "RxFcsErr"),
225 MIB_DESC(1, AR8236_STATS_RXALIGNERR
, "RxAlignErr"),
226 MIB_DESC(1, AR8236_STATS_RXRUNT
, "RxRunt"),
227 MIB_DESC(1, AR8236_STATS_RXFRAGMENT
, "RxFragment"),
228 MIB_DESC(1, AR8236_STATS_RX64BYTE
, "Rx64Byte"),
229 MIB_DESC(1, AR8236_STATS_RX128BYTE
, "Rx128Byte"),
230 MIB_DESC(1, AR8236_STATS_RX256BYTE
, "Rx256Byte"),
231 MIB_DESC(1, AR8236_STATS_RX512BYTE
, "Rx512Byte"),
232 MIB_DESC(1, AR8236_STATS_RX1024BYTE
, "Rx1024Byte"),
233 MIB_DESC(1, AR8236_STATS_RX1518BYTE
, "Rx1518Byte"),
234 MIB_DESC(1, AR8236_STATS_RXMAXBYTE
, "RxMaxByte"),
235 MIB_DESC(1, AR8236_STATS_RXTOOLONG
, "RxTooLong"),
236 MIB_DESC(2, AR8236_STATS_RXGOODBYTE
, "RxGoodByte"),
237 MIB_DESC(2, AR8236_STATS_RXBADBYTE
, "RxBadByte"),
238 MIB_DESC(1, AR8236_STATS_RXOVERFLOW
, "RxOverFlow"),
239 MIB_DESC(1, AR8236_STATS_FILTERED
, "Filtered"),
240 MIB_DESC(1, AR8236_STATS_TXBROAD
, "TxBroad"),
241 MIB_DESC(1, AR8236_STATS_TXPAUSE
, "TxPause"),
242 MIB_DESC(1, AR8236_STATS_TXMULTI
, "TxMulti"),
243 MIB_DESC(1, AR8236_STATS_TXUNDERRUN
, "TxUnderRun"),
244 MIB_DESC(1, AR8236_STATS_TX64BYTE
, "Tx64Byte"),
245 MIB_DESC(1, AR8236_STATS_TX128BYTE
, "Tx128Byte"),
246 MIB_DESC(1, AR8236_STATS_TX256BYTE
, "Tx256Byte"),
247 MIB_DESC(1, AR8236_STATS_TX512BYTE
, "Tx512Byte"),
248 MIB_DESC(1, AR8236_STATS_TX1024BYTE
, "Tx1024Byte"),
249 MIB_DESC(1, AR8236_STATS_TX1518BYTE
, "Tx1518Byte"),
250 MIB_DESC(1, AR8236_STATS_TXMAXBYTE
, "TxMaxByte"),
251 MIB_DESC(1, AR8236_STATS_TXOVERSIZE
, "TxOverSize"),
252 MIB_DESC(2, AR8236_STATS_TXBYTE
, "TxByte"),
253 MIB_DESC(1, AR8236_STATS_TXCOLLISION
, "TxCollision"),
254 MIB_DESC(1, AR8236_STATS_TXABORTCOL
, "TxAbortCol"),
255 MIB_DESC(1, AR8236_STATS_TXMULTICOL
, "TxMultiCol"),
256 MIB_DESC(1, AR8236_STATS_TXSINGLECOL
, "TxSingleCol"),
257 MIB_DESC(1, AR8236_STATS_TXEXCDEFER
, "TxExcDefer"),
258 MIB_DESC(1, AR8236_STATS_TXDEFER
, "TxDefer"),
259 MIB_DESC(1, AR8236_STATS_TXLATECOL
, "TxLateCol"),
262 static DEFINE_MUTEX(ar8xxx_dev_list_lock
);
263 static LIST_HEAD(ar8xxx_dev_list
);
265 static inline struct ar8xxx_priv
*
266 swdev_to_ar8xxx(struct switch_dev
*swdev
)
268 return container_of(swdev
, struct ar8xxx_priv
, dev
);
271 static inline bool ar8xxx_has_gige(struct ar8xxx_priv
*priv
)
273 return priv
->chip
->caps
& AR8XXX_CAP_GIGE
;
276 static inline bool ar8xxx_has_mib_counters(struct ar8xxx_priv
*priv
)
278 return priv
->chip
->caps
& AR8XXX_CAP_MIB_COUNTERS
;
281 static inline bool chip_is_ar8216(struct ar8xxx_priv
*priv
)
283 return priv
->chip_ver
== AR8XXX_VER_AR8216
;
286 static inline bool chip_is_ar8236(struct ar8xxx_priv
*priv
)
288 return priv
->chip_ver
== AR8XXX_VER_AR8236
;
291 static inline bool chip_is_ar8316(struct ar8xxx_priv
*priv
)
293 return priv
->chip_ver
== AR8XXX_VER_AR8316
;
296 static inline bool chip_is_ar8327(struct ar8xxx_priv
*priv
)
298 return priv
->chip_ver
== AR8XXX_VER_AR8327
;
301 static inline bool chip_is_ar8337(struct ar8xxx_priv
*priv
)
303 return priv
->chip_ver
== AR8XXX_VER_AR8337
;
307 split_addr(u32 regaddr
, u16
*r1
, u16
*r2
, u16
*page
)
310 *r1
= regaddr
& 0x1e;
316 *page
= regaddr
& 0x1ff;
320 ar8xxx_mii_read(struct ar8xxx_priv
*priv
, int reg
)
322 struct mii_bus
*bus
= priv
->mii_bus
;
326 split_addr((u32
) reg
, &r1
, &r2
, &page
);
328 mutex_lock(&bus
->mdio_lock
);
330 bus
->write(bus
, 0x18, 0, page
);
331 usleep_range(1000, 2000); /* wait for the page switch to propagate */
332 lo
= bus
->read(bus
, 0x10 | r2
, r1
);
333 hi
= bus
->read(bus
, 0x10 | r2
, r1
+ 1);
335 mutex_unlock(&bus
->mdio_lock
);
337 return (hi
<< 16) | lo
;
341 ar8xxx_mii_write(struct ar8xxx_priv
*priv
, int reg
, u32 val
)
343 struct mii_bus
*bus
= priv
->mii_bus
;
347 split_addr((u32
) reg
, &r1
, &r2
, &r3
);
349 hi
= (u16
) (val
>> 16);
351 mutex_lock(&bus
->mdio_lock
);
353 bus
->write(bus
, 0x18, 0, r3
);
354 usleep_range(1000, 2000); /* wait for the page switch to propagate */
355 if (priv
->mii_lo_first
) {
356 bus
->write(bus
, 0x10 | r2
, r1
, lo
);
357 bus
->write(bus
, 0x10 | r2
, r1
+ 1, hi
);
359 bus
->write(bus
, 0x10 | r2
, r1
+ 1, hi
);
360 bus
->write(bus
, 0x10 | r2
, r1
, lo
);
363 mutex_unlock(&bus
->mdio_lock
);
367 ar8xxx_mii_rmw(struct ar8xxx_priv
*priv
, int reg
, u32 mask
, u32 val
)
369 struct mii_bus
*bus
= priv
->mii_bus
;
374 split_addr((u32
) reg
, &r1
, &r2
, &page
);
376 mutex_lock(&bus
->mdio_lock
);
378 bus
->write(bus
, 0x18, 0, page
);
379 usleep_range(1000, 2000); /* wait for the page switch to propagate */
381 lo
= bus
->read(bus
, 0x10 | r2
, r1
);
382 hi
= bus
->read(bus
, 0x10 | r2
, r1
+ 1);
389 hi
= (u16
) (ret
>> 16);
391 if (priv
->mii_lo_first
) {
392 bus
->write(bus
, 0x10 | r2
, r1
, lo
);
393 bus
->write(bus
, 0x10 | r2
, r1
+ 1, hi
);
395 bus
->write(bus
, 0x10 | r2
, r1
+ 1, hi
);
396 bus
->write(bus
, 0x10 | r2
, r1
, lo
);
399 mutex_unlock(&bus
->mdio_lock
);
406 ar8xxx_phy_dbg_write(struct ar8xxx_priv
*priv
, int phy_addr
,
407 u16 dbg_addr
, u16 dbg_data
)
409 struct mii_bus
*bus
= priv
->mii_bus
;
411 mutex_lock(&bus
->mdio_lock
);
412 bus
->write(bus
, phy_addr
, MII_ATH_DBG_ADDR
, dbg_addr
);
413 bus
->write(bus
, phy_addr
, MII_ATH_DBG_DATA
, dbg_data
);
414 mutex_unlock(&bus
->mdio_lock
);
418 ar8xxx_phy_mmd_write(struct ar8xxx_priv
*priv
, int phy_addr
, u16 addr
, u16 data
)
420 struct mii_bus
*bus
= priv
->mii_bus
;
422 mutex_lock(&bus
->mdio_lock
);
423 bus
->write(bus
, phy_addr
, MII_ATH_MMD_ADDR
, addr
);
424 bus
->write(bus
, phy_addr
, MII_ATH_MMD_DATA
, data
);
425 mutex_unlock(&bus
->mdio_lock
);
429 ar8xxx_rmw(struct ar8xxx_priv
*priv
, int reg
, u32 mask
, u32 val
)
431 return priv
->rmw(priv
, reg
, mask
, val
);
435 ar8xxx_reg_set(struct ar8xxx_priv
*priv
, int reg
, u32 val
)
437 priv
->rmw(priv
, reg
, 0, val
);
441 ar8xxx_reg_wait(struct ar8xxx_priv
*priv
, u32 reg
, u32 mask
, u32 val
,
446 for (i
= 0; i
< timeout
; i
++) {
449 t
= priv
->read(priv
, reg
);
450 if ((t
& mask
) == val
)
453 usleep_range(1000, 2000);
460 ar8xxx_mib_op(struct ar8xxx_priv
*priv
, u32 op
)
465 lockdep_assert_held(&priv
->mib_lock
);
467 if (chip_is_ar8327(priv
) || chip_is_ar8337(priv
))
468 mib_func
= AR8327_REG_MIB_FUNC
;
470 mib_func
= AR8216_REG_MIB_FUNC
;
472 /* Capture the hardware statistics for all ports */
473 ar8xxx_rmw(priv
, mib_func
, AR8216_MIB_FUNC
, (op
<< AR8216_MIB_FUNC_S
));
475 /* Wait for the capturing to complete. */
476 ret
= ar8xxx_reg_wait(priv
, mib_func
, AR8216_MIB_BUSY
, 0, 10);
487 ar8xxx_mib_capture(struct ar8xxx_priv
*priv
)
489 return ar8xxx_mib_op(priv
, AR8216_MIB_FUNC_CAPTURE
);
493 ar8xxx_mib_flush(struct ar8xxx_priv
*priv
)
495 return ar8xxx_mib_op(priv
, AR8216_MIB_FUNC_FLUSH
);
499 ar8xxx_mib_fetch_port_stat(struct ar8xxx_priv
*priv
, int port
, bool flush
)
505 WARN_ON(port
>= priv
->dev
.ports
);
507 lockdep_assert_held(&priv
->mib_lock
);
509 if (chip_is_ar8327(priv
) || chip_is_ar8337(priv
))
510 base
= AR8327_REG_PORT_STATS_BASE(port
);
511 else if (chip_is_ar8236(priv
) ||
512 chip_is_ar8316(priv
))
513 base
= AR8236_REG_PORT_STATS_BASE(port
);
515 base
= AR8216_REG_PORT_STATS_BASE(port
);
517 mib_stats
= &priv
->mib_stats
[port
* priv
->chip
->num_mibs
];
518 for (i
= 0; i
< priv
->chip
->num_mibs
; i
++) {
519 const struct ar8xxx_mib_desc
*mib
;
522 mib
= &priv
->chip
->mib_decs
[i
];
523 t
= priv
->read(priv
, base
+ mib
->offset
);
524 if (mib
->size
== 2) {
527 hi
= priv
->read(priv
, base
+ mib
->offset
+ 4);
539 ar8216_read_port_link(struct ar8xxx_priv
*priv
, int port
,
540 struct switch_port_link
*link
)
545 memset(link
, '\0', sizeof(*link
));
547 status
= priv
->chip
->read_port_status(priv
, port
);
549 link
->aneg
= !!(status
& AR8216_PORT_STATUS_LINK_AUTO
);
551 link
->link
= !!(status
& AR8216_PORT_STATUS_LINK_UP
);
555 if (priv
->get_port_link
) {
558 err
= priv
->get_port_link(port
);
567 link
->duplex
= !!(status
& AR8216_PORT_STATUS_DUPLEX
);
568 link
->tx_flow
= !!(status
& AR8216_PORT_STATUS_TXFLOW
);
569 link
->rx_flow
= !!(status
& AR8216_PORT_STATUS_RXFLOW
);
571 speed
= (status
& AR8216_PORT_STATUS_SPEED
) >>
572 AR8216_PORT_STATUS_SPEED_S
;
575 case AR8216_PORT_SPEED_10M
:
576 link
->speed
= SWITCH_PORT_SPEED_10
;
578 case AR8216_PORT_SPEED_100M
:
579 link
->speed
= SWITCH_PORT_SPEED_100
;
581 case AR8216_PORT_SPEED_1000M
:
582 link
->speed
= SWITCH_PORT_SPEED_1000
;
585 link
->speed
= SWITCH_PORT_SPEED_UNKNOWN
;
590 static struct sk_buff
*
591 ar8216_mangle_tx(struct net_device
*dev
, struct sk_buff
*skb
)
593 struct ar8xxx_priv
*priv
= dev
->phy_ptr
;
602 if (unlikely(skb_headroom(skb
) < 2)) {
603 if (pskb_expand_head(skb
, 2, 0, GFP_ATOMIC
) < 0)
607 buf
= skb_push(skb
, 2);
615 dev_kfree_skb_any(skb
);
620 ar8216_mangle_rx(struct net_device
*dev
, struct sk_buff
*skb
)
622 struct ar8xxx_priv
*priv
;
630 /* don't strip the header if vlan mode is disabled */
634 /* strip header, get vlan id */
638 /* check for vlan header presence */
639 if ((buf
[12 + 2] != 0x81) || (buf
[13 + 2] != 0x00))
644 /* no need to fix up packets coming from a tagged source */
645 if (priv
->vlan_tagged
& (1 << port
))
648 /* lookup port vid from local table, the switch passes an invalid vlan id */
649 vlan
= priv
->vlan_id
[priv
->pvid
[port
]];
652 buf
[14 + 2] |= vlan
>> 8;
653 buf
[15 + 2] = vlan
& 0xff;
657 ar8216_wait_bit(struct ar8xxx_priv
*priv
, int reg
, u32 mask
, u32 val
)
663 t
= priv
->read(priv
, reg
);
664 if ((t
& mask
) == val
)
673 pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
674 (unsigned int) reg
, t
, mask
, val
);
679 ar8216_vtu_op(struct ar8xxx_priv
*priv
, u32 op
, u32 val
)
681 if (ar8216_wait_bit(priv
, AR8216_REG_VTU
, AR8216_VTU_ACTIVE
, 0))
683 if ((op
& AR8216_VTU_OP
) == AR8216_VTU_OP_LOAD
) {
684 val
&= AR8216_VTUDATA_MEMBER
;
685 val
|= AR8216_VTUDATA_VALID
;
686 priv
->write(priv
, AR8216_REG_VTU_DATA
, val
);
688 op
|= AR8216_VTU_ACTIVE
;
689 priv
->write(priv
, AR8216_REG_VTU
, op
);
693 ar8216_vtu_flush(struct ar8xxx_priv
*priv
)
695 ar8216_vtu_op(priv
, AR8216_VTU_OP_FLUSH
, 0);
699 ar8216_vtu_load_vlan(struct ar8xxx_priv
*priv
, u32 vid
, u32 port_mask
)
703 op
= AR8216_VTU_OP_LOAD
| (vid
<< AR8216_VTU_VID_S
);
704 ar8216_vtu_op(priv
, op
, port_mask
);
708 ar8216_atu_flush(struct ar8xxx_priv
*priv
)
712 ret
= ar8216_wait_bit(priv
, AR8216_REG_ATU
, AR8216_ATU_ACTIVE
, 0);
714 priv
->write(priv
, AR8216_REG_ATU
, AR8216_ATU_OP_FLUSH
);
720 ar8216_read_port_status(struct ar8xxx_priv
*priv
, int port
)
722 return priv
->read(priv
, AR8216_REG_PORT_STATUS(port
));
726 ar8216_setup_port(struct ar8xxx_priv
*priv
, int port
, u32 members
)
733 pvid
= priv
->vlan_id
[priv
->pvid
[port
]];
734 if (priv
->vlan_tagged
& (1 << port
))
735 egress
= AR8216_OUT_ADD_VLAN
;
737 egress
= AR8216_OUT_STRIP_VLAN
;
738 ingress
= AR8216_IN_SECURE
;
741 egress
= AR8216_OUT_KEEP
;
742 ingress
= AR8216_IN_PORT_ONLY
;
745 if (chip_is_ar8216(priv
) && priv
->vlan
&& port
== AR8216_PORT_CPU
)
746 header
= AR8216_PORT_CTRL_HEADER
;
750 ar8xxx_rmw(priv
, AR8216_REG_PORT_CTRL(port
),
751 AR8216_PORT_CTRL_LEARN
| AR8216_PORT_CTRL_VLAN_MODE
|
752 AR8216_PORT_CTRL_SINGLE_VLAN
| AR8216_PORT_CTRL_STATE
|
753 AR8216_PORT_CTRL_HEADER
| AR8216_PORT_CTRL_LEARN_LOCK
,
754 AR8216_PORT_CTRL_LEARN
| header
|
755 (egress
<< AR8216_PORT_CTRL_VLAN_MODE_S
) |
756 (AR8216_PORT_STATE_FORWARD
<< AR8216_PORT_CTRL_STATE_S
));
758 ar8xxx_rmw(priv
, AR8216_REG_PORT_VLAN(port
),
759 AR8216_PORT_VLAN_DEST_PORTS
| AR8216_PORT_VLAN_MODE
|
760 AR8216_PORT_VLAN_DEFAULT_ID
,
761 (members
<< AR8216_PORT_VLAN_DEST_PORTS_S
) |
762 (ingress
<< AR8216_PORT_VLAN_MODE_S
) |
763 (pvid
<< AR8216_PORT_VLAN_DEFAULT_ID_S
));
767 ar8216_hw_init(struct ar8xxx_priv
*priv
)
773 ar8216_init_globals(struct ar8xxx_priv
*priv
)
775 /* standard atheros magic */
776 priv
->write(priv
, 0x38, 0xc000050e);
778 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
779 AR8216_GCTRL_MTU
, 1518 + 8 + 2);
783 ar8216_init_port(struct ar8xxx_priv
*priv
, int port
)
785 /* Enable port learning and tx */
786 priv
->write(priv
, AR8216_REG_PORT_CTRL(port
),
787 AR8216_PORT_CTRL_LEARN
|
788 (4 << AR8216_PORT_CTRL_STATE_S
));
790 priv
->write(priv
, AR8216_REG_PORT_VLAN(port
), 0);
792 if (port
== AR8216_PORT_CPU
) {
793 priv
->write(priv
, AR8216_REG_PORT_STATUS(port
),
794 AR8216_PORT_STATUS_LINK_UP
|
795 (ar8xxx_has_gige(priv
) ?
796 AR8216_PORT_SPEED_1000M
: AR8216_PORT_SPEED_100M
) |
797 AR8216_PORT_STATUS_TXMAC
|
798 AR8216_PORT_STATUS_RXMAC
|
799 (chip_is_ar8316(priv
) ? AR8216_PORT_STATUS_RXFLOW
: 0) |
800 (chip_is_ar8316(priv
) ? AR8216_PORT_STATUS_TXFLOW
: 0) |
801 AR8216_PORT_STATUS_DUPLEX
);
803 priv
->write(priv
, AR8216_REG_PORT_STATUS(port
),
804 AR8216_PORT_STATUS_LINK_AUTO
);
808 static const struct ar8xxx_chip ar8216_chip
= {
809 .caps
= AR8XXX_CAP_MIB_COUNTERS
,
811 .hw_init
= ar8216_hw_init
,
812 .init_globals
= ar8216_init_globals
,
813 .init_port
= ar8216_init_port
,
814 .setup_port
= ar8216_setup_port
,
815 .read_port_status
= ar8216_read_port_status
,
816 .atu_flush
= ar8216_atu_flush
,
817 .vtu_flush
= ar8216_vtu_flush
,
818 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
820 .num_mibs
= ARRAY_SIZE(ar8216_mibs
),
821 .mib_decs
= ar8216_mibs
,
825 ar8236_setup_port(struct ar8xxx_priv
*priv
, int port
, u32 members
)
831 pvid
= priv
->vlan_id
[priv
->pvid
[port
]];
832 if (priv
->vlan_tagged
& (1 << port
))
833 egress
= AR8216_OUT_ADD_VLAN
;
835 egress
= AR8216_OUT_STRIP_VLAN
;
836 ingress
= AR8216_IN_SECURE
;
839 egress
= AR8216_OUT_KEEP
;
840 ingress
= AR8216_IN_PORT_ONLY
;
843 ar8xxx_rmw(priv
, AR8216_REG_PORT_CTRL(port
),
844 AR8216_PORT_CTRL_LEARN
| AR8216_PORT_CTRL_VLAN_MODE
|
845 AR8216_PORT_CTRL_SINGLE_VLAN
| AR8216_PORT_CTRL_STATE
|
846 AR8216_PORT_CTRL_HEADER
| AR8216_PORT_CTRL_LEARN_LOCK
,
847 AR8216_PORT_CTRL_LEARN
|
848 (egress
<< AR8216_PORT_CTRL_VLAN_MODE_S
) |
849 (AR8216_PORT_STATE_FORWARD
<< AR8216_PORT_CTRL_STATE_S
));
851 ar8xxx_rmw(priv
, AR8236_REG_PORT_VLAN(port
),
852 AR8236_PORT_VLAN_DEFAULT_ID
,
853 (pvid
<< AR8236_PORT_VLAN_DEFAULT_ID_S
));
855 ar8xxx_rmw(priv
, AR8236_REG_PORT_VLAN2(port
),
856 AR8236_PORT_VLAN2_VLAN_MODE
|
857 AR8236_PORT_VLAN2_MEMBER
,
858 (ingress
<< AR8236_PORT_VLAN2_VLAN_MODE_S
) |
859 (members
<< AR8236_PORT_VLAN2_MEMBER_S
));
863 ar8236_hw_init(struct ar8xxx_priv
*priv
)
868 if (priv
->initialized
)
871 /* Initialize the PHYs */
873 for (i
= 0; i
< AR8XXX_NUM_PHYS
; i
++) {
874 mdiobus_write(bus
, i
, MII_ADVERTISE
,
875 ADVERTISE_ALL
| ADVERTISE_PAUSE_CAP
|
876 ADVERTISE_PAUSE_ASYM
);
877 mdiobus_write(bus
, i
, MII_BMCR
, BMCR_RESET
| BMCR_ANENABLE
);
881 priv
->initialized
= true;
886 ar8236_init_globals(struct ar8xxx_priv
*priv
)
888 /* enable jumbo frames */
889 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
890 AR8316_GCTRL_MTU
, 9018 + 8 + 2);
892 /* Enable MIB counters */
893 ar8xxx_rmw(priv
, AR8216_REG_MIB_FUNC
, AR8216_MIB_FUNC
| AR8236_MIB_EN
,
894 (AR8216_MIB_FUNC_NO_OP
<< AR8216_MIB_FUNC_S
) |
898 static const struct ar8xxx_chip ar8236_chip
= {
899 .caps
= AR8XXX_CAP_MIB_COUNTERS
,
900 .hw_init
= ar8236_hw_init
,
901 .init_globals
= ar8236_init_globals
,
902 .init_port
= ar8216_init_port
,
903 .setup_port
= ar8236_setup_port
,
904 .read_port_status
= ar8216_read_port_status
,
905 .atu_flush
= ar8216_atu_flush
,
906 .vtu_flush
= ar8216_vtu_flush
,
907 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
909 .num_mibs
= ARRAY_SIZE(ar8236_mibs
),
910 .mib_decs
= ar8236_mibs
,
914 ar8316_hw_init(struct ar8xxx_priv
*priv
)
920 val
= priv
->read(priv
, AR8316_REG_POSTRIP
);
922 if (priv
->phy
->interface
== PHY_INTERFACE_MODE_RGMII
) {
923 if (priv
->port4_phy
) {
924 /* value taken from Ubiquiti RouterStation Pro */
926 pr_info("ar8316: Using port 4 as PHY\n");
929 pr_info("ar8316: Using port 4 as switch port\n");
931 } else if (priv
->phy
->interface
== PHY_INTERFACE_MODE_GMII
) {
932 /* value taken from AVM Fritz!Box 7390 sources */
935 /* no known value for phy interface */
936 pr_err("ar8316: unsupported mii mode: %d.\n",
937 priv
->phy
->interface
);
944 priv
->write(priv
, AR8316_REG_POSTRIP
, newval
);
946 if (priv
->port4_phy
&&
947 priv
->phy
->interface
== PHY_INTERFACE_MODE_RGMII
) {
948 /* work around for phy4 rgmii mode */
949 ar8xxx_phy_dbg_write(priv
, 4, 0x12, 0x480c);
951 ar8xxx_phy_dbg_write(priv
, 4, 0x0, 0x824e);
953 ar8xxx_phy_dbg_write(priv
, 4, 0x5, 0x3d47);
957 /* Initialize the ports */
959 for (i
= 0; i
< AR8XXX_NUM_PHYS
; i
++) {
960 /* initialize the port itself */
961 mdiobus_write(bus
, i
, MII_ADVERTISE
,
962 ADVERTISE_ALL
| ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
);
963 mdiobus_write(bus
, i
, MII_CTRL1000
, ADVERTISE_1000FULL
);
964 mdiobus_write(bus
, i
, MII_BMCR
, BMCR_RESET
| BMCR_ANENABLE
);
970 priv
->initialized
= true;
975 ar8316_init_globals(struct ar8xxx_priv
*priv
)
977 /* standard atheros magic */
978 priv
->write(priv
, 0x38, 0xc000050e);
980 /* enable cpu port to receive multicast and broadcast frames */
981 priv
->write(priv
, AR8216_REG_FLOOD_MASK
, 0x003f003f);
983 /* enable jumbo frames */
984 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
985 AR8316_GCTRL_MTU
, 9018 + 8 + 2);
987 /* Enable MIB counters */
988 ar8xxx_rmw(priv
, AR8216_REG_MIB_FUNC
, AR8216_MIB_FUNC
| AR8236_MIB_EN
,
989 (AR8216_MIB_FUNC_NO_OP
<< AR8216_MIB_FUNC_S
) |
993 static const struct ar8xxx_chip ar8316_chip
= {
994 .caps
= AR8XXX_CAP_GIGE
| AR8XXX_CAP_MIB_COUNTERS
,
995 .hw_init
= ar8316_hw_init
,
996 .init_globals
= ar8316_init_globals
,
997 .init_port
= ar8216_init_port
,
998 .setup_port
= ar8216_setup_port
,
999 .read_port_status
= ar8216_read_port_status
,
1000 .atu_flush
= ar8216_atu_flush
,
1001 .vtu_flush
= ar8216_vtu_flush
,
1002 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
1004 .num_mibs
= ARRAY_SIZE(ar8236_mibs
),
1005 .mib_decs
= ar8236_mibs
,
1009 ar8327_get_pad_cfg(struct ar8327_pad_cfg
*cfg
)
1017 switch (cfg
->mode
) {
1021 case AR8327_PAD_MAC2MAC_MII
:
1022 t
= AR8327_PAD_MAC_MII_EN
;
1024 t
|= AR8327_PAD_MAC_MII_RXCLK_SEL
;
1026 t
|= AR8327_PAD_MAC_MII_TXCLK_SEL
;
1029 case AR8327_PAD_MAC2MAC_GMII
:
1030 t
= AR8327_PAD_MAC_GMII_EN
;
1032 t
|= AR8327_PAD_MAC_GMII_RXCLK_SEL
;
1034 t
|= AR8327_PAD_MAC_GMII_TXCLK_SEL
;
1037 case AR8327_PAD_MAC_SGMII
:
1038 t
= AR8327_PAD_SGMII_EN
;
1041 * WAR for the QUalcomm Atheros AP136 board.
1042 * It seems that RGMII TX/RX delay settings needs to be
1043 * applied for SGMII mode as well, The ethernet is not
1044 * reliable without this.
1046 t
|= cfg
->txclk_delay_sel
<< AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S
;
1047 t
|= cfg
->rxclk_delay_sel
<< AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S
;
1048 if (cfg
->rxclk_delay_en
)
1049 t
|= AR8327_PAD_RGMII_RXCLK_DELAY_EN
;
1050 if (cfg
->txclk_delay_en
)
1051 t
|= AR8327_PAD_RGMII_TXCLK_DELAY_EN
;
1053 if (cfg
->sgmii_delay_en
)
1054 t
|= AR8327_PAD_SGMII_DELAY_EN
;
1058 case AR8327_PAD_MAC2PHY_MII
:
1059 t
= AR8327_PAD_PHY_MII_EN
;
1061 t
|= AR8327_PAD_PHY_MII_RXCLK_SEL
;
1063 t
|= AR8327_PAD_PHY_MII_TXCLK_SEL
;
1066 case AR8327_PAD_MAC2PHY_GMII
:
1067 t
= AR8327_PAD_PHY_GMII_EN
;
1068 if (cfg
->pipe_rxclk_sel
)
1069 t
|= AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL
;
1071 t
|= AR8327_PAD_PHY_GMII_RXCLK_SEL
;
1073 t
|= AR8327_PAD_PHY_GMII_TXCLK_SEL
;
1076 case AR8327_PAD_MAC_RGMII
:
1077 t
= AR8327_PAD_RGMII_EN
;
1078 t
|= cfg
->txclk_delay_sel
<< AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S
;
1079 t
|= cfg
->rxclk_delay_sel
<< AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S
;
1080 if (cfg
->rxclk_delay_en
)
1081 t
|= AR8327_PAD_RGMII_RXCLK_DELAY_EN
;
1082 if (cfg
->txclk_delay_en
)
1083 t
|= AR8327_PAD_RGMII_TXCLK_DELAY_EN
;
1086 case AR8327_PAD_PHY_GMII
:
1087 t
= AR8327_PAD_PHYX_GMII_EN
;
1090 case AR8327_PAD_PHY_RGMII
:
1091 t
= AR8327_PAD_PHYX_RGMII_EN
;
1094 case AR8327_PAD_PHY_MII
:
1095 t
= AR8327_PAD_PHYX_MII_EN
;
1103 ar8327_phy_fixup(struct ar8xxx_priv
*priv
, int phy
)
1105 switch (priv
->chip_rev
) {
1107 /* For 100M waveform */
1108 ar8xxx_phy_dbg_write(priv
, phy
, 0, 0x02ea);
1109 /* Turn on Gigabit clock */
1110 ar8xxx_phy_dbg_write(priv
, phy
, 0x3d, 0x68a0);
1114 ar8xxx_phy_mmd_write(priv
, phy
, 0x7, 0x3c);
1115 ar8xxx_phy_mmd_write(priv
, phy
, 0x4007, 0x0);
1118 ar8xxx_phy_mmd_write(priv
, phy
, 0x3, 0x800d);
1119 ar8xxx_phy_mmd_write(priv
, phy
, 0x4003, 0x803f);
1121 ar8xxx_phy_dbg_write(priv
, phy
, 0x3d, 0x6860);
1122 ar8xxx_phy_dbg_write(priv
, phy
, 0x5, 0x2c46);
1123 ar8xxx_phy_dbg_write(priv
, phy
, 0x3c, 0x6000);
1129 ar8327_get_port_init_status(struct ar8327_port_cfg
*cfg
)
1133 if (!cfg
->force_link
)
1134 return AR8216_PORT_STATUS_LINK_AUTO
;
1136 t
= AR8216_PORT_STATUS_TXMAC
| AR8216_PORT_STATUS_RXMAC
;
1137 t
|= cfg
->duplex
? AR8216_PORT_STATUS_DUPLEX
: 0;
1138 t
|= cfg
->rxpause
? AR8216_PORT_STATUS_RXFLOW
: 0;
1139 t
|= cfg
->txpause
? AR8216_PORT_STATUS_TXFLOW
: 0;
1141 switch (cfg
->speed
) {
1142 case AR8327_PORT_SPEED_10
:
1143 t
|= AR8216_PORT_SPEED_10M
;
1145 case AR8327_PORT_SPEED_100
:
1146 t
|= AR8216_PORT_SPEED_100M
;
1148 case AR8327_PORT_SPEED_1000
:
1149 t
|= AR8216_PORT_SPEED_1000M
;
1156 #define AR8327_LED_ENTRY(_num, _reg, _shift) \
1157 [_num] = { .reg = (_reg), .shift = (_shift) }
1159 static const struct ar8327_led_entry
1160 ar8327_led_map
[AR8327_NUM_LEDS
] = {
1161 AR8327_LED_ENTRY(AR8327_LED_PHY0_0
, 0, 14),
1162 AR8327_LED_ENTRY(AR8327_LED_PHY0_1
, 1, 14),
1163 AR8327_LED_ENTRY(AR8327_LED_PHY0_2
, 2, 14),
1165 AR8327_LED_ENTRY(AR8327_LED_PHY1_0
, 3, 8),
1166 AR8327_LED_ENTRY(AR8327_LED_PHY1_1
, 3, 10),
1167 AR8327_LED_ENTRY(AR8327_LED_PHY1_2
, 3, 12),
1169 AR8327_LED_ENTRY(AR8327_LED_PHY2_0
, 3, 14),
1170 AR8327_LED_ENTRY(AR8327_LED_PHY2_1
, 3, 16),
1171 AR8327_LED_ENTRY(AR8327_LED_PHY2_2
, 3, 18),
1173 AR8327_LED_ENTRY(AR8327_LED_PHY3_0
, 3, 20),
1174 AR8327_LED_ENTRY(AR8327_LED_PHY3_1
, 3, 22),
1175 AR8327_LED_ENTRY(AR8327_LED_PHY3_2
, 3, 24),
1177 AR8327_LED_ENTRY(AR8327_LED_PHY4_0
, 0, 30),
1178 AR8327_LED_ENTRY(AR8327_LED_PHY4_1
, 1, 30),
1179 AR8327_LED_ENTRY(AR8327_LED_PHY4_2
, 2, 30),
1183 ar8327_set_led_pattern(struct ar8xxx_priv
*priv
, unsigned int led_num
,
1184 enum ar8327_led_pattern pattern
)
1186 const struct ar8327_led_entry
*entry
;
1188 entry
= &ar8327_led_map
[led_num
];
1189 ar8xxx_rmw(priv
, AR8327_REG_LED_CTRL(entry
->reg
),
1190 (3 << entry
->shift
), pattern
<< entry
->shift
);
1194 ar8327_led_work_func(struct work_struct
*work
)
1196 struct ar8327_led
*aled
;
1199 aled
= container_of(work
, struct ar8327_led
, led_work
);
1201 spin_lock(&aled
->lock
);
1202 pattern
= aled
->pattern
;
1203 spin_unlock(&aled
->lock
);
1205 ar8327_set_led_pattern(aled
->sw_priv
, aled
->led_num
,
1210 ar8327_led_schedule_change(struct ar8327_led
*aled
, u8 pattern
)
1212 if (aled
->pattern
== pattern
)
1215 aled
->pattern
= pattern
;
1216 schedule_work(&aled
->led_work
);
1219 static inline struct ar8327_led
*
1220 led_cdev_to_ar8327_led(struct led_classdev
*led_cdev
)
1222 return container_of(led_cdev
, struct ar8327_led
, cdev
);
1226 ar8327_led_blink_set(struct led_classdev
*led_cdev
,
1227 unsigned long *delay_on
,
1228 unsigned long *delay_off
)
1230 struct ar8327_led
*aled
= led_cdev_to_ar8327_led(led_cdev
);
1232 if (*delay_on
== 0 && *delay_off
== 0) {
1237 if (*delay_on
!= 125 || *delay_off
!= 125) {
1239 * The hardware only supports blinking at 4Hz. Fall back
1240 * to software implementation in other cases.
1245 spin_lock(&aled
->lock
);
1247 aled
->enable_hw_mode
= false;
1248 ar8327_led_schedule_change(aled
, AR8327_LED_PATTERN_BLINK
);
1250 spin_unlock(&aled
->lock
);
1256 ar8327_led_set_brightness(struct led_classdev
*led_cdev
,
1257 enum led_brightness brightness
)
1259 struct ar8327_led
*aled
= led_cdev_to_ar8327_led(led_cdev
);
1263 active
= (brightness
!= LED_OFF
);
1264 active
^= aled
->active_low
;
1266 pattern
= (active
) ? AR8327_LED_PATTERN_ON
:
1267 AR8327_LED_PATTERN_OFF
;
1269 spin_lock(&aled
->lock
);
1271 aled
->enable_hw_mode
= false;
1272 ar8327_led_schedule_change(aled
, pattern
);
1274 spin_unlock(&aled
->lock
);
1278 ar8327_led_enable_hw_mode_show(struct device
*dev
,
1279 struct device_attribute
*attr
,
1282 struct led_classdev
*led_cdev
= dev_get_drvdata(dev
);
1283 struct ar8327_led
*aled
= led_cdev_to_ar8327_led(led_cdev
);
1286 spin_lock(&aled
->lock
);
1287 ret
+= sprintf(buf
, "%d\n", aled
->enable_hw_mode
);
1288 spin_unlock(&aled
->lock
);
1294 ar8327_led_enable_hw_mode_store(struct device
*dev
,
1295 struct device_attribute
*attr
,
1299 struct led_classdev
*led_cdev
= dev_get_drvdata(dev
);
1300 struct ar8327_led
*aled
= led_cdev_to_ar8327_led(led_cdev
);
1305 ret
= kstrtou8(buf
, 10, &value
);
1309 spin_lock(&aled
->lock
);
1311 aled
->enable_hw_mode
= !!value
;
1312 if (aled
->enable_hw_mode
)
1313 pattern
= AR8327_LED_PATTERN_RULE
;
1315 pattern
= AR8327_LED_PATTERN_OFF
;
1317 ar8327_led_schedule_change(aled
, pattern
);
1319 spin_unlock(&aled
->lock
);
1324 static DEVICE_ATTR(enable_hw_mode
, S_IRUGO
| S_IWUSR
,
1325 ar8327_led_enable_hw_mode_show
,
1326 ar8327_led_enable_hw_mode_store
);
1329 ar8327_led_register(struct ar8xxx_priv
*priv
, struct ar8327_led
*aled
)
1333 ret
= led_classdev_register(NULL
, &aled
->cdev
);
1337 if (aled
->mode
== AR8327_LED_MODE_HW
) {
1338 ret
= device_create_file(aled
->cdev
.dev
,
1339 &dev_attr_enable_hw_mode
);
1341 goto err_unregister
;
1347 led_classdev_unregister(&aled
->cdev
);
1352 ar8327_led_unregister(struct ar8327_led
*aled
)
1354 if (aled
->mode
== AR8327_LED_MODE_HW
)
1355 device_remove_file(aled
->cdev
.dev
, &dev_attr_enable_hw_mode
);
1357 led_classdev_unregister(&aled
->cdev
);
1358 cancel_work_sync(&aled
->led_work
);
1362 ar8327_led_create(struct ar8xxx_priv
*priv
,
1363 const struct ar8327_led_info
*led_info
)
1365 struct ar8327_data
*data
= &priv
->chip_data
.ar8327
;
1366 struct ar8327_led
*aled
;
1369 if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS
))
1372 if (!led_info
->name
)
1375 if (led_info
->led_num
>= AR8327_NUM_LEDS
)
1378 aled
= kzalloc(sizeof(*aled
) + strlen(led_info
->name
) + 1,
1383 aled
->sw_priv
= priv
;
1384 aled
->led_num
= led_info
->led_num
;
1385 aled
->active_low
= led_info
->active_low
;
1386 aled
->mode
= led_info
->mode
;
1388 if (aled
->mode
== AR8327_LED_MODE_HW
)
1389 aled
->enable_hw_mode
= true;
1391 aled
->name
= (char *)(aled
+ 1);
1392 strcpy(aled
->name
, led_info
->name
);
1394 aled
->cdev
.name
= aled
->name
;
1395 aled
->cdev
.brightness_set
= ar8327_led_set_brightness
;
1396 aled
->cdev
.blink_set
= ar8327_led_blink_set
;
1397 aled
->cdev
.default_trigger
= led_info
->default_trigger
;
1399 spin_lock_init(&aled
->lock
);
1400 mutex_init(&aled
->mutex
);
1401 INIT_WORK(&aled
->led_work
, ar8327_led_work_func
);
1403 ret
= ar8327_led_register(priv
, aled
);
1407 data
->leds
[data
->num_leds
++] = aled
;
1417 ar8327_led_destroy(struct ar8327_led
*aled
)
1419 ar8327_led_unregister(aled
);
1424 ar8327_leds_init(struct ar8xxx_priv
*priv
)
1426 struct ar8327_data
*data
;
1429 if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS
))
1432 data
= &priv
->chip_data
.ar8327
;
1434 for (i
= 0; i
< data
->num_leds
; i
++) {
1435 struct ar8327_led
*aled
;
1437 aled
= data
->leds
[i
];
1439 if (aled
->enable_hw_mode
)
1440 aled
->pattern
= AR8327_LED_PATTERN_RULE
;
1442 aled
->pattern
= AR8327_LED_PATTERN_OFF
;
1444 ar8327_set_led_pattern(priv
, aled
->led_num
, aled
->pattern
);
1449 ar8327_leds_cleanup(struct ar8xxx_priv
*priv
)
1451 struct ar8327_data
*data
= &priv
->chip_data
.ar8327
;
1454 if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS
))
1457 for (i
= 0; i
< data
->num_leds
; i
++) {
1458 struct ar8327_led
*aled
;
1460 aled
= data
->leds
[i
];
1461 ar8327_led_destroy(aled
);
1468 ar8327_hw_config_pdata(struct ar8xxx_priv
*priv
,
1469 struct ar8327_platform_data
*pdata
)
1471 struct ar8327_led_cfg
*led_cfg
;
1472 struct ar8327_data
*data
;
1479 priv
->get_port_link
= pdata
->get_port_link
;
1481 data
= &priv
->chip_data
.ar8327
;
1483 data
->port0_status
= ar8327_get_port_init_status(&pdata
->port0_cfg
);
1484 data
->port6_status
= ar8327_get_port_init_status(&pdata
->port6_cfg
);
1486 t
= ar8327_get_pad_cfg(pdata
->pad0_cfg
);
1487 if (chip_is_ar8337(priv
))
1488 t
|= AR8337_PAD_MAC06_EXCHANGE_EN
;
1490 priv
->write(priv
, AR8327_REG_PAD0_MODE
, t
);
1491 t
= ar8327_get_pad_cfg(pdata
->pad5_cfg
);
1492 priv
->write(priv
, AR8327_REG_PAD5_MODE
, t
);
1493 t
= ar8327_get_pad_cfg(pdata
->pad6_cfg
);
1494 priv
->write(priv
, AR8327_REG_PAD6_MODE
, t
);
1496 pos
= priv
->read(priv
, AR8327_REG_POWER_ON_STRIP
);
1499 led_cfg
= pdata
->led_cfg
;
1501 if (led_cfg
->open_drain
)
1502 new_pos
|= AR8327_POWER_ON_STRIP_LED_OPEN_EN
;
1504 new_pos
&= ~AR8327_POWER_ON_STRIP_LED_OPEN_EN
;
1506 priv
->write(priv
, AR8327_REG_LED_CTRL0
, led_cfg
->led_ctrl0
);
1507 priv
->write(priv
, AR8327_REG_LED_CTRL1
, led_cfg
->led_ctrl1
);
1508 priv
->write(priv
, AR8327_REG_LED_CTRL2
, led_cfg
->led_ctrl2
);
1509 priv
->write(priv
, AR8327_REG_LED_CTRL3
, led_cfg
->led_ctrl3
);
1512 new_pos
|= AR8327_POWER_ON_STRIP_POWER_ON_SEL
;
1515 if (pdata
->sgmii_cfg
) {
1516 t
= pdata
->sgmii_cfg
->sgmii_ctrl
;
1517 if (priv
->chip_rev
== 1)
1518 t
|= AR8327_SGMII_CTRL_EN_PLL
|
1519 AR8327_SGMII_CTRL_EN_RX
|
1520 AR8327_SGMII_CTRL_EN_TX
;
1522 t
&= ~(AR8327_SGMII_CTRL_EN_PLL
|
1523 AR8327_SGMII_CTRL_EN_RX
|
1524 AR8327_SGMII_CTRL_EN_TX
);
1526 priv
->write(priv
, AR8327_REG_SGMII_CTRL
, t
);
1528 if (pdata
->sgmii_cfg
->serdes_aen
)
1529 new_pos
&= ~AR8327_POWER_ON_STRIP_SERDES_AEN
;
1531 new_pos
|= AR8327_POWER_ON_STRIP_SERDES_AEN
;
1534 priv
->write(priv
, AR8327_REG_POWER_ON_STRIP
, new_pos
);
1536 if (pdata
->leds
&& pdata
->num_leds
) {
1539 data
->leds
= kzalloc(pdata
->num_leds
* sizeof(void *),
1544 for (i
= 0; i
< pdata
->num_leds
; i
++)
1545 ar8327_led_create(priv
, &pdata
->leds
[i
]);
1553 ar8327_hw_config_of(struct ar8xxx_priv
*priv
, struct device_node
*np
)
1555 const __be32
*paddr
;
1559 paddr
= of_get_property(np
, "qca,ar8327-initvals", &len
);
1560 if (!paddr
|| len
< (2 * sizeof(*paddr
)))
1563 len
/= sizeof(*paddr
);
1565 for (i
= 0; i
< len
- 1; i
+= 2) {
1569 reg
= be32_to_cpup(paddr
+ i
);
1570 val
= be32_to_cpup(paddr
+ i
+ 1);
1573 case AR8327_REG_PORT_STATUS(0):
1574 priv
->chip_data
.ar8327
.port0_status
= val
;
1576 case AR8327_REG_PORT_STATUS(6):
1577 priv
->chip_data
.ar8327
.port6_status
= val
;
1580 priv
->write(priv
, reg
, val
);
1589 ar8327_hw_config_of(struct ar8xxx_priv
*priv
, struct device_node
*np
)
1596 ar8327_hw_init(struct ar8xxx_priv
*priv
)
1598 struct mii_bus
*bus
;
1602 if (priv
->phy
->dev
.of_node
)
1603 ret
= ar8327_hw_config_of(priv
, priv
->phy
->dev
.of_node
);
1605 ret
= ar8327_hw_config_pdata(priv
,
1606 priv
->phy
->dev
.platform_data
);
1611 ar8327_leds_init(priv
);
1613 bus
= priv
->mii_bus
;
1614 for (i
= 0; i
< AR8XXX_NUM_PHYS
; i
++) {
1615 ar8327_phy_fixup(priv
, i
);
1617 /* start aneg on the PHY */
1618 mdiobus_write(bus
, i
, MII_ADVERTISE
, ADVERTISE_ALL
|
1619 ADVERTISE_PAUSE_CAP
|
1620 ADVERTISE_PAUSE_ASYM
);
1621 mdiobus_write(bus
, i
, MII_CTRL1000
, ADVERTISE_1000FULL
);
1622 mdiobus_write(bus
, i
, MII_BMCR
, BMCR_RESET
| BMCR_ANENABLE
);
1631 ar8327_cleanup(struct ar8xxx_priv
*priv
)
1633 ar8327_leds_cleanup(priv
);
1637 ar8327_init_globals(struct ar8xxx_priv
*priv
)
1641 /* enable CPU port and disable mirror port */
1642 t
= AR8327_FWD_CTRL0_CPU_PORT_EN
|
1643 AR8327_FWD_CTRL0_MIRROR_PORT
;
1644 priv
->write(priv
, AR8327_REG_FWD_CTRL0
, t
);
1646 /* forward multicast and broadcast frames to CPU */
1647 t
= (AR8327_PORTS_ALL
<< AR8327_FWD_CTRL1_UC_FLOOD_S
) |
1648 (AR8327_PORTS_ALL
<< AR8327_FWD_CTRL1_MC_FLOOD_S
) |
1649 (AR8327_PORTS_ALL
<< AR8327_FWD_CTRL1_BC_FLOOD_S
);
1650 priv
->write(priv
, AR8327_REG_FWD_CTRL1
, t
);
1652 /* enable jumbo frames */
1653 ar8xxx_rmw(priv
, AR8327_REG_MAX_FRAME_SIZE
,
1654 AR8327_MAX_FRAME_SIZE_MTU
, 9018 + 8 + 2);
1656 /* Enable MIB counters */
1657 ar8xxx_reg_set(priv
, AR8327_REG_MODULE_EN
,
1658 AR8327_MODULE_EN_MIB
);
1660 /* Disable EEE on all ports due to stability issues */
1661 t
= priv
->read(priv
, AR8327_REG_EEE_CTRL
);
1662 t
|= AR8327_EEE_CTRL_DISABLE_PHY(0) |
1663 AR8327_EEE_CTRL_DISABLE_PHY(1) |
1664 AR8327_EEE_CTRL_DISABLE_PHY(2) |
1665 AR8327_EEE_CTRL_DISABLE_PHY(3) |
1666 AR8327_EEE_CTRL_DISABLE_PHY(4);
1667 priv
->write(priv
, AR8327_REG_EEE_CTRL
, t
);
1671 ar8327_init_port(struct ar8xxx_priv
*priv
, int port
)
1675 if (port
== AR8216_PORT_CPU
)
1676 t
= priv
->chip_data
.ar8327
.port0_status
;
1678 t
= priv
->chip_data
.ar8327
.port6_status
;
1680 t
= AR8216_PORT_STATUS_LINK_AUTO
;
1682 priv
->write(priv
, AR8327_REG_PORT_STATUS(port
), t
);
1683 priv
->write(priv
, AR8327_REG_PORT_HEADER(port
), 0);
1685 t
= 1 << AR8327_PORT_VLAN0_DEF_SVID_S
;
1686 t
|= 1 << AR8327_PORT_VLAN0_DEF_CVID_S
;
1687 priv
->write(priv
, AR8327_REG_PORT_VLAN0(port
), t
);
1689 t
= AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH
<< AR8327_PORT_VLAN1_OUT_MODE_S
;
1690 priv
->write(priv
, AR8327_REG_PORT_VLAN1(port
), t
);
1692 t
= AR8327_PORT_LOOKUP_LEARN
;
1693 t
|= AR8216_PORT_STATE_FORWARD
<< AR8327_PORT_LOOKUP_STATE_S
;
1694 priv
->write(priv
, AR8327_REG_PORT_LOOKUP(port
), t
);
1698 ar8327_read_port_status(struct ar8xxx_priv
*priv
, int port
)
1700 return priv
->read(priv
, AR8327_REG_PORT_STATUS(port
));
1704 ar8327_atu_flush(struct ar8xxx_priv
*priv
)
1708 ret
= ar8216_wait_bit(priv
, AR8327_REG_ATU_FUNC
,
1709 AR8327_ATU_FUNC_BUSY
, 0);
1711 priv
->write(priv
, AR8327_REG_ATU_FUNC
,
1712 AR8327_ATU_FUNC_OP_FLUSH
);
1718 ar8327_vtu_op(struct ar8xxx_priv
*priv
, u32 op
, u32 val
)
1720 if (ar8216_wait_bit(priv
, AR8327_REG_VTU_FUNC1
,
1721 AR8327_VTU_FUNC1_BUSY
, 0))
1724 if ((op
& AR8327_VTU_FUNC1_OP
) == AR8327_VTU_FUNC1_OP_LOAD
)
1725 priv
->write(priv
, AR8327_REG_VTU_FUNC0
, val
);
1727 op
|= AR8327_VTU_FUNC1_BUSY
;
1728 priv
->write(priv
, AR8327_REG_VTU_FUNC1
, op
);
1732 ar8327_vtu_flush(struct ar8xxx_priv
*priv
)
1734 ar8327_vtu_op(priv
, AR8327_VTU_FUNC1_OP_FLUSH
, 0);
1738 ar8327_vtu_load_vlan(struct ar8xxx_priv
*priv
, u32 vid
, u32 port_mask
)
1744 op
= AR8327_VTU_FUNC1_OP_LOAD
| (vid
<< AR8327_VTU_FUNC1_VID_S
);
1745 val
= AR8327_VTU_FUNC0_VALID
| AR8327_VTU_FUNC0_IVL
;
1746 for (i
= 0; i
< AR8327_NUM_PORTS
; i
++) {
1749 if ((port_mask
& BIT(i
)) == 0)
1750 mode
= AR8327_VTU_FUNC0_EG_MODE_NOT
;
1751 else if (priv
->vlan
== 0)
1752 mode
= AR8327_VTU_FUNC0_EG_MODE_KEEP
;
1753 else if ((priv
->vlan_tagged
& BIT(i
)) || (priv
->vlan_id
[priv
->pvid
[i
]] != vid
))
1754 mode
= AR8327_VTU_FUNC0_EG_MODE_TAG
;
1756 mode
= AR8327_VTU_FUNC0_EG_MODE_UNTAG
;
1758 val
|= mode
<< AR8327_VTU_FUNC0_EG_MODE_S(i
);
1760 ar8327_vtu_op(priv
, op
, val
);
1764 ar8327_setup_port(struct ar8xxx_priv
*priv
, int port
, u32 members
)
1767 u32 egress
, ingress
;
1768 u32 pvid
= priv
->vlan_id
[priv
->pvid
[port
]];
1771 egress
= AR8327_PORT_VLAN1_OUT_MODE_UNMOD
;
1772 ingress
= AR8216_IN_SECURE
;
1774 egress
= AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH
;
1775 ingress
= AR8216_IN_PORT_ONLY
;
1778 t
= pvid
<< AR8327_PORT_VLAN0_DEF_SVID_S
;
1779 t
|= pvid
<< AR8327_PORT_VLAN0_DEF_CVID_S
;
1780 priv
->write(priv
, AR8327_REG_PORT_VLAN0(port
), t
);
1782 t
= AR8327_PORT_VLAN1_PORT_VLAN_PROP
;
1783 t
|= egress
<< AR8327_PORT_VLAN1_OUT_MODE_S
;
1784 priv
->write(priv
, AR8327_REG_PORT_VLAN1(port
), t
);
1787 t
|= AR8327_PORT_LOOKUP_LEARN
;
1788 t
|= ingress
<< AR8327_PORT_LOOKUP_IN_MODE_S
;
1789 t
|= AR8216_PORT_STATE_FORWARD
<< AR8327_PORT_LOOKUP_STATE_S
;
1790 priv
->write(priv
, AR8327_REG_PORT_LOOKUP(port
), t
);
1793 static const struct ar8xxx_chip ar8327_chip
= {
1794 .caps
= AR8XXX_CAP_GIGE
| AR8XXX_CAP_MIB_COUNTERS
,
1795 .hw_init
= ar8327_hw_init
,
1796 .cleanup
= ar8327_cleanup
,
1797 .init_globals
= ar8327_init_globals
,
1798 .init_port
= ar8327_init_port
,
1799 .setup_port
= ar8327_setup_port
,
1800 .read_port_status
= ar8327_read_port_status
,
1801 .atu_flush
= ar8327_atu_flush
,
1802 .vtu_flush
= ar8327_vtu_flush
,
1803 .vtu_load_vlan
= ar8327_vtu_load_vlan
,
1805 .num_mibs
= ARRAY_SIZE(ar8236_mibs
),
1806 .mib_decs
= ar8236_mibs
,
1810 ar8xxx_sw_set_vlan(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1811 struct switch_val
*val
)
1813 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1814 priv
->vlan
= !!val
->value
.i
;
1819 ar8xxx_sw_get_vlan(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1820 struct switch_val
*val
)
1822 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1823 val
->value
.i
= priv
->vlan
;
1829 ar8xxx_sw_set_pvid(struct switch_dev
*dev
, int port
, int vlan
)
1831 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1833 /* make sure no invalid PVIDs get set */
1835 if (vlan
>= dev
->vlans
)
1838 priv
->pvid
[port
] = vlan
;
1843 ar8xxx_sw_get_pvid(struct switch_dev
*dev
, int port
, int *vlan
)
1845 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1846 *vlan
= priv
->pvid
[port
];
1851 ar8xxx_sw_set_vid(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1852 struct switch_val
*val
)
1854 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1855 priv
->vlan_id
[val
->port_vlan
] = val
->value
.i
;
1860 ar8xxx_sw_get_vid(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1861 struct switch_val
*val
)
1863 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1864 val
->value
.i
= priv
->vlan_id
[val
->port_vlan
];
1869 ar8xxx_sw_get_port_link(struct switch_dev
*dev
, int port
,
1870 struct switch_port_link
*link
)
1872 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1874 ar8216_read_port_link(priv
, port
, link
);
1879 ar8xxx_sw_get_ports(struct switch_dev
*dev
, struct switch_val
*val
)
1881 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1882 u8 ports
= priv
->vlan_table
[val
->port_vlan
];
1886 for (i
= 0; i
< dev
->ports
; i
++) {
1887 struct switch_port
*p
;
1889 if (!(ports
& (1 << i
)))
1892 p
= &val
->value
.ports
[val
->len
++];
1894 if (priv
->vlan_tagged
& (1 << i
))
1895 p
->flags
= (1 << SWITCH_PORT_FLAG_TAGGED
);
1903 ar8327_sw_get_ports(struct switch_dev
*dev
, struct switch_val
*val
)
1905 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1906 u8 ports
= priv
->vlan_table
[val
->port_vlan
];
1910 for (i
= 0; i
< dev
->ports
; i
++) {
1911 struct switch_port
*p
;
1913 if (!(ports
& (1 << i
)))
1916 p
= &val
->value
.ports
[val
->len
++];
1918 if ((priv
->vlan_tagged
& (1 << i
)) || (priv
->pvid
[i
] != val
->port_vlan
))
1919 p
->flags
= (1 << SWITCH_PORT_FLAG_TAGGED
);
1927 ar8xxx_sw_set_ports(struct switch_dev
*dev
, struct switch_val
*val
)
1929 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1930 u8
*vt
= &priv
->vlan_table
[val
->port_vlan
];
1934 for (i
= 0; i
< val
->len
; i
++) {
1935 struct switch_port
*p
= &val
->value
.ports
[i
];
1937 if (p
->flags
& (1 << SWITCH_PORT_FLAG_TAGGED
)) {
1938 priv
->vlan_tagged
|= (1 << p
->id
);
1940 priv
->vlan_tagged
&= ~(1 << p
->id
);
1941 priv
->pvid
[p
->id
] = val
->port_vlan
;
1943 /* make sure that an untagged port does not
1944 * appear in other vlans */
1945 for (j
= 0; j
< AR8X16_MAX_VLANS
; j
++) {
1946 if (j
== val
->port_vlan
)
1948 priv
->vlan_table
[j
] &= ~(1 << p
->id
);
1958 ar8327_sw_set_ports(struct switch_dev
*dev
, struct switch_val
*val
)
1960 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1961 u8
*vt
= &priv
->vlan_table
[val
->port_vlan
];
1965 for (i
= 0; i
< val
->len
; i
++) {
1966 struct switch_port
*p
= &val
->value
.ports
[i
];
1968 if (p
->flags
& (1 << SWITCH_PORT_FLAG_TAGGED
)) {
1969 if (val
->port_vlan
== priv
->pvid
[p
->id
]) {
1970 priv
->vlan_tagged
|= (1 << p
->id
);
1973 priv
->vlan_tagged
&= ~(1 << p
->id
);
1974 priv
->pvid
[p
->id
] = val
->port_vlan
;
1983 ar8327_set_mirror_regs(struct ar8xxx_priv
*priv
)
1987 /* reset all mirror registers */
1988 ar8xxx_rmw(priv
, AR8327_REG_FWD_CTRL0
,
1989 AR8327_FWD_CTRL0_MIRROR_PORT
,
1990 (0xF << AR8327_FWD_CTRL0_MIRROR_PORT_S
));
1991 for (port
= 0; port
< AR8327_NUM_PORTS
; port
++) {
1992 ar8xxx_rmw(priv
, AR8327_REG_PORT_LOOKUP(port
),
1993 AR8327_PORT_LOOKUP_ING_MIRROR_EN
,
1996 ar8xxx_rmw(priv
, AR8327_REG_PORT_HOL_CTRL1(port
),
1997 AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN
,
2001 /* now enable mirroring if necessary */
2002 if (priv
->source_port
>= AR8327_NUM_PORTS
||
2003 priv
->monitor_port
>= AR8327_NUM_PORTS
||
2004 priv
->source_port
== priv
->monitor_port
) {
2008 ar8xxx_rmw(priv
, AR8327_REG_FWD_CTRL0
,
2009 AR8327_FWD_CTRL0_MIRROR_PORT
,
2010 (priv
->monitor_port
<< AR8327_FWD_CTRL0_MIRROR_PORT_S
));
2012 if (priv
->mirror_rx
)
2013 ar8xxx_rmw(priv
, AR8327_REG_PORT_LOOKUP(priv
->source_port
),
2014 AR8327_PORT_LOOKUP_ING_MIRROR_EN
,
2015 AR8327_PORT_LOOKUP_ING_MIRROR_EN
);
2017 if (priv
->mirror_tx
)
2018 ar8xxx_rmw(priv
, AR8327_REG_PORT_HOL_CTRL1(priv
->source_port
),
2019 AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN
,
2020 AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN
);
2024 ar8216_set_mirror_regs(struct ar8xxx_priv
*priv
)
2028 /* reset all mirror registers */
2029 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CPUPORT
,
2030 AR8216_GLOBAL_CPUPORT_MIRROR_PORT
,
2031 (0xF << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S
));
2032 for (port
= 0; port
< AR8216_NUM_PORTS
; port
++) {
2033 ar8xxx_rmw(priv
, AR8216_REG_PORT_CTRL(port
),
2034 AR8216_PORT_CTRL_MIRROR_RX
,
2037 ar8xxx_rmw(priv
, AR8216_REG_PORT_CTRL(port
),
2038 AR8216_PORT_CTRL_MIRROR_TX
,
2042 /* now enable mirroring if necessary */
2043 if (priv
->source_port
>= AR8216_NUM_PORTS
||
2044 priv
->monitor_port
>= AR8216_NUM_PORTS
||
2045 priv
->source_port
== priv
->monitor_port
) {
2049 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CPUPORT
,
2050 AR8216_GLOBAL_CPUPORT_MIRROR_PORT
,
2051 (priv
->monitor_port
<< AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S
));
2053 if (priv
->mirror_rx
)
2054 ar8xxx_rmw(priv
, AR8216_REG_PORT_CTRL(priv
->source_port
),
2055 AR8216_PORT_CTRL_MIRROR_RX
,
2056 AR8216_PORT_CTRL_MIRROR_RX
);
2058 if (priv
->mirror_tx
)
2059 ar8xxx_rmw(priv
, AR8216_REG_PORT_CTRL(priv
->source_port
),
2060 AR8216_PORT_CTRL_MIRROR_TX
,
2061 AR8216_PORT_CTRL_MIRROR_TX
);
2065 ar8xxx_set_mirror_regs(struct ar8xxx_priv
*priv
)
2067 if (chip_is_ar8327(priv
) || chip_is_ar8337(priv
)) {
2068 ar8327_set_mirror_regs(priv
);
2070 ar8216_set_mirror_regs(priv
);
2075 ar8xxx_sw_hw_apply(struct switch_dev
*dev
)
2077 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
2078 u8 portmask
[AR8X16_MAX_PORTS
];
2081 mutex_lock(&priv
->reg_mutex
);
2082 /* flush all vlan translation unit entries */
2083 priv
->chip
->vtu_flush(priv
);
2085 memset(portmask
, 0, sizeof(portmask
));
2087 /* calculate the port destination masks and load vlans
2088 * into the vlan translation unit */
2089 for (j
= 0; j
< AR8X16_MAX_VLANS
; j
++) {
2090 u8 vp
= priv
->vlan_table
[j
];
2095 for (i
= 0; i
< dev
->ports
; i
++) {
2098 portmask
[i
] |= vp
& ~mask
;
2101 priv
->chip
->vtu_load_vlan(priv
, priv
->vlan_id
[j
],
2102 priv
->vlan_table
[j
]);
2106 * isolate all ports, but connect them to the cpu port */
2107 for (i
= 0; i
< dev
->ports
; i
++) {
2108 if (i
== AR8216_PORT_CPU
)
2111 portmask
[i
] = 1 << AR8216_PORT_CPU
;
2112 portmask
[AR8216_PORT_CPU
] |= (1 << i
);
2116 /* update the port destination mask registers and tag settings */
2117 for (i
= 0; i
< dev
->ports
; i
++) {
2118 priv
->chip
->setup_port(priv
, i
, portmask
[i
]);
2121 ar8xxx_set_mirror_regs(priv
);
2123 mutex_unlock(&priv
->reg_mutex
);
2128 ar8xxx_sw_reset_switch(struct switch_dev
*dev
)
2130 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
2133 mutex_lock(&priv
->reg_mutex
);
2134 memset(&priv
->vlan
, 0, sizeof(struct ar8xxx_priv
) -
2135 offsetof(struct ar8xxx_priv
, vlan
));
2137 for (i
= 0; i
< AR8X16_MAX_VLANS
; i
++)
2138 priv
->vlan_id
[i
] = i
;
2140 /* Configure all ports */
2141 for (i
= 0; i
< dev
->ports
; i
++)
2142 priv
->chip
->init_port(priv
, i
);
2144 priv
->mirror_rx
= false;
2145 priv
->mirror_tx
= false;
2146 priv
->source_port
= 0;
2147 priv
->monitor_port
= 0;
2149 priv
->chip
->init_globals(priv
);
2151 mutex_unlock(&priv
->reg_mutex
);
2153 return ar8xxx_sw_hw_apply(dev
);
2157 ar8xxx_sw_set_reset_mibs(struct switch_dev
*dev
,
2158 const struct switch_attr
*attr
,
2159 struct switch_val
*val
)
2161 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
2165 if (!ar8xxx_has_mib_counters(priv
))
2168 mutex_lock(&priv
->mib_lock
);
2170 len
= priv
->dev
.ports
* priv
->chip
->num_mibs
*
2171 sizeof(*priv
->mib_stats
);
2172 memset(priv
->mib_stats
, '\0', len
);
2173 ret
= ar8xxx_mib_flush(priv
);
2180 mutex_unlock(&priv
->mib_lock
);
2185 ar8xxx_sw_set_mirror_rx_enable(struct switch_dev
*dev
,
2186 const struct switch_attr
*attr
,
2187 struct switch_val
*val
)
2189 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
2191 mutex_lock(&priv
->reg_mutex
);
2192 priv
->mirror_rx
= !!val
->value
.i
;
2193 ar8xxx_set_mirror_regs(priv
);
2194 mutex_unlock(&priv
->reg_mutex
);
2200 ar8xxx_sw_get_mirror_rx_enable(struct switch_dev
*dev
,
2201 const struct switch_attr
*attr
,
2202 struct switch_val
*val
)
2204 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
2205 val
->value
.i
= priv
->mirror_rx
;
2210 ar8xxx_sw_set_mirror_tx_enable(struct switch_dev
*dev
,
2211 const struct switch_attr
*attr
,
2212 struct switch_val
*val
)
2214 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
2216 mutex_lock(&priv
->reg_mutex
);
2217 priv
->mirror_tx
= !!val
->value
.i
;
2218 ar8xxx_set_mirror_regs(priv
);
2219 mutex_unlock(&priv
->reg_mutex
);
2225 ar8xxx_sw_get_mirror_tx_enable(struct switch_dev
*dev
,
2226 const struct switch_attr
*attr
,
2227 struct switch_val
*val
)
2229 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
2230 val
->value
.i
= priv
->mirror_tx
;
2235 ar8xxx_sw_set_mirror_monitor_port(struct switch_dev
*dev
,
2236 const struct switch_attr
*attr
,
2237 struct switch_val
*val
)
2239 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
2241 mutex_lock(&priv
->reg_mutex
);
2242 priv
->monitor_port
= val
->value
.i
;
2243 ar8xxx_set_mirror_regs(priv
);
2244 mutex_unlock(&priv
->reg_mutex
);
2250 ar8xxx_sw_get_mirror_monitor_port(struct switch_dev
*dev
,
2251 const struct switch_attr
*attr
,
2252 struct switch_val
*val
)
2254 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
2255 val
->value
.i
= priv
->monitor_port
;
2260 ar8xxx_sw_set_mirror_source_port(struct switch_dev
*dev
,
2261 const struct switch_attr
*attr
,
2262 struct switch_val
*val
)
2264 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
2266 mutex_lock(&priv
->reg_mutex
);
2267 priv
->source_port
= val
->value
.i
;
2268 ar8xxx_set_mirror_regs(priv
);
2269 mutex_unlock(&priv
->reg_mutex
);
2275 ar8xxx_sw_get_mirror_source_port(struct switch_dev
*dev
,
2276 const struct switch_attr
*attr
,
2277 struct switch_val
*val
)
2279 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
2280 val
->value
.i
= priv
->source_port
;
2285 ar8xxx_sw_set_port_reset_mib(struct switch_dev
*dev
,
2286 const struct switch_attr
*attr
,
2287 struct switch_val
*val
)
2289 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
2293 if (!ar8xxx_has_mib_counters(priv
))
2296 port
= val
->port_vlan
;
2297 if (port
>= dev
->ports
)
2300 mutex_lock(&priv
->mib_lock
);
2301 ret
= ar8xxx_mib_capture(priv
);
2305 ar8xxx_mib_fetch_port_stat(priv
, port
, true);
2310 mutex_unlock(&priv
->mib_lock
);
2315 ar8xxx_sw_get_port_mib(struct switch_dev
*dev
,
2316 const struct switch_attr
*attr
,
2317 struct switch_val
*val
)
2319 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
2320 const struct ar8xxx_chip
*chip
= priv
->chip
;
2324 char *buf
= priv
->buf
;
2327 if (!ar8xxx_has_mib_counters(priv
))
2330 port
= val
->port_vlan
;
2331 if (port
>= dev
->ports
)
2334 mutex_lock(&priv
->mib_lock
);
2335 ret
= ar8xxx_mib_capture(priv
);
2339 ar8xxx_mib_fetch_port_stat(priv
, port
, false);
2341 len
+= snprintf(buf
+ len
, sizeof(priv
->buf
) - len
,
2342 "Port %d MIB counters\n",
2345 mib_stats
= &priv
->mib_stats
[port
* chip
->num_mibs
];
2346 for (i
= 0; i
< chip
->num_mibs
; i
++)
2347 len
+= snprintf(buf
+ len
, sizeof(priv
->buf
) - len
,
2349 chip
->mib_decs
[i
].name
,
2358 mutex_unlock(&priv
->mib_lock
);
2362 static struct switch_attr ar8xxx_sw_attr_globals
[] = {
2364 .type
= SWITCH_TYPE_INT
,
2365 .name
= "enable_vlan",
2366 .description
= "Enable VLAN mode",
2367 .set
= ar8xxx_sw_set_vlan
,
2368 .get
= ar8xxx_sw_get_vlan
,
2372 .type
= SWITCH_TYPE_NOVAL
,
2373 .name
= "reset_mibs",
2374 .description
= "Reset all MIB counters",
2375 .set
= ar8xxx_sw_set_reset_mibs
,
2378 .type
= SWITCH_TYPE_INT
,
2379 .name
= "enable_mirror_rx",
2380 .description
= "Enable mirroring of RX packets",
2381 .set
= ar8xxx_sw_set_mirror_rx_enable
,
2382 .get
= ar8xxx_sw_get_mirror_rx_enable
,
2386 .type
= SWITCH_TYPE_INT
,
2387 .name
= "enable_mirror_tx",
2388 .description
= "Enable mirroring of TX packets",
2389 .set
= ar8xxx_sw_set_mirror_tx_enable
,
2390 .get
= ar8xxx_sw_get_mirror_tx_enable
,
2394 .type
= SWITCH_TYPE_INT
,
2395 .name
= "mirror_monitor_port",
2396 .description
= "Mirror monitor port",
2397 .set
= ar8xxx_sw_set_mirror_monitor_port
,
2398 .get
= ar8xxx_sw_get_mirror_monitor_port
,
2399 .max
= AR8216_NUM_PORTS
- 1
2402 .type
= SWITCH_TYPE_INT
,
2403 .name
= "mirror_source_port",
2404 .description
= "Mirror source port",
2405 .set
= ar8xxx_sw_set_mirror_source_port
,
2406 .get
= ar8xxx_sw_get_mirror_source_port
,
2407 .max
= AR8216_NUM_PORTS
- 1
2411 static struct switch_attr ar8327_sw_attr_globals
[] = {
2413 .type
= SWITCH_TYPE_INT
,
2414 .name
= "enable_vlan",
2415 .description
= "Enable VLAN mode",
2416 .set
= ar8xxx_sw_set_vlan
,
2417 .get
= ar8xxx_sw_get_vlan
,
2421 .type
= SWITCH_TYPE_NOVAL
,
2422 .name
= "reset_mibs",
2423 .description
= "Reset all MIB counters",
2424 .set
= ar8xxx_sw_set_reset_mibs
,
2427 .type
= SWITCH_TYPE_INT
,
2428 .name
= "enable_mirror_rx",
2429 .description
= "Enable mirroring of RX packets",
2430 .set
= ar8xxx_sw_set_mirror_rx_enable
,
2431 .get
= ar8xxx_sw_get_mirror_rx_enable
,
2435 .type
= SWITCH_TYPE_INT
,
2436 .name
= "enable_mirror_tx",
2437 .description
= "Enable mirroring of TX packets",
2438 .set
= ar8xxx_sw_set_mirror_tx_enable
,
2439 .get
= ar8xxx_sw_get_mirror_tx_enable
,
2443 .type
= SWITCH_TYPE_INT
,
2444 .name
= "mirror_monitor_port",
2445 .description
= "Mirror monitor port",
2446 .set
= ar8xxx_sw_set_mirror_monitor_port
,
2447 .get
= ar8xxx_sw_get_mirror_monitor_port
,
2448 .max
= AR8327_NUM_PORTS
- 1
2451 .type
= SWITCH_TYPE_INT
,
2452 .name
= "mirror_source_port",
2453 .description
= "Mirror source port",
2454 .set
= ar8xxx_sw_set_mirror_source_port
,
2455 .get
= ar8xxx_sw_get_mirror_source_port
,
2456 .max
= AR8327_NUM_PORTS
- 1
2460 static struct switch_attr ar8xxx_sw_attr_port
[] = {
2462 .type
= SWITCH_TYPE_NOVAL
,
2463 .name
= "reset_mib",
2464 .description
= "Reset single port MIB counters",
2465 .set
= ar8xxx_sw_set_port_reset_mib
,
2468 .type
= SWITCH_TYPE_STRING
,
2470 .description
= "Get port's MIB counters",
2472 .get
= ar8xxx_sw_get_port_mib
,
2476 static struct switch_attr ar8xxx_sw_attr_vlan
[] = {
2478 .type
= SWITCH_TYPE_INT
,
2480 .description
= "VLAN ID (0-4094)",
2481 .set
= ar8xxx_sw_set_vid
,
2482 .get
= ar8xxx_sw_get_vid
,
2487 static const struct switch_dev_ops ar8xxx_sw_ops
= {
2489 .attr
= ar8xxx_sw_attr_globals
,
2490 .n_attr
= ARRAY_SIZE(ar8xxx_sw_attr_globals
),
2493 .attr
= ar8xxx_sw_attr_port
,
2494 .n_attr
= ARRAY_SIZE(ar8xxx_sw_attr_port
),
2497 .attr
= ar8xxx_sw_attr_vlan
,
2498 .n_attr
= ARRAY_SIZE(ar8xxx_sw_attr_vlan
),
2500 .get_port_pvid
= ar8xxx_sw_get_pvid
,
2501 .set_port_pvid
= ar8xxx_sw_set_pvid
,
2502 .get_vlan_ports
= ar8xxx_sw_get_ports
,
2503 .set_vlan_ports
= ar8xxx_sw_set_ports
,
2504 .apply_config
= ar8xxx_sw_hw_apply
,
2505 .reset_switch
= ar8xxx_sw_reset_switch
,
2506 .get_port_link
= ar8xxx_sw_get_port_link
,
2509 static const struct switch_dev_ops ar8327_sw_ops
= {
2511 .attr
= ar8327_sw_attr_globals
,
2512 .n_attr
= ARRAY_SIZE(ar8327_sw_attr_globals
),
2515 .attr
= ar8xxx_sw_attr_port
,
2516 .n_attr
= ARRAY_SIZE(ar8xxx_sw_attr_port
),
2519 .attr
= ar8xxx_sw_attr_vlan
,
2520 .n_attr
= ARRAY_SIZE(ar8xxx_sw_attr_vlan
),
2522 .get_port_pvid
= ar8xxx_sw_get_pvid
,
2523 .set_port_pvid
= ar8xxx_sw_set_pvid
,
2524 .get_vlan_ports
= ar8327_sw_get_ports
,
2525 .set_vlan_ports
= ar8327_sw_set_ports
,
2526 .apply_config
= ar8xxx_sw_hw_apply
,
2527 .reset_switch
= ar8xxx_sw_reset_switch
,
2528 .get_port_link
= ar8xxx_sw_get_port_link
,
2532 ar8xxx_id_chip(struct ar8xxx_priv
*priv
)
2538 val
= priv
->read(priv
, AR8216_REG_CTRL
);
2542 id
= val
& (AR8216_CTRL_REVISION
| AR8216_CTRL_VERSION
);
2543 for (i
= 0; i
< AR8X16_PROBE_RETRIES
; i
++) {
2546 val
= priv
->read(priv
, AR8216_REG_CTRL
);
2550 t
= val
& (AR8216_CTRL_REVISION
| AR8216_CTRL_VERSION
);
2555 priv
->chip_ver
= (id
& AR8216_CTRL_VERSION
) >> AR8216_CTRL_VERSION_S
;
2556 priv
->chip_rev
= (id
& AR8216_CTRL_REVISION
);
2558 switch (priv
->chip_ver
) {
2559 case AR8XXX_VER_AR8216
:
2560 priv
->chip
= &ar8216_chip
;
2562 case AR8XXX_VER_AR8236
:
2563 priv
->chip
= &ar8236_chip
;
2565 case AR8XXX_VER_AR8316
:
2566 priv
->chip
= &ar8316_chip
;
2568 case AR8XXX_VER_AR8327
:
2569 priv
->mii_lo_first
= true;
2570 priv
->chip
= &ar8327_chip
;
2572 case AR8XXX_VER_AR8337
:
2573 priv
->mii_lo_first
= true;
2574 priv
->chip
= &ar8327_chip
;
2577 pr_err("ar8216: Unknown Atheros device [ver=%d, rev=%d]\n",
2578 priv
->chip_ver
, priv
->chip_rev
);
2587 ar8xxx_mib_work_func(struct work_struct
*work
)
2589 struct ar8xxx_priv
*priv
;
2592 priv
= container_of(work
, struct ar8xxx_priv
, mib_work
.work
);
2594 mutex_lock(&priv
->mib_lock
);
2596 err
= ar8xxx_mib_capture(priv
);
2600 ar8xxx_mib_fetch_port_stat(priv
, priv
->mib_next_port
, false);
2603 priv
->mib_next_port
++;
2604 if (priv
->mib_next_port
>= priv
->dev
.ports
)
2605 priv
->mib_next_port
= 0;
2607 mutex_unlock(&priv
->mib_lock
);
2608 schedule_delayed_work(&priv
->mib_work
,
2609 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY
));
2613 ar8xxx_mib_init(struct ar8xxx_priv
*priv
)
2617 if (!ar8xxx_has_mib_counters(priv
))
2620 BUG_ON(!priv
->chip
->mib_decs
|| !priv
->chip
->num_mibs
);
2622 len
= priv
->dev
.ports
* priv
->chip
->num_mibs
*
2623 sizeof(*priv
->mib_stats
);
2624 priv
->mib_stats
= kzalloc(len
, GFP_KERNEL
);
2626 if (!priv
->mib_stats
)
2633 ar8xxx_mib_start(struct ar8xxx_priv
*priv
)
2635 if (!ar8xxx_has_mib_counters(priv
))
2638 schedule_delayed_work(&priv
->mib_work
,
2639 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY
));
2643 ar8xxx_mib_stop(struct ar8xxx_priv
*priv
)
2645 if (!ar8xxx_has_mib_counters(priv
))
2648 cancel_delayed_work(&priv
->mib_work
);
2651 static struct ar8xxx_priv
*
2654 struct ar8xxx_priv
*priv
;
2656 priv
= kzalloc(sizeof(struct ar8xxx_priv
), GFP_KERNEL
);
2660 mutex_init(&priv
->reg_mutex
);
2661 mutex_init(&priv
->mib_lock
);
2662 INIT_DELAYED_WORK(&priv
->mib_work
, ar8xxx_mib_work_func
);
2668 ar8xxx_free(struct ar8xxx_priv
*priv
)
2670 if (priv
->chip
&& priv
->chip
->cleanup
)
2671 priv
->chip
->cleanup(priv
);
2673 kfree(priv
->mib_stats
);
2677 static struct ar8xxx_priv
*
2678 ar8xxx_create_mii(struct mii_bus
*bus
)
2680 struct ar8xxx_priv
*priv
;
2682 priv
= ar8xxx_create();
2684 priv
->mii_bus
= bus
;
2685 priv
->read
= ar8xxx_mii_read
;
2686 priv
->write
= ar8xxx_mii_write
;
2687 priv
->rmw
= ar8xxx_mii_rmw
;
2694 ar8xxx_probe_switch(struct ar8xxx_priv
*priv
)
2696 struct switch_dev
*swdev
;
2699 ret
= ar8xxx_id_chip(priv
);
2704 swdev
->cpu_port
= AR8216_PORT_CPU
;
2705 swdev
->ops
= &ar8xxx_sw_ops
;
2707 if (chip_is_ar8316(priv
)) {
2708 swdev
->name
= "Atheros AR8316";
2709 swdev
->vlans
= AR8X16_MAX_VLANS
;
2710 swdev
->ports
= AR8216_NUM_PORTS
;
2711 } else if (chip_is_ar8236(priv
)) {
2712 swdev
->name
= "Atheros AR8236";
2713 swdev
->vlans
= AR8216_NUM_VLANS
;
2714 swdev
->ports
= AR8216_NUM_PORTS
;
2715 } else if (chip_is_ar8327(priv
)) {
2716 swdev
->name
= "Atheros AR8327";
2717 swdev
->vlans
= AR8X16_MAX_VLANS
;
2718 swdev
->ports
= AR8327_NUM_PORTS
;
2719 swdev
->ops
= &ar8327_sw_ops
;
2720 } else if (chip_is_ar8337(priv
)) {
2721 swdev
->name
= "Atheros AR8337";
2722 swdev
->vlans
= AR8X16_MAX_VLANS
;
2723 swdev
->ports
= AR8327_NUM_PORTS
;
2724 swdev
->ops
= &ar8327_sw_ops
;
2726 swdev
->name
= "Atheros AR8216";
2727 swdev
->vlans
= AR8216_NUM_VLANS
;
2728 swdev
->ports
= AR8216_NUM_PORTS
;
2731 ret
= ar8xxx_mib_init(priv
);
2739 ar8xxx_start(struct ar8xxx_priv
*priv
)
2745 ret
= priv
->chip
->hw_init(priv
);
2749 ret
= ar8xxx_sw_reset_switch(&priv
->dev
);
2755 ar8xxx_mib_start(priv
);
2761 ar8xxx_phy_config_init(struct phy_device
*phydev
)
2763 struct ar8xxx_priv
*priv
= phydev
->priv
;
2764 struct net_device
*dev
= phydev
->attached_dev
;
2770 if (chip_is_ar8327(priv
) || chip_is_ar8337(priv
))
2775 if (phydev
->addr
!= 0) {
2776 if (chip_is_ar8316(priv
)) {
2777 /* switch device has been initialized, reinit */
2778 priv
->dev
.ports
= (AR8216_NUM_PORTS
- 1);
2779 priv
->initialized
= false;
2780 priv
->port4_phy
= true;
2781 ar8316_hw_init(priv
);
2788 ret
= ar8xxx_start(priv
);
2792 /* VID fixup only needed on ar8216 */
2793 if (chip_is_ar8216(priv
)) {
2794 dev
->phy_ptr
= priv
;
2795 dev
->priv_flags
|= IFF_NO_IP_ALIGN
;
2796 dev
->eth_mangle_rx
= ar8216_mangle_rx
;
2797 dev
->eth_mangle_tx
= ar8216_mangle_tx
;
2804 ar8xxx_phy_read_status(struct phy_device
*phydev
)
2806 struct ar8xxx_priv
*priv
= phydev
->priv
;
2807 struct switch_port_link link
;
2810 if (phydev
->addr
!= 0)
2811 return genphy_read_status(phydev
);
2813 ar8216_read_port_link(priv
, phydev
->addr
, &link
);
2814 phydev
->link
= !!link
.link
;
2818 switch (link
.speed
) {
2819 case SWITCH_PORT_SPEED_10
:
2820 phydev
->speed
= SPEED_10
;
2822 case SWITCH_PORT_SPEED_100
:
2823 phydev
->speed
= SPEED_100
;
2825 case SWITCH_PORT_SPEED_1000
:
2826 phydev
->speed
= SPEED_1000
;
2831 phydev
->duplex
= link
.duplex
? DUPLEX_FULL
: DUPLEX_HALF
;
2833 /* flush the address translation unit */
2834 mutex_lock(&priv
->reg_mutex
);
2835 ret
= priv
->chip
->atu_flush(priv
);
2836 mutex_unlock(&priv
->reg_mutex
);
2838 phydev
->state
= PHY_RUNNING
;
2839 netif_carrier_on(phydev
->attached_dev
);
2840 phydev
->adjust_link(phydev
->attached_dev
);
2846 ar8xxx_phy_config_aneg(struct phy_device
*phydev
)
2848 if (phydev
->addr
== 0)
2851 return genphy_config_aneg(phydev
);
2854 static const u32 ar8xxx_phy_ids
[] = {
2856 0x004dd034, /* AR8327 */
2857 0x004dd036, /* AR8337 */
2860 0x004dd043, /* AR8236 */
2864 ar8xxx_phy_match(u32 phy_id
)
2868 for (i
= 0; i
< ARRAY_SIZE(ar8xxx_phy_ids
); i
++)
2869 if (phy_id
== ar8xxx_phy_ids
[i
])
2876 ar8xxx_is_possible(struct mii_bus
*bus
)
2880 for (i
= 0; i
< 4; i
++) {
2883 phy_id
= mdiobus_read(bus
, i
, MII_PHYSID1
) << 16;
2884 phy_id
|= mdiobus_read(bus
, i
, MII_PHYSID2
);
2885 if (!ar8xxx_phy_match(phy_id
)) {
2886 pr_debug("ar8xxx: unknown PHY at %s:%02x id:%08x\n",
2887 dev_name(&bus
->dev
), i
, phy_id
);
2896 ar8xxx_phy_probe(struct phy_device
*phydev
)
2898 struct ar8xxx_priv
*priv
;
2899 struct switch_dev
*swdev
;
2902 /* skip PHYs at unused adresses */
2903 if (phydev
->addr
!= 0 && phydev
->addr
!= 4)
2906 if (!ar8xxx_is_possible(phydev
->bus
))
2909 mutex_lock(&ar8xxx_dev_list_lock
);
2910 list_for_each_entry(priv
, &ar8xxx_dev_list
, list
)
2911 if (priv
->mii_bus
== phydev
->bus
)
2914 priv
= ar8xxx_create_mii(phydev
->bus
);
2920 ret
= ar8xxx_probe_switch(priv
);
2925 swdev
->alias
= dev_name(&priv
->mii_bus
->dev
);
2926 ret
= register_switch(swdev
, NULL
);
2930 pr_info("%s: %s rev. %u switch registered on %s\n",
2931 swdev
->devname
, swdev
->name
, priv
->chip_rev
,
2932 dev_name(&priv
->mii_bus
->dev
));
2937 if (phydev
->addr
== 0) {
2938 if (ar8xxx_has_gige(priv
)) {
2939 phydev
->supported
= SUPPORTED_1000baseT_Full
;
2940 phydev
->advertising
= ADVERTISED_1000baseT_Full
;
2942 phydev
->supported
= SUPPORTED_100baseT_Full
;
2943 phydev
->advertising
= ADVERTISED_100baseT_Full
;
2946 if (chip_is_ar8327(priv
) || chip_is_ar8337(priv
)) {
2949 ret
= ar8xxx_start(priv
);
2951 goto err_unregister_switch
;
2954 if (ar8xxx_has_gige(priv
)) {
2955 phydev
->supported
|= SUPPORTED_1000baseT_Full
;
2956 phydev
->advertising
|= ADVERTISED_1000baseT_Full
;
2960 phydev
->priv
= priv
;
2962 list_add(&priv
->list
, &ar8xxx_dev_list
);
2964 mutex_unlock(&ar8xxx_dev_list_lock
);
2968 err_unregister_switch
:
2969 if (--priv
->use_count
)
2972 unregister_switch(&priv
->dev
);
2977 mutex_unlock(&ar8xxx_dev_list_lock
);
2982 ar8xxx_phy_detach(struct phy_device
*phydev
)
2984 struct net_device
*dev
= phydev
->attached_dev
;
2989 dev
->phy_ptr
= NULL
;
2990 dev
->priv_flags
&= ~IFF_NO_IP_ALIGN
;
2991 dev
->eth_mangle_rx
= NULL
;
2992 dev
->eth_mangle_tx
= NULL
;
2996 ar8xxx_phy_remove(struct phy_device
*phydev
)
2998 struct ar8xxx_priv
*priv
= phydev
->priv
;
3003 phydev
->priv
= NULL
;
3004 if (--priv
->use_count
> 0)
3007 mutex_lock(&ar8xxx_dev_list_lock
);
3008 list_del(&priv
->list
);
3009 mutex_unlock(&ar8xxx_dev_list_lock
);
3011 unregister_switch(&priv
->dev
);
3012 ar8xxx_mib_stop(priv
);
3016 static struct phy_driver ar8xxx_phy_driver
= {
3017 .phy_id
= 0x004d0000,
3018 .name
= "Atheros AR8216/AR8236/AR8316",
3019 .phy_id_mask
= 0xffff0000,
3020 .features
= PHY_BASIC_FEATURES
,
3021 .probe
= ar8xxx_phy_probe
,
3022 .remove
= ar8xxx_phy_remove
,
3023 .detach
= ar8xxx_phy_detach
,
3024 .config_init
= ar8xxx_phy_config_init
,
3025 .config_aneg
= ar8xxx_phy_config_aneg
,
3026 .read_status
= ar8xxx_phy_read_status
,
3027 .driver
= { .owner
= THIS_MODULE
},
3033 return phy_driver_register(&ar8xxx_phy_driver
);
3039 phy_driver_unregister(&ar8xxx_phy_driver
);
3042 module_init(ar8xxx_init
);
3043 module_exit(ar8xxx_exit
);
3044 MODULE_LICENSE("GPL");