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ar8216: factor out PHY init code into a generic function
[openwrt/staging/blogic.git] / target / linux / generic / files / drivers / net / phy / ar8216.c
1 /*
2 * ar8216.c: AR8216 switch driver
3 *
4 * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18 #include <linux/if.h>
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/list.h>
22 #include <linux/if_ether.h>
23 #include <linux/skbuff.h>
24 #include <linux/netdevice.h>
25 #include <linux/netlink.h>
26 #include <linux/bitops.h>
27 #include <net/genetlink.h>
28 #include <linux/switch.h>
29 #include <linux/delay.h>
30 #include <linux/phy.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/lockdep.h>
34 #include <linux/ar8216_platform.h>
35 #include <linux/workqueue.h>
36 #include <linux/of_device.h>
37 #include <linux/leds.h>
38 #include <linux/gpio.h>
39
40 #include "ar8216.h"
41
42 /* size of the vlan table */
43 #define AR8X16_MAX_VLANS 128
44 #define AR8X16_PROBE_RETRIES 10
45 #define AR8X16_MAX_PORTS 8
46
47 #define AR8XXX_MIB_WORK_DELAY 2000 /* msecs */
48
49 struct ar8xxx_priv;
50
51 #define AR8XXX_CAP_GIGE BIT(0)
52 #define AR8XXX_CAP_MIB_COUNTERS BIT(1)
53
54 #define AR8XXX_NUM_PHYS 5
55
56 enum {
57 AR8XXX_VER_AR8216 = 0x01,
58 AR8XXX_VER_AR8236 = 0x03,
59 AR8XXX_VER_AR8316 = 0x10,
60 AR8XXX_VER_AR8327 = 0x12,
61 AR8XXX_VER_AR8337 = 0x13,
62 };
63
64 struct ar8xxx_mib_desc {
65 unsigned int size;
66 unsigned int offset;
67 const char *name;
68 };
69
70 struct ar8xxx_chip {
71 unsigned long caps;
72
73 int (*hw_init)(struct ar8xxx_priv *priv);
74 void (*cleanup)(struct ar8xxx_priv *priv);
75
76 void (*init_globals)(struct ar8xxx_priv *priv);
77 void (*init_port)(struct ar8xxx_priv *priv, int port);
78 void (*setup_port)(struct ar8xxx_priv *priv, int port, u32 members);
79 u32 (*read_port_status)(struct ar8xxx_priv *priv, int port);
80 int (*atu_flush)(struct ar8xxx_priv *priv);
81 void (*vtu_flush)(struct ar8xxx_priv *priv);
82 void (*vtu_load_vlan)(struct ar8xxx_priv *priv, u32 vid, u32 port_mask);
83 void (*fixup_phys)(struct ar8xxx_priv *priv);
84
85 const struct ar8xxx_mib_desc *mib_decs;
86 unsigned num_mibs;
87 };
88
89 enum ar8327_led_pattern {
90 AR8327_LED_PATTERN_OFF = 0,
91 AR8327_LED_PATTERN_BLINK,
92 AR8327_LED_PATTERN_ON,
93 AR8327_LED_PATTERN_RULE,
94 };
95
96 struct ar8327_led_entry {
97 unsigned reg;
98 unsigned shift;
99 };
100
101 struct ar8327_led {
102 struct led_classdev cdev;
103 struct ar8xxx_priv *sw_priv;
104
105 char *name;
106 bool active_low;
107 u8 led_num;
108 enum ar8327_led_mode mode;
109
110 struct mutex mutex;
111 spinlock_t lock;
112 struct work_struct led_work;
113 bool enable_hw_mode;
114 enum ar8327_led_pattern pattern;
115 };
116
117 struct ar8327_data {
118 u32 port0_status;
119 u32 port6_status;
120
121 struct ar8327_led **leds;
122 unsigned int num_leds;
123 };
124
125 struct ar8xxx_priv {
126 struct switch_dev dev;
127 struct mii_bus *mii_bus;
128 struct phy_device *phy;
129
130 u32 (*read)(struct ar8xxx_priv *priv, int reg);
131 void (*write)(struct ar8xxx_priv *priv, int reg, u32 val);
132 u32 (*rmw)(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val);
133
134 int (*get_port_link)(unsigned port);
135
136 const struct net_device_ops *ndo_old;
137 struct net_device_ops ndo;
138 struct mutex reg_mutex;
139 u8 chip_ver;
140 u8 chip_rev;
141 const struct ar8xxx_chip *chip;
142 union {
143 struct ar8327_data ar8327;
144 } chip_data;
145 bool initialized;
146 bool port4_phy;
147 char buf[2048];
148
149 bool init;
150 bool mii_lo_first;
151
152 struct mutex mib_lock;
153 struct delayed_work mib_work;
154 int mib_next_port;
155 u64 *mib_stats;
156
157 struct list_head list;
158 unsigned int use_count;
159
160 /* all fields below are cleared on reset */
161 bool vlan;
162 u16 vlan_id[AR8X16_MAX_VLANS];
163 u8 vlan_table[AR8X16_MAX_VLANS];
164 u8 vlan_tagged;
165 u16 pvid[AR8X16_MAX_PORTS];
166
167 /* mirroring */
168 bool mirror_rx;
169 bool mirror_tx;
170 int source_port;
171 int monitor_port;
172 };
173
174 #define MIB_DESC(_s , _o, _n) \
175 { \
176 .size = (_s), \
177 .offset = (_o), \
178 .name = (_n), \
179 }
180
181 static const struct ar8xxx_mib_desc ar8216_mibs[] = {
182 MIB_DESC(1, AR8216_STATS_RXBROAD, "RxBroad"),
183 MIB_DESC(1, AR8216_STATS_RXPAUSE, "RxPause"),
184 MIB_DESC(1, AR8216_STATS_RXMULTI, "RxMulti"),
185 MIB_DESC(1, AR8216_STATS_RXFCSERR, "RxFcsErr"),
186 MIB_DESC(1, AR8216_STATS_RXALIGNERR, "RxAlignErr"),
187 MIB_DESC(1, AR8216_STATS_RXRUNT, "RxRunt"),
188 MIB_DESC(1, AR8216_STATS_RXFRAGMENT, "RxFragment"),
189 MIB_DESC(1, AR8216_STATS_RX64BYTE, "Rx64Byte"),
190 MIB_DESC(1, AR8216_STATS_RX128BYTE, "Rx128Byte"),
191 MIB_DESC(1, AR8216_STATS_RX256BYTE, "Rx256Byte"),
192 MIB_DESC(1, AR8216_STATS_RX512BYTE, "Rx512Byte"),
193 MIB_DESC(1, AR8216_STATS_RX1024BYTE, "Rx1024Byte"),
194 MIB_DESC(1, AR8216_STATS_RXMAXBYTE, "RxMaxByte"),
195 MIB_DESC(1, AR8216_STATS_RXTOOLONG, "RxTooLong"),
196 MIB_DESC(2, AR8216_STATS_RXGOODBYTE, "RxGoodByte"),
197 MIB_DESC(2, AR8216_STATS_RXBADBYTE, "RxBadByte"),
198 MIB_DESC(1, AR8216_STATS_RXOVERFLOW, "RxOverFlow"),
199 MIB_DESC(1, AR8216_STATS_FILTERED, "Filtered"),
200 MIB_DESC(1, AR8216_STATS_TXBROAD, "TxBroad"),
201 MIB_DESC(1, AR8216_STATS_TXPAUSE, "TxPause"),
202 MIB_DESC(1, AR8216_STATS_TXMULTI, "TxMulti"),
203 MIB_DESC(1, AR8216_STATS_TXUNDERRUN, "TxUnderRun"),
204 MIB_DESC(1, AR8216_STATS_TX64BYTE, "Tx64Byte"),
205 MIB_DESC(1, AR8216_STATS_TX128BYTE, "Tx128Byte"),
206 MIB_DESC(1, AR8216_STATS_TX256BYTE, "Tx256Byte"),
207 MIB_DESC(1, AR8216_STATS_TX512BYTE, "Tx512Byte"),
208 MIB_DESC(1, AR8216_STATS_TX1024BYTE, "Tx1024Byte"),
209 MIB_DESC(1, AR8216_STATS_TXMAXBYTE, "TxMaxByte"),
210 MIB_DESC(1, AR8216_STATS_TXOVERSIZE, "TxOverSize"),
211 MIB_DESC(2, AR8216_STATS_TXBYTE, "TxByte"),
212 MIB_DESC(1, AR8216_STATS_TXCOLLISION, "TxCollision"),
213 MIB_DESC(1, AR8216_STATS_TXABORTCOL, "TxAbortCol"),
214 MIB_DESC(1, AR8216_STATS_TXMULTICOL, "TxMultiCol"),
215 MIB_DESC(1, AR8216_STATS_TXSINGLECOL, "TxSingleCol"),
216 MIB_DESC(1, AR8216_STATS_TXEXCDEFER, "TxExcDefer"),
217 MIB_DESC(1, AR8216_STATS_TXDEFER, "TxDefer"),
218 MIB_DESC(1, AR8216_STATS_TXLATECOL, "TxLateCol"),
219 };
220
221 static const struct ar8xxx_mib_desc ar8236_mibs[] = {
222 MIB_DESC(1, AR8236_STATS_RXBROAD, "RxBroad"),
223 MIB_DESC(1, AR8236_STATS_RXPAUSE, "RxPause"),
224 MIB_DESC(1, AR8236_STATS_RXMULTI, "RxMulti"),
225 MIB_DESC(1, AR8236_STATS_RXFCSERR, "RxFcsErr"),
226 MIB_DESC(1, AR8236_STATS_RXALIGNERR, "RxAlignErr"),
227 MIB_DESC(1, AR8236_STATS_RXRUNT, "RxRunt"),
228 MIB_DESC(1, AR8236_STATS_RXFRAGMENT, "RxFragment"),
229 MIB_DESC(1, AR8236_STATS_RX64BYTE, "Rx64Byte"),
230 MIB_DESC(1, AR8236_STATS_RX128BYTE, "Rx128Byte"),
231 MIB_DESC(1, AR8236_STATS_RX256BYTE, "Rx256Byte"),
232 MIB_DESC(1, AR8236_STATS_RX512BYTE, "Rx512Byte"),
233 MIB_DESC(1, AR8236_STATS_RX1024BYTE, "Rx1024Byte"),
234 MIB_DESC(1, AR8236_STATS_RX1518BYTE, "Rx1518Byte"),
235 MIB_DESC(1, AR8236_STATS_RXMAXBYTE, "RxMaxByte"),
236 MIB_DESC(1, AR8236_STATS_RXTOOLONG, "RxTooLong"),
237 MIB_DESC(2, AR8236_STATS_RXGOODBYTE, "RxGoodByte"),
238 MIB_DESC(2, AR8236_STATS_RXBADBYTE, "RxBadByte"),
239 MIB_DESC(1, AR8236_STATS_RXOVERFLOW, "RxOverFlow"),
240 MIB_DESC(1, AR8236_STATS_FILTERED, "Filtered"),
241 MIB_DESC(1, AR8236_STATS_TXBROAD, "TxBroad"),
242 MIB_DESC(1, AR8236_STATS_TXPAUSE, "TxPause"),
243 MIB_DESC(1, AR8236_STATS_TXMULTI, "TxMulti"),
244 MIB_DESC(1, AR8236_STATS_TXUNDERRUN, "TxUnderRun"),
245 MIB_DESC(1, AR8236_STATS_TX64BYTE, "Tx64Byte"),
246 MIB_DESC(1, AR8236_STATS_TX128BYTE, "Tx128Byte"),
247 MIB_DESC(1, AR8236_STATS_TX256BYTE, "Tx256Byte"),
248 MIB_DESC(1, AR8236_STATS_TX512BYTE, "Tx512Byte"),
249 MIB_DESC(1, AR8236_STATS_TX1024BYTE, "Tx1024Byte"),
250 MIB_DESC(1, AR8236_STATS_TX1518BYTE, "Tx1518Byte"),
251 MIB_DESC(1, AR8236_STATS_TXMAXBYTE, "TxMaxByte"),
252 MIB_DESC(1, AR8236_STATS_TXOVERSIZE, "TxOverSize"),
253 MIB_DESC(2, AR8236_STATS_TXBYTE, "TxByte"),
254 MIB_DESC(1, AR8236_STATS_TXCOLLISION, "TxCollision"),
255 MIB_DESC(1, AR8236_STATS_TXABORTCOL, "TxAbortCol"),
256 MIB_DESC(1, AR8236_STATS_TXMULTICOL, "TxMultiCol"),
257 MIB_DESC(1, AR8236_STATS_TXSINGLECOL, "TxSingleCol"),
258 MIB_DESC(1, AR8236_STATS_TXEXCDEFER, "TxExcDefer"),
259 MIB_DESC(1, AR8236_STATS_TXDEFER, "TxDefer"),
260 MIB_DESC(1, AR8236_STATS_TXLATECOL, "TxLateCol"),
261 };
262
263 static DEFINE_MUTEX(ar8xxx_dev_list_lock);
264 static LIST_HEAD(ar8xxx_dev_list);
265
266 static inline struct ar8xxx_priv *
267 swdev_to_ar8xxx(struct switch_dev *swdev)
268 {
269 return container_of(swdev, struct ar8xxx_priv, dev);
270 }
271
272 static inline bool ar8xxx_has_gige(struct ar8xxx_priv *priv)
273 {
274 return priv->chip->caps & AR8XXX_CAP_GIGE;
275 }
276
277 static inline bool ar8xxx_has_mib_counters(struct ar8xxx_priv *priv)
278 {
279 return priv->chip->caps & AR8XXX_CAP_MIB_COUNTERS;
280 }
281
282 static inline bool chip_is_ar8216(struct ar8xxx_priv *priv)
283 {
284 return priv->chip_ver == AR8XXX_VER_AR8216;
285 }
286
287 static inline bool chip_is_ar8236(struct ar8xxx_priv *priv)
288 {
289 return priv->chip_ver == AR8XXX_VER_AR8236;
290 }
291
292 static inline bool chip_is_ar8316(struct ar8xxx_priv *priv)
293 {
294 return priv->chip_ver == AR8XXX_VER_AR8316;
295 }
296
297 static inline bool chip_is_ar8327(struct ar8xxx_priv *priv)
298 {
299 return priv->chip_ver == AR8XXX_VER_AR8327;
300 }
301
302 static inline bool chip_is_ar8337(struct ar8xxx_priv *priv)
303 {
304 return priv->chip_ver == AR8XXX_VER_AR8337;
305 }
306
307 static inline void
308 split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
309 {
310 regaddr >>= 1;
311 *r1 = regaddr & 0x1e;
312
313 regaddr >>= 5;
314 *r2 = regaddr & 0x7;
315
316 regaddr >>= 3;
317 *page = regaddr & 0x1ff;
318 }
319
320 /* inspired by phy_poll_reset in drivers/net/phy/phy_device.c */
321 static int
322 ar8xxx_phy_poll_reset(struct mii_bus *bus)
323 {
324 unsigned int sleep_msecs = 20;
325 int ret, elapsed, i;
326
327 for (elapsed = sleep_msecs; elapsed <= 600;
328 elapsed += sleep_msecs) {
329 msleep(sleep_msecs);
330 for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
331 ret = mdiobus_read(bus, i, MII_BMCR);
332 if (ret < 0)
333 return ret;
334 if (ret & BMCR_RESET)
335 break;
336 if (i == AR8XXX_NUM_PHYS - 1) {
337 usleep_range(1000, 2000);
338 return 0;
339 }
340 }
341 }
342 return -ETIMEDOUT;
343 }
344
345 static void
346 ar8xxx_phy_init(struct ar8xxx_priv *priv, bool support_1000)
347 {
348 int i;
349 struct mii_bus *bus;
350
351 if (priv->chip->fixup_phys)
352 priv->chip->fixup_phys(priv);
353
354 bus = priv->mii_bus;
355 for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
356 /* initialize the port itself */
357 mdiobus_write(bus, i, MII_ADVERTISE,
358 ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
359 if (support_1000)
360 mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
361 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
362 }
363
364 ar8xxx_phy_poll_reset(bus);
365 }
366
367 static u32
368 ar8xxx_mii_read(struct ar8xxx_priv *priv, int reg)
369 {
370 struct mii_bus *bus = priv->mii_bus;
371 u16 r1, r2, page;
372 u16 lo, hi;
373
374 split_addr((u32) reg, &r1, &r2, &page);
375
376 mutex_lock(&bus->mdio_lock);
377
378 bus->write(bus, 0x18, 0, page);
379 usleep_range(1000, 2000); /* wait for the page switch to propagate */
380 lo = bus->read(bus, 0x10 | r2, r1);
381 hi = bus->read(bus, 0x10 | r2, r1 + 1);
382
383 mutex_unlock(&bus->mdio_lock);
384
385 return (hi << 16) | lo;
386 }
387
388 static void
389 ar8xxx_mii_write(struct ar8xxx_priv *priv, int reg, u32 val)
390 {
391 struct mii_bus *bus = priv->mii_bus;
392 u16 r1, r2, r3;
393 u16 lo, hi;
394
395 split_addr((u32) reg, &r1, &r2, &r3);
396 lo = val & 0xffff;
397 hi = (u16) (val >> 16);
398
399 mutex_lock(&bus->mdio_lock);
400
401 bus->write(bus, 0x18, 0, r3);
402 usleep_range(1000, 2000); /* wait for the page switch to propagate */
403 if (priv->mii_lo_first) {
404 bus->write(bus, 0x10 | r2, r1, lo);
405 bus->write(bus, 0x10 | r2, r1 + 1, hi);
406 } else {
407 bus->write(bus, 0x10 | r2, r1 + 1, hi);
408 bus->write(bus, 0x10 | r2, r1, lo);
409 }
410
411 mutex_unlock(&bus->mdio_lock);
412 }
413
414 static u32
415 ar8xxx_mii_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
416 {
417 struct mii_bus *bus = priv->mii_bus;
418 u16 r1, r2, page;
419 u16 lo, hi;
420 u32 ret;
421
422 split_addr((u32) reg, &r1, &r2, &page);
423
424 mutex_lock(&bus->mdio_lock);
425
426 bus->write(bus, 0x18, 0, page);
427 usleep_range(1000, 2000); /* wait for the page switch to propagate */
428
429 lo = bus->read(bus, 0x10 | r2, r1);
430 hi = bus->read(bus, 0x10 | r2, r1 + 1);
431
432 ret = hi << 16 | lo;
433 ret &= ~mask;
434 ret |= val;
435
436 lo = ret & 0xffff;
437 hi = (u16) (ret >> 16);
438
439 if (priv->mii_lo_first) {
440 bus->write(bus, 0x10 | r2, r1, lo);
441 bus->write(bus, 0x10 | r2, r1 + 1, hi);
442 } else {
443 bus->write(bus, 0x10 | r2, r1 + 1, hi);
444 bus->write(bus, 0x10 | r2, r1, lo);
445 }
446
447 mutex_unlock(&bus->mdio_lock);
448
449 return ret;
450 }
451
452
453 static void
454 ar8xxx_phy_dbg_write(struct ar8xxx_priv *priv, int phy_addr,
455 u16 dbg_addr, u16 dbg_data)
456 {
457 struct mii_bus *bus = priv->mii_bus;
458
459 mutex_lock(&bus->mdio_lock);
460 bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr);
461 bus->write(bus, phy_addr, MII_ATH_DBG_DATA, dbg_data);
462 mutex_unlock(&bus->mdio_lock);
463 }
464
465 static void
466 ar8xxx_phy_mmd_write(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 data)
467 {
468 struct mii_bus *bus = priv->mii_bus;
469
470 mutex_lock(&bus->mdio_lock);
471 bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr);
472 bus->write(bus, phy_addr, MII_ATH_MMD_DATA, data);
473 mutex_unlock(&bus->mdio_lock);
474 }
475
476 static inline u32
477 ar8xxx_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
478 {
479 return priv->rmw(priv, reg, mask, val);
480 }
481
482 static inline void
483 ar8xxx_reg_set(struct ar8xxx_priv *priv, int reg, u32 val)
484 {
485 priv->rmw(priv, reg, 0, val);
486 }
487
488 static int
489 ar8xxx_reg_wait(struct ar8xxx_priv *priv, u32 reg, u32 mask, u32 val,
490 unsigned timeout)
491 {
492 int i;
493
494 for (i = 0; i < timeout; i++) {
495 u32 t;
496
497 t = priv->read(priv, reg);
498 if ((t & mask) == val)
499 return 0;
500
501 usleep_range(1000, 2000);
502 }
503
504 return -ETIMEDOUT;
505 }
506
507 static int
508 ar8xxx_mib_op(struct ar8xxx_priv *priv, u32 op)
509 {
510 unsigned mib_func;
511 int ret;
512
513 lockdep_assert_held(&priv->mib_lock);
514
515 if (chip_is_ar8327(priv) || chip_is_ar8337(priv))
516 mib_func = AR8327_REG_MIB_FUNC;
517 else
518 mib_func = AR8216_REG_MIB_FUNC;
519
520 /* Capture the hardware statistics for all ports */
521 ar8xxx_rmw(priv, mib_func, AR8216_MIB_FUNC, (op << AR8216_MIB_FUNC_S));
522
523 /* Wait for the capturing to complete. */
524 ret = ar8xxx_reg_wait(priv, mib_func, AR8216_MIB_BUSY, 0, 10);
525 if (ret)
526 goto out;
527
528 ret = 0;
529
530 out:
531 return ret;
532 }
533
534 static int
535 ar8xxx_mib_capture(struct ar8xxx_priv *priv)
536 {
537 return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_CAPTURE);
538 }
539
540 static int
541 ar8xxx_mib_flush(struct ar8xxx_priv *priv)
542 {
543 return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_FLUSH);
544 }
545
546 static void
547 ar8xxx_mib_fetch_port_stat(struct ar8xxx_priv *priv, int port, bool flush)
548 {
549 unsigned int base;
550 u64 *mib_stats;
551 int i;
552
553 WARN_ON(port >= priv->dev.ports);
554
555 lockdep_assert_held(&priv->mib_lock);
556
557 if (chip_is_ar8327(priv) || chip_is_ar8337(priv))
558 base = AR8327_REG_PORT_STATS_BASE(port);
559 else if (chip_is_ar8236(priv) ||
560 chip_is_ar8316(priv))
561 base = AR8236_REG_PORT_STATS_BASE(port);
562 else
563 base = AR8216_REG_PORT_STATS_BASE(port);
564
565 mib_stats = &priv->mib_stats[port * priv->chip->num_mibs];
566 for (i = 0; i < priv->chip->num_mibs; i++) {
567 const struct ar8xxx_mib_desc *mib;
568 u64 t;
569
570 mib = &priv->chip->mib_decs[i];
571 t = priv->read(priv, base + mib->offset);
572 if (mib->size == 2) {
573 u64 hi;
574
575 hi = priv->read(priv, base + mib->offset + 4);
576 t |= hi << 32;
577 }
578
579 if (flush)
580 mib_stats[i] = 0;
581 else
582 mib_stats[i] += t;
583 }
584 }
585
586 static void
587 ar8216_read_port_link(struct ar8xxx_priv *priv, int port,
588 struct switch_port_link *link)
589 {
590 u32 status;
591 u32 speed;
592
593 memset(link, '\0', sizeof(*link));
594
595 status = priv->chip->read_port_status(priv, port);
596
597 link->aneg = !!(status & AR8216_PORT_STATUS_LINK_AUTO);
598 if (link->aneg) {
599 link->link = !!(status & AR8216_PORT_STATUS_LINK_UP);
600 } else {
601 link->link = true;
602
603 if (priv->get_port_link) {
604 int err;
605
606 err = priv->get_port_link(port);
607 if (err >= 0)
608 link->link = !!err;
609 }
610 }
611
612 if (!link->link)
613 return;
614
615 link->duplex = !!(status & AR8216_PORT_STATUS_DUPLEX);
616 link->tx_flow = !!(status & AR8216_PORT_STATUS_TXFLOW);
617 link->rx_flow = !!(status & AR8216_PORT_STATUS_RXFLOW);
618
619 speed = (status & AR8216_PORT_STATUS_SPEED) >>
620 AR8216_PORT_STATUS_SPEED_S;
621
622 switch (speed) {
623 case AR8216_PORT_SPEED_10M:
624 link->speed = SWITCH_PORT_SPEED_10;
625 break;
626 case AR8216_PORT_SPEED_100M:
627 link->speed = SWITCH_PORT_SPEED_100;
628 break;
629 case AR8216_PORT_SPEED_1000M:
630 link->speed = SWITCH_PORT_SPEED_1000;
631 break;
632 default:
633 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
634 break;
635 }
636 }
637
638 static struct sk_buff *
639 ar8216_mangle_tx(struct net_device *dev, struct sk_buff *skb)
640 {
641 struct ar8xxx_priv *priv = dev->phy_ptr;
642 unsigned char *buf;
643
644 if (unlikely(!priv))
645 goto error;
646
647 if (!priv->vlan)
648 goto send;
649
650 if (unlikely(skb_headroom(skb) < 2)) {
651 if (pskb_expand_head(skb, 2, 0, GFP_ATOMIC) < 0)
652 goto error;
653 }
654
655 buf = skb_push(skb, 2);
656 buf[0] = 0x10;
657 buf[1] = 0x80;
658
659 send:
660 return skb;
661
662 error:
663 dev_kfree_skb_any(skb);
664 return NULL;
665 }
666
667 static void
668 ar8216_mangle_rx(struct net_device *dev, struct sk_buff *skb)
669 {
670 struct ar8xxx_priv *priv;
671 unsigned char *buf;
672 int port, vlan;
673
674 priv = dev->phy_ptr;
675 if (!priv)
676 return;
677
678 /* don't strip the header if vlan mode is disabled */
679 if (!priv->vlan)
680 return;
681
682 /* strip header, get vlan id */
683 buf = skb->data;
684 skb_pull(skb, 2);
685
686 /* check for vlan header presence */
687 if ((buf[12 + 2] != 0x81) || (buf[13 + 2] != 0x00))
688 return;
689
690 port = buf[0] & 0xf;
691
692 /* no need to fix up packets coming from a tagged source */
693 if (priv->vlan_tagged & (1 << port))
694 return;
695
696 /* lookup port vid from local table, the switch passes an invalid vlan id */
697 vlan = priv->vlan_id[priv->pvid[port]];
698
699 buf[14 + 2] &= 0xf0;
700 buf[14 + 2] |= vlan >> 8;
701 buf[15 + 2] = vlan & 0xff;
702 }
703
704 static int
705 ar8216_wait_bit(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
706 {
707 int timeout = 20;
708 u32 t = 0;
709
710 while (1) {
711 t = priv->read(priv, reg);
712 if ((t & mask) == val)
713 return 0;
714
715 if (timeout-- <= 0)
716 break;
717
718 udelay(10);
719 }
720
721 pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
722 (unsigned int) reg, t, mask, val);
723 return -ETIMEDOUT;
724 }
725
726 static void
727 ar8216_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
728 {
729 if (ar8216_wait_bit(priv, AR8216_REG_VTU, AR8216_VTU_ACTIVE, 0))
730 return;
731 if ((op & AR8216_VTU_OP) == AR8216_VTU_OP_LOAD) {
732 val &= AR8216_VTUDATA_MEMBER;
733 val |= AR8216_VTUDATA_VALID;
734 priv->write(priv, AR8216_REG_VTU_DATA, val);
735 }
736 op |= AR8216_VTU_ACTIVE;
737 priv->write(priv, AR8216_REG_VTU, op);
738 }
739
740 static void
741 ar8216_vtu_flush(struct ar8xxx_priv *priv)
742 {
743 ar8216_vtu_op(priv, AR8216_VTU_OP_FLUSH, 0);
744 }
745
746 static void
747 ar8216_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)
748 {
749 u32 op;
750
751 op = AR8216_VTU_OP_LOAD | (vid << AR8216_VTU_VID_S);
752 ar8216_vtu_op(priv, op, port_mask);
753 }
754
755 static int
756 ar8216_atu_flush(struct ar8xxx_priv *priv)
757 {
758 int ret;
759
760 ret = ar8216_wait_bit(priv, AR8216_REG_ATU, AR8216_ATU_ACTIVE, 0);
761 if (!ret)
762 priv->write(priv, AR8216_REG_ATU, AR8216_ATU_OP_FLUSH);
763
764 return ret;
765 }
766
767 static u32
768 ar8216_read_port_status(struct ar8xxx_priv *priv, int port)
769 {
770 return priv->read(priv, AR8216_REG_PORT_STATUS(port));
771 }
772
773 static void
774 ar8216_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
775 {
776 u32 header;
777 u32 egress, ingress;
778 u32 pvid;
779
780 if (priv->vlan) {
781 pvid = priv->vlan_id[priv->pvid[port]];
782 if (priv->vlan_tagged & (1 << port))
783 egress = AR8216_OUT_ADD_VLAN;
784 else
785 egress = AR8216_OUT_STRIP_VLAN;
786 ingress = AR8216_IN_SECURE;
787 } else {
788 pvid = port;
789 egress = AR8216_OUT_KEEP;
790 ingress = AR8216_IN_PORT_ONLY;
791 }
792
793 if (chip_is_ar8216(priv) && priv->vlan && port == AR8216_PORT_CPU)
794 header = AR8216_PORT_CTRL_HEADER;
795 else
796 header = 0;
797
798 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
799 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
800 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
801 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
802 AR8216_PORT_CTRL_LEARN | header |
803 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
804 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
805
806 ar8xxx_rmw(priv, AR8216_REG_PORT_VLAN(port),
807 AR8216_PORT_VLAN_DEST_PORTS | AR8216_PORT_VLAN_MODE |
808 AR8216_PORT_VLAN_DEFAULT_ID,
809 (members << AR8216_PORT_VLAN_DEST_PORTS_S) |
810 (ingress << AR8216_PORT_VLAN_MODE_S) |
811 (pvid << AR8216_PORT_VLAN_DEFAULT_ID_S));
812 }
813
814 static int
815 ar8216_hw_init(struct ar8xxx_priv *priv)
816 {
817 return 0;
818 }
819
820 static void
821 ar8216_init_globals(struct ar8xxx_priv *priv)
822 {
823 /* standard atheros magic */
824 priv->write(priv, 0x38, 0xc000050e);
825
826 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
827 AR8216_GCTRL_MTU, 1518 + 8 + 2);
828 }
829
830 static void
831 ar8216_init_port(struct ar8xxx_priv *priv, int port)
832 {
833 /* Enable port learning and tx */
834 priv->write(priv, AR8216_REG_PORT_CTRL(port),
835 AR8216_PORT_CTRL_LEARN |
836 (4 << AR8216_PORT_CTRL_STATE_S));
837
838 priv->write(priv, AR8216_REG_PORT_VLAN(port), 0);
839
840 if (port == AR8216_PORT_CPU) {
841 priv->write(priv, AR8216_REG_PORT_STATUS(port),
842 AR8216_PORT_STATUS_LINK_UP |
843 (ar8xxx_has_gige(priv) ?
844 AR8216_PORT_SPEED_1000M : AR8216_PORT_SPEED_100M) |
845 AR8216_PORT_STATUS_TXMAC |
846 AR8216_PORT_STATUS_RXMAC |
847 (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_RXFLOW : 0) |
848 (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_TXFLOW : 0) |
849 AR8216_PORT_STATUS_DUPLEX);
850 } else {
851 priv->write(priv, AR8216_REG_PORT_STATUS(port),
852 AR8216_PORT_STATUS_LINK_AUTO);
853 }
854 }
855
856 static const struct ar8xxx_chip ar8216_chip = {
857 .caps = AR8XXX_CAP_MIB_COUNTERS,
858
859 .hw_init = ar8216_hw_init,
860 .init_globals = ar8216_init_globals,
861 .init_port = ar8216_init_port,
862 .setup_port = ar8216_setup_port,
863 .read_port_status = ar8216_read_port_status,
864 .atu_flush = ar8216_atu_flush,
865 .vtu_flush = ar8216_vtu_flush,
866 .vtu_load_vlan = ar8216_vtu_load_vlan,
867
868 .num_mibs = ARRAY_SIZE(ar8216_mibs),
869 .mib_decs = ar8216_mibs,
870 };
871
872 static void
873 ar8236_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
874 {
875 u32 egress, ingress;
876 u32 pvid;
877
878 if (priv->vlan) {
879 pvid = priv->vlan_id[priv->pvid[port]];
880 if (priv->vlan_tagged & (1 << port))
881 egress = AR8216_OUT_ADD_VLAN;
882 else
883 egress = AR8216_OUT_STRIP_VLAN;
884 ingress = AR8216_IN_SECURE;
885 } else {
886 pvid = port;
887 egress = AR8216_OUT_KEEP;
888 ingress = AR8216_IN_PORT_ONLY;
889 }
890
891 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
892 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
893 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
894 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
895 AR8216_PORT_CTRL_LEARN |
896 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
897 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
898
899 ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN(port),
900 AR8236_PORT_VLAN_DEFAULT_ID,
901 (pvid << AR8236_PORT_VLAN_DEFAULT_ID_S));
902
903 ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN2(port),
904 AR8236_PORT_VLAN2_VLAN_MODE |
905 AR8236_PORT_VLAN2_MEMBER,
906 (ingress << AR8236_PORT_VLAN2_VLAN_MODE_S) |
907 (members << AR8236_PORT_VLAN2_MEMBER_S));
908 }
909
910 static int
911 ar8236_hw_init(struct ar8xxx_priv *priv)
912 {
913 if (priv->initialized)
914 return 0;
915
916 ar8xxx_phy_init(priv, false);
917
918 priv->initialized = true;
919 return 0;
920 }
921
922 static void
923 ar8236_init_globals(struct ar8xxx_priv *priv)
924 {
925 /* enable jumbo frames */
926 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
927 AR8316_GCTRL_MTU, 9018 + 8 + 2);
928
929 /* Enable MIB counters */
930 ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
931 (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
932 AR8236_MIB_EN);
933 }
934
935 static const struct ar8xxx_chip ar8236_chip = {
936 .caps = AR8XXX_CAP_MIB_COUNTERS,
937 .hw_init = ar8236_hw_init,
938 .init_globals = ar8236_init_globals,
939 .init_port = ar8216_init_port,
940 .setup_port = ar8236_setup_port,
941 .read_port_status = ar8216_read_port_status,
942 .atu_flush = ar8216_atu_flush,
943 .vtu_flush = ar8216_vtu_flush,
944 .vtu_load_vlan = ar8216_vtu_load_vlan,
945
946 .num_mibs = ARRAY_SIZE(ar8236_mibs),
947 .mib_decs = ar8236_mibs,
948 };
949
950 static int
951 ar8316_hw_init(struct ar8xxx_priv *priv)
952 {
953 u32 val, newval;
954
955 val = priv->read(priv, AR8316_REG_POSTRIP);
956
957 if (priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
958 if (priv->port4_phy) {
959 /* value taken from Ubiquiti RouterStation Pro */
960 newval = 0x81461bea;
961 pr_info("ar8316: Using port 4 as PHY\n");
962 } else {
963 newval = 0x01261be2;
964 pr_info("ar8316: Using port 4 as switch port\n");
965 }
966 } else if (priv->phy->interface == PHY_INTERFACE_MODE_GMII) {
967 /* value taken from AVM Fritz!Box 7390 sources */
968 newval = 0x010e5b71;
969 } else {
970 /* no known value for phy interface */
971 pr_err("ar8316: unsupported mii mode: %d.\n",
972 priv->phy->interface);
973 return -EINVAL;
974 }
975
976 if (val == newval)
977 goto out;
978
979 priv->write(priv, AR8316_REG_POSTRIP, newval);
980
981 if (priv->port4_phy &&
982 priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
983 /* work around for phy4 rgmii mode */
984 ar8xxx_phy_dbg_write(priv, 4, 0x12, 0x480c);
985 /* rx delay */
986 ar8xxx_phy_dbg_write(priv, 4, 0x0, 0x824e);
987 /* tx delay */
988 ar8xxx_phy_dbg_write(priv, 4, 0x5, 0x3d47);
989 msleep(1000);
990 }
991
992 ar8xxx_phy_init(priv, true);
993
994 out:
995 priv->initialized = true;
996 return 0;
997 }
998
999 static void
1000 ar8316_init_globals(struct ar8xxx_priv *priv)
1001 {
1002 /* standard atheros magic */
1003 priv->write(priv, 0x38, 0xc000050e);
1004
1005 /* enable cpu port to receive multicast and broadcast frames */
1006 priv->write(priv, AR8216_REG_FLOOD_MASK, 0x003f003f);
1007
1008 /* enable jumbo frames */
1009 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
1010 AR8316_GCTRL_MTU, 9018 + 8 + 2);
1011
1012 /* Enable MIB counters */
1013 ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
1014 (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
1015 AR8236_MIB_EN);
1016 }
1017
1018 static const struct ar8xxx_chip ar8316_chip = {
1019 .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
1020 .hw_init = ar8316_hw_init,
1021 .init_globals = ar8316_init_globals,
1022 .init_port = ar8216_init_port,
1023 .setup_port = ar8216_setup_port,
1024 .read_port_status = ar8216_read_port_status,
1025 .atu_flush = ar8216_atu_flush,
1026 .vtu_flush = ar8216_vtu_flush,
1027 .vtu_load_vlan = ar8216_vtu_load_vlan,
1028
1029 .num_mibs = ARRAY_SIZE(ar8236_mibs),
1030 .mib_decs = ar8236_mibs,
1031 };
1032
1033 static u32
1034 ar8327_get_pad_cfg(struct ar8327_pad_cfg *cfg)
1035 {
1036 u32 t;
1037
1038 if (!cfg)
1039 return 0;
1040
1041 t = 0;
1042 switch (cfg->mode) {
1043 case AR8327_PAD_NC:
1044 break;
1045
1046 case AR8327_PAD_MAC2MAC_MII:
1047 t = AR8327_PAD_MAC_MII_EN;
1048 if (cfg->rxclk_sel)
1049 t |= AR8327_PAD_MAC_MII_RXCLK_SEL;
1050 if (cfg->txclk_sel)
1051 t |= AR8327_PAD_MAC_MII_TXCLK_SEL;
1052 break;
1053
1054 case AR8327_PAD_MAC2MAC_GMII:
1055 t = AR8327_PAD_MAC_GMII_EN;
1056 if (cfg->rxclk_sel)
1057 t |= AR8327_PAD_MAC_GMII_RXCLK_SEL;
1058 if (cfg->txclk_sel)
1059 t |= AR8327_PAD_MAC_GMII_TXCLK_SEL;
1060 break;
1061
1062 case AR8327_PAD_MAC_SGMII:
1063 t = AR8327_PAD_SGMII_EN;
1064
1065 /*
1066 * WAR for the QUalcomm Atheros AP136 board.
1067 * It seems that RGMII TX/RX delay settings needs to be
1068 * applied for SGMII mode as well, The ethernet is not
1069 * reliable without this.
1070 */
1071 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
1072 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
1073 if (cfg->rxclk_delay_en)
1074 t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
1075 if (cfg->txclk_delay_en)
1076 t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
1077
1078 if (cfg->sgmii_delay_en)
1079 t |= AR8327_PAD_SGMII_DELAY_EN;
1080
1081 break;
1082
1083 case AR8327_PAD_MAC2PHY_MII:
1084 t = AR8327_PAD_PHY_MII_EN;
1085 if (cfg->rxclk_sel)
1086 t |= AR8327_PAD_PHY_MII_RXCLK_SEL;
1087 if (cfg->txclk_sel)
1088 t |= AR8327_PAD_PHY_MII_TXCLK_SEL;
1089 break;
1090
1091 case AR8327_PAD_MAC2PHY_GMII:
1092 t = AR8327_PAD_PHY_GMII_EN;
1093 if (cfg->pipe_rxclk_sel)
1094 t |= AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL;
1095 if (cfg->rxclk_sel)
1096 t |= AR8327_PAD_PHY_GMII_RXCLK_SEL;
1097 if (cfg->txclk_sel)
1098 t |= AR8327_PAD_PHY_GMII_TXCLK_SEL;
1099 break;
1100
1101 case AR8327_PAD_MAC_RGMII:
1102 t = AR8327_PAD_RGMII_EN;
1103 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
1104 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
1105 if (cfg->rxclk_delay_en)
1106 t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
1107 if (cfg->txclk_delay_en)
1108 t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
1109 break;
1110
1111 case AR8327_PAD_PHY_GMII:
1112 t = AR8327_PAD_PHYX_GMII_EN;
1113 break;
1114
1115 case AR8327_PAD_PHY_RGMII:
1116 t = AR8327_PAD_PHYX_RGMII_EN;
1117 break;
1118
1119 case AR8327_PAD_PHY_MII:
1120 t = AR8327_PAD_PHYX_MII_EN;
1121 break;
1122 }
1123
1124 return t;
1125 }
1126
1127 static void
1128 ar8327_phy_fixup(struct ar8xxx_priv *priv, int phy)
1129 {
1130 switch (priv->chip_rev) {
1131 case 1:
1132 /* For 100M waveform */
1133 ar8xxx_phy_dbg_write(priv, phy, 0, 0x02ea);
1134 /* Turn on Gigabit clock */
1135 ar8xxx_phy_dbg_write(priv, phy, 0x3d, 0x68a0);
1136 break;
1137
1138 case 2:
1139 ar8xxx_phy_mmd_write(priv, phy, 0x7, 0x3c);
1140 ar8xxx_phy_mmd_write(priv, phy, 0x4007, 0x0);
1141 /* fallthrough */
1142 case 4:
1143 ar8xxx_phy_mmd_write(priv, phy, 0x3, 0x800d);
1144 ar8xxx_phy_mmd_write(priv, phy, 0x4003, 0x803f);
1145
1146 ar8xxx_phy_dbg_write(priv, phy, 0x3d, 0x6860);
1147 ar8xxx_phy_dbg_write(priv, phy, 0x5, 0x2c46);
1148 ar8xxx_phy_dbg_write(priv, phy, 0x3c, 0x6000);
1149 break;
1150 }
1151 }
1152
1153 static u32
1154 ar8327_get_port_init_status(struct ar8327_port_cfg *cfg)
1155 {
1156 u32 t;
1157
1158 if (!cfg->force_link)
1159 return AR8216_PORT_STATUS_LINK_AUTO;
1160
1161 t = AR8216_PORT_STATUS_TXMAC | AR8216_PORT_STATUS_RXMAC;
1162 t |= cfg->duplex ? AR8216_PORT_STATUS_DUPLEX : 0;
1163 t |= cfg->rxpause ? AR8216_PORT_STATUS_RXFLOW : 0;
1164 t |= cfg->txpause ? AR8216_PORT_STATUS_TXFLOW : 0;
1165
1166 switch (cfg->speed) {
1167 case AR8327_PORT_SPEED_10:
1168 t |= AR8216_PORT_SPEED_10M;
1169 break;
1170 case AR8327_PORT_SPEED_100:
1171 t |= AR8216_PORT_SPEED_100M;
1172 break;
1173 case AR8327_PORT_SPEED_1000:
1174 t |= AR8216_PORT_SPEED_1000M;
1175 break;
1176 }
1177
1178 return t;
1179 }
1180
1181 #define AR8327_LED_ENTRY(_num, _reg, _shift) \
1182 [_num] = { .reg = (_reg), .shift = (_shift) }
1183
1184 static const struct ar8327_led_entry
1185 ar8327_led_map[AR8327_NUM_LEDS] = {
1186 AR8327_LED_ENTRY(AR8327_LED_PHY0_0, 0, 14),
1187 AR8327_LED_ENTRY(AR8327_LED_PHY0_1, 1, 14),
1188 AR8327_LED_ENTRY(AR8327_LED_PHY0_2, 2, 14),
1189
1190 AR8327_LED_ENTRY(AR8327_LED_PHY1_0, 3, 8),
1191 AR8327_LED_ENTRY(AR8327_LED_PHY1_1, 3, 10),
1192 AR8327_LED_ENTRY(AR8327_LED_PHY1_2, 3, 12),
1193
1194 AR8327_LED_ENTRY(AR8327_LED_PHY2_0, 3, 14),
1195 AR8327_LED_ENTRY(AR8327_LED_PHY2_1, 3, 16),
1196 AR8327_LED_ENTRY(AR8327_LED_PHY2_2, 3, 18),
1197
1198 AR8327_LED_ENTRY(AR8327_LED_PHY3_0, 3, 20),
1199 AR8327_LED_ENTRY(AR8327_LED_PHY3_1, 3, 22),
1200 AR8327_LED_ENTRY(AR8327_LED_PHY3_2, 3, 24),
1201
1202 AR8327_LED_ENTRY(AR8327_LED_PHY4_0, 0, 30),
1203 AR8327_LED_ENTRY(AR8327_LED_PHY4_1, 1, 30),
1204 AR8327_LED_ENTRY(AR8327_LED_PHY4_2, 2, 30),
1205 };
1206
1207 static void
1208 ar8327_set_led_pattern(struct ar8xxx_priv *priv, unsigned int led_num,
1209 enum ar8327_led_pattern pattern)
1210 {
1211 const struct ar8327_led_entry *entry;
1212
1213 entry = &ar8327_led_map[led_num];
1214 ar8xxx_rmw(priv, AR8327_REG_LED_CTRL(entry->reg),
1215 (3 << entry->shift), pattern << entry->shift);
1216 }
1217
1218 static void
1219 ar8327_led_work_func(struct work_struct *work)
1220 {
1221 struct ar8327_led *aled;
1222 u8 pattern;
1223
1224 aled = container_of(work, struct ar8327_led, led_work);
1225
1226 spin_lock(&aled->lock);
1227 pattern = aled->pattern;
1228 spin_unlock(&aled->lock);
1229
1230 ar8327_set_led_pattern(aled->sw_priv, aled->led_num,
1231 pattern);
1232 }
1233
1234 static void
1235 ar8327_led_schedule_change(struct ar8327_led *aled, u8 pattern)
1236 {
1237 if (aled->pattern == pattern)
1238 return;
1239
1240 aled->pattern = pattern;
1241 schedule_work(&aled->led_work);
1242 }
1243
1244 static inline struct ar8327_led *
1245 led_cdev_to_ar8327_led(struct led_classdev *led_cdev)
1246 {
1247 return container_of(led_cdev, struct ar8327_led, cdev);
1248 }
1249
1250 static int
1251 ar8327_led_blink_set(struct led_classdev *led_cdev,
1252 unsigned long *delay_on,
1253 unsigned long *delay_off)
1254 {
1255 struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
1256
1257 if (*delay_on == 0 && *delay_off == 0) {
1258 *delay_on = 125;
1259 *delay_off = 125;
1260 }
1261
1262 if (*delay_on != 125 || *delay_off != 125) {
1263 /*
1264 * The hardware only supports blinking at 4Hz. Fall back
1265 * to software implementation in other cases.
1266 */
1267 return -EINVAL;
1268 }
1269
1270 spin_lock(&aled->lock);
1271
1272 aled->enable_hw_mode = false;
1273 ar8327_led_schedule_change(aled, AR8327_LED_PATTERN_BLINK);
1274
1275 spin_unlock(&aled->lock);
1276
1277 return 0;
1278 }
1279
1280 static void
1281 ar8327_led_set_brightness(struct led_classdev *led_cdev,
1282 enum led_brightness brightness)
1283 {
1284 struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
1285 u8 pattern;
1286 bool active;
1287
1288 active = (brightness != LED_OFF);
1289 active ^= aled->active_low;
1290
1291 pattern = (active) ? AR8327_LED_PATTERN_ON :
1292 AR8327_LED_PATTERN_OFF;
1293
1294 spin_lock(&aled->lock);
1295
1296 aled->enable_hw_mode = false;
1297 ar8327_led_schedule_change(aled, pattern);
1298
1299 spin_unlock(&aled->lock);
1300 }
1301
1302 static ssize_t
1303 ar8327_led_enable_hw_mode_show(struct device *dev,
1304 struct device_attribute *attr,
1305 char *buf)
1306 {
1307 struct led_classdev *led_cdev = dev_get_drvdata(dev);
1308 struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
1309 ssize_t ret = 0;
1310
1311 spin_lock(&aled->lock);
1312 ret += sprintf(buf, "%d\n", aled->enable_hw_mode);
1313 spin_unlock(&aled->lock);
1314
1315 return ret;
1316 }
1317
1318 static ssize_t
1319 ar8327_led_enable_hw_mode_store(struct device *dev,
1320 struct device_attribute *attr,
1321 const char *buf,
1322 size_t size)
1323 {
1324 struct led_classdev *led_cdev = dev_get_drvdata(dev);
1325 struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
1326 u8 pattern;
1327 u8 value;
1328 int ret;
1329
1330 ret = kstrtou8(buf, 10, &value);
1331 if (ret < 0)
1332 return -EINVAL;
1333
1334 spin_lock(&aled->lock);
1335
1336 aled->enable_hw_mode = !!value;
1337 if (aled->enable_hw_mode)
1338 pattern = AR8327_LED_PATTERN_RULE;
1339 else
1340 pattern = AR8327_LED_PATTERN_OFF;
1341
1342 ar8327_led_schedule_change(aled, pattern);
1343
1344 spin_unlock(&aled->lock);
1345
1346 return size;
1347 }
1348
1349 static DEVICE_ATTR(enable_hw_mode, S_IRUGO | S_IWUSR,
1350 ar8327_led_enable_hw_mode_show,
1351 ar8327_led_enable_hw_mode_store);
1352
1353 static int
1354 ar8327_led_register(struct ar8xxx_priv *priv, struct ar8327_led *aled)
1355 {
1356 int ret;
1357
1358 ret = led_classdev_register(NULL, &aled->cdev);
1359 if (ret < 0)
1360 return ret;
1361
1362 if (aled->mode == AR8327_LED_MODE_HW) {
1363 ret = device_create_file(aled->cdev.dev,
1364 &dev_attr_enable_hw_mode);
1365 if (ret)
1366 goto err_unregister;
1367 }
1368
1369 return 0;
1370
1371 err_unregister:
1372 led_classdev_unregister(&aled->cdev);
1373 return ret;
1374 }
1375
1376 static void
1377 ar8327_led_unregister(struct ar8327_led *aled)
1378 {
1379 if (aled->mode == AR8327_LED_MODE_HW)
1380 device_remove_file(aled->cdev.dev, &dev_attr_enable_hw_mode);
1381
1382 led_classdev_unregister(&aled->cdev);
1383 cancel_work_sync(&aled->led_work);
1384 }
1385
1386 static int
1387 ar8327_led_create(struct ar8xxx_priv *priv,
1388 const struct ar8327_led_info *led_info)
1389 {
1390 struct ar8327_data *data = &priv->chip_data.ar8327;
1391 struct ar8327_led *aled;
1392 int ret;
1393
1394 if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS))
1395 return 0;
1396
1397 if (!led_info->name)
1398 return -EINVAL;
1399
1400 if (led_info->led_num >= AR8327_NUM_LEDS)
1401 return -EINVAL;
1402
1403 aled = kzalloc(sizeof(*aled) + strlen(led_info->name) + 1,
1404 GFP_KERNEL);
1405 if (!aled)
1406 return -ENOMEM;
1407
1408 aled->sw_priv = priv;
1409 aled->led_num = led_info->led_num;
1410 aled->active_low = led_info->active_low;
1411 aled->mode = led_info->mode;
1412
1413 if (aled->mode == AR8327_LED_MODE_HW)
1414 aled->enable_hw_mode = true;
1415
1416 aled->name = (char *)(aled + 1);
1417 strcpy(aled->name, led_info->name);
1418
1419 aled->cdev.name = aled->name;
1420 aled->cdev.brightness_set = ar8327_led_set_brightness;
1421 aled->cdev.blink_set = ar8327_led_blink_set;
1422 aled->cdev.default_trigger = led_info->default_trigger;
1423
1424 spin_lock_init(&aled->lock);
1425 mutex_init(&aled->mutex);
1426 INIT_WORK(&aled->led_work, ar8327_led_work_func);
1427
1428 ret = ar8327_led_register(priv, aled);
1429 if (ret)
1430 goto err_free;
1431
1432 data->leds[data->num_leds++] = aled;
1433
1434 return 0;
1435
1436 err_free:
1437 kfree(aled);
1438 return ret;
1439 }
1440
1441 static void
1442 ar8327_led_destroy(struct ar8327_led *aled)
1443 {
1444 ar8327_led_unregister(aled);
1445 kfree(aled);
1446 }
1447
1448 static void
1449 ar8327_leds_init(struct ar8xxx_priv *priv)
1450 {
1451 struct ar8327_data *data;
1452 unsigned i;
1453
1454 if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS))
1455 return;
1456
1457 data = &priv->chip_data.ar8327;
1458
1459 for (i = 0; i < data->num_leds; i++) {
1460 struct ar8327_led *aled;
1461
1462 aled = data->leds[i];
1463
1464 if (aled->enable_hw_mode)
1465 aled->pattern = AR8327_LED_PATTERN_RULE;
1466 else
1467 aled->pattern = AR8327_LED_PATTERN_OFF;
1468
1469 ar8327_set_led_pattern(priv, aled->led_num, aled->pattern);
1470 }
1471 }
1472
1473 static void
1474 ar8327_leds_cleanup(struct ar8xxx_priv *priv)
1475 {
1476 struct ar8327_data *data = &priv->chip_data.ar8327;
1477 unsigned i;
1478
1479 if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS))
1480 return;
1481
1482 for (i = 0; i < data->num_leds; i++) {
1483 struct ar8327_led *aled;
1484
1485 aled = data->leds[i];
1486 ar8327_led_destroy(aled);
1487 }
1488
1489 kfree(data->leds);
1490 }
1491
1492 static int
1493 ar8327_hw_config_pdata(struct ar8xxx_priv *priv,
1494 struct ar8327_platform_data *pdata)
1495 {
1496 struct ar8327_led_cfg *led_cfg;
1497 struct ar8327_data *data;
1498 u32 pos, new_pos;
1499 u32 t;
1500
1501 if (!pdata)
1502 return -EINVAL;
1503
1504 priv->get_port_link = pdata->get_port_link;
1505
1506 data = &priv->chip_data.ar8327;
1507
1508 data->port0_status = ar8327_get_port_init_status(&pdata->port0_cfg);
1509 data->port6_status = ar8327_get_port_init_status(&pdata->port6_cfg);
1510
1511 t = ar8327_get_pad_cfg(pdata->pad0_cfg);
1512 if (chip_is_ar8337(priv))
1513 t |= AR8337_PAD_MAC06_EXCHANGE_EN;
1514
1515 priv->write(priv, AR8327_REG_PAD0_MODE, t);
1516 t = ar8327_get_pad_cfg(pdata->pad5_cfg);
1517 priv->write(priv, AR8327_REG_PAD5_MODE, t);
1518 t = ar8327_get_pad_cfg(pdata->pad6_cfg);
1519 priv->write(priv, AR8327_REG_PAD6_MODE, t);
1520
1521 pos = priv->read(priv, AR8327_REG_POWER_ON_STRIP);
1522 new_pos = pos;
1523
1524 led_cfg = pdata->led_cfg;
1525 if (led_cfg) {
1526 if (led_cfg->open_drain)
1527 new_pos |= AR8327_POWER_ON_STRIP_LED_OPEN_EN;
1528 else
1529 new_pos &= ~AR8327_POWER_ON_STRIP_LED_OPEN_EN;
1530
1531 priv->write(priv, AR8327_REG_LED_CTRL0, led_cfg->led_ctrl0);
1532 priv->write(priv, AR8327_REG_LED_CTRL1, led_cfg->led_ctrl1);
1533 priv->write(priv, AR8327_REG_LED_CTRL2, led_cfg->led_ctrl2);
1534 priv->write(priv, AR8327_REG_LED_CTRL3, led_cfg->led_ctrl3);
1535
1536 if (new_pos != pos)
1537 new_pos |= AR8327_POWER_ON_STRIP_POWER_ON_SEL;
1538 }
1539
1540 if (pdata->sgmii_cfg) {
1541 t = pdata->sgmii_cfg->sgmii_ctrl;
1542 if (priv->chip_rev == 1)
1543 t |= AR8327_SGMII_CTRL_EN_PLL |
1544 AR8327_SGMII_CTRL_EN_RX |
1545 AR8327_SGMII_CTRL_EN_TX;
1546 else
1547 t &= ~(AR8327_SGMII_CTRL_EN_PLL |
1548 AR8327_SGMII_CTRL_EN_RX |
1549 AR8327_SGMII_CTRL_EN_TX);
1550
1551 priv->write(priv, AR8327_REG_SGMII_CTRL, t);
1552
1553 if (pdata->sgmii_cfg->serdes_aen)
1554 new_pos &= ~AR8327_POWER_ON_STRIP_SERDES_AEN;
1555 else
1556 new_pos |= AR8327_POWER_ON_STRIP_SERDES_AEN;
1557 }
1558
1559 priv->write(priv, AR8327_REG_POWER_ON_STRIP, new_pos);
1560
1561 if (pdata->leds && pdata->num_leds) {
1562 int i;
1563
1564 data->leds = kzalloc(pdata->num_leds * sizeof(void *),
1565 GFP_KERNEL);
1566 if (!data->leds)
1567 return -ENOMEM;
1568
1569 for (i = 0; i < pdata->num_leds; i++)
1570 ar8327_led_create(priv, &pdata->leds[i]);
1571 }
1572
1573 return 0;
1574 }
1575
1576 #ifdef CONFIG_OF
1577 static int
1578 ar8327_hw_config_of(struct ar8xxx_priv *priv, struct device_node *np)
1579 {
1580 const __be32 *paddr;
1581 int len;
1582 int i;
1583
1584 paddr = of_get_property(np, "qca,ar8327-initvals", &len);
1585 if (!paddr || len < (2 * sizeof(*paddr)))
1586 return -EINVAL;
1587
1588 len /= sizeof(*paddr);
1589
1590 for (i = 0; i < len - 1; i += 2) {
1591 u32 reg;
1592 u32 val;
1593
1594 reg = be32_to_cpup(paddr + i);
1595 val = be32_to_cpup(paddr + i + 1);
1596
1597 switch (reg) {
1598 case AR8327_REG_PORT_STATUS(0):
1599 priv->chip_data.ar8327.port0_status = val;
1600 break;
1601 case AR8327_REG_PORT_STATUS(6):
1602 priv->chip_data.ar8327.port6_status = val;
1603 break;
1604 default:
1605 priv->write(priv, reg, val);
1606 break;
1607 }
1608 }
1609
1610 return 0;
1611 }
1612 #else
1613 static inline int
1614 ar8327_hw_config_of(struct ar8xxx_priv *priv, struct device_node *np)
1615 {
1616 return -EINVAL;
1617 }
1618 #endif
1619
1620 static int
1621 ar8327_hw_init(struct ar8xxx_priv *priv)
1622 {
1623 int ret;
1624
1625 if (priv->phy->dev.of_node)
1626 ret = ar8327_hw_config_of(priv, priv->phy->dev.of_node);
1627 else
1628 ret = ar8327_hw_config_pdata(priv,
1629 priv->phy->dev.platform_data);
1630
1631 if (ret)
1632 return ret;
1633
1634 ar8327_leds_init(priv);
1635
1636 ar8xxx_phy_init(priv, true);
1637
1638 return 0;
1639 }
1640
1641 static void
1642 ar8327_cleanup(struct ar8xxx_priv *priv)
1643 {
1644 ar8327_leds_cleanup(priv);
1645 }
1646
1647 static void
1648 ar8327_init_globals(struct ar8xxx_priv *priv)
1649 {
1650 u32 t;
1651
1652 /* enable CPU port and disable mirror port */
1653 t = AR8327_FWD_CTRL0_CPU_PORT_EN |
1654 AR8327_FWD_CTRL0_MIRROR_PORT;
1655 priv->write(priv, AR8327_REG_FWD_CTRL0, t);
1656
1657 /* forward multicast and broadcast frames to CPU */
1658 t = (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_UC_FLOOD_S) |
1659 (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_MC_FLOOD_S) |
1660 (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_BC_FLOOD_S);
1661 priv->write(priv, AR8327_REG_FWD_CTRL1, t);
1662
1663 /* enable jumbo frames */
1664 ar8xxx_rmw(priv, AR8327_REG_MAX_FRAME_SIZE,
1665 AR8327_MAX_FRAME_SIZE_MTU, 9018 + 8 + 2);
1666
1667 /* Enable MIB counters */
1668 ar8xxx_reg_set(priv, AR8327_REG_MODULE_EN,
1669 AR8327_MODULE_EN_MIB);
1670
1671 /* Disable EEE on all ports due to stability issues */
1672 t = priv->read(priv, AR8327_REG_EEE_CTRL);
1673 t |= AR8327_EEE_CTRL_DISABLE_PHY(0) |
1674 AR8327_EEE_CTRL_DISABLE_PHY(1) |
1675 AR8327_EEE_CTRL_DISABLE_PHY(2) |
1676 AR8327_EEE_CTRL_DISABLE_PHY(3) |
1677 AR8327_EEE_CTRL_DISABLE_PHY(4);
1678 priv->write(priv, AR8327_REG_EEE_CTRL, t);
1679 }
1680
1681 static void
1682 ar8327_init_port(struct ar8xxx_priv *priv, int port)
1683 {
1684 u32 t;
1685
1686 if (port == AR8216_PORT_CPU)
1687 t = priv->chip_data.ar8327.port0_status;
1688 else if (port == 6)
1689 t = priv->chip_data.ar8327.port6_status;
1690 else
1691 t = AR8216_PORT_STATUS_LINK_AUTO;
1692
1693 priv->write(priv, AR8327_REG_PORT_STATUS(port), t);
1694 priv->write(priv, AR8327_REG_PORT_HEADER(port), 0);
1695
1696 t = 1 << AR8327_PORT_VLAN0_DEF_SVID_S;
1697 t |= 1 << AR8327_PORT_VLAN0_DEF_CVID_S;
1698 priv->write(priv, AR8327_REG_PORT_VLAN0(port), t);
1699
1700 t = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH << AR8327_PORT_VLAN1_OUT_MODE_S;
1701 priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
1702
1703 t = AR8327_PORT_LOOKUP_LEARN;
1704 t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
1705 priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
1706 }
1707
1708 static u32
1709 ar8327_read_port_status(struct ar8xxx_priv *priv, int port)
1710 {
1711 return priv->read(priv, AR8327_REG_PORT_STATUS(port));
1712 }
1713
1714 static int
1715 ar8327_atu_flush(struct ar8xxx_priv *priv)
1716 {
1717 int ret;
1718
1719 ret = ar8216_wait_bit(priv, AR8327_REG_ATU_FUNC,
1720 AR8327_ATU_FUNC_BUSY, 0);
1721 if (!ret)
1722 priv->write(priv, AR8327_REG_ATU_FUNC,
1723 AR8327_ATU_FUNC_OP_FLUSH);
1724
1725 return ret;
1726 }
1727
1728 static void
1729 ar8327_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
1730 {
1731 if (ar8216_wait_bit(priv, AR8327_REG_VTU_FUNC1,
1732 AR8327_VTU_FUNC1_BUSY, 0))
1733 return;
1734
1735 if ((op & AR8327_VTU_FUNC1_OP) == AR8327_VTU_FUNC1_OP_LOAD)
1736 priv->write(priv, AR8327_REG_VTU_FUNC0, val);
1737
1738 op |= AR8327_VTU_FUNC1_BUSY;
1739 priv->write(priv, AR8327_REG_VTU_FUNC1, op);
1740 }
1741
1742 static void
1743 ar8327_vtu_flush(struct ar8xxx_priv *priv)
1744 {
1745 ar8327_vtu_op(priv, AR8327_VTU_FUNC1_OP_FLUSH, 0);
1746 }
1747
1748 static void
1749 ar8327_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)
1750 {
1751 u32 op;
1752 u32 val;
1753 int i;
1754
1755 op = AR8327_VTU_FUNC1_OP_LOAD | (vid << AR8327_VTU_FUNC1_VID_S);
1756 val = AR8327_VTU_FUNC0_VALID | AR8327_VTU_FUNC0_IVL;
1757 for (i = 0; i < AR8327_NUM_PORTS; i++) {
1758 u32 mode;
1759
1760 if ((port_mask & BIT(i)) == 0)
1761 mode = AR8327_VTU_FUNC0_EG_MODE_NOT;
1762 else if (priv->vlan == 0)
1763 mode = AR8327_VTU_FUNC0_EG_MODE_KEEP;
1764 else if ((priv->vlan_tagged & BIT(i)) || (priv->vlan_id[priv->pvid[i]] != vid))
1765 mode = AR8327_VTU_FUNC0_EG_MODE_TAG;
1766 else
1767 mode = AR8327_VTU_FUNC0_EG_MODE_UNTAG;
1768
1769 val |= mode << AR8327_VTU_FUNC0_EG_MODE_S(i);
1770 }
1771 ar8327_vtu_op(priv, op, val);
1772 }
1773
1774 static void
1775 ar8327_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
1776 {
1777 u32 t;
1778 u32 egress, ingress;
1779 u32 pvid = priv->vlan_id[priv->pvid[port]];
1780
1781 if (priv->vlan) {
1782 egress = AR8327_PORT_VLAN1_OUT_MODE_UNMOD;
1783 ingress = AR8216_IN_SECURE;
1784 } else {
1785 egress = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH;
1786 ingress = AR8216_IN_PORT_ONLY;
1787 }
1788
1789 t = pvid << AR8327_PORT_VLAN0_DEF_SVID_S;
1790 t |= pvid << AR8327_PORT_VLAN0_DEF_CVID_S;
1791 priv->write(priv, AR8327_REG_PORT_VLAN0(port), t);
1792
1793 t = AR8327_PORT_VLAN1_PORT_VLAN_PROP;
1794 t |= egress << AR8327_PORT_VLAN1_OUT_MODE_S;
1795 priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
1796
1797 t = members;
1798 t |= AR8327_PORT_LOOKUP_LEARN;
1799 t |= ingress << AR8327_PORT_LOOKUP_IN_MODE_S;
1800 t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
1801 priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
1802 }
1803
1804 static void
1805 ar8327_fixup_phys(struct ar8xxx_priv *priv)
1806 {
1807 int i;
1808
1809 for (i = 0; i < AR8XXX_NUM_PHYS; i++)
1810 ar8327_phy_fixup(priv, i);
1811 }
1812
1813 static const struct ar8xxx_chip ar8327_chip = {
1814 .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
1815 .hw_init = ar8327_hw_init,
1816 .cleanup = ar8327_cleanup,
1817 .init_globals = ar8327_init_globals,
1818 .init_port = ar8327_init_port,
1819 .setup_port = ar8327_setup_port,
1820 .read_port_status = ar8327_read_port_status,
1821 .atu_flush = ar8327_atu_flush,
1822 .vtu_flush = ar8327_vtu_flush,
1823 .vtu_load_vlan = ar8327_vtu_load_vlan,
1824 .fixup_phys = ar8327_fixup_phys,
1825
1826 .num_mibs = ARRAY_SIZE(ar8236_mibs),
1827 .mib_decs = ar8236_mibs,
1828 };
1829
1830 static int
1831 ar8xxx_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
1832 struct switch_val *val)
1833 {
1834 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1835 priv->vlan = !!val->value.i;
1836 return 0;
1837 }
1838
1839 static int
1840 ar8xxx_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
1841 struct switch_val *val)
1842 {
1843 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1844 val->value.i = priv->vlan;
1845 return 0;
1846 }
1847
1848
1849 static int
1850 ar8xxx_sw_set_pvid(struct switch_dev *dev, int port, int vlan)
1851 {
1852 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1853
1854 /* make sure no invalid PVIDs get set */
1855
1856 if (vlan >= dev->vlans)
1857 return -EINVAL;
1858
1859 priv->pvid[port] = vlan;
1860 return 0;
1861 }
1862
1863 static int
1864 ar8xxx_sw_get_pvid(struct switch_dev *dev, int port, int *vlan)
1865 {
1866 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1867 *vlan = priv->pvid[port];
1868 return 0;
1869 }
1870
1871 static int
1872 ar8xxx_sw_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
1873 struct switch_val *val)
1874 {
1875 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1876 priv->vlan_id[val->port_vlan] = val->value.i;
1877 return 0;
1878 }
1879
1880 static int
1881 ar8xxx_sw_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
1882 struct switch_val *val)
1883 {
1884 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1885 val->value.i = priv->vlan_id[val->port_vlan];
1886 return 0;
1887 }
1888
1889 static int
1890 ar8xxx_sw_get_port_link(struct switch_dev *dev, int port,
1891 struct switch_port_link *link)
1892 {
1893 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1894
1895 ar8216_read_port_link(priv, port, link);
1896 return 0;
1897 }
1898
1899 static int
1900 ar8xxx_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
1901 {
1902 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1903 u8 ports = priv->vlan_table[val->port_vlan];
1904 int i;
1905
1906 val->len = 0;
1907 for (i = 0; i < dev->ports; i++) {
1908 struct switch_port *p;
1909
1910 if (!(ports & (1 << i)))
1911 continue;
1912
1913 p = &val->value.ports[val->len++];
1914 p->id = i;
1915 if (priv->vlan_tagged & (1 << i))
1916 p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
1917 else
1918 p->flags = 0;
1919 }
1920 return 0;
1921 }
1922
1923 static int
1924 ar8327_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
1925 {
1926 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1927 u8 ports = priv->vlan_table[val->port_vlan];
1928 int i;
1929
1930 val->len = 0;
1931 for (i = 0; i < dev->ports; i++) {
1932 struct switch_port *p;
1933
1934 if (!(ports & (1 << i)))
1935 continue;
1936
1937 p = &val->value.ports[val->len++];
1938 p->id = i;
1939 if ((priv->vlan_tagged & (1 << i)) || (priv->pvid[i] != val->port_vlan))
1940 p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
1941 else
1942 p->flags = 0;
1943 }
1944 return 0;
1945 }
1946
1947 static int
1948 ar8xxx_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
1949 {
1950 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1951 u8 *vt = &priv->vlan_table[val->port_vlan];
1952 int i, j;
1953
1954 *vt = 0;
1955 for (i = 0; i < val->len; i++) {
1956 struct switch_port *p = &val->value.ports[i];
1957
1958 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
1959 priv->vlan_tagged |= (1 << p->id);
1960 } else {
1961 priv->vlan_tagged &= ~(1 << p->id);
1962 priv->pvid[p->id] = val->port_vlan;
1963
1964 /* make sure that an untagged port does not
1965 * appear in other vlans */
1966 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1967 if (j == val->port_vlan)
1968 continue;
1969 priv->vlan_table[j] &= ~(1 << p->id);
1970 }
1971 }
1972
1973 *vt |= 1 << p->id;
1974 }
1975 return 0;
1976 }
1977
1978 static int
1979 ar8327_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
1980 {
1981 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1982 u8 *vt = &priv->vlan_table[val->port_vlan];
1983 int i;
1984
1985 *vt = 0;
1986 for (i = 0; i < val->len; i++) {
1987 struct switch_port *p = &val->value.ports[i];
1988
1989 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
1990 if (val->port_vlan == priv->pvid[p->id]) {
1991 priv->vlan_tagged |= (1 << p->id);
1992 }
1993 } else {
1994 priv->vlan_tagged &= ~(1 << p->id);
1995 priv->pvid[p->id] = val->port_vlan;
1996 }
1997
1998 *vt |= 1 << p->id;
1999 }
2000 return 0;
2001 }
2002
2003 static void
2004 ar8327_set_mirror_regs(struct ar8xxx_priv *priv)
2005 {
2006 int port;
2007
2008 /* reset all mirror registers */
2009 ar8xxx_rmw(priv, AR8327_REG_FWD_CTRL0,
2010 AR8327_FWD_CTRL0_MIRROR_PORT,
2011 (0xF << AR8327_FWD_CTRL0_MIRROR_PORT_S));
2012 for (port = 0; port < AR8327_NUM_PORTS; port++) {
2013 ar8xxx_rmw(priv, AR8327_REG_PORT_LOOKUP(port),
2014 AR8327_PORT_LOOKUP_ING_MIRROR_EN,
2015 0);
2016
2017 ar8xxx_rmw(priv, AR8327_REG_PORT_HOL_CTRL1(port),
2018 AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN,
2019 0);
2020 }
2021
2022 /* now enable mirroring if necessary */
2023 if (priv->source_port >= AR8327_NUM_PORTS ||
2024 priv->monitor_port >= AR8327_NUM_PORTS ||
2025 priv->source_port == priv->monitor_port) {
2026 return;
2027 }
2028
2029 ar8xxx_rmw(priv, AR8327_REG_FWD_CTRL0,
2030 AR8327_FWD_CTRL0_MIRROR_PORT,
2031 (priv->monitor_port << AR8327_FWD_CTRL0_MIRROR_PORT_S));
2032
2033 if (priv->mirror_rx)
2034 ar8xxx_rmw(priv, AR8327_REG_PORT_LOOKUP(priv->source_port),
2035 AR8327_PORT_LOOKUP_ING_MIRROR_EN,
2036 AR8327_PORT_LOOKUP_ING_MIRROR_EN);
2037
2038 if (priv->mirror_tx)
2039 ar8xxx_rmw(priv, AR8327_REG_PORT_HOL_CTRL1(priv->source_port),
2040 AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN,
2041 AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN);
2042 }
2043
2044 static void
2045 ar8216_set_mirror_regs(struct ar8xxx_priv *priv)
2046 {
2047 int port;
2048
2049 /* reset all mirror registers */
2050 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
2051 AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
2052 (0xF << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
2053 for (port = 0; port < AR8216_NUM_PORTS; port++) {
2054 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
2055 AR8216_PORT_CTRL_MIRROR_RX,
2056 0);
2057
2058 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
2059 AR8216_PORT_CTRL_MIRROR_TX,
2060 0);
2061 }
2062
2063 /* now enable mirroring if necessary */
2064 if (priv->source_port >= AR8216_NUM_PORTS ||
2065 priv->monitor_port >= AR8216_NUM_PORTS ||
2066 priv->source_port == priv->monitor_port) {
2067 return;
2068 }
2069
2070 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
2071 AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
2072 (priv->monitor_port << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
2073
2074 if (priv->mirror_rx)
2075 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(priv->source_port),
2076 AR8216_PORT_CTRL_MIRROR_RX,
2077 AR8216_PORT_CTRL_MIRROR_RX);
2078
2079 if (priv->mirror_tx)
2080 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(priv->source_port),
2081 AR8216_PORT_CTRL_MIRROR_TX,
2082 AR8216_PORT_CTRL_MIRROR_TX);
2083 }
2084
2085 static void
2086 ar8xxx_set_mirror_regs(struct ar8xxx_priv *priv)
2087 {
2088 if (chip_is_ar8327(priv) || chip_is_ar8337(priv)) {
2089 ar8327_set_mirror_regs(priv);
2090 } else {
2091 ar8216_set_mirror_regs(priv);
2092 }
2093 }
2094
2095 static int
2096 ar8xxx_sw_hw_apply(struct switch_dev *dev)
2097 {
2098 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2099 u8 portmask[AR8X16_MAX_PORTS];
2100 int i, j;
2101
2102 mutex_lock(&priv->reg_mutex);
2103 /* flush all vlan translation unit entries */
2104 priv->chip->vtu_flush(priv);
2105
2106 memset(portmask, 0, sizeof(portmask));
2107 if (!priv->init) {
2108 /* calculate the port destination masks and load vlans
2109 * into the vlan translation unit */
2110 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
2111 u8 vp = priv->vlan_table[j];
2112
2113 if (!vp)
2114 continue;
2115
2116 for (i = 0; i < dev->ports; i++) {
2117 u8 mask = (1 << i);
2118 if (vp & mask)
2119 portmask[i] |= vp & ~mask;
2120 }
2121
2122 priv->chip->vtu_load_vlan(priv, priv->vlan_id[j],
2123 priv->vlan_table[j]);
2124 }
2125 } else {
2126 /* vlan disabled:
2127 * isolate all ports, but connect them to the cpu port */
2128 for (i = 0; i < dev->ports; i++) {
2129 if (i == AR8216_PORT_CPU)
2130 continue;
2131
2132 portmask[i] = 1 << AR8216_PORT_CPU;
2133 portmask[AR8216_PORT_CPU] |= (1 << i);
2134 }
2135 }
2136
2137 /* update the port destination mask registers and tag settings */
2138 for (i = 0; i < dev->ports; i++) {
2139 priv->chip->setup_port(priv, i, portmask[i]);
2140 }
2141
2142 ar8xxx_set_mirror_regs(priv);
2143
2144 mutex_unlock(&priv->reg_mutex);
2145 return 0;
2146 }
2147
2148 static int
2149 ar8xxx_sw_reset_switch(struct switch_dev *dev)
2150 {
2151 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2152 int i;
2153
2154 mutex_lock(&priv->reg_mutex);
2155 memset(&priv->vlan, 0, sizeof(struct ar8xxx_priv) -
2156 offsetof(struct ar8xxx_priv, vlan));
2157
2158 for (i = 0; i < AR8X16_MAX_VLANS; i++)
2159 priv->vlan_id[i] = i;
2160
2161 /* Configure all ports */
2162 for (i = 0; i < dev->ports; i++)
2163 priv->chip->init_port(priv, i);
2164
2165 priv->mirror_rx = false;
2166 priv->mirror_tx = false;
2167 priv->source_port = 0;
2168 priv->monitor_port = 0;
2169
2170 priv->chip->init_globals(priv);
2171
2172 mutex_unlock(&priv->reg_mutex);
2173
2174 return ar8xxx_sw_hw_apply(dev);
2175 }
2176
2177 static int
2178 ar8xxx_sw_set_reset_mibs(struct switch_dev *dev,
2179 const struct switch_attr *attr,
2180 struct switch_val *val)
2181 {
2182 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2183 unsigned int len;
2184 int ret;
2185
2186 if (!ar8xxx_has_mib_counters(priv))
2187 return -EOPNOTSUPP;
2188
2189 mutex_lock(&priv->mib_lock);
2190
2191 len = priv->dev.ports * priv->chip->num_mibs *
2192 sizeof(*priv->mib_stats);
2193 memset(priv->mib_stats, '\0', len);
2194 ret = ar8xxx_mib_flush(priv);
2195 if (ret)
2196 goto unlock;
2197
2198 ret = 0;
2199
2200 unlock:
2201 mutex_unlock(&priv->mib_lock);
2202 return ret;
2203 }
2204
2205 static int
2206 ar8xxx_sw_set_mirror_rx_enable(struct switch_dev *dev,
2207 const struct switch_attr *attr,
2208 struct switch_val *val)
2209 {
2210 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2211
2212 mutex_lock(&priv->reg_mutex);
2213 priv->mirror_rx = !!val->value.i;
2214 ar8xxx_set_mirror_regs(priv);
2215 mutex_unlock(&priv->reg_mutex);
2216
2217 return 0;
2218 }
2219
2220 static int
2221 ar8xxx_sw_get_mirror_rx_enable(struct switch_dev *dev,
2222 const struct switch_attr *attr,
2223 struct switch_val *val)
2224 {
2225 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2226 val->value.i = priv->mirror_rx;
2227 return 0;
2228 }
2229
2230 static int
2231 ar8xxx_sw_set_mirror_tx_enable(struct switch_dev *dev,
2232 const struct switch_attr *attr,
2233 struct switch_val *val)
2234 {
2235 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2236
2237 mutex_lock(&priv->reg_mutex);
2238 priv->mirror_tx = !!val->value.i;
2239 ar8xxx_set_mirror_regs(priv);
2240 mutex_unlock(&priv->reg_mutex);
2241
2242 return 0;
2243 }
2244
2245 static int
2246 ar8xxx_sw_get_mirror_tx_enable(struct switch_dev *dev,
2247 const struct switch_attr *attr,
2248 struct switch_val *val)
2249 {
2250 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2251 val->value.i = priv->mirror_tx;
2252 return 0;
2253 }
2254
2255 static int
2256 ar8xxx_sw_set_mirror_monitor_port(struct switch_dev *dev,
2257 const struct switch_attr *attr,
2258 struct switch_val *val)
2259 {
2260 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2261
2262 mutex_lock(&priv->reg_mutex);
2263 priv->monitor_port = val->value.i;
2264 ar8xxx_set_mirror_regs(priv);
2265 mutex_unlock(&priv->reg_mutex);
2266
2267 return 0;
2268 }
2269
2270 static int
2271 ar8xxx_sw_get_mirror_monitor_port(struct switch_dev *dev,
2272 const struct switch_attr *attr,
2273 struct switch_val *val)
2274 {
2275 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2276 val->value.i = priv->monitor_port;
2277 return 0;
2278 }
2279
2280 static int
2281 ar8xxx_sw_set_mirror_source_port(struct switch_dev *dev,
2282 const struct switch_attr *attr,
2283 struct switch_val *val)
2284 {
2285 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2286
2287 mutex_lock(&priv->reg_mutex);
2288 priv->source_port = val->value.i;
2289 ar8xxx_set_mirror_regs(priv);
2290 mutex_unlock(&priv->reg_mutex);
2291
2292 return 0;
2293 }
2294
2295 static int
2296 ar8xxx_sw_get_mirror_source_port(struct switch_dev *dev,
2297 const struct switch_attr *attr,
2298 struct switch_val *val)
2299 {
2300 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2301 val->value.i = priv->source_port;
2302 return 0;
2303 }
2304
2305 static int
2306 ar8xxx_sw_set_port_reset_mib(struct switch_dev *dev,
2307 const struct switch_attr *attr,
2308 struct switch_val *val)
2309 {
2310 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2311 int port;
2312 int ret;
2313
2314 if (!ar8xxx_has_mib_counters(priv))
2315 return -EOPNOTSUPP;
2316
2317 port = val->port_vlan;
2318 if (port >= dev->ports)
2319 return -EINVAL;
2320
2321 mutex_lock(&priv->mib_lock);
2322 ret = ar8xxx_mib_capture(priv);
2323 if (ret)
2324 goto unlock;
2325
2326 ar8xxx_mib_fetch_port_stat(priv, port, true);
2327
2328 ret = 0;
2329
2330 unlock:
2331 mutex_unlock(&priv->mib_lock);
2332 return ret;
2333 }
2334
2335 static int
2336 ar8xxx_sw_get_port_mib(struct switch_dev *dev,
2337 const struct switch_attr *attr,
2338 struct switch_val *val)
2339 {
2340 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2341 const struct ar8xxx_chip *chip = priv->chip;
2342 u64 *mib_stats;
2343 int port;
2344 int ret;
2345 char *buf = priv->buf;
2346 int i, len = 0;
2347
2348 if (!ar8xxx_has_mib_counters(priv))
2349 return -EOPNOTSUPP;
2350
2351 port = val->port_vlan;
2352 if (port >= dev->ports)
2353 return -EINVAL;
2354
2355 mutex_lock(&priv->mib_lock);
2356 ret = ar8xxx_mib_capture(priv);
2357 if (ret)
2358 goto unlock;
2359
2360 ar8xxx_mib_fetch_port_stat(priv, port, false);
2361
2362 len += snprintf(buf + len, sizeof(priv->buf) - len,
2363 "Port %d MIB counters\n",
2364 port);
2365
2366 mib_stats = &priv->mib_stats[port * chip->num_mibs];
2367 for (i = 0; i < chip->num_mibs; i++)
2368 len += snprintf(buf + len, sizeof(priv->buf) - len,
2369 "%-12s: %llu\n",
2370 chip->mib_decs[i].name,
2371 mib_stats[i]);
2372
2373 val->value.s = buf;
2374 val->len = len;
2375
2376 ret = 0;
2377
2378 unlock:
2379 mutex_unlock(&priv->mib_lock);
2380 return ret;
2381 }
2382
2383 static struct switch_attr ar8xxx_sw_attr_globals[] = {
2384 {
2385 .type = SWITCH_TYPE_INT,
2386 .name = "enable_vlan",
2387 .description = "Enable VLAN mode",
2388 .set = ar8xxx_sw_set_vlan,
2389 .get = ar8xxx_sw_get_vlan,
2390 .max = 1
2391 },
2392 {
2393 .type = SWITCH_TYPE_NOVAL,
2394 .name = "reset_mibs",
2395 .description = "Reset all MIB counters",
2396 .set = ar8xxx_sw_set_reset_mibs,
2397 },
2398 {
2399 .type = SWITCH_TYPE_INT,
2400 .name = "enable_mirror_rx",
2401 .description = "Enable mirroring of RX packets",
2402 .set = ar8xxx_sw_set_mirror_rx_enable,
2403 .get = ar8xxx_sw_get_mirror_rx_enable,
2404 .max = 1
2405 },
2406 {
2407 .type = SWITCH_TYPE_INT,
2408 .name = "enable_mirror_tx",
2409 .description = "Enable mirroring of TX packets",
2410 .set = ar8xxx_sw_set_mirror_tx_enable,
2411 .get = ar8xxx_sw_get_mirror_tx_enable,
2412 .max = 1
2413 },
2414 {
2415 .type = SWITCH_TYPE_INT,
2416 .name = "mirror_monitor_port",
2417 .description = "Mirror monitor port",
2418 .set = ar8xxx_sw_set_mirror_monitor_port,
2419 .get = ar8xxx_sw_get_mirror_monitor_port,
2420 .max = AR8216_NUM_PORTS - 1
2421 },
2422 {
2423 .type = SWITCH_TYPE_INT,
2424 .name = "mirror_source_port",
2425 .description = "Mirror source port",
2426 .set = ar8xxx_sw_set_mirror_source_port,
2427 .get = ar8xxx_sw_get_mirror_source_port,
2428 .max = AR8216_NUM_PORTS - 1
2429 },
2430 };
2431
2432 static struct switch_attr ar8327_sw_attr_globals[] = {
2433 {
2434 .type = SWITCH_TYPE_INT,
2435 .name = "enable_vlan",
2436 .description = "Enable VLAN mode",
2437 .set = ar8xxx_sw_set_vlan,
2438 .get = ar8xxx_sw_get_vlan,
2439 .max = 1
2440 },
2441 {
2442 .type = SWITCH_TYPE_NOVAL,
2443 .name = "reset_mibs",
2444 .description = "Reset all MIB counters",
2445 .set = ar8xxx_sw_set_reset_mibs,
2446 },
2447 {
2448 .type = SWITCH_TYPE_INT,
2449 .name = "enable_mirror_rx",
2450 .description = "Enable mirroring of RX packets",
2451 .set = ar8xxx_sw_set_mirror_rx_enable,
2452 .get = ar8xxx_sw_get_mirror_rx_enable,
2453 .max = 1
2454 },
2455 {
2456 .type = SWITCH_TYPE_INT,
2457 .name = "enable_mirror_tx",
2458 .description = "Enable mirroring of TX packets",
2459 .set = ar8xxx_sw_set_mirror_tx_enable,
2460 .get = ar8xxx_sw_get_mirror_tx_enable,
2461 .max = 1
2462 },
2463 {
2464 .type = SWITCH_TYPE_INT,
2465 .name = "mirror_monitor_port",
2466 .description = "Mirror monitor port",
2467 .set = ar8xxx_sw_set_mirror_monitor_port,
2468 .get = ar8xxx_sw_get_mirror_monitor_port,
2469 .max = AR8327_NUM_PORTS - 1
2470 },
2471 {
2472 .type = SWITCH_TYPE_INT,
2473 .name = "mirror_source_port",
2474 .description = "Mirror source port",
2475 .set = ar8xxx_sw_set_mirror_source_port,
2476 .get = ar8xxx_sw_get_mirror_source_port,
2477 .max = AR8327_NUM_PORTS - 1
2478 },
2479 };
2480
2481 static struct switch_attr ar8xxx_sw_attr_port[] = {
2482 {
2483 .type = SWITCH_TYPE_NOVAL,
2484 .name = "reset_mib",
2485 .description = "Reset single port MIB counters",
2486 .set = ar8xxx_sw_set_port_reset_mib,
2487 },
2488 {
2489 .type = SWITCH_TYPE_STRING,
2490 .name = "mib",
2491 .description = "Get port's MIB counters",
2492 .set = NULL,
2493 .get = ar8xxx_sw_get_port_mib,
2494 },
2495 };
2496
2497 static struct switch_attr ar8xxx_sw_attr_vlan[] = {
2498 {
2499 .type = SWITCH_TYPE_INT,
2500 .name = "vid",
2501 .description = "VLAN ID (0-4094)",
2502 .set = ar8xxx_sw_set_vid,
2503 .get = ar8xxx_sw_get_vid,
2504 .max = 4094,
2505 },
2506 };
2507
2508 static const struct switch_dev_ops ar8xxx_sw_ops = {
2509 .attr_global = {
2510 .attr = ar8xxx_sw_attr_globals,
2511 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_globals),
2512 },
2513 .attr_port = {
2514 .attr = ar8xxx_sw_attr_port,
2515 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_port),
2516 },
2517 .attr_vlan = {
2518 .attr = ar8xxx_sw_attr_vlan,
2519 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan),
2520 },
2521 .get_port_pvid = ar8xxx_sw_get_pvid,
2522 .set_port_pvid = ar8xxx_sw_set_pvid,
2523 .get_vlan_ports = ar8xxx_sw_get_ports,
2524 .set_vlan_ports = ar8xxx_sw_set_ports,
2525 .apply_config = ar8xxx_sw_hw_apply,
2526 .reset_switch = ar8xxx_sw_reset_switch,
2527 .get_port_link = ar8xxx_sw_get_port_link,
2528 };
2529
2530 static const struct switch_dev_ops ar8327_sw_ops = {
2531 .attr_global = {
2532 .attr = ar8327_sw_attr_globals,
2533 .n_attr = ARRAY_SIZE(ar8327_sw_attr_globals),
2534 },
2535 .attr_port = {
2536 .attr = ar8xxx_sw_attr_port,
2537 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_port),
2538 },
2539 .attr_vlan = {
2540 .attr = ar8xxx_sw_attr_vlan,
2541 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan),
2542 },
2543 .get_port_pvid = ar8xxx_sw_get_pvid,
2544 .set_port_pvid = ar8xxx_sw_set_pvid,
2545 .get_vlan_ports = ar8327_sw_get_ports,
2546 .set_vlan_ports = ar8327_sw_set_ports,
2547 .apply_config = ar8xxx_sw_hw_apply,
2548 .reset_switch = ar8xxx_sw_reset_switch,
2549 .get_port_link = ar8xxx_sw_get_port_link,
2550 };
2551
2552 static int
2553 ar8xxx_id_chip(struct ar8xxx_priv *priv)
2554 {
2555 u32 val;
2556 u16 id;
2557 int i;
2558
2559 val = priv->read(priv, AR8216_REG_CTRL);
2560 if (val == ~0)
2561 return -ENODEV;
2562
2563 id = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
2564 for (i = 0; i < AR8X16_PROBE_RETRIES; i++) {
2565 u16 t;
2566
2567 val = priv->read(priv, AR8216_REG_CTRL);
2568 if (val == ~0)
2569 return -ENODEV;
2570
2571 t = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
2572 if (t != id)
2573 return -ENODEV;
2574 }
2575
2576 priv->chip_ver = (id & AR8216_CTRL_VERSION) >> AR8216_CTRL_VERSION_S;
2577 priv->chip_rev = (id & AR8216_CTRL_REVISION);
2578
2579 switch (priv->chip_ver) {
2580 case AR8XXX_VER_AR8216:
2581 priv->chip = &ar8216_chip;
2582 break;
2583 case AR8XXX_VER_AR8236:
2584 priv->chip = &ar8236_chip;
2585 break;
2586 case AR8XXX_VER_AR8316:
2587 priv->chip = &ar8316_chip;
2588 break;
2589 case AR8XXX_VER_AR8327:
2590 priv->mii_lo_first = true;
2591 priv->chip = &ar8327_chip;
2592 break;
2593 case AR8XXX_VER_AR8337:
2594 priv->mii_lo_first = true;
2595 priv->chip = &ar8327_chip;
2596 break;
2597 default:
2598 pr_err("ar8216: Unknown Atheros device [ver=%d, rev=%d]\n",
2599 priv->chip_ver, priv->chip_rev);
2600
2601 return -ENODEV;
2602 }
2603
2604 return 0;
2605 }
2606
2607 static void
2608 ar8xxx_mib_work_func(struct work_struct *work)
2609 {
2610 struct ar8xxx_priv *priv;
2611 int err;
2612
2613 priv = container_of(work, struct ar8xxx_priv, mib_work.work);
2614
2615 mutex_lock(&priv->mib_lock);
2616
2617 err = ar8xxx_mib_capture(priv);
2618 if (err)
2619 goto next_port;
2620
2621 ar8xxx_mib_fetch_port_stat(priv, priv->mib_next_port, false);
2622
2623 next_port:
2624 priv->mib_next_port++;
2625 if (priv->mib_next_port >= priv->dev.ports)
2626 priv->mib_next_port = 0;
2627
2628 mutex_unlock(&priv->mib_lock);
2629 schedule_delayed_work(&priv->mib_work,
2630 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
2631 }
2632
2633 static int
2634 ar8xxx_mib_init(struct ar8xxx_priv *priv)
2635 {
2636 unsigned int len;
2637
2638 if (!ar8xxx_has_mib_counters(priv))
2639 return 0;
2640
2641 BUG_ON(!priv->chip->mib_decs || !priv->chip->num_mibs);
2642
2643 len = priv->dev.ports * priv->chip->num_mibs *
2644 sizeof(*priv->mib_stats);
2645 priv->mib_stats = kzalloc(len, GFP_KERNEL);
2646
2647 if (!priv->mib_stats)
2648 return -ENOMEM;
2649
2650 return 0;
2651 }
2652
2653 static void
2654 ar8xxx_mib_start(struct ar8xxx_priv *priv)
2655 {
2656 if (!ar8xxx_has_mib_counters(priv))
2657 return;
2658
2659 schedule_delayed_work(&priv->mib_work,
2660 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
2661 }
2662
2663 static void
2664 ar8xxx_mib_stop(struct ar8xxx_priv *priv)
2665 {
2666 if (!ar8xxx_has_mib_counters(priv))
2667 return;
2668
2669 cancel_delayed_work(&priv->mib_work);
2670 }
2671
2672 static struct ar8xxx_priv *
2673 ar8xxx_create(void)
2674 {
2675 struct ar8xxx_priv *priv;
2676
2677 priv = kzalloc(sizeof(struct ar8xxx_priv), GFP_KERNEL);
2678 if (priv == NULL)
2679 return NULL;
2680
2681 mutex_init(&priv->reg_mutex);
2682 mutex_init(&priv->mib_lock);
2683 INIT_DELAYED_WORK(&priv->mib_work, ar8xxx_mib_work_func);
2684
2685 return priv;
2686 }
2687
2688 static void
2689 ar8xxx_free(struct ar8xxx_priv *priv)
2690 {
2691 if (priv->chip && priv->chip->cleanup)
2692 priv->chip->cleanup(priv);
2693
2694 kfree(priv->mib_stats);
2695 kfree(priv);
2696 }
2697
2698 static struct ar8xxx_priv *
2699 ar8xxx_create_mii(struct mii_bus *bus)
2700 {
2701 struct ar8xxx_priv *priv;
2702
2703 priv = ar8xxx_create();
2704 if (priv) {
2705 priv->mii_bus = bus;
2706 priv->read = ar8xxx_mii_read;
2707 priv->write = ar8xxx_mii_write;
2708 priv->rmw = ar8xxx_mii_rmw;
2709 }
2710
2711 return priv;
2712 }
2713
2714 static int
2715 ar8xxx_probe_switch(struct ar8xxx_priv *priv)
2716 {
2717 struct switch_dev *swdev;
2718 int ret;
2719
2720 ret = ar8xxx_id_chip(priv);
2721 if (ret)
2722 return ret;
2723
2724 swdev = &priv->dev;
2725 swdev->cpu_port = AR8216_PORT_CPU;
2726 swdev->ops = &ar8xxx_sw_ops;
2727
2728 if (chip_is_ar8316(priv)) {
2729 swdev->name = "Atheros AR8316";
2730 swdev->vlans = AR8X16_MAX_VLANS;
2731 swdev->ports = AR8216_NUM_PORTS;
2732 } else if (chip_is_ar8236(priv)) {
2733 swdev->name = "Atheros AR8236";
2734 swdev->vlans = AR8216_NUM_VLANS;
2735 swdev->ports = AR8216_NUM_PORTS;
2736 } else if (chip_is_ar8327(priv)) {
2737 swdev->name = "Atheros AR8327";
2738 swdev->vlans = AR8X16_MAX_VLANS;
2739 swdev->ports = AR8327_NUM_PORTS;
2740 swdev->ops = &ar8327_sw_ops;
2741 } else if (chip_is_ar8337(priv)) {
2742 swdev->name = "Atheros AR8337";
2743 swdev->vlans = AR8X16_MAX_VLANS;
2744 swdev->ports = AR8327_NUM_PORTS;
2745 swdev->ops = &ar8327_sw_ops;
2746 } else {
2747 swdev->name = "Atheros AR8216";
2748 swdev->vlans = AR8216_NUM_VLANS;
2749 swdev->ports = AR8216_NUM_PORTS;
2750 }
2751
2752 ret = ar8xxx_mib_init(priv);
2753 if (ret)
2754 return ret;
2755
2756 return 0;
2757 }
2758
2759 static int
2760 ar8xxx_start(struct ar8xxx_priv *priv)
2761 {
2762 int ret;
2763
2764 priv->init = true;
2765
2766 ret = priv->chip->hw_init(priv);
2767 if (ret)
2768 return ret;
2769
2770 ret = ar8xxx_sw_reset_switch(&priv->dev);
2771 if (ret)
2772 return ret;
2773
2774 priv->init = false;
2775
2776 ar8xxx_mib_start(priv);
2777
2778 return 0;
2779 }
2780
2781 static int
2782 ar8xxx_phy_config_init(struct phy_device *phydev)
2783 {
2784 struct ar8xxx_priv *priv = phydev->priv;
2785 struct net_device *dev = phydev->attached_dev;
2786 int ret;
2787
2788 if (WARN_ON(!priv))
2789 return -ENODEV;
2790
2791 if (chip_is_ar8327(priv) || chip_is_ar8337(priv))
2792 return 0;
2793
2794 priv->phy = phydev;
2795
2796 if (phydev->addr != 0) {
2797 if (chip_is_ar8316(priv)) {
2798 /* switch device has been initialized, reinit */
2799 priv->dev.ports = (AR8216_NUM_PORTS - 1);
2800 priv->initialized = false;
2801 priv->port4_phy = true;
2802 ar8316_hw_init(priv);
2803 return 0;
2804 }
2805
2806 return 0;
2807 }
2808
2809 ret = ar8xxx_start(priv);
2810 if (ret)
2811 return ret;
2812
2813 /* VID fixup only needed on ar8216 */
2814 if (chip_is_ar8216(priv)) {
2815 dev->phy_ptr = priv;
2816 dev->priv_flags |= IFF_NO_IP_ALIGN;
2817 dev->eth_mangle_rx = ar8216_mangle_rx;
2818 dev->eth_mangle_tx = ar8216_mangle_tx;
2819 }
2820
2821 return 0;
2822 }
2823
2824 static int
2825 ar8xxx_phy_read_status(struct phy_device *phydev)
2826 {
2827 struct ar8xxx_priv *priv = phydev->priv;
2828 struct switch_port_link link;
2829 int ret;
2830
2831 if (phydev->addr != 0)
2832 return genphy_read_status(phydev);
2833
2834 ar8216_read_port_link(priv, phydev->addr, &link);
2835 phydev->link = !!link.link;
2836 if (!phydev->link)
2837 return 0;
2838
2839 switch (link.speed) {
2840 case SWITCH_PORT_SPEED_10:
2841 phydev->speed = SPEED_10;
2842 break;
2843 case SWITCH_PORT_SPEED_100:
2844 phydev->speed = SPEED_100;
2845 break;
2846 case SWITCH_PORT_SPEED_1000:
2847 phydev->speed = SPEED_1000;
2848 break;
2849 default:
2850 phydev->speed = 0;
2851 }
2852 phydev->duplex = link.duplex ? DUPLEX_FULL : DUPLEX_HALF;
2853
2854 /* flush the address translation unit */
2855 mutex_lock(&priv->reg_mutex);
2856 ret = priv->chip->atu_flush(priv);
2857 mutex_unlock(&priv->reg_mutex);
2858
2859 phydev->state = PHY_RUNNING;
2860 netif_carrier_on(phydev->attached_dev);
2861 phydev->adjust_link(phydev->attached_dev);
2862
2863 return ret;
2864 }
2865
2866 static int
2867 ar8xxx_phy_config_aneg(struct phy_device *phydev)
2868 {
2869 if (phydev->addr == 0)
2870 return 0;
2871
2872 return genphy_config_aneg(phydev);
2873 }
2874
2875 static const u32 ar8xxx_phy_ids[] = {
2876 0x004dd033,
2877 0x004dd034, /* AR8327 */
2878 0x004dd036, /* AR8337 */
2879 0x004dd041,
2880 0x004dd042,
2881 0x004dd043, /* AR8236 */
2882 };
2883
2884 static bool
2885 ar8xxx_phy_match(u32 phy_id)
2886 {
2887 int i;
2888
2889 for (i = 0; i < ARRAY_SIZE(ar8xxx_phy_ids); i++)
2890 if (phy_id == ar8xxx_phy_ids[i])
2891 return true;
2892
2893 return false;
2894 }
2895
2896 static bool
2897 ar8xxx_is_possible(struct mii_bus *bus)
2898 {
2899 unsigned i;
2900
2901 for (i = 0; i < 4; i++) {
2902 u32 phy_id;
2903
2904 phy_id = mdiobus_read(bus, i, MII_PHYSID1) << 16;
2905 phy_id |= mdiobus_read(bus, i, MII_PHYSID2);
2906 if (!ar8xxx_phy_match(phy_id)) {
2907 pr_debug("ar8xxx: unknown PHY at %s:%02x id:%08x\n",
2908 dev_name(&bus->dev), i, phy_id);
2909 return false;
2910 }
2911 }
2912
2913 return true;
2914 }
2915
2916 static int
2917 ar8xxx_phy_probe(struct phy_device *phydev)
2918 {
2919 struct ar8xxx_priv *priv;
2920 struct switch_dev *swdev;
2921 int ret;
2922
2923 /* skip PHYs at unused adresses */
2924 if (phydev->addr != 0 && phydev->addr != 4)
2925 return -ENODEV;
2926
2927 if (!ar8xxx_is_possible(phydev->bus))
2928 return -ENODEV;
2929
2930 mutex_lock(&ar8xxx_dev_list_lock);
2931 list_for_each_entry(priv, &ar8xxx_dev_list, list)
2932 if (priv->mii_bus == phydev->bus)
2933 goto found;
2934
2935 priv = ar8xxx_create_mii(phydev->bus);
2936 if (priv == NULL) {
2937 ret = -ENOMEM;
2938 goto unlock;
2939 }
2940
2941 ret = ar8xxx_probe_switch(priv);
2942 if (ret)
2943 goto free_priv;
2944
2945 swdev = &priv->dev;
2946 swdev->alias = dev_name(&priv->mii_bus->dev);
2947 ret = register_switch(swdev, NULL);
2948 if (ret)
2949 goto free_priv;
2950
2951 pr_info("%s: %s rev. %u switch registered on %s\n",
2952 swdev->devname, swdev->name, priv->chip_rev,
2953 dev_name(&priv->mii_bus->dev));
2954
2955 found:
2956 priv->use_count++;
2957
2958 if (phydev->addr == 0) {
2959 if (ar8xxx_has_gige(priv)) {
2960 phydev->supported = SUPPORTED_1000baseT_Full;
2961 phydev->advertising = ADVERTISED_1000baseT_Full;
2962 } else {
2963 phydev->supported = SUPPORTED_100baseT_Full;
2964 phydev->advertising = ADVERTISED_100baseT_Full;
2965 }
2966
2967 if (chip_is_ar8327(priv) || chip_is_ar8337(priv)) {
2968 priv->phy = phydev;
2969
2970 ret = ar8xxx_start(priv);
2971 if (ret)
2972 goto err_unregister_switch;
2973 }
2974 } else {
2975 if (ar8xxx_has_gige(priv)) {
2976 phydev->supported |= SUPPORTED_1000baseT_Full;
2977 phydev->advertising |= ADVERTISED_1000baseT_Full;
2978 }
2979 }
2980
2981 phydev->priv = priv;
2982
2983 list_add(&priv->list, &ar8xxx_dev_list);
2984
2985 mutex_unlock(&ar8xxx_dev_list_lock);
2986
2987 return 0;
2988
2989 err_unregister_switch:
2990 if (--priv->use_count)
2991 goto unlock;
2992
2993 unregister_switch(&priv->dev);
2994
2995 free_priv:
2996 ar8xxx_free(priv);
2997 unlock:
2998 mutex_unlock(&ar8xxx_dev_list_lock);
2999 return ret;
3000 }
3001
3002 static void
3003 ar8xxx_phy_detach(struct phy_device *phydev)
3004 {
3005 struct net_device *dev = phydev->attached_dev;
3006
3007 if (!dev)
3008 return;
3009
3010 dev->phy_ptr = NULL;
3011 dev->priv_flags &= ~IFF_NO_IP_ALIGN;
3012 dev->eth_mangle_rx = NULL;
3013 dev->eth_mangle_tx = NULL;
3014 }
3015
3016 static void
3017 ar8xxx_phy_remove(struct phy_device *phydev)
3018 {
3019 struct ar8xxx_priv *priv = phydev->priv;
3020
3021 if (WARN_ON(!priv))
3022 return;
3023
3024 phydev->priv = NULL;
3025 if (--priv->use_count > 0)
3026 return;
3027
3028 mutex_lock(&ar8xxx_dev_list_lock);
3029 list_del(&priv->list);
3030 mutex_unlock(&ar8xxx_dev_list_lock);
3031
3032 unregister_switch(&priv->dev);
3033 ar8xxx_mib_stop(priv);
3034 ar8xxx_free(priv);
3035 }
3036
3037 static struct phy_driver ar8xxx_phy_driver = {
3038 .phy_id = 0x004d0000,
3039 .name = "Atheros AR8216/AR8236/AR8316",
3040 .phy_id_mask = 0xffff0000,
3041 .features = PHY_BASIC_FEATURES,
3042 .probe = ar8xxx_phy_probe,
3043 .remove = ar8xxx_phy_remove,
3044 .detach = ar8xxx_phy_detach,
3045 .config_init = ar8xxx_phy_config_init,
3046 .config_aneg = ar8xxx_phy_config_aneg,
3047 .read_status = ar8xxx_phy_read_status,
3048 .driver = { .owner = THIS_MODULE },
3049 };
3050
3051 int __init
3052 ar8xxx_init(void)
3053 {
3054 return phy_driver_register(&ar8xxx_phy_driver);
3055 }
3056
3057 void __exit
3058 ar8xxx_exit(void)
3059 {
3060 phy_driver_unregister(&ar8xxx_phy_driver);
3061 }
3062
3063 module_init(ar8xxx_init);
3064 module_exit(ar8xxx_exit);
3065 MODULE_LICENSE("GPL");
3066
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