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generic: ar8216: add revision specific PHY fixups for AR8327
[openwrt/staging/yousong.git] / target / linux / generic / files / drivers / net / phy / ar8216.c
1 /*
2 * ar8216.c: AR8216 switch driver
3 *
4 * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18 #include <linux/if.h>
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/list.h>
22 #include <linux/if_ether.h>
23 #include <linux/skbuff.h>
24 #include <linux/netdevice.h>
25 #include <linux/netlink.h>
26 #include <linux/bitops.h>
27 #include <net/genetlink.h>
28 #include <linux/switch.h>
29 #include <linux/delay.h>
30 #include <linux/phy.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/lockdep.h>
34 #include <linux/ar8216_platform.h>
35 #include "ar8216.h"
36
37 /* size of the vlan table */
38 #define AR8X16_MAX_VLANS 128
39 #define AR8X16_PROBE_RETRIES 10
40 #define AR8X16_MAX_PORTS 8
41
42 struct ar8216_priv;
43
44 #define AR8XXX_CAP_GIGE BIT(0)
45
46 enum {
47 AR8XXX_VER_AR8216 = 0x01,
48 AR8XXX_VER_AR8236 = 0x03,
49 AR8XXX_VER_AR8316 = 0x10,
50 AR8XXX_VER_AR8327 = 0x12,
51 };
52
53 struct ar8xxx_chip {
54 unsigned long caps;
55
56 int (*hw_init)(struct ar8216_priv *priv);
57 void (*init_globals)(struct ar8216_priv *priv);
58 void (*init_port)(struct ar8216_priv *priv, int port);
59 void (*setup_port)(struct ar8216_priv *priv, int port, u32 egress,
60 u32 ingress, u32 members, u32 pvid);
61 u32 (*read_port_status)(struct ar8216_priv *priv, int port);
62 int (*atu_flush)(struct ar8216_priv *priv);
63 void (*vtu_flush)(struct ar8216_priv *priv);
64 void (*vtu_load_vlan)(struct ar8216_priv *priv, u32 vid, u32 port_mask);
65 };
66
67 struct ar8216_priv {
68 struct switch_dev dev;
69 struct phy_device *phy;
70 u32 (*read)(struct ar8216_priv *priv, int reg);
71 void (*write)(struct ar8216_priv *priv, int reg, u32 val);
72 const struct net_device_ops *ndo_old;
73 struct net_device_ops ndo;
74 struct mutex reg_mutex;
75 u8 chip_ver;
76 u8 chip_rev;
77 const struct ar8xxx_chip *chip;
78 bool initialized;
79 bool port4_phy;
80 char buf[80];
81
82 bool init;
83 bool mii_lo_first;
84
85 /* all fields below are cleared on reset */
86 bool vlan;
87 u16 vlan_id[AR8X16_MAX_VLANS];
88 u8 vlan_table[AR8X16_MAX_VLANS];
89 u8 vlan_tagged;
90 u16 pvid[AR8X16_MAX_PORTS];
91 };
92
93 #define to_ar8216(_dev) container_of(_dev, struct ar8216_priv, dev)
94
95 static inline bool ar8xxx_has_gige(struct ar8216_priv *priv)
96 {
97 return priv->chip->caps & AR8XXX_CAP_GIGE;
98 }
99
100 static inline bool chip_is_ar8216(struct ar8216_priv *priv)
101 {
102 return priv->chip_ver == AR8XXX_VER_AR8216;
103 }
104
105 static inline bool chip_is_ar8236(struct ar8216_priv *priv)
106 {
107 return priv->chip_ver == AR8XXX_VER_AR8236;
108 }
109
110 static inline bool chip_is_ar8316(struct ar8216_priv *priv)
111 {
112 return priv->chip_ver == AR8XXX_VER_AR8316;
113 }
114
115 static inline bool chip_is_ar8327(struct ar8216_priv *priv)
116 {
117 return priv->chip_ver == AR8XXX_VER_AR8327;
118 }
119
120 static inline void
121 split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
122 {
123 regaddr >>= 1;
124 *r1 = regaddr & 0x1e;
125
126 regaddr >>= 5;
127 *r2 = regaddr & 0x7;
128
129 regaddr >>= 3;
130 *page = regaddr & 0x1ff;
131 }
132
133 static u32
134 ar8216_mii_read(struct ar8216_priv *priv, int reg)
135 {
136 struct phy_device *phy = priv->phy;
137 struct mii_bus *bus = phy->bus;
138 u16 r1, r2, page;
139 u16 lo, hi;
140
141 split_addr((u32) reg, &r1, &r2, &page);
142
143 mutex_lock(&bus->mdio_lock);
144
145 bus->write(bus, 0x18, 0, page);
146 usleep_range(1000, 2000); /* wait for the page switch to propagate */
147 lo = bus->read(bus, 0x10 | r2, r1);
148 hi = bus->read(bus, 0x10 | r2, r1 + 1);
149
150 mutex_unlock(&bus->mdio_lock);
151
152 return (hi << 16) | lo;
153 }
154
155 static void
156 ar8216_mii_write(struct ar8216_priv *priv, int reg, u32 val)
157 {
158 struct phy_device *phy = priv->phy;
159 struct mii_bus *bus = phy->bus;
160 u16 r1, r2, r3;
161 u16 lo, hi;
162
163 split_addr((u32) reg, &r1, &r2, &r3);
164 lo = val & 0xffff;
165 hi = (u16) (val >> 16);
166
167 mutex_lock(&bus->mdio_lock);
168
169 bus->write(bus, 0x18, 0, r3);
170 usleep_range(1000, 2000); /* wait for the page switch to propagate */
171 if (priv->mii_lo_first) {
172 bus->write(bus, 0x10 | r2, r1, lo);
173 bus->write(bus, 0x10 | r2, r1 + 1, hi);
174 } else {
175 bus->write(bus, 0x10 | r2, r1 + 1, hi);
176 bus->write(bus, 0x10 | r2, r1, lo);
177 }
178
179 mutex_unlock(&bus->mdio_lock);
180 }
181
182 static void
183 ar8216_phy_dbg_write(struct ar8216_priv *priv, int phy_addr,
184 u16 dbg_addr, u16 dbg_data)
185 {
186 struct mii_bus *bus = priv->phy->bus;
187
188 mutex_lock(&bus->mdio_lock);
189 bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr);
190 bus->write(bus, phy_addr, MII_ATH_DBG_DATA, dbg_data);
191 mutex_unlock(&bus->mdio_lock);
192 }
193
194 static void
195 ar8216_phy_mmd_write(struct ar8216_priv *priv, int phy_addr, u16 addr, u16 data)
196 {
197 struct mii_bus *bus = priv->phy->bus;
198
199 mutex_lock(&bus->mdio_lock);
200 bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr);
201 bus->write(bus, phy_addr, MII_ATH_MMD_DATA, data);
202 mutex_unlock(&bus->mdio_lock);
203 }
204
205 static u32
206 ar8216_rmw(struct ar8216_priv *priv, int reg, u32 mask, u32 val)
207 {
208 u32 v;
209
210 lockdep_assert_held(&priv->reg_mutex);
211
212 v = priv->read(priv, reg);
213 v &= ~mask;
214 v |= val;
215 priv->write(priv, reg, v);
216
217 return v;
218 }
219
220 static void
221 ar8216_read_port_link(struct ar8216_priv *priv, int port,
222 struct switch_port_link *link)
223 {
224 u32 status;
225 u32 speed;
226
227 memset(link, '\0', sizeof(*link));
228
229 status = priv->chip->read_port_status(priv, port);
230
231 link->aneg = !!(status & AR8216_PORT_STATUS_LINK_AUTO);
232 if (link->aneg) {
233 link->link = !!(status & AR8216_PORT_STATUS_LINK_UP);
234 if (!link->link)
235 return;
236 } else {
237 link->link = true;
238 }
239
240 link->duplex = !!(status & AR8216_PORT_STATUS_DUPLEX);
241 link->tx_flow = !!(status & AR8216_PORT_STATUS_TXFLOW);
242 link->rx_flow = !!(status & AR8216_PORT_STATUS_RXFLOW);
243
244 speed = (status & AR8216_PORT_STATUS_SPEED) >>
245 AR8216_PORT_STATUS_SPEED_S;
246
247 switch (speed) {
248 case AR8216_PORT_SPEED_10M:
249 link->speed = SWITCH_PORT_SPEED_10;
250 break;
251 case AR8216_PORT_SPEED_100M:
252 link->speed = SWITCH_PORT_SPEED_100;
253 break;
254 case AR8216_PORT_SPEED_1000M:
255 link->speed = SWITCH_PORT_SPEED_1000;
256 break;
257 default:
258 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
259 break;
260 }
261 }
262
263 static struct sk_buff *
264 ar8216_mangle_tx(struct net_device *dev, struct sk_buff *skb)
265 {
266 struct ar8216_priv *priv = dev->phy_ptr;
267 unsigned char *buf;
268
269 if (unlikely(!priv))
270 goto error;
271
272 if (!priv->vlan)
273 goto send;
274
275 if (unlikely(skb_headroom(skb) < 2)) {
276 if (pskb_expand_head(skb, 2, 0, GFP_ATOMIC) < 0)
277 goto error;
278 }
279
280 buf = skb_push(skb, 2);
281 buf[0] = 0x10;
282 buf[1] = 0x80;
283
284 send:
285 return skb;
286
287 error:
288 dev_kfree_skb_any(skb);
289 return NULL;
290 }
291
292 static void
293 ar8216_mangle_rx(struct net_device *dev, struct sk_buff *skb)
294 {
295 struct ar8216_priv *priv;
296 unsigned char *buf;
297 int port, vlan;
298
299 priv = dev->phy_ptr;
300 if (!priv)
301 return;
302
303 /* don't strip the header if vlan mode is disabled */
304 if (!priv->vlan)
305 return;
306
307 /* strip header, get vlan id */
308 buf = skb->data;
309 skb_pull(skb, 2);
310
311 /* check for vlan header presence */
312 if ((buf[12 + 2] != 0x81) || (buf[13 + 2] != 0x00))
313 return;
314
315 port = buf[0] & 0xf;
316
317 /* no need to fix up packets coming from a tagged source */
318 if (priv->vlan_tagged & (1 << port))
319 return;
320
321 /* lookup port vid from local table, the switch passes an invalid vlan id */
322 vlan = priv->vlan_id[priv->pvid[port]];
323
324 buf[14 + 2] &= 0xf0;
325 buf[14 + 2] |= vlan >> 8;
326 buf[15 + 2] = vlan & 0xff;
327 }
328
329 static int
330 ar8216_wait_bit(struct ar8216_priv *priv, int reg, u32 mask, u32 val)
331 {
332 int timeout = 20;
333 u32 t = 0;
334
335 while (1) {
336 t = priv->read(priv, reg);
337 if ((t & mask) == val)
338 return 0;
339
340 if (timeout-- <= 0)
341 break;
342
343 udelay(10);
344 }
345
346 pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
347 (unsigned int) reg, t, mask, val);
348 return -ETIMEDOUT;
349 }
350
351 static void
352 ar8216_vtu_op(struct ar8216_priv *priv, u32 op, u32 val)
353 {
354 if (ar8216_wait_bit(priv, AR8216_REG_VTU, AR8216_VTU_ACTIVE, 0))
355 return;
356 if ((op & AR8216_VTU_OP) == AR8216_VTU_OP_LOAD) {
357 val &= AR8216_VTUDATA_MEMBER;
358 val |= AR8216_VTUDATA_VALID;
359 priv->write(priv, AR8216_REG_VTU_DATA, val);
360 }
361 op |= AR8216_VTU_ACTIVE;
362 priv->write(priv, AR8216_REG_VTU, op);
363 }
364
365 static void
366 ar8216_vtu_flush(struct ar8216_priv *priv)
367 {
368 ar8216_vtu_op(priv, AR8216_VTU_OP_FLUSH, 0);
369 }
370
371 static void
372 ar8216_vtu_load_vlan(struct ar8216_priv *priv, u32 vid, u32 port_mask)
373 {
374 u32 op;
375
376 op = AR8216_VTU_OP_LOAD | (vid << AR8216_VTU_VID_S);
377 ar8216_vtu_op(priv, op, port_mask);
378 }
379
380 static int
381 ar8216_atu_flush(struct ar8216_priv *priv)
382 {
383 int ret;
384
385 ret = ar8216_wait_bit(priv, AR8216_REG_ATU, AR8216_ATU_ACTIVE, 0);
386 if (!ret)
387 priv->write(priv, AR8216_REG_ATU, AR8216_ATU_OP_FLUSH);
388
389 return ret;
390 }
391
392 static u32
393 ar8216_read_port_status(struct ar8216_priv *priv, int port)
394 {
395 return priv->read(priv, AR8216_REG_PORT_STATUS(port));
396 }
397
398 static void
399 ar8216_setup_port(struct ar8216_priv *priv, int port, u32 egress, u32 ingress,
400 u32 members, u32 pvid)
401 {
402 u32 header;
403
404 if (chip_is_ar8216(priv) && priv->vlan && port == AR8216_PORT_CPU)
405 header = AR8216_PORT_CTRL_HEADER;
406 else
407 header = 0;
408
409 ar8216_rmw(priv, AR8216_REG_PORT_CTRL(port),
410 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
411 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
412 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
413 AR8216_PORT_CTRL_LEARN | header |
414 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
415 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
416
417 ar8216_rmw(priv, AR8216_REG_PORT_VLAN(port),
418 AR8216_PORT_VLAN_DEST_PORTS | AR8216_PORT_VLAN_MODE |
419 AR8216_PORT_VLAN_DEFAULT_ID,
420 (members << AR8216_PORT_VLAN_DEST_PORTS_S) |
421 (ingress << AR8216_PORT_VLAN_MODE_S) |
422 (pvid << AR8216_PORT_VLAN_DEFAULT_ID_S));
423 }
424
425 static int
426 ar8216_hw_init(struct ar8216_priv *priv)
427 {
428 return 0;
429 }
430
431 static void
432 ar8216_init_globals(struct ar8216_priv *priv)
433 {
434 /* standard atheros magic */
435 priv->write(priv, 0x38, 0xc000050e);
436
437 ar8216_rmw(priv, AR8216_REG_GLOBAL_CTRL,
438 AR8216_GCTRL_MTU, 1518 + 8 + 2);
439 }
440
441 static void
442 ar8216_init_port(struct ar8216_priv *priv, int port)
443 {
444 /* Enable port learning and tx */
445 priv->write(priv, AR8216_REG_PORT_CTRL(port),
446 AR8216_PORT_CTRL_LEARN |
447 (4 << AR8216_PORT_CTRL_STATE_S));
448
449 priv->write(priv, AR8216_REG_PORT_VLAN(port), 0);
450
451 if (port == AR8216_PORT_CPU) {
452 priv->write(priv, AR8216_REG_PORT_STATUS(port),
453 AR8216_PORT_STATUS_LINK_UP |
454 (ar8xxx_has_gige(priv) ?
455 AR8216_PORT_SPEED_1000M : AR8216_PORT_SPEED_100M) |
456 AR8216_PORT_STATUS_TXMAC |
457 AR8216_PORT_STATUS_RXMAC |
458 (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_RXFLOW : 0) |
459 (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_TXFLOW : 0) |
460 AR8216_PORT_STATUS_DUPLEX);
461 } else {
462 priv->write(priv, AR8216_REG_PORT_STATUS(port),
463 AR8216_PORT_STATUS_LINK_AUTO);
464 }
465 }
466
467 static const struct ar8xxx_chip ar8216_chip = {
468 .hw_init = ar8216_hw_init,
469 .init_globals = ar8216_init_globals,
470 .init_port = ar8216_init_port,
471 .setup_port = ar8216_setup_port,
472 .read_port_status = ar8216_read_port_status,
473 .atu_flush = ar8216_atu_flush,
474 .vtu_flush = ar8216_vtu_flush,
475 .vtu_load_vlan = ar8216_vtu_load_vlan,
476 };
477
478 static void
479 ar8236_setup_port(struct ar8216_priv *priv, int port, u32 egress, u32 ingress,
480 u32 members, u32 pvid)
481 {
482 ar8216_rmw(priv, AR8216_REG_PORT_CTRL(port),
483 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
484 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
485 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
486 AR8216_PORT_CTRL_LEARN |
487 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
488 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
489
490 ar8216_rmw(priv, AR8236_REG_PORT_VLAN(port),
491 AR8236_PORT_VLAN_DEFAULT_ID,
492 (pvid << AR8236_PORT_VLAN_DEFAULT_ID_S));
493
494 ar8216_rmw(priv, AR8236_REG_PORT_VLAN2(port),
495 AR8236_PORT_VLAN2_VLAN_MODE |
496 AR8236_PORT_VLAN2_MEMBER,
497 (ingress << AR8236_PORT_VLAN2_VLAN_MODE_S) |
498 (members << AR8236_PORT_VLAN2_MEMBER_S));
499 }
500
501 static int
502 ar8236_hw_init(struct ar8216_priv *priv)
503 {
504 int i;
505 struct mii_bus *bus;
506
507 if (priv->initialized)
508 return 0;
509
510 /* Initialize the PHYs */
511 bus = priv->phy->bus;
512 for (i = 0; i < 5; i++) {
513 mdiobus_write(bus, i, MII_ADVERTISE,
514 ADVERTISE_ALL | ADVERTISE_PAUSE_CAP |
515 ADVERTISE_PAUSE_ASYM);
516 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
517 }
518 msleep(1000);
519
520 priv->initialized = true;
521 return 0;
522 }
523
524 static void
525 ar8236_init_globals(struct ar8216_priv *priv)
526 {
527 /* enable jumbo frames */
528 ar8216_rmw(priv, AR8216_REG_GLOBAL_CTRL,
529 AR8316_GCTRL_MTU, 9018 + 8 + 2);
530 }
531
532 static const struct ar8xxx_chip ar8236_chip = {
533 .hw_init = ar8236_hw_init,
534 .init_globals = ar8236_init_globals,
535 .init_port = ar8216_init_port,
536 .setup_port = ar8236_setup_port,
537 .read_port_status = ar8216_read_port_status,
538 .atu_flush = ar8216_atu_flush,
539 .vtu_flush = ar8216_vtu_flush,
540 .vtu_load_vlan = ar8216_vtu_load_vlan,
541 };
542
543 static int
544 ar8316_hw_init(struct ar8216_priv *priv)
545 {
546 int i;
547 u32 val, newval;
548 struct mii_bus *bus;
549
550 val = priv->read(priv, 0x8);
551
552 if (priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
553 if (priv->port4_phy) {
554 /* value taken from Ubiquiti RouterStation Pro */
555 newval = 0x81461bea;
556 printk(KERN_INFO "ar8316: Using port 4 as PHY\n");
557 } else {
558 newval = 0x01261be2;
559 printk(KERN_INFO "ar8316: Using port 4 as switch port\n");
560 }
561 } else if (priv->phy->interface == PHY_INTERFACE_MODE_GMII) {
562 /* value taken from AVM Fritz!Box 7390 sources */
563 newval = 0x010e5b71;
564 } else {
565 /* no known value for phy interface */
566 printk(KERN_ERR "ar8316: unsupported mii mode: %d.\n",
567 priv->phy->interface);
568 return -EINVAL;
569 }
570
571 if (val == newval)
572 goto out;
573
574 priv->write(priv, 0x8, newval);
575
576 /* Initialize the ports */
577 bus = priv->phy->bus;
578 for (i = 0; i < 5; i++) {
579 if ((i == 4) && priv->port4_phy &&
580 priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
581 /* work around for phy4 rgmii mode */
582 ar8216_phy_dbg_write(priv, i, 0x12, 0x480c);
583 /* rx delay */
584 ar8216_phy_dbg_write(priv, i, 0x0, 0x824e);
585 /* tx delay */
586 ar8216_phy_dbg_write(priv, i, 0x5, 0x3d47);
587 msleep(1000);
588 }
589
590 /* initialize the port itself */
591 mdiobus_write(bus, i, MII_ADVERTISE,
592 ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
593 mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
594 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
595 msleep(1000);
596 }
597
598 out:
599 priv->initialized = true;
600 return 0;
601 }
602
603 static void
604 ar8316_init_globals(struct ar8216_priv *priv)
605 {
606 /* standard atheros magic */
607 priv->write(priv, 0x38, 0xc000050e);
608
609 /* enable cpu port to receive multicast and broadcast frames */
610 priv->write(priv, AR8216_REG_FLOOD_MASK, 0x003f003f);
611
612 /* enable jumbo frames */
613 ar8216_rmw(priv, AR8216_REG_GLOBAL_CTRL,
614 AR8316_GCTRL_MTU, 9018 + 8 + 2);
615 }
616
617 static const struct ar8xxx_chip ar8316_chip = {
618 .caps = AR8XXX_CAP_GIGE,
619 .hw_init = ar8316_hw_init,
620 .init_globals = ar8316_init_globals,
621 .init_port = ar8216_init_port,
622 .setup_port = ar8216_setup_port,
623 .read_port_status = ar8216_read_port_status,
624 .atu_flush = ar8216_atu_flush,
625 .vtu_flush = ar8216_vtu_flush,
626 .vtu_load_vlan = ar8216_vtu_load_vlan,
627 };
628
629 static u32
630 ar8327_get_pad_cfg(struct ar8327_pad_cfg *cfg)
631 {
632 u32 t;
633
634 if (!cfg)
635 return 0;
636
637 t = 0;
638 switch (cfg->mode) {
639 case AR8327_PAD_NC:
640 break;
641
642 case AR8327_PAD_MAC2MAC_MII:
643 t = AR8327_PAD_MAC_MII_EN;
644 if (cfg->rxclk_sel)
645 t |= AR8327_PAD_MAC_MII_RXCLK_SEL;
646 if (cfg->txclk_sel)
647 t |= AR8327_PAD_MAC_MII_TXCLK_SEL;
648 break;
649
650 case AR8327_PAD_MAC2MAC_GMII:
651 t = AR8327_PAD_MAC_GMII_EN;
652 if (cfg->rxclk_sel)
653 t |= AR8327_PAD_MAC_GMII_RXCLK_SEL;
654 if (cfg->txclk_sel)
655 t |= AR8327_PAD_MAC_GMII_TXCLK_SEL;
656 break;
657
658 case AR8327_PAD_MAC_SGMII:
659 t = AR8327_PAD_SGMII_EN;
660 break;
661
662 case AR8327_PAD_MAC2PHY_MII:
663 t = AR8327_PAD_PHY_MII_EN;
664 if (cfg->rxclk_sel)
665 t |= AR8327_PAD_PHY_MII_RXCLK_SEL;
666 if (cfg->txclk_sel)
667 t |= AR8327_PAD_PHY_MII_TXCLK_SEL;
668 break;
669
670 case AR8327_PAD_MAC2PHY_GMII:
671 t = AR8327_PAD_PHY_GMII_EN;
672 if (cfg->pipe_rxclk_sel)
673 t |= AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL;
674 if (cfg->rxclk_sel)
675 t |= AR8327_PAD_PHY_GMII_RXCLK_SEL;
676 if (cfg->txclk_sel)
677 t |= AR8327_PAD_PHY_GMII_TXCLK_SEL;
678 break;
679
680 case AR8327_PAD_MAC_RGMII:
681 t = AR8327_PAD_RGMII_EN;
682 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
683 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
684 if (cfg->rxclk_delay_en)
685 t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
686 if (cfg->txclk_delay_en)
687 t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
688 break;
689
690 case AR8327_PAD_PHY_GMII:
691 t = AR8327_PAD_PHYX_GMII_EN;
692 break;
693
694 case AR8327_PAD_PHY_RGMII:
695 t = AR8327_PAD_PHYX_RGMII_EN;
696 break;
697
698 case AR8327_PAD_PHY_MII:
699 t = AR8327_PAD_PHYX_MII_EN;
700 break;
701 }
702
703 return t;
704 }
705
706 static void
707 ar8327_phy_fixup(struct ar8216_priv *priv, int phy)
708 {
709 switch (priv->chip_rev) {
710 case 1:
711 /* For 100M waveform */
712 ar8216_phy_dbg_write(priv, phy, 0, 0x02ea);
713 /* Turn on Gigabit clock */
714 ar8216_phy_dbg_write(priv, phy, 0x3d, 0x68a0);
715 break;
716
717 case 2:
718 ar8216_phy_mmd_write(priv, phy, 0x7, 0x3c);
719 ar8216_phy_mmd_write(priv, phy, 0x4007, 0x0);
720 /* fallthrough */
721 case 4:
722 ar8216_phy_mmd_write(priv, phy, 0x3, 0x800d);
723 ar8216_phy_mmd_write(priv, phy, 0x4003, 0x803f);
724
725 ar8216_phy_dbg_write(priv, phy, 0x3d, 0x6860);
726 ar8216_phy_dbg_write(priv, phy, 0x5, 0x2c46);
727 ar8216_phy_dbg_write(priv, phy, 0x3c, 0x6000);
728 break;
729 }
730 }
731
732 static int
733 ar8327_hw_init(struct ar8216_priv *priv)
734 {
735 struct ar8327_platform_data *pdata;
736 u32 t;
737 int i;
738
739 pdata = priv->phy->dev.platform_data;
740 if (!pdata)
741 return -EINVAL;
742
743 t = ar8327_get_pad_cfg(pdata->pad0_cfg);
744 priv->write(priv, AR8327_REG_PAD0_MODE, t);
745 t = ar8327_get_pad_cfg(pdata->pad5_cfg);
746 priv->write(priv, AR8327_REG_PAD5_MODE, t);
747 t = ar8327_get_pad_cfg(pdata->pad6_cfg);
748 priv->write(priv, AR8327_REG_PAD6_MODE, t);
749
750 priv->write(priv, AR8327_REG_POWER_ON_STRIP, 0x40000000);
751
752 for (i = 0; i < AR8327_NUM_PHYS; i++)
753 ar8327_phy_fixup(priv, i);
754
755 return 0;
756 }
757
758 static void
759 ar8327_init_globals(struct ar8216_priv *priv)
760 {
761 u32 t;
762
763 /* enable CPU port and disable mirror port */
764 t = AR8327_FWD_CTRL0_CPU_PORT_EN |
765 AR8327_FWD_CTRL0_MIRROR_PORT;
766 priv->write(priv, AR8327_REG_FWD_CTRL0, t);
767
768 /* forward multicast and broadcast frames to CPU */
769 t = (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_UC_FLOOD_S) |
770 (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_MC_FLOOD_S) |
771 (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_BC_FLOOD_S);
772 priv->write(priv, AR8327_REG_FWD_CTRL1, t);
773
774 /* setup MTU */
775 ar8216_rmw(priv, AR8327_REG_MAX_FRAME_SIZE,
776 AR8327_MAX_FRAME_SIZE_MTU, 1518 + 8 + 2);
777 }
778
779 static void
780 ar8327_init_cpuport(struct ar8216_priv *priv)
781 {
782 struct ar8327_platform_data *pdata;
783 struct ar8327_port_cfg *cfg;
784 u32 t;
785
786 pdata = priv->phy->dev.platform_data;
787 if (!pdata)
788 return;
789
790 cfg = &pdata->cpuport_cfg;
791 if (!cfg->force_link) {
792 priv->write(priv, AR8327_REG_PORT_STATUS(AR8216_PORT_CPU),
793 AR8216_PORT_STATUS_LINK_AUTO);
794 return;
795 }
796
797 t = AR8216_PORT_STATUS_TXMAC | AR8216_PORT_STATUS_RXMAC;
798 t |= cfg->duplex ? AR8216_PORT_STATUS_DUPLEX : 0;
799 t |= cfg->rxpause ? AR8216_PORT_STATUS_RXFLOW : 0;
800 t |= cfg->txpause ? AR8216_PORT_STATUS_TXFLOW : 0;
801 switch (cfg->speed) {
802 case AR8327_PORT_SPEED_10:
803 t |= AR8216_PORT_SPEED_10M;
804 break;
805 case AR8327_PORT_SPEED_100:
806 t |= AR8216_PORT_SPEED_100M;
807 break;
808 case AR8327_PORT_SPEED_1000:
809 t |= AR8216_PORT_SPEED_1000M;
810 break;
811 }
812
813 priv->write(priv, AR8327_REG_PORT_STATUS(AR8216_PORT_CPU), t);
814 }
815
816 static void
817 ar8327_init_port(struct ar8216_priv *priv, int port)
818 {
819 u32 t;
820
821 if (port == AR8216_PORT_CPU) {
822 ar8327_init_cpuport(priv);
823 } else {
824 t = AR8216_PORT_STATUS_LINK_AUTO;
825 priv->write(priv, AR8327_REG_PORT_STATUS(port), t);
826 }
827
828 priv->write(priv, AR8327_REG_PORT_HEADER(port), 0);
829
830 priv->write(priv, AR8327_REG_PORT_VLAN0(port), 0);
831
832 t = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH << AR8327_PORT_VLAN1_OUT_MODE_S;
833 priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
834
835 t = AR8327_PORT_LOOKUP_LEARN;
836 t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
837 priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
838 }
839
840 static u32
841 ar8327_read_port_status(struct ar8216_priv *priv, int port)
842 {
843 return priv->read(priv, AR8327_REG_PORT_STATUS(port));
844 }
845
846 static int
847 ar8327_atu_flush(struct ar8216_priv *priv)
848 {
849 int ret;
850
851 ret = ar8216_wait_bit(priv, AR8327_REG_ATU_FUNC,
852 AR8327_ATU_FUNC_BUSY, 0);
853 if (!ret)
854 priv->write(priv, AR8327_REG_ATU_FUNC,
855 AR8327_ATU_FUNC_OP_FLUSH);
856
857 return ret;
858 }
859
860 static void
861 ar8327_vtu_op(struct ar8216_priv *priv, u32 op, u32 val)
862 {
863 if (ar8216_wait_bit(priv, AR8327_REG_VTU_FUNC1,
864 AR8327_VTU_FUNC1_BUSY, 0))
865 return;
866
867 if ((op & AR8327_VTU_FUNC1_OP) == AR8327_VTU_FUNC1_OP_LOAD)
868 priv->write(priv, AR8327_REG_VTU_FUNC0, val);
869
870 op |= AR8327_VTU_FUNC1_BUSY;
871 priv->write(priv, AR8327_REG_VTU_FUNC1, op);
872 }
873
874 static void
875 ar8327_vtu_flush(struct ar8216_priv *priv)
876 {
877 ar8327_vtu_op(priv, AR8327_VTU_FUNC1_OP_FLUSH, 0);
878 }
879
880 static void
881 ar8327_vtu_load_vlan(struct ar8216_priv *priv, u32 vid, u32 port_mask)
882 {
883 u32 op;
884 u32 val;
885 int i;
886
887 op = AR8327_VTU_FUNC1_OP_LOAD | (vid << AR8327_VTU_FUNC1_VID_S);
888 val = AR8327_VTU_FUNC0_VALID | AR8327_VTU_FUNC0_IVL;
889 for (i = 0; i < AR8327_NUM_PORTS; i++) {
890 u32 mode;
891
892 if ((port_mask & BIT(i)) == 0)
893 mode = AR8327_VTU_FUNC0_EG_MODE_NOT;
894 else if (priv->vlan == 0)
895 mode = AR8327_VTU_FUNC0_EG_MODE_KEEP;
896 else if (priv->vlan_tagged & BIT(i))
897 mode = AR8327_VTU_FUNC0_EG_MODE_TAG;
898 else
899 mode = AR8327_VTU_FUNC0_EG_MODE_UNTAG;
900
901 val |= mode << AR8327_VTU_FUNC0_EG_MODE_S(i);
902 }
903 ar8327_vtu_op(priv, op, val);
904 }
905
906 static void
907 ar8327_setup_port(struct ar8216_priv *priv, int port, u32 egress, u32 ingress,
908 u32 members, u32 pvid)
909 {
910 u32 t;
911 u32 mode;
912
913 t = pvid << AR8327_PORT_VLAN0_DEF_SVID_S;
914 t |= pvid << AR8327_PORT_VLAN0_DEF_CVID_S;
915 priv->write(priv, AR8327_REG_PORT_VLAN0(port), t);
916
917 mode = AR8327_PORT_VLAN1_OUT_MODE_UNMOD;
918 switch (egress) {
919 case AR8216_OUT_KEEP:
920 mode = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH;
921 break;
922 case AR8216_OUT_STRIP_VLAN:
923 mode = AR8327_PORT_VLAN1_OUT_MODE_UNTAG;
924 break;
925 case AR8216_OUT_ADD_VLAN:
926 mode = AR8327_PORT_VLAN1_OUT_MODE_TAG;
927 break;
928 }
929
930 t = AR8327_PORT_VLAN1_PORT_VLAN_PROP;
931 t |= mode << AR8327_PORT_VLAN1_OUT_MODE_S;
932 priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
933
934 t = members;
935 t |= AR8327_PORT_LOOKUP_LEARN;
936 t |= ingress << AR8327_PORT_LOOKUP_IN_MODE_S;
937 t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
938 priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
939 }
940
941 static const struct ar8xxx_chip ar8327_chip = {
942 .caps = AR8XXX_CAP_GIGE,
943 .hw_init = ar8327_hw_init,
944 .init_globals = ar8327_init_globals,
945 .init_port = ar8327_init_port,
946 .setup_port = ar8327_setup_port,
947 .read_port_status = ar8327_read_port_status,
948 .atu_flush = ar8327_atu_flush,
949 .vtu_flush = ar8327_vtu_flush,
950 .vtu_load_vlan = ar8327_vtu_load_vlan,
951 };
952
953 static int
954 ar8216_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
955 struct switch_val *val)
956 {
957 struct ar8216_priv *priv = to_ar8216(dev);
958 priv->vlan = !!val->value.i;
959 return 0;
960 }
961
962 static int
963 ar8216_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
964 struct switch_val *val)
965 {
966 struct ar8216_priv *priv = to_ar8216(dev);
967 val->value.i = priv->vlan;
968 return 0;
969 }
970
971
972 static int
973 ar8216_sw_set_pvid(struct switch_dev *dev, int port, int vlan)
974 {
975 struct ar8216_priv *priv = to_ar8216(dev);
976
977 /* make sure no invalid PVIDs get set */
978
979 if (vlan >= dev->vlans)
980 return -EINVAL;
981
982 priv->pvid[port] = vlan;
983 return 0;
984 }
985
986 static int
987 ar8216_sw_get_pvid(struct switch_dev *dev, int port, int *vlan)
988 {
989 struct ar8216_priv *priv = to_ar8216(dev);
990 *vlan = priv->pvid[port];
991 return 0;
992 }
993
994 static int
995 ar8216_sw_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
996 struct switch_val *val)
997 {
998 struct ar8216_priv *priv = to_ar8216(dev);
999 priv->vlan_id[val->port_vlan] = val->value.i;
1000 return 0;
1001 }
1002
1003 static int
1004 ar8216_sw_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
1005 struct switch_val *val)
1006 {
1007 struct ar8216_priv *priv = to_ar8216(dev);
1008 val->value.i = priv->vlan_id[val->port_vlan];
1009 return 0;
1010 }
1011
1012 static int
1013 ar8216_sw_get_port_link(struct switch_dev *dev, int port,
1014 struct switch_port_link *link)
1015 {
1016 struct ar8216_priv *priv = to_ar8216(dev);
1017
1018 ar8216_read_port_link(priv, port, link);
1019 return 0;
1020 }
1021
1022 static int
1023 ar8216_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
1024 {
1025 struct ar8216_priv *priv = to_ar8216(dev);
1026 u8 ports = priv->vlan_table[val->port_vlan];
1027 int i;
1028
1029 val->len = 0;
1030 for (i = 0; i < dev->ports; i++) {
1031 struct switch_port *p;
1032
1033 if (!(ports & (1 << i)))
1034 continue;
1035
1036 p = &val->value.ports[val->len++];
1037 p->id = i;
1038 if (priv->vlan_tagged & (1 << i))
1039 p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
1040 else
1041 p->flags = 0;
1042 }
1043 return 0;
1044 }
1045
1046 static int
1047 ar8216_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
1048 {
1049 struct ar8216_priv *priv = to_ar8216(dev);
1050 u8 *vt = &priv->vlan_table[val->port_vlan];
1051 int i, j;
1052
1053 *vt = 0;
1054 for (i = 0; i < val->len; i++) {
1055 struct switch_port *p = &val->value.ports[i];
1056
1057 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
1058 priv->vlan_tagged |= (1 << p->id);
1059 } else {
1060 priv->vlan_tagged &= ~(1 << p->id);
1061 priv->pvid[p->id] = val->port_vlan;
1062
1063 /* make sure that an untagged port does not
1064 * appear in other vlans */
1065 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1066 if (j == val->port_vlan)
1067 continue;
1068 priv->vlan_table[j] &= ~(1 << p->id);
1069 }
1070 }
1071
1072 *vt |= 1 << p->id;
1073 }
1074 return 0;
1075 }
1076
1077 static int
1078 ar8216_sw_hw_apply(struct switch_dev *dev)
1079 {
1080 struct ar8216_priv *priv = to_ar8216(dev);
1081 u8 portmask[AR8X16_MAX_PORTS];
1082 int i, j;
1083
1084 mutex_lock(&priv->reg_mutex);
1085 /* flush all vlan translation unit entries */
1086 priv->chip->vtu_flush(priv);
1087
1088 memset(portmask, 0, sizeof(portmask));
1089 if (!priv->init) {
1090 /* calculate the port destination masks and load vlans
1091 * into the vlan translation unit */
1092 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1093 u8 vp = priv->vlan_table[j];
1094
1095 if (!vp)
1096 continue;
1097
1098 for (i = 0; i < dev->ports; i++) {
1099 u8 mask = (1 << i);
1100 if (vp & mask)
1101 portmask[i] |= vp & ~mask;
1102 }
1103
1104 priv->chip->vtu_load_vlan(priv, priv->vlan_id[j],
1105 priv->vlan_table[j]);
1106 }
1107 } else {
1108 /* vlan disabled:
1109 * isolate all ports, but connect them to the cpu port */
1110 for (i = 0; i < dev->ports; i++) {
1111 if (i == AR8216_PORT_CPU)
1112 continue;
1113
1114 portmask[i] = 1 << AR8216_PORT_CPU;
1115 portmask[AR8216_PORT_CPU] |= (1 << i);
1116 }
1117 }
1118
1119 /* update the port destination mask registers and tag settings */
1120 for (i = 0; i < dev->ports; i++) {
1121 int egress, ingress;
1122 int pvid;
1123
1124 if (priv->vlan) {
1125 pvid = priv->vlan_id[priv->pvid[i]];
1126 if (priv->vlan_tagged & (1 << i))
1127 egress = AR8216_OUT_ADD_VLAN;
1128 else
1129 egress = AR8216_OUT_STRIP_VLAN;
1130 ingress = AR8216_IN_SECURE;
1131 } else {
1132 pvid = i;
1133 egress = AR8216_OUT_KEEP;
1134 ingress = AR8216_IN_PORT_ONLY;
1135 }
1136
1137 priv->chip->setup_port(priv, i, egress, ingress, portmask[i],
1138 pvid);
1139 }
1140 mutex_unlock(&priv->reg_mutex);
1141 return 0;
1142 }
1143
1144 static int
1145 ar8216_sw_reset_switch(struct switch_dev *dev)
1146 {
1147 struct ar8216_priv *priv = to_ar8216(dev);
1148 int i;
1149
1150 mutex_lock(&priv->reg_mutex);
1151 memset(&priv->vlan, 0, sizeof(struct ar8216_priv) -
1152 offsetof(struct ar8216_priv, vlan));
1153
1154 for (i = 0; i < AR8X16_MAX_VLANS; i++)
1155 priv->vlan_id[i] = i;
1156
1157 /* Configure all ports */
1158 for (i = 0; i < dev->ports; i++)
1159 priv->chip->init_port(priv, i);
1160
1161 priv->chip->init_globals(priv);
1162 mutex_unlock(&priv->reg_mutex);
1163
1164 return ar8216_sw_hw_apply(dev);
1165 }
1166
1167 static struct switch_attr ar8216_globals[] = {
1168 {
1169 .type = SWITCH_TYPE_INT,
1170 .name = "enable_vlan",
1171 .description = "Enable VLAN mode",
1172 .set = ar8216_sw_set_vlan,
1173 .get = ar8216_sw_get_vlan,
1174 .max = 1
1175 },
1176 };
1177
1178 static struct switch_attr ar8216_port[] = {
1179 };
1180
1181 static struct switch_attr ar8216_vlan[] = {
1182 {
1183 .type = SWITCH_TYPE_INT,
1184 .name = "vid",
1185 .description = "VLAN ID (0-4094)",
1186 .set = ar8216_sw_set_vid,
1187 .get = ar8216_sw_get_vid,
1188 .max = 4094,
1189 },
1190 };
1191
1192 static const struct switch_dev_ops ar8216_sw_ops = {
1193 .attr_global = {
1194 .attr = ar8216_globals,
1195 .n_attr = ARRAY_SIZE(ar8216_globals),
1196 },
1197 .attr_port = {
1198 .attr = ar8216_port,
1199 .n_attr = ARRAY_SIZE(ar8216_port),
1200 },
1201 .attr_vlan = {
1202 .attr = ar8216_vlan,
1203 .n_attr = ARRAY_SIZE(ar8216_vlan),
1204 },
1205 .get_port_pvid = ar8216_sw_get_pvid,
1206 .set_port_pvid = ar8216_sw_set_pvid,
1207 .get_vlan_ports = ar8216_sw_get_ports,
1208 .set_vlan_ports = ar8216_sw_set_ports,
1209 .apply_config = ar8216_sw_hw_apply,
1210 .reset_switch = ar8216_sw_reset_switch,
1211 .get_port_link = ar8216_sw_get_port_link,
1212 };
1213
1214 static int
1215 ar8216_id_chip(struct ar8216_priv *priv)
1216 {
1217 u32 val;
1218 u16 id;
1219 int i;
1220
1221 val = ar8216_mii_read(priv, AR8216_REG_CTRL);
1222 if (val == ~0)
1223 return -ENODEV;
1224
1225 id = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
1226 for (i = 0; i < AR8X16_PROBE_RETRIES; i++) {
1227 u16 t;
1228
1229 val = ar8216_mii_read(priv, AR8216_REG_CTRL);
1230 if (val == ~0)
1231 return -ENODEV;
1232
1233 t = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
1234 if (t != id)
1235 return -ENODEV;
1236 }
1237
1238 priv->chip_ver = (id & AR8216_CTRL_VERSION) >> AR8216_CTRL_VERSION_S;
1239 priv->chip_rev = (id & AR8216_CTRL_REVISION);
1240
1241 switch (priv->chip_ver) {
1242 case AR8XXX_VER_AR8216:
1243 priv->chip = &ar8216_chip;
1244 break;
1245 case AR8XXX_VER_AR8236:
1246 priv->chip = &ar8236_chip;
1247 break;
1248 case AR8XXX_VER_AR8316:
1249 priv->chip = &ar8316_chip;
1250 break;
1251 case AR8XXX_VER_AR8327:
1252 priv->mii_lo_first = true;
1253 priv->chip = &ar8327_chip;
1254 break;
1255 default:
1256 printk(KERN_DEBUG
1257 "ar8216: Unknown Atheros device [ver=%d, rev=%d, phy_id=%04x%04x]\n",
1258 priv->chip_ver, priv->chip_rev,
1259 mdiobus_read(priv->phy->bus, priv->phy->addr, 2),
1260 mdiobus_read(priv->phy->bus, priv->phy->addr, 3));
1261
1262 return -ENODEV;
1263 }
1264
1265 return 0;
1266 }
1267
1268 static int
1269 ar8216_config_init(struct phy_device *pdev)
1270 {
1271 struct ar8216_priv *priv = pdev->priv;
1272 struct net_device *dev = pdev->attached_dev;
1273 struct switch_dev *swdev;
1274 int ret;
1275
1276 if (!priv) {
1277 priv = kzalloc(sizeof(struct ar8216_priv), GFP_KERNEL);
1278 if (priv == NULL)
1279 return -ENOMEM;
1280 }
1281
1282 priv->phy = pdev;
1283
1284 ret = ar8216_id_chip(priv);
1285 if (ret)
1286 goto err_free_priv;
1287
1288 if (pdev->addr != 0) {
1289 if (ar8xxx_has_gige(priv)) {
1290 pdev->supported |= SUPPORTED_1000baseT_Full;
1291 pdev->advertising |= ADVERTISED_1000baseT_Full;
1292 }
1293
1294 if (chip_is_ar8316(priv)) {
1295 /* check if we're attaching to the switch twice */
1296 pdev = pdev->bus->phy_map[0];
1297 if (!pdev) {
1298 kfree(priv);
1299 return 0;
1300 }
1301
1302 /* switch device has not been initialized, reuse priv */
1303 if (!pdev->priv) {
1304 priv->port4_phy = true;
1305 pdev->priv = priv;
1306 return 0;
1307 }
1308
1309 kfree(priv);
1310
1311 /* switch device has been initialized, reinit */
1312 priv = pdev->priv;
1313 priv->dev.ports = (AR8216_NUM_PORTS - 1);
1314 priv->initialized = false;
1315 priv->port4_phy = true;
1316 ar8316_hw_init(priv);
1317 return 0;
1318 }
1319
1320 kfree(priv);
1321 return 0;
1322 }
1323
1324 if (ar8xxx_has_gige(priv))
1325 pdev->supported = SUPPORTED_1000baseT_Full;
1326 else
1327 pdev->supported = SUPPORTED_100baseT_Full;
1328 pdev->advertising = pdev->supported;
1329
1330 mutex_init(&priv->reg_mutex);
1331 priv->read = ar8216_mii_read;
1332 priv->write = ar8216_mii_write;
1333
1334 pdev->priv = priv;
1335
1336 swdev = &priv->dev;
1337 swdev->cpu_port = AR8216_PORT_CPU;
1338 swdev->ops = &ar8216_sw_ops;
1339 swdev->ports = AR8216_NUM_PORTS;
1340
1341 if (chip_is_ar8316(priv)) {
1342 swdev->name = "Atheros AR8316";
1343 swdev->vlans = AR8X16_MAX_VLANS;
1344
1345 if (priv->port4_phy) {
1346 /* port 5 connected to the other mac, therefore unusable */
1347 swdev->ports = (AR8216_NUM_PORTS - 1);
1348 }
1349 } else if (chip_is_ar8236(priv)) {
1350 swdev->name = "Atheros AR8236";
1351 swdev->vlans = AR8216_NUM_VLANS;
1352 swdev->ports = AR8216_NUM_PORTS;
1353 } else if (chip_is_ar8327(priv)) {
1354 swdev->name = "Atheros AR8327";
1355 swdev->vlans = AR8X16_MAX_VLANS;
1356 swdev->ports = AR8327_NUM_PORTS;
1357 } else {
1358 swdev->name = "Atheros AR8216";
1359 swdev->vlans = AR8216_NUM_VLANS;
1360 }
1361
1362 ret = register_switch(&priv->dev, pdev->attached_dev);
1363 if (ret)
1364 goto err_free_priv;
1365
1366 printk(KERN_INFO "%s: %s switch driver attached.\n",
1367 pdev->attached_dev->name, swdev->name);
1368
1369 priv->init = true;
1370
1371 ret = priv->chip->hw_init(priv);
1372 if (ret)
1373 goto err_free_priv;
1374
1375 ret = ar8216_sw_reset_switch(&priv->dev);
1376 if (ret)
1377 goto err_free_priv;
1378
1379 dev->phy_ptr = priv;
1380
1381 /* VID fixup only needed on ar8216 */
1382 if (chip_is_ar8216(priv) && pdev->addr == 0) {
1383 dev->priv_flags |= IFF_NO_IP_ALIGN;
1384 dev->eth_mangle_rx = ar8216_mangle_rx;
1385 dev->eth_mangle_tx = ar8216_mangle_tx;
1386 }
1387
1388 priv->init = false;
1389
1390 return 0;
1391
1392 err_free_priv:
1393 kfree(priv);
1394 return ret;
1395 }
1396
1397 static int
1398 ar8216_read_status(struct phy_device *phydev)
1399 {
1400 struct ar8216_priv *priv = phydev->priv;
1401 struct switch_port_link link;
1402 int ret;
1403
1404 if (phydev->addr != 0)
1405 return genphy_read_status(phydev);
1406
1407 ar8216_read_port_link(priv, phydev->addr, &link);
1408 phydev->link = !!link.link;
1409 if (!phydev->link)
1410 return 0;
1411
1412 switch (link.speed) {
1413 case SWITCH_PORT_SPEED_10:
1414 phydev->speed = SPEED_10;
1415 break;
1416 case SWITCH_PORT_SPEED_100:
1417 phydev->speed = SPEED_100;
1418 break;
1419 case SWITCH_PORT_SPEED_1000:
1420 phydev->speed = SPEED_1000;
1421 break;
1422 default:
1423 phydev->speed = 0;
1424 }
1425 phydev->duplex = link.duplex ? DUPLEX_FULL : DUPLEX_HALF;
1426
1427 /* flush the address translation unit */
1428 mutex_lock(&priv->reg_mutex);
1429 ret = priv->chip->atu_flush(priv);
1430 mutex_unlock(&priv->reg_mutex);
1431
1432 phydev->state = PHY_RUNNING;
1433 netif_carrier_on(phydev->attached_dev);
1434 phydev->adjust_link(phydev->attached_dev);
1435
1436 return ret;
1437 }
1438
1439 static int
1440 ar8216_config_aneg(struct phy_device *phydev)
1441 {
1442 if (phydev->addr == 0)
1443 return 0;
1444
1445 return genphy_config_aneg(phydev);
1446 }
1447
1448 static int
1449 ar8216_probe(struct phy_device *pdev)
1450 {
1451 struct ar8216_priv priv;
1452
1453 priv.phy = pdev;
1454 return ar8216_id_chip(&priv);
1455 }
1456
1457 static void
1458 ar8216_remove(struct phy_device *pdev)
1459 {
1460 struct ar8216_priv *priv = pdev->priv;
1461 struct net_device *dev = pdev->attached_dev;
1462
1463 if (!priv)
1464 return;
1465
1466 dev->priv_flags &= ~IFF_NO_IP_ALIGN;
1467 dev->eth_mangle_rx = NULL;
1468 dev->eth_mangle_tx = NULL;
1469
1470 if (pdev->addr == 0)
1471 unregister_switch(&priv->dev);
1472 kfree(priv);
1473 }
1474
1475 static struct phy_driver ar8216_driver = {
1476 .phy_id = 0x004d0000,
1477 .name = "Atheros AR8216/AR8236/AR8316",
1478 .phy_id_mask = 0xffff0000,
1479 .features = PHY_BASIC_FEATURES,
1480 .probe = ar8216_probe,
1481 .remove = ar8216_remove,
1482 .config_init = &ar8216_config_init,
1483 .config_aneg = &ar8216_config_aneg,
1484 .read_status = &ar8216_read_status,
1485 .driver = { .owner = THIS_MODULE },
1486 };
1487
1488 int __init
1489 ar8216_init(void)
1490 {
1491 return phy_driver_register(&ar8216_driver);
1492 }
1493
1494 void __exit
1495 ar8216_exit(void)
1496 {
1497 phy_driver_unregister(&ar8216_driver);
1498 }
1499
1500 module_init(ar8216_init);
1501 module_exit(ar8216_exit);
1502 MODULE_LICENSE("GPL");
1503
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