2 * ar8216.c: AR8216 switch driver
4 * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/list.h>
22 #include <linux/if_ether.h>
23 #include <linux/skbuff.h>
24 #include <linux/netdevice.h>
25 #include <linux/netlink.h>
26 #include <linux/bitops.h>
27 #include <net/genetlink.h>
28 #include <linux/switch.h>
29 #include <linux/delay.h>
30 #include <linux/phy.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/lockdep.h>
34 #include <linux/ar8216_platform.h>
35 #include <linux/workqueue.h>
36 #include <linux/version.h>
40 extern const struct ar8xxx_chip ar8327_chip
;
41 extern const struct ar8xxx_chip ar8337_chip
;
43 #define AR8XXX_MIB_WORK_DELAY 2000 /* msecs */
45 #define MIB_DESC(_s , _o, _n) \
52 static const struct ar8xxx_mib_desc ar8216_mibs
[] = {
53 MIB_DESC(1, AR8216_STATS_RXBROAD
, "RxBroad"),
54 MIB_DESC(1, AR8216_STATS_RXPAUSE
, "RxPause"),
55 MIB_DESC(1, AR8216_STATS_RXMULTI
, "RxMulti"),
56 MIB_DESC(1, AR8216_STATS_RXFCSERR
, "RxFcsErr"),
57 MIB_DESC(1, AR8216_STATS_RXALIGNERR
, "RxAlignErr"),
58 MIB_DESC(1, AR8216_STATS_RXRUNT
, "RxRunt"),
59 MIB_DESC(1, AR8216_STATS_RXFRAGMENT
, "RxFragment"),
60 MIB_DESC(1, AR8216_STATS_RX64BYTE
, "Rx64Byte"),
61 MIB_DESC(1, AR8216_STATS_RX128BYTE
, "Rx128Byte"),
62 MIB_DESC(1, AR8216_STATS_RX256BYTE
, "Rx256Byte"),
63 MIB_DESC(1, AR8216_STATS_RX512BYTE
, "Rx512Byte"),
64 MIB_DESC(1, AR8216_STATS_RX1024BYTE
, "Rx1024Byte"),
65 MIB_DESC(1, AR8216_STATS_RXMAXBYTE
, "RxMaxByte"),
66 MIB_DESC(1, AR8216_STATS_RXTOOLONG
, "RxTooLong"),
67 MIB_DESC(2, AR8216_STATS_RXGOODBYTE
, "RxGoodByte"),
68 MIB_DESC(2, AR8216_STATS_RXBADBYTE
, "RxBadByte"),
69 MIB_DESC(1, AR8216_STATS_RXOVERFLOW
, "RxOverFlow"),
70 MIB_DESC(1, AR8216_STATS_FILTERED
, "Filtered"),
71 MIB_DESC(1, AR8216_STATS_TXBROAD
, "TxBroad"),
72 MIB_DESC(1, AR8216_STATS_TXPAUSE
, "TxPause"),
73 MIB_DESC(1, AR8216_STATS_TXMULTI
, "TxMulti"),
74 MIB_DESC(1, AR8216_STATS_TXUNDERRUN
, "TxUnderRun"),
75 MIB_DESC(1, AR8216_STATS_TX64BYTE
, "Tx64Byte"),
76 MIB_DESC(1, AR8216_STATS_TX128BYTE
, "Tx128Byte"),
77 MIB_DESC(1, AR8216_STATS_TX256BYTE
, "Tx256Byte"),
78 MIB_DESC(1, AR8216_STATS_TX512BYTE
, "Tx512Byte"),
79 MIB_DESC(1, AR8216_STATS_TX1024BYTE
, "Tx1024Byte"),
80 MIB_DESC(1, AR8216_STATS_TXMAXBYTE
, "TxMaxByte"),
81 MIB_DESC(1, AR8216_STATS_TXOVERSIZE
, "TxOverSize"),
82 MIB_DESC(2, AR8216_STATS_TXBYTE
, "TxByte"),
83 MIB_DESC(1, AR8216_STATS_TXCOLLISION
, "TxCollision"),
84 MIB_DESC(1, AR8216_STATS_TXABORTCOL
, "TxAbortCol"),
85 MIB_DESC(1, AR8216_STATS_TXMULTICOL
, "TxMultiCol"),
86 MIB_DESC(1, AR8216_STATS_TXSINGLECOL
, "TxSingleCol"),
87 MIB_DESC(1, AR8216_STATS_TXEXCDEFER
, "TxExcDefer"),
88 MIB_DESC(1, AR8216_STATS_TXDEFER
, "TxDefer"),
89 MIB_DESC(1, AR8216_STATS_TXLATECOL
, "TxLateCol"),
92 const struct ar8xxx_mib_desc ar8236_mibs
[39] = {
93 MIB_DESC(1, AR8236_STATS_RXBROAD
, "RxBroad"),
94 MIB_DESC(1, AR8236_STATS_RXPAUSE
, "RxPause"),
95 MIB_DESC(1, AR8236_STATS_RXMULTI
, "RxMulti"),
96 MIB_DESC(1, AR8236_STATS_RXFCSERR
, "RxFcsErr"),
97 MIB_DESC(1, AR8236_STATS_RXALIGNERR
, "RxAlignErr"),
98 MIB_DESC(1, AR8236_STATS_RXRUNT
, "RxRunt"),
99 MIB_DESC(1, AR8236_STATS_RXFRAGMENT
, "RxFragment"),
100 MIB_DESC(1, AR8236_STATS_RX64BYTE
, "Rx64Byte"),
101 MIB_DESC(1, AR8236_STATS_RX128BYTE
, "Rx128Byte"),
102 MIB_DESC(1, AR8236_STATS_RX256BYTE
, "Rx256Byte"),
103 MIB_DESC(1, AR8236_STATS_RX512BYTE
, "Rx512Byte"),
104 MIB_DESC(1, AR8236_STATS_RX1024BYTE
, "Rx1024Byte"),
105 MIB_DESC(1, AR8236_STATS_RX1518BYTE
, "Rx1518Byte"),
106 MIB_DESC(1, AR8236_STATS_RXMAXBYTE
, "RxMaxByte"),
107 MIB_DESC(1, AR8236_STATS_RXTOOLONG
, "RxTooLong"),
108 MIB_DESC(2, AR8236_STATS_RXGOODBYTE
, "RxGoodByte"),
109 MIB_DESC(2, AR8236_STATS_RXBADBYTE
, "RxBadByte"),
110 MIB_DESC(1, AR8236_STATS_RXOVERFLOW
, "RxOverFlow"),
111 MIB_DESC(1, AR8236_STATS_FILTERED
, "Filtered"),
112 MIB_DESC(1, AR8236_STATS_TXBROAD
, "TxBroad"),
113 MIB_DESC(1, AR8236_STATS_TXPAUSE
, "TxPause"),
114 MIB_DESC(1, AR8236_STATS_TXMULTI
, "TxMulti"),
115 MIB_DESC(1, AR8236_STATS_TXUNDERRUN
, "TxUnderRun"),
116 MIB_DESC(1, AR8236_STATS_TX64BYTE
, "Tx64Byte"),
117 MIB_DESC(1, AR8236_STATS_TX128BYTE
, "Tx128Byte"),
118 MIB_DESC(1, AR8236_STATS_TX256BYTE
, "Tx256Byte"),
119 MIB_DESC(1, AR8236_STATS_TX512BYTE
, "Tx512Byte"),
120 MIB_DESC(1, AR8236_STATS_TX1024BYTE
, "Tx1024Byte"),
121 MIB_DESC(1, AR8236_STATS_TX1518BYTE
, "Tx1518Byte"),
122 MIB_DESC(1, AR8236_STATS_TXMAXBYTE
, "TxMaxByte"),
123 MIB_DESC(1, AR8236_STATS_TXOVERSIZE
, "TxOverSize"),
124 MIB_DESC(2, AR8236_STATS_TXBYTE
, "TxByte"),
125 MIB_DESC(1, AR8236_STATS_TXCOLLISION
, "TxCollision"),
126 MIB_DESC(1, AR8236_STATS_TXABORTCOL
, "TxAbortCol"),
127 MIB_DESC(1, AR8236_STATS_TXMULTICOL
, "TxMultiCol"),
128 MIB_DESC(1, AR8236_STATS_TXSINGLECOL
, "TxSingleCol"),
129 MIB_DESC(1, AR8236_STATS_TXEXCDEFER
, "TxExcDefer"),
130 MIB_DESC(1, AR8236_STATS_TXDEFER
, "TxDefer"),
131 MIB_DESC(1, AR8236_STATS_TXLATECOL
, "TxLateCol"),
134 static DEFINE_MUTEX(ar8xxx_dev_list_lock
);
135 static LIST_HEAD(ar8xxx_dev_list
);
138 split_addr(u32 regaddr
, u16
*r1
, u16
*r2
, u16
*page
)
141 *r1
= regaddr
& 0x1e;
147 *page
= regaddr
& 0x1ff;
150 /* inspired by phy_poll_reset in drivers/net/phy/phy_device.c */
152 ar8xxx_phy_poll_reset(struct mii_bus
*bus
)
154 unsigned int sleep_msecs
= 20;
157 for (elapsed
= sleep_msecs
; elapsed
<= 600;
158 elapsed
+= sleep_msecs
) {
160 for (i
= 0; i
< AR8XXX_NUM_PHYS
; i
++) {
161 ret
= mdiobus_read(bus
, i
, MII_BMCR
);
164 if (ret
& BMCR_RESET
)
166 if (i
== AR8XXX_NUM_PHYS
- 1) {
167 usleep_range(1000, 2000);
176 ar8xxx_phy_check_aneg(struct phy_device
*phydev
)
180 if (phydev
->autoneg
!= AUTONEG_ENABLE
)
183 * BMCR_ANENABLE might have been cleared
184 * by phy_init_hw in certain kernel versions
185 * therefore check for it
187 ret
= phy_read(phydev
, MII_BMCR
);
190 if (ret
& BMCR_ANENABLE
)
193 dev_info(&phydev
->dev
, "ANEG disabled, re-enabling ...\n");
194 ret
|= BMCR_ANENABLE
| BMCR_ANRESTART
;
195 return phy_write(phydev
, MII_BMCR
, ret
);
199 ar8xxx_phy_init(struct ar8xxx_priv
*priv
)
205 for (i
= 0; i
< AR8XXX_NUM_PHYS
; i
++) {
206 if (priv
->chip
->phy_fixup
)
207 priv
->chip
->phy_fixup(priv
, i
);
209 /* initialize the port itself */
210 mdiobus_write(bus
, i
, MII_ADVERTISE
,
211 ADVERTISE_ALL
| ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
);
212 if (ar8xxx_has_gige(priv
))
213 mdiobus_write(bus
, i
, MII_CTRL1000
, ADVERTISE_1000FULL
);
214 mdiobus_write(bus
, i
, MII_BMCR
, BMCR_RESET
| BMCR_ANENABLE
);
217 ar8xxx_phy_poll_reset(bus
);
221 mii_read32(struct ar8xxx_priv
*priv
, int phy_id
, int regnum
)
223 struct mii_bus
*bus
= priv
->mii_bus
;
226 lo
= bus
->read(bus
, phy_id
, regnum
);
227 hi
= bus
->read(bus
, phy_id
, regnum
+ 1);
229 return (hi
<< 16) | lo
;
233 mii_write32(struct ar8xxx_priv
*priv
, int phy_id
, int regnum
, u32 val
)
235 struct mii_bus
*bus
= priv
->mii_bus
;
239 hi
= (u16
) (val
>> 16);
241 if (priv
->chip
->mii_lo_first
)
243 bus
->write(bus
, phy_id
, regnum
, lo
);
244 bus
->write(bus
, phy_id
, regnum
+ 1, hi
);
246 bus
->write(bus
, phy_id
, regnum
+ 1, hi
);
247 bus
->write(bus
, phy_id
, regnum
, lo
);
252 ar8xxx_read(struct ar8xxx_priv
*priv
, int reg
)
254 struct mii_bus
*bus
= priv
->mii_bus
;
258 split_addr((u32
) reg
, &r1
, &r2
, &page
);
260 mutex_lock(&bus
->mdio_lock
);
262 bus
->write(bus
, 0x18, 0, page
);
263 usleep_range(1000, 2000); /* wait for the page switch to propagate */
264 val
= mii_read32(priv
, 0x10 | r2
, r1
);
266 mutex_unlock(&bus
->mdio_lock
);
272 ar8xxx_write(struct ar8xxx_priv
*priv
, int reg
, u32 val
)
274 struct mii_bus
*bus
= priv
->mii_bus
;
277 split_addr((u32
) reg
, &r1
, &r2
, &page
);
279 mutex_lock(&bus
->mdio_lock
);
281 bus
->write(bus
, 0x18, 0, page
);
282 usleep_range(1000, 2000); /* wait for the page switch to propagate */
283 mii_write32(priv
, 0x10 | r2
, r1
, val
);
285 mutex_unlock(&bus
->mdio_lock
);
289 ar8xxx_rmw(struct ar8xxx_priv
*priv
, int reg
, u32 mask
, u32 val
)
291 struct mii_bus
*bus
= priv
->mii_bus
;
295 split_addr((u32
) reg
, &r1
, &r2
, &page
);
297 mutex_lock(&bus
->mdio_lock
);
299 bus
->write(bus
, 0x18, 0, page
);
300 usleep_range(1000, 2000); /* wait for the page switch to propagate */
302 ret
= mii_read32(priv
, 0x10 | r2
, r1
);
305 mii_write32(priv
, 0x10 | r2
, r1
, ret
);
307 mutex_unlock(&bus
->mdio_lock
);
313 ar8xxx_phy_dbg_write(struct ar8xxx_priv
*priv
, int phy_addr
,
314 u16 dbg_addr
, u16 dbg_data
)
316 struct mii_bus
*bus
= priv
->mii_bus
;
318 mutex_lock(&bus
->mdio_lock
);
319 bus
->write(bus
, phy_addr
, MII_ATH_DBG_ADDR
, dbg_addr
);
320 bus
->write(bus
, phy_addr
, MII_ATH_DBG_DATA
, dbg_data
);
321 mutex_unlock(&bus
->mdio_lock
);
325 ar8xxx_phy_mmd_write(struct ar8xxx_priv
*priv
, int phy_addr
, u16 addr
, u16 data
)
327 struct mii_bus
*bus
= priv
->mii_bus
;
329 mutex_lock(&bus
->mdio_lock
);
330 bus
->write(bus
, phy_addr
, MII_ATH_MMD_ADDR
, addr
);
331 bus
->write(bus
, phy_addr
, MII_ATH_MMD_DATA
, data
);
332 mutex_unlock(&bus
->mdio_lock
);
336 ar8xxx_phy_mmd_read(struct ar8xxx_priv
*priv
, int phy_addr
, u16 addr
)
338 struct mii_bus
*bus
= priv
->mii_bus
;
341 mutex_lock(&bus
->mdio_lock
);
342 bus
->write(bus
, phy_addr
, MII_ATH_MMD_ADDR
, addr
);
343 data
= bus
->read(bus
, phy_addr
, MII_ATH_MMD_DATA
);
344 mutex_unlock(&bus
->mdio_lock
);
350 ar8xxx_reg_wait(struct ar8xxx_priv
*priv
, u32 reg
, u32 mask
, u32 val
,
355 for (i
= 0; i
< timeout
; i
++) {
358 t
= ar8xxx_read(priv
, reg
);
359 if ((t
& mask
) == val
)
362 usleep_range(1000, 2000);
369 ar8xxx_mib_op(struct ar8xxx_priv
*priv
, u32 op
)
371 unsigned mib_func
= priv
->chip
->mib_func
;
374 lockdep_assert_held(&priv
->mib_lock
);
376 /* Capture the hardware statistics for all ports */
377 ar8xxx_rmw(priv
, mib_func
, AR8216_MIB_FUNC
, (op
<< AR8216_MIB_FUNC_S
));
379 /* Wait for the capturing to complete. */
380 ret
= ar8xxx_reg_wait(priv
, mib_func
, AR8216_MIB_BUSY
, 0, 10);
391 ar8xxx_mib_capture(struct ar8xxx_priv
*priv
)
393 return ar8xxx_mib_op(priv
, AR8216_MIB_FUNC_CAPTURE
);
397 ar8xxx_mib_flush(struct ar8xxx_priv
*priv
)
399 return ar8xxx_mib_op(priv
, AR8216_MIB_FUNC_FLUSH
);
403 ar8xxx_mib_fetch_port_stat(struct ar8xxx_priv
*priv
, int port
, bool flush
)
409 WARN_ON(port
>= priv
->dev
.ports
);
411 lockdep_assert_held(&priv
->mib_lock
);
413 base
= priv
->chip
->reg_port_stats_start
+
414 priv
->chip
->reg_port_stats_length
* port
;
416 mib_stats
= &priv
->mib_stats
[port
* priv
->chip
->num_mibs
];
417 for (i
= 0; i
< priv
->chip
->num_mibs
; i
++) {
418 const struct ar8xxx_mib_desc
*mib
;
421 mib
= &priv
->chip
->mib_decs
[i
];
422 t
= ar8xxx_read(priv
, base
+ mib
->offset
);
423 if (mib
->size
== 2) {
426 hi
= ar8xxx_read(priv
, base
+ mib
->offset
+ 4);
438 ar8216_read_port_link(struct ar8xxx_priv
*priv
, int port
,
439 struct switch_port_link
*link
)
444 memset(link
, '\0', sizeof(*link
));
446 status
= priv
->chip
->read_port_status(priv
, port
);
448 link
->aneg
= !!(status
& AR8216_PORT_STATUS_LINK_AUTO
);
450 link
->link
= !!(status
& AR8216_PORT_STATUS_LINK_UP
);
454 if (priv
->get_port_link
) {
457 err
= priv
->get_port_link(port
);
466 link
->duplex
= !!(status
& AR8216_PORT_STATUS_DUPLEX
);
467 link
->tx_flow
= !!(status
& AR8216_PORT_STATUS_TXFLOW
);
468 link
->rx_flow
= !!(status
& AR8216_PORT_STATUS_RXFLOW
);
470 if (link
->aneg
&& link
->duplex
&& priv
->chip
->read_port_eee_status
)
471 link
->eee
= priv
->chip
->read_port_eee_status(priv
, port
);
473 speed
= (status
& AR8216_PORT_STATUS_SPEED
) >>
474 AR8216_PORT_STATUS_SPEED_S
;
477 case AR8216_PORT_SPEED_10M
:
478 link
->speed
= SWITCH_PORT_SPEED_10
;
480 case AR8216_PORT_SPEED_100M
:
481 link
->speed
= SWITCH_PORT_SPEED_100
;
483 case AR8216_PORT_SPEED_1000M
:
484 link
->speed
= SWITCH_PORT_SPEED_1000
;
487 link
->speed
= SWITCH_PORT_SPEED_UNKNOWN
;
492 static struct sk_buff
*
493 ar8216_mangle_tx(struct net_device
*dev
, struct sk_buff
*skb
)
495 struct ar8xxx_priv
*priv
= dev
->phy_ptr
;
504 if (unlikely(skb_headroom(skb
) < 2)) {
505 if (pskb_expand_head(skb
, 2, 0, GFP_ATOMIC
) < 0)
509 buf
= skb_push(skb
, 2);
517 dev_kfree_skb_any(skb
);
522 ar8216_mangle_rx(struct net_device
*dev
, struct sk_buff
*skb
)
524 struct ar8xxx_priv
*priv
;
532 /* don't strip the header if vlan mode is disabled */
536 /* strip header, get vlan id */
540 /* check for vlan header presence */
541 if ((buf
[12 + 2] != 0x81) || (buf
[13 + 2] != 0x00))
546 /* no need to fix up packets coming from a tagged source */
547 if (priv
->vlan_tagged
& (1 << port
))
550 /* lookup port vid from local table, the switch passes an invalid vlan id */
551 vlan
= priv
->vlan_id
[priv
->pvid
[port
]];
554 buf
[14 + 2] |= vlan
>> 8;
555 buf
[15 + 2] = vlan
& 0xff;
559 ar8216_wait_bit(struct ar8xxx_priv
*priv
, int reg
, u32 mask
, u32 val
)
565 t
= ar8xxx_read(priv
, reg
);
566 if ((t
& mask
) == val
)
575 pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
576 (unsigned int) reg
, t
, mask
, val
);
581 ar8216_vtu_op(struct ar8xxx_priv
*priv
, u32 op
, u32 val
)
583 if (ar8216_wait_bit(priv
, AR8216_REG_VTU
, AR8216_VTU_ACTIVE
, 0))
585 if ((op
& AR8216_VTU_OP
) == AR8216_VTU_OP_LOAD
) {
586 val
&= AR8216_VTUDATA_MEMBER
;
587 val
|= AR8216_VTUDATA_VALID
;
588 ar8xxx_write(priv
, AR8216_REG_VTU_DATA
, val
);
590 op
|= AR8216_VTU_ACTIVE
;
591 ar8xxx_write(priv
, AR8216_REG_VTU
, op
);
595 ar8216_vtu_flush(struct ar8xxx_priv
*priv
)
597 ar8216_vtu_op(priv
, AR8216_VTU_OP_FLUSH
, 0);
601 ar8216_vtu_load_vlan(struct ar8xxx_priv
*priv
, u32 vid
, u32 port_mask
)
605 op
= AR8216_VTU_OP_LOAD
| (vid
<< AR8216_VTU_VID_S
);
606 ar8216_vtu_op(priv
, op
, port_mask
);
610 ar8216_atu_flush(struct ar8xxx_priv
*priv
)
614 ret
= ar8216_wait_bit(priv
, AR8216_REG_ATU
, AR8216_ATU_ACTIVE
, 0);
616 ar8xxx_write(priv
, AR8216_REG_ATU
, AR8216_ATU_OP_FLUSH
|
623 ar8216_read_port_status(struct ar8xxx_priv
*priv
, int port
)
625 return ar8xxx_read(priv
, AR8216_REG_PORT_STATUS(port
));
629 ar8216_setup_port(struct ar8xxx_priv
*priv
, int port
, u32 members
)
636 pvid
= priv
->vlan_id
[priv
->pvid
[port
]];
637 if (priv
->vlan_tagged
& (1 << port
))
638 egress
= AR8216_OUT_ADD_VLAN
;
640 egress
= AR8216_OUT_STRIP_VLAN
;
641 ingress
= AR8216_IN_SECURE
;
644 egress
= AR8216_OUT_KEEP
;
645 ingress
= AR8216_IN_PORT_ONLY
;
648 if (chip_is_ar8216(priv
) && priv
->vlan
&& port
== AR8216_PORT_CPU
)
649 header
= AR8216_PORT_CTRL_HEADER
;
653 ar8xxx_rmw(priv
, AR8216_REG_PORT_CTRL(port
),
654 AR8216_PORT_CTRL_LEARN
| AR8216_PORT_CTRL_VLAN_MODE
|
655 AR8216_PORT_CTRL_SINGLE_VLAN
| AR8216_PORT_CTRL_STATE
|
656 AR8216_PORT_CTRL_HEADER
| AR8216_PORT_CTRL_LEARN_LOCK
,
657 AR8216_PORT_CTRL_LEARN
| header
|
658 (egress
<< AR8216_PORT_CTRL_VLAN_MODE_S
) |
659 (AR8216_PORT_STATE_FORWARD
<< AR8216_PORT_CTRL_STATE_S
));
661 ar8xxx_rmw(priv
, AR8216_REG_PORT_VLAN(port
),
662 AR8216_PORT_VLAN_DEST_PORTS
| AR8216_PORT_VLAN_MODE
|
663 AR8216_PORT_VLAN_DEFAULT_ID
,
664 (members
<< AR8216_PORT_VLAN_DEST_PORTS_S
) |
665 (ingress
<< AR8216_PORT_VLAN_MODE_S
) |
666 (pvid
<< AR8216_PORT_VLAN_DEFAULT_ID_S
));
670 ar8216_hw_init(struct ar8xxx_priv
*priv
)
672 if (priv
->initialized
)
675 ar8xxx_phy_init(priv
);
677 priv
->initialized
= true;
682 ar8216_init_globals(struct ar8xxx_priv
*priv
)
684 /* standard atheros magic */
685 ar8xxx_write(priv
, 0x38, 0xc000050e);
687 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
688 AR8216_GCTRL_MTU
, 1518 + 8 + 2);
692 ar8216_init_port(struct ar8xxx_priv
*priv
, int port
)
694 /* Enable port learning and tx */
695 ar8xxx_write(priv
, AR8216_REG_PORT_CTRL(port
),
696 AR8216_PORT_CTRL_LEARN
|
697 (4 << AR8216_PORT_CTRL_STATE_S
));
699 ar8xxx_write(priv
, AR8216_REG_PORT_VLAN(port
), 0);
701 if (port
== AR8216_PORT_CPU
) {
702 ar8xxx_write(priv
, AR8216_REG_PORT_STATUS(port
),
703 AR8216_PORT_STATUS_LINK_UP
|
704 (ar8xxx_has_gige(priv
) ?
705 AR8216_PORT_SPEED_1000M
: AR8216_PORT_SPEED_100M
) |
706 AR8216_PORT_STATUS_TXMAC
|
707 AR8216_PORT_STATUS_RXMAC
|
708 (chip_is_ar8316(priv
) ? AR8216_PORT_STATUS_RXFLOW
: 0) |
709 (chip_is_ar8316(priv
) ? AR8216_PORT_STATUS_TXFLOW
: 0) |
710 AR8216_PORT_STATUS_DUPLEX
);
712 ar8xxx_write(priv
, AR8216_REG_PORT_STATUS(port
),
713 AR8216_PORT_STATUS_LINK_AUTO
);
718 ar8236_setup_port(struct ar8xxx_priv
*priv
, int port
, u32 members
)
724 pvid
= priv
->vlan_id
[priv
->pvid
[port
]];
725 if (priv
->vlan_tagged
& (1 << port
))
726 egress
= AR8216_OUT_ADD_VLAN
;
728 egress
= AR8216_OUT_STRIP_VLAN
;
729 ingress
= AR8216_IN_SECURE
;
732 egress
= AR8216_OUT_KEEP
;
733 ingress
= AR8216_IN_PORT_ONLY
;
736 ar8xxx_rmw(priv
, AR8216_REG_PORT_CTRL(port
),
737 AR8216_PORT_CTRL_LEARN
| AR8216_PORT_CTRL_VLAN_MODE
|
738 AR8216_PORT_CTRL_SINGLE_VLAN
| AR8216_PORT_CTRL_STATE
|
739 AR8216_PORT_CTRL_HEADER
| AR8216_PORT_CTRL_LEARN_LOCK
,
740 AR8216_PORT_CTRL_LEARN
|
741 (egress
<< AR8216_PORT_CTRL_VLAN_MODE_S
) |
742 (AR8216_PORT_STATE_FORWARD
<< AR8216_PORT_CTRL_STATE_S
));
744 ar8xxx_rmw(priv
, AR8236_REG_PORT_VLAN(port
),
745 AR8236_PORT_VLAN_DEFAULT_ID
,
746 (pvid
<< AR8236_PORT_VLAN_DEFAULT_ID_S
));
748 ar8xxx_rmw(priv
, AR8236_REG_PORT_VLAN2(port
),
749 AR8236_PORT_VLAN2_VLAN_MODE
|
750 AR8236_PORT_VLAN2_MEMBER
,
751 (ingress
<< AR8236_PORT_VLAN2_VLAN_MODE_S
) |
752 (members
<< AR8236_PORT_VLAN2_MEMBER_S
));
756 ar8236_init_globals(struct ar8xxx_priv
*priv
)
758 /* enable jumbo frames */
759 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
760 AR8316_GCTRL_MTU
, 9018 + 8 + 2);
762 /* enable cpu port to receive arp frames */
763 ar8xxx_reg_set(priv
, AR8216_REG_ATU_CTRL
,
764 AR8236_ATU_CTRL_RES
);
766 /* enable cpu port to receive multicast and broadcast frames */
767 ar8xxx_reg_set(priv
, AR8216_REG_FLOOD_MASK
,
768 AR8236_FM_CPU_BROADCAST_EN
| AR8236_FM_CPU_BCAST_FWD_EN
);
770 /* Enable MIB counters */
771 ar8xxx_rmw(priv
, AR8216_REG_MIB_FUNC
, AR8216_MIB_FUNC
| AR8236_MIB_EN
,
772 (AR8216_MIB_FUNC_NO_OP
<< AR8216_MIB_FUNC_S
) |
777 ar8316_hw_init(struct ar8xxx_priv
*priv
)
781 val
= ar8xxx_read(priv
, AR8316_REG_POSTRIP
);
783 if (priv
->phy
->interface
== PHY_INTERFACE_MODE_RGMII
) {
784 if (priv
->port4_phy
) {
785 /* value taken from Ubiquiti RouterStation Pro */
787 pr_info("ar8316: Using port 4 as PHY\n");
790 pr_info("ar8316: Using port 4 as switch port\n");
792 } else if (priv
->phy
->interface
== PHY_INTERFACE_MODE_GMII
) {
793 /* value taken from AVM Fritz!Box 7390 sources */
796 /* no known value for phy interface */
797 pr_err("ar8316: unsupported mii mode: %d.\n",
798 priv
->phy
->interface
);
805 ar8xxx_write(priv
, AR8316_REG_POSTRIP
, newval
);
807 if (priv
->port4_phy
&&
808 priv
->phy
->interface
== PHY_INTERFACE_MODE_RGMII
) {
809 /* work around for phy4 rgmii mode */
810 ar8xxx_phy_dbg_write(priv
, 4, 0x12, 0x480c);
812 ar8xxx_phy_dbg_write(priv
, 4, 0x0, 0x824e);
814 ar8xxx_phy_dbg_write(priv
, 4, 0x5, 0x3d47);
818 ar8xxx_phy_init(priv
);
821 priv
->initialized
= true;
826 ar8316_init_globals(struct ar8xxx_priv
*priv
)
828 /* standard atheros magic */
829 ar8xxx_write(priv
, 0x38, 0xc000050e);
831 /* enable cpu port to receive multicast and broadcast frames */
832 ar8xxx_write(priv
, AR8216_REG_FLOOD_MASK
, 0x003f003f);
834 /* enable jumbo frames */
835 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
836 AR8316_GCTRL_MTU
, 9018 + 8 + 2);
838 /* Enable MIB counters */
839 ar8xxx_rmw(priv
, AR8216_REG_MIB_FUNC
, AR8216_MIB_FUNC
| AR8236_MIB_EN
,
840 (AR8216_MIB_FUNC_NO_OP
<< AR8216_MIB_FUNC_S
) |
845 ar8xxx_sw_set_vlan(struct switch_dev
*dev
, const struct switch_attr
*attr
,
846 struct switch_val
*val
)
848 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
849 priv
->vlan
= !!val
->value
.i
;
854 ar8xxx_sw_get_vlan(struct switch_dev
*dev
, const struct switch_attr
*attr
,
855 struct switch_val
*val
)
857 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
858 val
->value
.i
= priv
->vlan
;
864 ar8xxx_sw_set_pvid(struct switch_dev
*dev
, int port
, int vlan
)
866 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
868 /* make sure no invalid PVIDs get set */
870 if (vlan
>= dev
->vlans
)
873 priv
->pvid
[port
] = vlan
;
878 ar8xxx_sw_get_pvid(struct switch_dev
*dev
, int port
, int *vlan
)
880 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
881 *vlan
= priv
->pvid
[port
];
886 ar8xxx_sw_set_vid(struct switch_dev
*dev
, const struct switch_attr
*attr
,
887 struct switch_val
*val
)
889 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
890 priv
->vlan_id
[val
->port_vlan
] = val
->value
.i
;
895 ar8xxx_sw_get_vid(struct switch_dev
*dev
, const struct switch_attr
*attr
,
896 struct switch_val
*val
)
898 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
899 val
->value
.i
= priv
->vlan_id
[val
->port_vlan
];
904 ar8xxx_sw_get_port_link(struct switch_dev
*dev
, int port
,
905 struct switch_port_link
*link
)
907 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
909 ar8216_read_port_link(priv
, port
, link
);
914 ar8xxx_sw_get_ports(struct switch_dev
*dev
, struct switch_val
*val
)
916 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
917 u8 ports
= priv
->vlan_table
[val
->port_vlan
];
921 for (i
= 0; i
< dev
->ports
; i
++) {
922 struct switch_port
*p
;
924 if (!(ports
& (1 << i
)))
927 p
= &val
->value
.ports
[val
->len
++];
929 if (priv
->vlan_tagged
& (1 << i
))
930 p
->flags
= (1 << SWITCH_PORT_FLAG_TAGGED
);
938 ar8xxx_sw_set_ports(struct switch_dev
*dev
, struct switch_val
*val
)
940 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
941 u8
*vt
= &priv
->vlan_table
[val
->port_vlan
];
945 for (i
= 0; i
< val
->len
; i
++) {
946 struct switch_port
*p
= &val
->value
.ports
[i
];
948 if (p
->flags
& (1 << SWITCH_PORT_FLAG_TAGGED
)) {
949 priv
->vlan_tagged
|= (1 << p
->id
);
951 priv
->vlan_tagged
&= ~(1 << p
->id
);
952 priv
->pvid
[p
->id
] = val
->port_vlan
;
954 /* make sure that an untagged port does not
955 * appear in other vlans */
956 for (j
= 0; j
< AR8X16_MAX_VLANS
; j
++) {
957 if (j
== val
->port_vlan
)
959 priv
->vlan_table
[j
] &= ~(1 << p
->id
);
969 ar8216_set_mirror_regs(struct ar8xxx_priv
*priv
)
973 /* reset all mirror registers */
974 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CPUPORT
,
975 AR8216_GLOBAL_CPUPORT_MIRROR_PORT
,
976 (0xF << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S
));
977 for (port
= 0; port
< AR8216_NUM_PORTS
; port
++) {
978 ar8xxx_reg_clear(priv
, AR8216_REG_PORT_CTRL(port
),
979 AR8216_PORT_CTRL_MIRROR_RX
);
981 ar8xxx_reg_clear(priv
, AR8216_REG_PORT_CTRL(port
),
982 AR8216_PORT_CTRL_MIRROR_TX
);
985 /* now enable mirroring if necessary */
986 if (priv
->source_port
>= AR8216_NUM_PORTS
||
987 priv
->monitor_port
>= AR8216_NUM_PORTS
||
988 priv
->source_port
== priv
->monitor_port
) {
992 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CPUPORT
,
993 AR8216_GLOBAL_CPUPORT_MIRROR_PORT
,
994 (priv
->monitor_port
<< AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S
));
997 ar8xxx_reg_set(priv
, AR8216_REG_PORT_CTRL(priv
->source_port
),
998 AR8216_PORT_CTRL_MIRROR_RX
);
1000 if (priv
->mirror_tx
)
1001 ar8xxx_reg_set(priv
, AR8216_REG_PORT_CTRL(priv
->source_port
),
1002 AR8216_PORT_CTRL_MIRROR_TX
);
1006 ar8xxx_sw_hw_apply(struct switch_dev
*dev
)
1008 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1009 u8 portmask
[AR8X16_MAX_PORTS
];
1012 mutex_lock(&priv
->reg_mutex
);
1013 /* flush all vlan translation unit entries */
1014 priv
->chip
->vtu_flush(priv
);
1016 memset(portmask
, 0, sizeof(portmask
));
1018 /* calculate the port destination masks and load vlans
1019 * into the vlan translation unit */
1020 for (j
= 0; j
< AR8X16_MAX_VLANS
; j
++) {
1021 u8 vp
= priv
->vlan_table
[j
];
1026 for (i
= 0; i
< dev
->ports
; i
++) {
1029 portmask
[i
] |= vp
& ~mask
;
1032 priv
->chip
->vtu_load_vlan(priv
, priv
->vlan_id
[j
],
1033 priv
->vlan_table
[j
]);
1037 * isolate all ports, but connect them to the cpu port */
1038 for (i
= 0; i
< dev
->ports
; i
++) {
1039 if (i
== AR8216_PORT_CPU
)
1042 portmask
[i
] = 1 << AR8216_PORT_CPU
;
1043 portmask
[AR8216_PORT_CPU
] |= (1 << i
);
1047 /* update the port destination mask registers and tag settings */
1048 for (i
= 0; i
< dev
->ports
; i
++) {
1049 priv
->chip
->setup_port(priv
, i
, portmask
[i
]);
1052 priv
->chip
->set_mirror_regs(priv
);
1054 mutex_unlock(&priv
->reg_mutex
);
1059 ar8xxx_sw_reset_switch(struct switch_dev
*dev
)
1061 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1062 const struct ar8xxx_chip
*chip
= priv
->chip
;
1065 mutex_lock(&priv
->reg_mutex
);
1066 memset(&priv
->vlan
, 0, sizeof(struct ar8xxx_priv
) -
1067 offsetof(struct ar8xxx_priv
, vlan
));
1069 for (i
= 0; i
< AR8X16_MAX_VLANS
; i
++)
1070 priv
->vlan_id
[i
] = i
;
1072 /* Configure all ports */
1073 for (i
= 0; i
< dev
->ports
; i
++)
1074 chip
->init_port(priv
, i
);
1076 priv
->mirror_rx
= false;
1077 priv
->mirror_tx
= false;
1078 priv
->source_port
= 0;
1079 priv
->monitor_port
= 0;
1081 chip
->init_globals(priv
);
1083 mutex_unlock(&priv
->reg_mutex
);
1085 return chip
->sw_hw_apply(dev
);
1089 ar8xxx_sw_set_reset_mibs(struct switch_dev
*dev
,
1090 const struct switch_attr
*attr
,
1091 struct switch_val
*val
)
1093 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1097 if (!ar8xxx_has_mib_counters(priv
))
1100 mutex_lock(&priv
->mib_lock
);
1102 len
= priv
->dev
.ports
* priv
->chip
->num_mibs
*
1103 sizeof(*priv
->mib_stats
);
1104 memset(priv
->mib_stats
, '\0', len
);
1105 ret
= ar8xxx_mib_flush(priv
);
1112 mutex_unlock(&priv
->mib_lock
);
1117 ar8xxx_sw_set_mirror_rx_enable(struct switch_dev
*dev
,
1118 const struct switch_attr
*attr
,
1119 struct switch_val
*val
)
1121 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1123 mutex_lock(&priv
->reg_mutex
);
1124 priv
->mirror_rx
= !!val
->value
.i
;
1125 priv
->chip
->set_mirror_regs(priv
);
1126 mutex_unlock(&priv
->reg_mutex
);
1132 ar8xxx_sw_get_mirror_rx_enable(struct switch_dev
*dev
,
1133 const struct switch_attr
*attr
,
1134 struct switch_val
*val
)
1136 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1137 val
->value
.i
= priv
->mirror_rx
;
1142 ar8xxx_sw_set_mirror_tx_enable(struct switch_dev
*dev
,
1143 const struct switch_attr
*attr
,
1144 struct switch_val
*val
)
1146 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1148 mutex_lock(&priv
->reg_mutex
);
1149 priv
->mirror_tx
= !!val
->value
.i
;
1150 priv
->chip
->set_mirror_regs(priv
);
1151 mutex_unlock(&priv
->reg_mutex
);
1157 ar8xxx_sw_get_mirror_tx_enable(struct switch_dev
*dev
,
1158 const struct switch_attr
*attr
,
1159 struct switch_val
*val
)
1161 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1162 val
->value
.i
= priv
->mirror_tx
;
1167 ar8xxx_sw_set_mirror_monitor_port(struct switch_dev
*dev
,
1168 const struct switch_attr
*attr
,
1169 struct switch_val
*val
)
1171 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1173 mutex_lock(&priv
->reg_mutex
);
1174 priv
->monitor_port
= val
->value
.i
;
1175 priv
->chip
->set_mirror_regs(priv
);
1176 mutex_unlock(&priv
->reg_mutex
);
1182 ar8xxx_sw_get_mirror_monitor_port(struct switch_dev
*dev
,
1183 const struct switch_attr
*attr
,
1184 struct switch_val
*val
)
1186 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1187 val
->value
.i
= priv
->monitor_port
;
1192 ar8xxx_sw_set_mirror_source_port(struct switch_dev
*dev
,
1193 const struct switch_attr
*attr
,
1194 struct switch_val
*val
)
1196 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1198 mutex_lock(&priv
->reg_mutex
);
1199 priv
->source_port
= val
->value
.i
;
1200 priv
->chip
->set_mirror_regs(priv
);
1201 mutex_unlock(&priv
->reg_mutex
);
1207 ar8xxx_sw_get_mirror_source_port(struct switch_dev
*dev
,
1208 const struct switch_attr
*attr
,
1209 struct switch_val
*val
)
1211 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1212 val
->value
.i
= priv
->source_port
;
1217 ar8xxx_sw_set_port_reset_mib(struct switch_dev
*dev
,
1218 const struct switch_attr
*attr
,
1219 struct switch_val
*val
)
1221 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1225 if (!ar8xxx_has_mib_counters(priv
))
1228 port
= val
->port_vlan
;
1229 if (port
>= dev
->ports
)
1232 mutex_lock(&priv
->mib_lock
);
1233 ret
= ar8xxx_mib_capture(priv
);
1237 ar8xxx_mib_fetch_port_stat(priv
, port
, true);
1242 mutex_unlock(&priv
->mib_lock
);
1247 ar8xxx_sw_get_port_mib(struct switch_dev
*dev
,
1248 const struct switch_attr
*attr
,
1249 struct switch_val
*val
)
1251 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1252 const struct ar8xxx_chip
*chip
= priv
->chip
;
1256 char *buf
= priv
->buf
;
1259 if (!ar8xxx_has_mib_counters(priv
))
1262 port
= val
->port_vlan
;
1263 if (port
>= dev
->ports
)
1266 mutex_lock(&priv
->mib_lock
);
1267 ret
= ar8xxx_mib_capture(priv
);
1271 ar8xxx_mib_fetch_port_stat(priv
, port
, false);
1273 len
+= snprintf(buf
+ len
, sizeof(priv
->buf
) - len
,
1274 "Port %d MIB counters\n",
1277 mib_stats
= &priv
->mib_stats
[port
* chip
->num_mibs
];
1278 for (i
= 0; i
< chip
->num_mibs
; i
++)
1279 len
+= snprintf(buf
+ len
, sizeof(priv
->buf
) - len
,
1281 chip
->mib_decs
[i
].name
,
1290 mutex_unlock(&priv
->mib_lock
);
1294 static const struct switch_attr ar8xxx_sw_attr_globals
[] = {
1296 .type
= SWITCH_TYPE_INT
,
1297 .name
= "enable_vlan",
1298 .description
= "Enable VLAN mode",
1299 .set
= ar8xxx_sw_set_vlan
,
1300 .get
= ar8xxx_sw_get_vlan
,
1304 .type
= SWITCH_TYPE_NOVAL
,
1305 .name
= "reset_mibs",
1306 .description
= "Reset all MIB counters",
1307 .set
= ar8xxx_sw_set_reset_mibs
,
1310 .type
= SWITCH_TYPE_INT
,
1311 .name
= "enable_mirror_rx",
1312 .description
= "Enable mirroring of RX packets",
1313 .set
= ar8xxx_sw_set_mirror_rx_enable
,
1314 .get
= ar8xxx_sw_get_mirror_rx_enable
,
1318 .type
= SWITCH_TYPE_INT
,
1319 .name
= "enable_mirror_tx",
1320 .description
= "Enable mirroring of TX packets",
1321 .set
= ar8xxx_sw_set_mirror_tx_enable
,
1322 .get
= ar8xxx_sw_get_mirror_tx_enable
,
1326 .type
= SWITCH_TYPE_INT
,
1327 .name
= "mirror_monitor_port",
1328 .description
= "Mirror monitor port",
1329 .set
= ar8xxx_sw_set_mirror_monitor_port
,
1330 .get
= ar8xxx_sw_get_mirror_monitor_port
,
1331 .max
= AR8216_NUM_PORTS
- 1
1334 .type
= SWITCH_TYPE_INT
,
1335 .name
= "mirror_source_port",
1336 .description
= "Mirror source port",
1337 .set
= ar8xxx_sw_set_mirror_source_port
,
1338 .get
= ar8xxx_sw_get_mirror_source_port
,
1339 .max
= AR8216_NUM_PORTS
- 1
1343 const struct switch_attr ar8xxx_sw_attr_port
[2] = {
1345 .type
= SWITCH_TYPE_NOVAL
,
1346 .name
= "reset_mib",
1347 .description
= "Reset single port MIB counters",
1348 .set
= ar8xxx_sw_set_port_reset_mib
,
1351 .type
= SWITCH_TYPE_STRING
,
1353 .description
= "Get port's MIB counters",
1355 .get
= ar8xxx_sw_get_port_mib
,
1359 const struct switch_attr ar8xxx_sw_attr_vlan
[1] = {
1361 .type
= SWITCH_TYPE_INT
,
1363 .description
= "VLAN ID (0-4094)",
1364 .set
= ar8xxx_sw_set_vid
,
1365 .get
= ar8xxx_sw_get_vid
,
1370 static const struct switch_dev_ops ar8xxx_sw_ops
= {
1372 .attr
= ar8xxx_sw_attr_globals
,
1373 .n_attr
= ARRAY_SIZE(ar8xxx_sw_attr_globals
),
1376 .attr
= ar8xxx_sw_attr_port
,
1377 .n_attr
= ARRAY_SIZE(ar8xxx_sw_attr_port
),
1380 .attr
= ar8xxx_sw_attr_vlan
,
1381 .n_attr
= ARRAY_SIZE(ar8xxx_sw_attr_vlan
),
1383 .get_port_pvid
= ar8xxx_sw_get_pvid
,
1384 .set_port_pvid
= ar8xxx_sw_set_pvid
,
1385 .get_vlan_ports
= ar8xxx_sw_get_ports
,
1386 .set_vlan_ports
= ar8xxx_sw_set_ports
,
1387 .apply_config
= ar8xxx_sw_hw_apply
,
1388 .reset_switch
= ar8xxx_sw_reset_switch
,
1389 .get_port_link
= ar8xxx_sw_get_port_link
,
1392 static const struct ar8xxx_chip ar8216_chip
= {
1393 .caps
= AR8XXX_CAP_MIB_COUNTERS
,
1395 .reg_port_stats_start
= 0x19000,
1396 .reg_port_stats_length
= 0xa0,
1398 .name
= "Atheros AR8216",
1399 .ports
= AR8216_NUM_PORTS
,
1400 .vlans
= AR8216_NUM_VLANS
,
1401 .swops
= &ar8xxx_sw_ops
,
1403 .hw_init
= ar8216_hw_init
,
1404 .init_globals
= ar8216_init_globals
,
1405 .init_port
= ar8216_init_port
,
1406 .setup_port
= ar8216_setup_port
,
1407 .read_port_status
= ar8216_read_port_status
,
1408 .atu_flush
= ar8216_atu_flush
,
1409 .vtu_flush
= ar8216_vtu_flush
,
1410 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
1411 .set_mirror_regs
= ar8216_set_mirror_regs
,
1412 .sw_hw_apply
= ar8xxx_sw_hw_apply
,
1414 .num_mibs
= ARRAY_SIZE(ar8216_mibs
),
1415 .mib_decs
= ar8216_mibs
,
1416 .mib_func
= AR8216_REG_MIB_FUNC
1419 static const struct ar8xxx_chip ar8236_chip
= {
1420 .caps
= AR8XXX_CAP_MIB_COUNTERS
,
1422 .reg_port_stats_start
= 0x20000,
1423 .reg_port_stats_length
= 0x100,
1425 .name
= "Atheros AR8236",
1426 .ports
= AR8216_NUM_PORTS
,
1427 .vlans
= AR8216_NUM_VLANS
,
1428 .swops
= &ar8xxx_sw_ops
,
1430 .hw_init
= ar8216_hw_init
,
1431 .init_globals
= ar8236_init_globals
,
1432 .init_port
= ar8216_init_port
,
1433 .setup_port
= ar8236_setup_port
,
1434 .read_port_status
= ar8216_read_port_status
,
1435 .atu_flush
= ar8216_atu_flush
,
1436 .vtu_flush
= ar8216_vtu_flush
,
1437 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
1438 .set_mirror_regs
= ar8216_set_mirror_regs
,
1439 .sw_hw_apply
= ar8xxx_sw_hw_apply
,
1441 .num_mibs
= ARRAY_SIZE(ar8236_mibs
),
1442 .mib_decs
= ar8236_mibs
,
1443 .mib_func
= AR8216_REG_MIB_FUNC
1446 static const struct ar8xxx_chip ar8316_chip
= {
1447 .caps
= AR8XXX_CAP_GIGE
| AR8XXX_CAP_MIB_COUNTERS
,
1449 .reg_port_stats_start
= 0x20000,
1450 .reg_port_stats_length
= 0x100,
1452 .name
= "Atheros AR8316",
1453 .ports
= AR8216_NUM_PORTS
,
1454 .vlans
= AR8X16_MAX_VLANS
,
1455 .swops
= &ar8xxx_sw_ops
,
1457 .hw_init
= ar8316_hw_init
,
1458 .init_globals
= ar8316_init_globals
,
1459 .init_port
= ar8216_init_port
,
1460 .setup_port
= ar8216_setup_port
,
1461 .read_port_status
= ar8216_read_port_status
,
1462 .atu_flush
= ar8216_atu_flush
,
1463 .vtu_flush
= ar8216_vtu_flush
,
1464 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
1465 .set_mirror_regs
= ar8216_set_mirror_regs
,
1466 .sw_hw_apply
= ar8xxx_sw_hw_apply
,
1468 .num_mibs
= ARRAY_SIZE(ar8236_mibs
),
1469 .mib_decs
= ar8236_mibs
,
1470 .mib_func
= AR8216_REG_MIB_FUNC
1474 ar8xxx_id_chip(struct ar8xxx_priv
*priv
)
1480 val
= ar8xxx_read(priv
, AR8216_REG_CTRL
);
1484 id
= val
& (AR8216_CTRL_REVISION
| AR8216_CTRL_VERSION
);
1485 for (i
= 0; i
< AR8X16_PROBE_RETRIES
; i
++) {
1488 val
= ar8xxx_read(priv
, AR8216_REG_CTRL
);
1492 t
= val
& (AR8216_CTRL_REVISION
| AR8216_CTRL_VERSION
);
1497 priv
->chip_ver
= (id
& AR8216_CTRL_VERSION
) >> AR8216_CTRL_VERSION_S
;
1498 priv
->chip_rev
= (id
& AR8216_CTRL_REVISION
);
1500 switch (priv
->chip_ver
) {
1501 case AR8XXX_VER_AR8216
:
1502 priv
->chip
= &ar8216_chip
;
1504 case AR8XXX_VER_AR8236
:
1505 priv
->chip
= &ar8236_chip
;
1507 case AR8XXX_VER_AR8316
:
1508 priv
->chip
= &ar8316_chip
;
1510 case AR8XXX_VER_AR8327
:
1511 priv
->chip
= &ar8327_chip
;
1513 case AR8XXX_VER_AR8337
:
1514 priv
->chip
= &ar8337_chip
;
1517 pr_err("ar8216: Unknown Atheros device [ver=%d, rev=%d]\n",
1518 priv
->chip_ver
, priv
->chip_rev
);
1527 ar8xxx_mib_work_func(struct work_struct
*work
)
1529 struct ar8xxx_priv
*priv
;
1532 priv
= container_of(work
, struct ar8xxx_priv
, mib_work
.work
);
1534 mutex_lock(&priv
->mib_lock
);
1536 err
= ar8xxx_mib_capture(priv
);
1540 ar8xxx_mib_fetch_port_stat(priv
, priv
->mib_next_port
, false);
1543 priv
->mib_next_port
++;
1544 if (priv
->mib_next_port
>= priv
->dev
.ports
)
1545 priv
->mib_next_port
= 0;
1547 mutex_unlock(&priv
->mib_lock
);
1548 schedule_delayed_work(&priv
->mib_work
,
1549 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY
));
1553 ar8xxx_mib_init(struct ar8xxx_priv
*priv
)
1557 if (!ar8xxx_has_mib_counters(priv
))
1560 BUG_ON(!priv
->chip
->mib_decs
|| !priv
->chip
->num_mibs
);
1562 len
= priv
->dev
.ports
* priv
->chip
->num_mibs
*
1563 sizeof(*priv
->mib_stats
);
1564 priv
->mib_stats
= kzalloc(len
, GFP_KERNEL
);
1566 if (!priv
->mib_stats
)
1573 ar8xxx_mib_start(struct ar8xxx_priv
*priv
)
1575 if (!ar8xxx_has_mib_counters(priv
))
1578 schedule_delayed_work(&priv
->mib_work
,
1579 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY
));
1583 ar8xxx_mib_stop(struct ar8xxx_priv
*priv
)
1585 if (!ar8xxx_has_mib_counters(priv
))
1588 cancel_delayed_work(&priv
->mib_work
);
1591 static struct ar8xxx_priv
*
1594 struct ar8xxx_priv
*priv
;
1596 priv
= kzalloc(sizeof(struct ar8xxx_priv
), GFP_KERNEL
);
1600 mutex_init(&priv
->reg_mutex
);
1601 mutex_init(&priv
->mib_lock
);
1602 INIT_DELAYED_WORK(&priv
->mib_work
, ar8xxx_mib_work_func
);
1608 ar8xxx_free(struct ar8xxx_priv
*priv
)
1610 if (priv
->chip
&& priv
->chip
->cleanup
)
1611 priv
->chip
->cleanup(priv
);
1613 kfree(priv
->chip_data
);
1614 kfree(priv
->mib_stats
);
1619 ar8xxx_probe_switch(struct ar8xxx_priv
*priv
)
1621 const struct ar8xxx_chip
*chip
;
1622 struct switch_dev
*swdev
;
1625 ret
= ar8xxx_id_chip(priv
);
1632 swdev
->cpu_port
= AR8216_PORT_CPU
;
1633 swdev
->name
= chip
->name
;
1634 swdev
->vlans
= chip
->vlans
;
1635 swdev
->ports
= chip
->ports
;
1636 swdev
->ops
= chip
->swops
;
1638 ret
= ar8xxx_mib_init(priv
);
1646 ar8xxx_start(struct ar8xxx_priv
*priv
)
1652 ret
= priv
->chip
->hw_init(priv
);
1656 ret
= ar8xxx_sw_reset_switch(&priv
->dev
);
1662 ar8xxx_mib_start(priv
);
1668 ar8xxx_phy_config_init(struct phy_device
*phydev
)
1670 struct ar8xxx_priv
*priv
= phydev
->priv
;
1671 struct net_device
*dev
= phydev
->attached_dev
;
1677 if (priv
->chip
->config_at_probe
)
1678 return ar8xxx_phy_check_aneg(phydev
);
1682 if (phydev
->addr
!= 0) {
1683 if (chip_is_ar8316(priv
)) {
1684 /* switch device has been initialized, reinit */
1685 priv
->dev
.ports
= (AR8216_NUM_PORTS
- 1);
1686 priv
->initialized
= false;
1687 priv
->port4_phy
= true;
1688 ar8316_hw_init(priv
);
1695 ret
= ar8xxx_start(priv
);
1699 /* VID fixup only needed on ar8216 */
1700 if (chip_is_ar8216(priv
)) {
1701 dev
->phy_ptr
= priv
;
1702 dev
->priv_flags
|= IFF_NO_IP_ALIGN
;
1703 dev
->eth_mangle_rx
= ar8216_mangle_rx
;
1704 dev
->eth_mangle_tx
= ar8216_mangle_tx
;
1711 ar8xxx_check_link_states(struct ar8xxx_priv
*priv
)
1713 bool link_new
, changed
= false;
1717 mutex_lock(&priv
->reg_mutex
);
1719 for (i
= 0; i
< priv
->dev
.ports
; i
++) {
1720 status
= priv
->chip
->read_port_status(priv
, i
);
1721 link_new
= !!(status
& AR8216_PORT_STATUS_LINK_UP
);
1722 if (link_new
== priv
->link_up
[i
])
1725 priv
->link_up
[i
] = link_new
;
1727 dev_info(&priv
->phy
->dev
, "Port %d is %s\n",
1728 i
, link_new
? "up" : "down");
1732 priv
->chip
->atu_flush(priv
);
1734 mutex_unlock(&priv
->reg_mutex
);
1740 ar8xxx_phy_read_status(struct phy_device
*phydev
)
1742 struct ar8xxx_priv
*priv
= phydev
->priv
;
1743 struct switch_port_link link
;
1745 /* check for link changes and flush ATU
1746 * if a change was detected
1748 if (phydev
->state
== PHY_CHANGELINK
)
1749 ar8xxx_check_link_states(priv
);
1751 if (phydev
->addr
!= 0)
1752 return genphy_read_status(phydev
);
1754 ar8216_read_port_link(priv
, phydev
->addr
, &link
);
1755 phydev
->link
= !!link
.link
;
1759 switch (link
.speed
) {
1760 case SWITCH_PORT_SPEED_10
:
1761 phydev
->speed
= SPEED_10
;
1763 case SWITCH_PORT_SPEED_100
:
1764 phydev
->speed
= SPEED_100
;
1766 case SWITCH_PORT_SPEED_1000
:
1767 phydev
->speed
= SPEED_1000
;
1772 phydev
->duplex
= link
.duplex
? DUPLEX_FULL
: DUPLEX_HALF
;
1774 phydev
->state
= PHY_RUNNING
;
1775 netif_carrier_on(phydev
->attached_dev
);
1776 phydev
->adjust_link(phydev
->attached_dev
);
1782 ar8xxx_phy_config_aneg(struct phy_device
*phydev
)
1784 if (phydev
->addr
== 0)
1787 return genphy_config_aneg(phydev
);
1790 static const u32 ar8xxx_phy_ids
[] = {
1792 0x004dd034, /* AR8327 */
1793 0x004dd036, /* AR8337 */
1796 0x004dd043, /* AR8236 */
1800 ar8xxx_phy_match(u32 phy_id
)
1804 for (i
= 0; i
< ARRAY_SIZE(ar8xxx_phy_ids
); i
++)
1805 if (phy_id
== ar8xxx_phy_ids
[i
])
1812 ar8xxx_is_possible(struct mii_bus
*bus
)
1816 for (i
= 0; i
< 4; i
++) {
1819 phy_id
= mdiobus_read(bus
, i
, MII_PHYSID1
) << 16;
1820 phy_id
|= mdiobus_read(bus
, i
, MII_PHYSID2
);
1821 if (!ar8xxx_phy_match(phy_id
)) {
1822 pr_debug("ar8xxx: unknown PHY at %s:%02x id:%08x\n",
1823 dev_name(&bus
->dev
), i
, phy_id
);
1832 ar8xxx_phy_probe(struct phy_device
*phydev
)
1834 struct ar8xxx_priv
*priv
;
1835 struct switch_dev
*swdev
;
1838 /* skip PHYs at unused adresses */
1839 if (phydev
->addr
!= 0 && phydev
->addr
!= 4)
1842 if (!ar8xxx_is_possible(phydev
->bus
))
1845 mutex_lock(&ar8xxx_dev_list_lock
);
1846 list_for_each_entry(priv
, &ar8xxx_dev_list
, list
)
1847 if (priv
->mii_bus
== phydev
->bus
)
1850 priv
= ar8xxx_create();
1856 priv
->mii_bus
= phydev
->bus
;
1858 ret
= ar8xxx_probe_switch(priv
);
1863 swdev
->alias
= dev_name(&priv
->mii_bus
->dev
);
1864 ret
= register_switch(swdev
, NULL
);
1868 pr_info("%s: %s rev. %u switch registered on %s\n",
1869 swdev
->devname
, swdev
->name
, priv
->chip_rev
,
1870 dev_name(&priv
->mii_bus
->dev
));
1875 if (phydev
->addr
== 0) {
1876 if (ar8xxx_has_gige(priv
)) {
1877 phydev
->supported
= SUPPORTED_1000baseT_Full
;
1878 phydev
->advertising
= ADVERTISED_1000baseT_Full
;
1880 phydev
->supported
= SUPPORTED_100baseT_Full
;
1881 phydev
->advertising
= ADVERTISED_100baseT_Full
;
1884 if (priv
->chip
->config_at_probe
) {
1887 ret
= ar8xxx_start(priv
);
1889 goto err_unregister_switch
;
1892 if (ar8xxx_has_gige(priv
)) {
1893 phydev
->supported
|= SUPPORTED_1000baseT_Full
;
1894 phydev
->advertising
|= ADVERTISED_1000baseT_Full
;
1898 phydev
->priv
= priv
;
1900 list_add(&priv
->list
, &ar8xxx_dev_list
);
1902 mutex_unlock(&ar8xxx_dev_list_lock
);
1906 err_unregister_switch
:
1907 if (--priv
->use_count
)
1910 unregister_switch(&priv
->dev
);
1915 mutex_unlock(&ar8xxx_dev_list_lock
);
1920 ar8xxx_phy_detach(struct phy_device
*phydev
)
1922 struct net_device
*dev
= phydev
->attached_dev
;
1927 dev
->phy_ptr
= NULL
;
1928 dev
->priv_flags
&= ~IFF_NO_IP_ALIGN
;
1929 dev
->eth_mangle_rx
= NULL
;
1930 dev
->eth_mangle_tx
= NULL
;
1934 ar8xxx_phy_remove(struct phy_device
*phydev
)
1936 struct ar8xxx_priv
*priv
= phydev
->priv
;
1941 phydev
->priv
= NULL
;
1942 if (--priv
->use_count
> 0)
1945 mutex_lock(&ar8xxx_dev_list_lock
);
1946 list_del(&priv
->list
);
1947 mutex_unlock(&ar8xxx_dev_list_lock
);
1949 unregister_switch(&priv
->dev
);
1950 ar8xxx_mib_stop(priv
);
1954 #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)
1956 ar8xxx_phy_soft_reset(struct phy_device
*phydev
)
1958 /* we don't need an extra reset */
1963 static struct phy_driver ar8xxx_phy_driver
= {
1964 .phy_id
= 0x004d0000,
1965 .name
= "Atheros AR8216/AR8236/AR8316",
1966 .phy_id_mask
= 0xffff0000,
1967 .features
= PHY_BASIC_FEATURES
,
1968 .probe
= ar8xxx_phy_probe
,
1969 .remove
= ar8xxx_phy_remove
,
1970 .detach
= ar8xxx_phy_detach
,
1971 .config_init
= ar8xxx_phy_config_init
,
1972 .config_aneg
= ar8xxx_phy_config_aneg
,
1973 .read_status
= ar8xxx_phy_read_status
,
1974 #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)
1975 .soft_reset
= ar8xxx_phy_soft_reset
,
1977 .driver
= { .owner
= THIS_MODULE
},
1983 return phy_driver_register(&ar8xxx_phy_driver
);
1989 phy_driver_unregister(&ar8xxx_phy_driver
);
1992 module_init(ar8xxx_init
);
1993 module_exit(ar8xxx_exit
);
1994 MODULE_LICENSE("GPL");