2 * ar8216.c: AR8216 switch driver
4 * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/list.h>
22 #include <linux/if_ether.h>
23 #include <linux/skbuff.h>
24 #include <linux/netdevice.h>
25 #include <linux/netlink.h>
26 #include <linux/bitops.h>
27 #include <net/genetlink.h>
28 #include <linux/switch.h>
29 #include <linux/delay.h>
30 #include <linux/phy.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/lockdep.h>
34 #include <linux/ar8216_platform.h>
35 #include <linux/workqueue.h>
38 /* size of the vlan table */
39 #define AR8X16_MAX_VLANS 128
40 #define AR8X16_PROBE_RETRIES 10
41 #define AR8X16_MAX_PORTS 8
43 #define AR8XXX_MIB_WORK_DELAY 2000 /* msecs */
47 #define AR8XXX_CAP_GIGE BIT(0)
48 #define AR8XXX_CAP_MIB_COUNTERS BIT(1)
51 AR8XXX_VER_AR8216
= 0x01,
52 AR8XXX_VER_AR8236
= 0x03,
53 AR8XXX_VER_AR8316
= 0x10,
54 AR8XXX_VER_AR8327
= 0x12,
57 struct ar8xxx_mib_desc
{
66 int (*hw_init
)(struct ar8216_priv
*priv
);
67 void (*init_globals
)(struct ar8216_priv
*priv
);
68 void (*init_port
)(struct ar8216_priv
*priv
, int port
);
69 void (*setup_port
)(struct ar8216_priv
*priv
, int port
, u32 egress
,
70 u32 ingress
, u32 members
, u32 pvid
);
71 u32 (*read_port_status
)(struct ar8216_priv
*priv
, int port
);
72 int (*atu_flush
)(struct ar8216_priv
*priv
);
73 void (*vtu_flush
)(struct ar8216_priv
*priv
);
74 void (*vtu_load_vlan
)(struct ar8216_priv
*priv
, u32 vid
, u32 port_mask
);
76 const struct ar8xxx_mib_desc
*mib_decs
;
81 struct switch_dev dev
;
82 struct mii_bus
*mii_bus
;
83 struct phy_device
*phy
;
84 u32 (*read
)(struct ar8216_priv
*priv
, int reg
);
85 void (*write
)(struct ar8216_priv
*priv
, int reg
, u32 val
);
86 const struct net_device_ops
*ndo_old
;
87 struct net_device_ops ndo
;
88 struct mutex reg_mutex
;
91 const struct ar8xxx_chip
*chip
;
99 struct mutex mib_lock
;
100 struct delayed_work mib_work
;
104 /* all fields below are cleared on reset */
106 u16 vlan_id
[AR8X16_MAX_VLANS
];
107 u8 vlan_table
[AR8X16_MAX_VLANS
];
109 u16 pvid
[AR8X16_MAX_PORTS
];
112 #define MIB_DESC(_s , _o, _n) \
119 static const struct ar8xxx_mib_desc ar8216_mibs
[] = {
120 MIB_DESC(1, AR8216_STATS_RXBROAD
, "RxBroad"),
121 MIB_DESC(1, AR8216_STATS_RXPAUSE
, "RxPause"),
122 MIB_DESC(1, AR8216_STATS_RXMULTI
, "RxMulti"),
123 MIB_DESC(1, AR8216_STATS_RXFCSERR
, "RxFcsErr"),
124 MIB_DESC(1, AR8216_STATS_RXALIGNERR
, "RxAlignErr"),
125 MIB_DESC(1, AR8216_STATS_RXRUNT
, "RxRunt"),
126 MIB_DESC(1, AR8216_STATS_RXFRAGMENT
, "RxFragment"),
127 MIB_DESC(1, AR8216_STATS_RX64BYTE
, "Rx64Byte"),
128 MIB_DESC(1, AR8216_STATS_RX128BYTE
, "Rx128Byte"),
129 MIB_DESC(1, AR8216_STATS_RX256BYTE
, "Rx256Byte"),
130 MIB_DESC(1, AR8216_STATS_RX512BYTE
, "Rx512Byte"),
131 MIB_DESC(1, AR8216_STATS_RX1024BYTE
, "Rx1024Byte"),
132 MIB_DESC(1, AR8216_STATS_RXMAXBYTE
, "RxMaxByte"),
133 MIB_DESC(1, AR8216_STATS_RXTOOLONG
, "RxTooLong"),
134 MIB_DESC(2, AR8216_STATS_RXGOODBYTE
, "RxGoodByte"),
135 MIB_DESC(2, AR8216_STATS_RXBADBYTE
, "RxBadByte"),
136 MIB_DESC(1, AR8216_STATS_RXOVERFLOW
, "RxOverFlow"),
137 MIB_DESC(1, AR8216_STATS_FILTERED
, "Filtered"),
138 MIB_DESC(1, AR8216_STATS_TXBROAD
, "TxBroad"),
139 MIB_DESC(1, AR8216_STATS_TXPAUSE
, "TxPause"),
140 MIB_DESC(1, AR8216_STATS_TXMULTI
, "TxMulti"),
141 MIB_DESC(1, AR8216_STATS_TXUNDERRUN
, "TxUnderRun"),
142 MIB_DESC(1, AR8216_STATS_TX64BYTE
, "Tx64Byte"),
143 MIB_DESC(1, AR8216_STATS_TX128BYTE
, "Tx128Byte"),
144 MIB_DESC(1, AR8216_STATS_TX256BYTE
, "Tx256Byte"),
145 MIB_DESC(1, AR8216_STATS_TX512BYTE
, "Tx512Byte"),
146 MIB_DESC(1, AR8216_STATS_TX1024BYTE
, "Tx1024Byte"),
147 MIB_DESC(1, AR8216_STATS_TXMAXBYTE
, "TxMaxByte"),
148 MIB_DESC(1, AR8216_STATS_TXOVERSIZE
, "TxOverSize"),
149 MIB_DESC(2, AR8216_STATS_TXBYTE
, "TxByte"),
150 MIB_DESC(1, AR8216_STATS_TXCOLLISION
, "TxCollision"),
151 MIB_DESC(1, AR8216_STATS_TXABORTCOL
, "TxAbortCol"),
152 MIB_DESC(1, AR8216_STATS_TXMULTICOL
, "TxMultiCol"),
153 MIB_DESC(1, AR8216_STATS_TXSINGLECOL
, "TxSingleCol"),
154 MIB_DESC(1, AR8216_STATS_TXEXCDEFER
, "TxExcDefer"),
155 MIB_DESC(1, AR8216_STATS_TXDEFER
, "TxDefer"),
156 MIB_DESC(1, AR8216_STATS_TXLATECOL
, "TxLateCol"),
159 static const struct ar8xxx_mib_desc ar8236_mibs
[] = {
160 MIB_DESC(1, AR8236_STATS_RXBROAD
, "RxBroad"),
161 MIB_DESC(1, AR8236_STATS_RXPAUSE
, "RxPause"),
162 MIB_DESC(1, AR8236_STATS_RXMULTI
, "RxMulti"),
163 MIB_DESC(1, AR8236_STATS_RXFCSERR
, "RxFcsErr"),
164 MIB_DESC(1, AR8236_STATS_RXALIGNERR
, "RxAlignErr"),
165 MIB_DESC(1, AR8236_STATS_RXRUNT
, "RxRunt"),
166 MIB_DESC(1, AR8236_STATS_RXFRAGMENT
, "RxFragment"),
167 MIB_DESC(1, AR8236_STATS_RX64BYTE
, "Rx64Byte"),
168 MIB_DESC(1, AR8236_STATS_RX128BYTE
, "Rx128Byte"),
169 MIB_DESC(1, AR8236_STATS_RX256BYTE
, "Rx256Byte"),
170 MIB_DESC(1, AR8236_STATS_RX512BYTE
, "Rx512Byte"),
171 MIB_DESC(1, AR8236_STATS_RX1024BYTE
, "Rx1024Byte"),
172 MIB_DESC(1, AR8236_STATS_RX1518BYTE
, "Rx1518Byte"),
173 MIB_DESC(1, AR8236_STATS_RXMAXBYTE
, "RxMaxByte"),
174 MIB_DESC(1, AR8236_STATS_RXTOOLONG
, "RxTooLong"),
175 MIB_DESC(2, AR8236_STATS_RXGOODBYTE
, "RxGoodByte"),
176 MIB_DESC(2, AR8236_STATS_RXBADBYTE
, "RxBadByte"),
177 MIB_DESC(1, AR8236_STATS_RXOVERFLOW
, "RxOverFlow"),
178 MIB_DESC(1, AR8236_STATS_FILTERED
, "Filtered"),
179 MIB_DESC(1, AR8236_STATS_TXBROAD
, "TxBroad"),
180 MIB_DESC(1, AR8236_STATS_TXPAUSE
, "TxPause"),
181 MIB_DESC(1, AR8236_STATS_TXMULTI
, "TxMulti"),
182 MIB_DESC(1, AR8236_STATS_TXUNDERRUN
, "TxUnderRun"),
183 MIB_DESC(1, AR8236_STATS_TX64BYTE
, "Tx64Byte"),
184 MIB_DESC(1, AR8236_STATS_TX128BYTE
, "Tx128Byte"),
185 MIB_DESC(1, AR8236_STATS_TX256BYTE
, "Tx256Byte"),
186 MIB_DESC(1, AR8236_STATS_TX512BYTE
, "Tx512Byte"),
187 MIB_DESC(1, AR8236_STATS_TX1024BYTE
, "Tx1024Byte"),
188 MIB_DESC(1, AR8236_STATS_TX1518BYTE
, "Tx1518Byte"),
189 MIB_DESC(1, AR8236_STATS_TXMAXBYTE
, "TxMaxByte"),
190 MIB_DESC(1, AR8236_STATS_TXOVERSIZE
, "TxOverSize"),
191 MIB_DESC(2, AR8236_STATS_TXBYTE
, "TxByte"),
192 MIB_DESC(1, AR8236_STATS_TXCOLLISION
, "TxCollision"),
193 MIB_DESC(1, AR8236_STATS_TXABORTCOL
, "TxAbortCol"),
194 MIB_DESC(1, AR8236_STATS_TXMULTICOL
, "TxMultiCol"),
195 MIB_DESC(1, AR8236_STATS_TXSINGLECOL
, "TxSingleCol"),
196 MIB_DESC(1, AR8236_STATS_TXEXCDEFER
, "TxExcDefer"),
197 MIB_DESC(1, AR8236_STATS_TXDEFER
, "TxDefer"),
198 MIB_DESC(1, AR8236_STATS_TXLATECOL
, "TxLateCol"),
201 #define to_ar8216(_dev) container_of(_dev, struct ar8216_priv, dev)
203 static inline bool ar8xxx_has_gige(struct ar8216_priv
*priv
)
205 return priv
->chip
->caps
& AR8XXX_CAP_GIGE
;
208 static inline bool ar8xxx_has_mib_counters(struct ar8216_priv
*priv
)
210 return priv
->chip
->caps
& AR8XXX_CAP_MIB_COUNTERS
;
213 static inline bool chip_is_ar8216(struct ar8216_priv
*priv
)
215 return priv
->chip_ver
== AR8XXX_VER_AR8216
;
218 static inline bool chip_is_ar8236(struct ar8216_priv
*priv
)
220 return priv
->chip_ver
== AR8XXX_VER_AR8236
;
223 static inline bool chip_is_ar8316(struct ar8216_priv
*priv
)
225 return priv
->chip_ver
== AR8XXX_VER_AR8316
;
228 static inline bool chip_is_ar8327(struct ar8216_priv
*priv
)
230 return priv
->chip_ver
== AR8XXX_VER_AR8327
;
234 split_addr(u32 regaddr
, u16
*r1
, u16
*r2
, u16
*page
)
237 *r1
= regaddr
& 0x1e;
243 *page
= regaddr
& 0x1ff;
247 ar8216_mii_read(struct ar8216_priv
*priv
, int reg
)
249 struct mii_bus
*bus
= priv
->mii_bus
;
253 split_addr((u32
) reg
, &r1
, &r2
, &page
);
255 mutex_lock(&bus
->mdio_lock
);
257 bus
->write(bus
, 0x18, 0, page
);
258 usleep_range(1000, 2000); /* wait for the page switch to propagate */
259 lo
= bus
->read(bus
, 0x10 | r2
, r1
);
260 hi
= bus
->read(bus
, 0x10 | r2
, r1
+ 1);
262 mutex_unlock(&bus
->mdio_lock
);
264 return (hi
<< 16) | lo
;
268 ar8216_mii_write(struct ar8216_priv
*priv
, int reg
, u32 val
)
270 struct mii_bus
*bus
= priv
->mii_bus
;
274 split_addr((u32
) reg
, &r1
, &r2
, &r3
);
276 hi
= (u16
) (val
>> 16);
278 mutex_lock(&bus
->mdio_lock
);
280 bus
->write(bus
, 0x18, 0, r3
);
281 usleep_range(1000, 2000); /* wait for the page switch to propagate */
282 if (priv
->mii_lo_first
) {
283 bus
->write(bus
, 0x10 | r2
, r1
, lo
);
284 bus
->write(bus
, 0x10 | r2
, r1
+ 1, hi
);
286 bus
->write(bus
, 0x10 | r2
, r1
+ 1, hi
);
287 bus
->write(bus
, 0x10 | r2
, r1
, lo
);
290 mutex_unlock(&bus
->mdio_lock
);
294 ar8216_phy_dbg_write(struct ar8216_priv
*priv
, int phy_addr
,
295 u16 dbg_addr
, u16 dbg_data
)
297 struct mii_bus
*bus
= priv
->mii_bus
;
299 mutex_lock(&bus
->mdio_lock
);
300 bus
->write(bus
, phy_addr
, MII_ATH_DBG_ADDR
, dbg_addr
);
301 bus
->write(bus
, phy_addr
, MII_ATH_DBG_DATA
, dbg_data
);
302 mutex_unlock(&bus
->mdio_lock
);
306 ar8216_phy_mmd_write(struct ar8216_priv
*priv
, int phy_addr
, u16 addr
, u16 data
)
308 struct mii_bus
*bus
= priv
->mii_bus
;
310 mutex_lock(&bus
->mdio_lock
);
311 bus
->write(bus
, phy_addr
, MII_ATH_MMD_ADDR
, addr
);
312 bus
->write(bus
, phy_addr
, MII_ATH_MMD_DATA
, data
);
313 mutex_unlock(&bus
->mdio_lock
);
317 ar8216_rmw(struct ar8216_priv
*priv
, int reg
, u32 mask
, u32 val
)
321 lockdep_assert_held(&priv
->reg_mutex
);
323 v
= priv
->read(priv
, reg
);
326 priv
->write(priv
, reg
, v
);
332 ar8216_reg_set(struct ar8216_priv
*priv
, int reg
, u32 val
)
336 lockdep_assert_held(&priv
->reg_mutex
);
338 v
= priv
->read(priv
, reg
);
340 priv
->write(priv
, reg
, v
);
344 ar8216_reg_wait(struct ar8216_priv
*priv
, u32 reg
, u32 mask
, u32 val
,
349 for (i
= 0; i
< timeout
; i
++) {
352 t
= priv
->read(priv
, reg
);
353 if ((t
& mask
) == val
)
356 usleep_range(1000, 2000);
363 ar8216_mib_op(struct ar8216_priv
*priv
, u32 op
)
368 lockdep_assert_held(&priv
->mib_lock
);
370 if (chip_is_ar8327(priv
))
371 mib_func
= AR8327_REG_MIB_FUNC
;
373 mib_func
= AR8216_REG_MIB_FUNC
;
375 mutex_lock(&priv
->reg_mutex
);
376 /* Capture the hardware statistics for all ports */
377 ar8216_rmw(priv
, mib_func
, AR8216_MIB_FUNC
, (op
<< AR8216_MIB_FUNC_S
));
378 mutex_unlock(&priv
->reg_mutex
);
380 /* Wait for the capturing to complete. */
381 ret
= ar8216_reg_wait(priv
, mib_func
, AR8216_MIB_BUSY
, 0, 10);
392 ar8216_mib_capture(struct ar8216_priv
*priv
)
394 return ar8216_mib_op(priv
, AR8216_MIB_FUNC_CAPTURE
);
398 ar8216_mib_flush(struct ar8216_priv
*priv
)
400 return ar8216_mib_op(priv
, AR8216_MIB_FUNC_FLUSH
);
404 ar8216_mib_fetch_port_stat(struct ar8216_priv
*priv
, int port
, bool flush
)
410 WARN_ON(port
>= priv
->dev
.ports
);
412 lockdep_assert_held(&priv
->mib_lock
);
414 if (chip_is_ar8327(priv
))
415 base
= AR8327_REG_PORT_STATS_BASE(port
);
416 else if (chip_is_ar8236(priv
) ||
417 chip_is_ar8316(priv
))
418 base
= AR8236_REG_PORT_STATS_BASE(port
);
420 base
= AR8216_REG_PORT_STATS_BASE(port
);
422 mib_stats
= &priv
->mib_stats
[port
* priv
->chip
->num_mibs
];
423 for (i
= 0; i
< priv
->chip
->num_mibs
; i
++) {
424 const struct ar8xxx_mib_desc
*mib
;
427 mib
= &priv
->chip
->mib_decs
[i
];
428 t
= priv
->read(priv
, base
+ mib
->offset
);
429 if (mib
->size
== 2) {
432 hi
= priv
->read(priv
, base
+ mib
->offset
+ 4);
444 ar8216_read_port_link(struct ar8216_priv
*priv
, int port
,
445 struct switch_port_link
*link
)
450 memset(link
, '\0', sizeof(*link
));
452 status
= priv
->chip
->read_port_status(priv
, port
);
454 link
->aneg
= !!(status
& AR8216_PORT_STATUS_LINK_AUTO
);
456 link
->link
= !!(status
& AR8216_PORT_STATUS_LINK_UP
);
463 link
->duplex
= !!(status
& AR8216_PORT_STATUS_DUPLEX
);
464 link
->tx_flow
= !!(status
& AR8216_PORT_STATUS_TXFLOW
);
465 link
->rx_flow
= !!(status
& AR8216_PORT_STATUS_RXFLOW
);
467 speed
= (status
& AR8216_PORT_STATUS_SPEED
) >>
468 AR8216_PORT_STATUS_SPEED_S
;
471 case AR8216_PORT_SPEED_10M
:
472 link
->speed
= SWITCH_PORT_SPEED_10
;
474 case AR8216_PORT_SPEED_100M
:
475 link
->speed
= SWITCH_PORT_SPEED_100
;
477 case AR8216_PORT_SPEED_1000M
:
478 link
->speed
= SWITCH_PORT_SPEED_1000
;
481 link
->speed
= SWITCH_PORT_SPEED_UNKNOWN
;
486 static struct sk_buff
*
487 ar8216_mangle_tx(struct net_device
*dev
, struct sk_buff
*skb
)
489 struct ar8216_priv
*priv
= dev
->phy_ptr
;
498 if (unlikely(skb_headroom(skb
) < 2)) {
499 if (pskb_expand_head(skb
, 2, 0, GFP_ATOMIC
) < 0)
503 buf
= skb_push(skb
, 2);
511 dev_kfree_skb_any(skb
);
516 ar8216_mangle_rx(struct net_device
*dev
, struct sk_buff
*skb
)
518 struct ar8216_priv
*priv
;
526 /* don't strip the header if vlan mode is disabled */
530 /* strip header, get vlan id */
534 /* check for vlan header presence */
535 if ((buf
[12 + 2] != 0x81) || (buf
[13 + 2] != 0x00))
540 /* no need to fix up packets coming from a tagged source */
541 if (priv
->vlan_tagged
& (1 << port
))
544 /* lookup port vid from local table, the switch passes an invalid vlan id */
545 vlan
= priv
->vlan_id
[priv
->pvid
[port
]];
548 buf
[14 + 2] |= vlan
>> 8;
549 buf
[15 + 2] = vlan
& 0xff;
553 ar8216_wait_bit(struct ar8216_priv
*priv
, int reg
, u32 mask
, u32 val
)
559 t
= priv
->read(priv
, reg
);
560 if ((t
& mask
) == val
)
569 pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
570 (unsigned int) reg
, t
, mask
, val
);
575 ar8216_vtu_op(struct ar8216_priv
*priv
, u32 op
, u32 val
)
577 if (ar8216_wait_bit(priv
, AR8216_REG_VTU
, AR8216_VTU_ACTIVE
, 0))
579 if ((op
& AR8216_VTU_OP
) == AR8216_VTU_OP_LOAD
) {
580 val
&= AR8216_VTUDATA_MEMBER
;
581 val
|= AR8216_VTUDATA_VALID
;
582 priv
->write(priv
, AR8216_REG_VTU_DATA
, val
);
584 op
|= AR8216_VTU_ACTIVE
;
585 priv
->write(priv
, AR8216_REG_VTU
, op
);
589 ar8216_vtu_flush(struct ar8216_priv
*priv
)
591 ar8216_vtu_op(priv
, AR8216_VTU_OP_FLUSH
, 0);
595 ar8216_vtu_load_vlan(struct ar8216_priv
*priv
, u32 vid
, u32 port_mask
)
599 op
= AR8216_VTU_OP_LOAD
| (vid
<< AR8216_VTU_VID_S
);
600 ar8216_vtu_op(priv
, op
, port_mask
);
604 ar8216_atu_flush(struct ar8216_priv
*priv
)
608 ret
= ar8216_wait_bit(priv
, AR8216_REG_ATU
, AR8216_ATU_ACTIVE
, 0);
610 priv
->write(priv
, AR8216_REG_ATU
, AR8216_ATU_OP_FLUSH
);
616 ar8216_read_port_status(struct ar8216_priv
*priv
, int port
)
618 return priv
->read(priv
, AR8216_REG_PORT_STATUS(port
));
622 ar8216_setup_port(struct ar8216_priv
*priv
, int port
, u32 egress
, u32 ingress
,
623 u32 members
, u32 pvid
)
627 if (chip_is_ar8216(priv
) && priv
->vlan
&& port
== AR8216_PORT_CPU
)
628 header
= AR8216_PORT_CTRL_HEADER
;
632 ar8216_rmw(priv
, AR8216_REG_PORT_CTRL(port
),
633 AR8216_PORT_CTRL_LEARN
| AR8216_PORT_CTRL_VLAN_MODE
|
634 AR8216_PORT_CTRL_SINGLE_VLAN
| AR8216_PORT_CTRL_STATE
|
635 AR8216_PORT_CTRL_HEADER
| AR8216_PORT_CTRL_LEARN_LOCK
,
636 AR8216_PORT_CTRL_LEARN
| header
|
637 (egress
<< AR8216_PORT_CTRL_VLAN_MODE_S
) |
638 (AR8216_PORT_STATE_FORWARD
<< AR8216_PORT_CTRL_STATE_S
));
640 ar8216_rmw(priv
, AR8216_REG_PORT_VLAN(port
),
641 AR8216_PORT_VLAN_DEST_PORTS
| AR8216_PORT_VLAN_MODE
|
642 AR8216_PORT_VLAN_DEFAULT_ID
,
643 (members
<< AR8216_PORT_VLAN_DEST_PORTS_S
) |
644 (ingress
<< AR8216_PORT_VLAN_MODE_S
) |
645 (pvid
<< AR8216_PORT_VLAN_DEFAULT_ID_S
));
649 ar8216_hw_init(struct ar8216_priv
*priv
)
655 ar8216_init_globals(struct ar8216_priv
*priv
)
657 /* standard atheros magic */
658 priv
->write(priv
, 0x38, 0xc000050e);
660 ar8216_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
661 AR8216_GCTRL_MTU
, 1518 + 8 + 2);
665 ar8216_init_port(struct ar8216_priv
*priv
, int port
)
667 /* Enable port learning and tx */
668 priv
->write(priv
, AR8216_REG_PORT_CTRL(port
),
669 AR8216_PORT_CTRL_LEARN
|
670 (4 << AR8216_PORT_CTRL_STATE_S
));
672 priv
->write(priv
, AR8216_REG_PORT_VLAN(port
), 0);
674 if (port
== AR8216_PORT_CPU
) {
675 priv
->write(priv
, AR8216_REG_PORT_STATUS(port
),
676 AR8216_PORT_STATUS_LINK_UP
|
677 (ar8xxx_has_gige(priv
) ?
678 AR8216_PORT_SPEED_1000M
: AR8216_PORT_SPEED_100M
) |
679 AR8216_PORT_STATUS_TXMAC
|
680 AR8216_PORT_STATUS_RXMAC
|
681 (chip_is_ar8316(priv
) ? AR8216_PORT_STATUS_RXFLOW
: 0) |
682 (chip_is_ar8316(priv
) ? AR8216_PORT_STATUS_TXFLOW
: 0) |
683 AR8216_PORT_STATUS_DUPLEX
);
685 priv
->write(priv
, AR8216_REG_PORT_STATUS(port
),
686 AR8216_PORT_STATUS_LINK_AUTO
);
690 static const struct ar8xxx_chip ar8216_chip
= {
691 .caps
= AR8XXX_CAP_MIB_COUNTERS
,
693 .hw_init
= ar8216_hw_init
,
694 .init_globals
= ar8216_init_globals
,
695 .init_port
= ar8216_init_port
,
696 .setup_port
= ar8216_setup_port
,
697 .read_port_status
= ar8216_read_port_status
,
698 .atu_flush
= ar8216_atu_flush
,
699 .vtu_flush
= ar8216_vtu_flush
,
700 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
702 .num_mibs
= ARRAY_SIZE(ar8216_mibs
),
703 .mib_decs
= ar8216_mibs
,
707 ar8236_setup_port(struct ar8216_priv
*priv
, int port
, u32 egress
, u32 ingress
,
708 u32 members
, u32 pvid
)
710 ar8216_rmw(priv
, AR8216_REG_PORT_CTRL(port
),
711 AR8216_PORT_CTRL_LEARN
| AR8216_PORT_CTRL_VLAN_MODE
|
712 AR8216_PORT_CTRL_SINGLE_VLAN
| AR8216_PORT_CTRL_STATE
|
713 AR8216_PORT_CTRL_HEADER
| AR8216_PORT_CTRL_LEARN_LOCK
,
714 AR8216_PORT_CTRL_LEARN
|
715 (egress
<< AR8216_PORT_CTRL_VLAN_MODE_S
) |
716 (AR8216_PORT_STATE_FORWARD
<< AR8216_PORT_CTRL_STATE_S
));
718 ar8216_rmw(priv
, AR8236_REG_PORT_VLAN(port
),
719 AR8236_PORT_VLAN_DEFAULT_ID
,
720 (pvid
<< AR8236_PORT_VLAN_DEFAULT_ID_S
));
722 ar8216_rmw(priv
, AR8236_REG_PORT_VLAN2(port
),
723 AR8236_PORT_VLAN2_VLAN_MODE
|
724 AR8236_PORT_VLAN2_MEMBER
,
725 (ingress
<< AR8236_PORT_VLAN2_VLAN_MODE_S
) |
726 (members
<< AR8236_PORT_VLAN2_MEMBER_S
));
730 ar8236_hw_init(struct ar8216_priv
*priv
)
735 if (priv
->initialized
)
738 /* Initialize the PHYs */
740 for (i
= 0; i
< 5; i
++) {
741 mdiobus_write(bus
, i
, MII_ADVERTISE
,
742 ADVERTISE_ALL
| ADVERTISE_PAUSE_CAP
|
743 ADVERTISE_PAUSE_ASYM
);
744 mdiobus_write(bus
, i
, MII_BMCR
, BMCR_RESET
| BMCR_ANENABLE
);
748 priv
->initialized
= true;
753 ar8236_init_globals(struct ar8216_priv
*priv
)
755 /* enable jumbo frames */
756 ar8216_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
757 AR8316_GCTRL_MTU
, 9018 + 8 + 2);
759 /* Enable MIB counters */
760 ar8216_rmw(priv
, AR8216_REG_MIB_FUNC
, AR8216_MIB_FUNC
| AR8236_MIB_EN
,
761 (AR8216_MIB_FUNC_NO_OP
<< AR8216_MIB_FUNC_S
) |
765 static const struct ar8xxx_chip ar8236_chip
= {
766 .caps
= AR8XXX_CAP_MIB_COUNTERS
,
767 .hw_init
= ar8236_hw_init
,
768 .init_globals
= ar8236_init_globals
,
769 .init_port
= ar8216_init_port
,
770 .setup_port
= ar8236_setup_port
,
771 .read_port_status
= ar8216_read_port_status
,
772 .atu_flush
= ar8216_atu_flush
,
773 .vtu_flush
= ar8216_vtu_flush
,
774 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
776 .num_mibs
= ARRAY_SIZE(ar8236_mibs
),
777 .mib_decs
= ar8236_mibs
,
781 ar8316_hw_init(struct ar8216_priv
*priv
)
787 val
= priv
->read(priv
, 0x8);
789 if (priv
->phy
->interface
== PHY_INTERFACE_MODE_RGMII
) {
790 if (priv
->port4_phy
) {
791 /* value taken from Ubiquiti RouterStation Pro */
793 printk(KERN_INFO
"ar8316: Using port 4 as PHY\n");
796 printk(KERN_INFO
"ar8316: Using port 4 as switch port\n");
798 } else if (priv
->phy
->interface
== PHY_INTERFACE_MODE_GMII
) {
799 /* value taken from AVM Fritz!Box 7390 sources */
802 /* no known value for phy interface */
803 printk(KERN_ERR
"ar8316: unsupported mii mode: %d.\n",
804 priv
->phy
->interface
);
811 priv
->write(priv
, 0x8, newval
);
813 /* Initialize the ports */
815 for (i
= 0; i
< 5; i
++) {
816 if ((i
== 4) && priv
->port4_phy
&&
817 priv
->phy
->interface
== PHY_INTERFACE_MODE_RGMII
) {
818 /* work around for phy4 rgmii mode */
819 ar8216_phy_dbg_write(priv
, i
, 0x12, 0x480c);
821 ar8216_phy_dbg_write(priv
, i
, 0x0, 0x824e);
823 ar8216_phy_dbg_write(priv
, i
, 0x5, 0x3d47);
827 /* initialize the port itself */
828 mdiobus_write(bus
, i
, MII_ADVERTISE
,
829 ADVERTISE_ALL
| ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
);
830 mdiobus_write(bus
, i
, MII_CTRL1000
, ADVERTISE_1000FULL
);
831 mdiobus_write(bus
, i
, MII_BMCR
, BMCR_RESET
| BMCR_ANENABLE
);
836 priv
->initialized
= true;
841 ar8316_init_globals(struct ar8216_priv
*priv
)
843 /* standard atheros magic */
844 priv
->write(priv
, 0x38, 0xc000050e);
846 /* enable cpu port to receive multicast and broadcast frames */
847 priv
->write(priv
, AR8216_REG_FLOOD_MASK
, 0x003f003f);
849 /* enable jumbo frames */
850 ar8216_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
851 AR8316_GCTRL_MTU
, 9018 + 8 + 2);
853 /* Enable MIB counters */
854 ar8216_rmw(priv
, AR8216_REG_MIB_FUNC
, AR8216_MIB_FUNC
| AR8236_MIB_EN
,
855 (AR8216_MIB_FUNC_NO_OP
<< AR8216_MIB_FUNC_S
) |
859 static const struct ar8xxx_chip ar8316_chip
= {
860 .caps
= AR8XXX_CAP_GIGE
| AR8XXX_CAP_MIB_COUNTERS
,
861 .hw_init
= ar8316_hw_init
,
862 .init_globals
= ar8316_init_globals
,
863 .init_port
= ar8216_init_port
,
864 .setup_port
= ar8216_setup_port
,
865 .read_port_status
= ar8216_read_port_status
,
866 .atu_flush
= ar8216_atu_flush
,
867 .vtu_flush
= ar8216_vtu_flush
,
868 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
870 .num_mibs
= ARRAY_SIZE(ar8236_mibs
),
871 .mib_decs
= ar8236_mibs
,
875 ar8327_get_pad_cfg(struct ar8327_pad_cfg
*cfg
)
887 case AR8327_PAD_MAC2MAC_MII
:
888 t
= AR8327_PAD_MAC_MII_EN
;
890 t
|= AR8327_PAD_MAC_MII_RXCLK_SEL
;
892 t
|= AR8327_PAD_MAC_MII_TXCLK_SEL
;
895 case AR8327_PAD_MAC2MAC_GMII
:
896 t
= AR8327_PAD_MAC_GMII_EN
;
898 t
|= AR8327_PAD_MAC_GMII_RXCLK_SEL
;
900 t
|= AR8327_PAD_MAC_GMII_TXCLK_SEL
;
903 case AR8327_PAD_MAC_SGMII
:
904 t
= AR8327_PAD_SGMII_EN
;
907 * WAR for the QUalcomm Atheros AP136 board.
908 * It seems that RGMII TX/RX delay settings needs to be
909 * applied for SGMII mode as well, The ethernet is not
910 * reliable without this.
912 t
|= cfg
->txclk_delay_sel
<< AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S
;
913 t
|= cfg
->rxclk_delay_sel
<< AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S
;
914 if (cfg
->rxclk_delay_en
)
915 t
|= AR8327_PAD_RGMII_RXCLK_DELAY_EN
;
916 if (cfg
->txclk_delay_en
)
917 t
|= AR8327_PAD_RGMII_TXCLK_DELAY_EN
;
919 if (cfg
->sgmii_delay_en
)
920 t
|= AR8327_PAD_SGMII_DELAY_EN
;
924 case AR8327_PAD_MAC2PHY_MII
:
925 t
= AR8327_PAD_PHY_MII_EN
;
927 t
|= AR8327_PAD_PHY_MII_RXCLK_SEL
;
929 t
|= AR8327_PAD_PHY_MII_TXCLK_SEL
;
932 case AR8327_PAD_MAC2PHY_GMII
:
933 t
= AR8327_PAD_PHY_GMII_EN
;
934 if (cfg
->pipe_rxclk_sel
)
935 t
|= AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL
;
937 t
|= AR8327_PAD_PHY_GMII_RXCLK_SEL
;
939 t
|= AR8327_PAD_PHY_GMII_TXCLK_SEL
;
942 case AR8327_PAD_MAC_RGMII
:
943 t
= AR8327_PAD_RGMII_EN
;
944 t
|= cfg
->txclk_delay_sel
<< AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S
;
945 t
|= cfg
->rxclk_delay_sel
<< AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S
;
946 if (cfg
->rxclk_delay_en
)
947 t
|= AR8327_PAD_RGMII_RXCLK_DELAY_EN
;
948 if (cfg
->txclk_delay_en
)
949 t
|= AR8327_PAD_RGMII_TXCLK_DELAY_EN
;
952 case AR8327_PAD_PHY_GMII
:
953 t
= AR8327_PAD_PHYX_GMII_EN
;
956 case AR8327_PAD_PHY_RGMII
:
957 t
= AR8327_PAD_PHYX_RGMII_EN
;
960 case AR8327_PAD_PHY_MII
:
961 t
= AR8327_PAD_PHYX_MII_EN
;
969 ar8327_phy_fixup(struct ar8216_priv
*priv
, int phy
)
971 switch (priv
->chip_rev
) {
973 /* For 100M waveform */
974 ar8216_phy_dbg_write(priv
, phy
, 0, 0x02ea);
975 /* Turn on Gigabit clock */
976 ar8216_phy_dbg_write(priv
, phy
, 0x3d, 0x68a0);
980 ar8216_phy_mmd_write(priv
, phy
, 0x7, 0x3c);
981 ar8216_phy_mmd_write(priv
, phy
, 0x4007, 0x0);
984 ar8216_phy_mmd_write(priv
, phy
, 0x3, 0x800d);
985 ar8216_phy_mmd_write(priv
, phy
, 0x4003, 0x803f);
987 ar8216_phy_dbg_write(priv
, phy
, 0x3d, 0x6860);
988 ar8216_phy_dbg_write(priv
, phy
, 0x5, 0x2c46);
989 ar8216_phy_dbg_write(priv
, phy
, 0x3c, 0x6000);
995 ar8327_hw_init(struct ar8216_priv
*priv
)
997 struct ar8327_platform_data
*pdata
;
998 struct ar8327_led_cfg
*led_cfg
;
1004 pdata
= priv
->phy
->dev
.platform_data
;
1008 t
= ar8327_get_pad_cfg(pdata
->pad0_cfg
);
1009 priv
->write(priv
, AR8327_REG_PAD0_MODE
, t
);
1010 t
= ar8327_get_pad_cfg(pdata
->pad5_cfg
);
1011 priv
->write(priv
, AR8327_REG_PAD5_MODE
, t
);
1012 t
= ar8327_get_pad_cfg(pdata
->pad6_cfg
);
1013 priv
->write(priv
, AR8327_REG_PAD6_MODE
, t
);
1015 pos
= priv
->read(priv
, AR8327_REG_POWER_ON_STRIP
);
1018 led_cfg
= pdata
->led_cfg
;
1020 if (led_cfg
->open_drain
)
1021 new_pos
|= AR8327_POWER_ON_STRIP_LED_OPEN_EN
;
1023 new_pos
&= ~AR8327_POWER_ON_STRIP_LED_OPEN_EN
;
1025 priv
->write(priv
, AR8327_REG_LED_CTRL0
, led_cfg
->led_ctrl0
);
1026 priv
->write(priv
, AR8327_REG_LED_CTRL1
, led_cfg
->led_ctrl1
);
1027 priv
->write(priv
, AR8327_REG_LED_CTRL2
, led_cfg
->led_ctrl2
);
1028 priv
->write(priv
, AR8327_REG_LED_CTRL3
, led_cfg
->led_ctrl3
);
1031 if (new_pos
!= pos
) {
1032 new_pos
|= AR8327_POWER_ON_STRIP_POWER_ON_SEL
;
1033 priv
->write(priv
, AR8327_REG_POWER_ON_STRIP
, new_pos
);
1036 bus
= priv
->mii_bus
;
1037 for (i
= 0; i
< AR8327_NUM_PHYS
; i
++) {
1038 ar8327_phy_fixup(priv
, i
);
1040 /* start aneg on the PHY */
1041 mdiobus_write(bus
, i
, MII_ADVERTISE
, ADVERTISE_ALL
|
1042 ADVERTISE_PAUSE_CAP
|
1043 ADVERTISE_PAUSE_ASYM
);
1044 mdiobus_write(bus
, i
, MII_CTRL1000
, ADVERTISE_1000FULL
);
1045 mdiobus_write(bus
, i
, MII_BMCR
, BMCR_RESET
| BMCR_ANENABLE
);
1054 ar8327_init_globals(struct ar8216_priv
*priv
)
1058 /* enable CPU port and disable mirror port */
1059 t
= AR8327_FWD_CTRL0_CPU_PORT_EN
|
1060 AR8327_FWD_CTRL0_MIRROR_PORT
;
1061 priv
->write(priv
, AR8327_REG_FWD_CTRL0
, t
);
1063 /* forward multicast and broadcast frames to CPU */
1064 t
= (AR8327_PORTS_ALL
<< AR8327_FWD_CTRL1_UC_FLOOD_S
) |
1065 (AR8327_PORTS_ALL
<< AR8327_FWD_CTRL1_MC_FLOOD_S
) |
1066 (AR8327_PORTS_ALL
<< AR8327_FWD_CTRL1_BC_FLOOD_S
);
1067 priv
->write(priv
, AR8327_REG_FWD_CTRL1
, t
);
1070 ar8216_rmw(priv
, AR8327_REG_MAX_FRAME_SIZE
,
1071 AR8327_MAX_FRAME_SIZE_MTU
, 1518 + 8 + 2);
1073 /* Enable MIB counters */
1074 ar8216_reg_set(priv
, AR8327_REG_MODULE_EN
,
1075 AR8327_MODULE_EN_MIB
);
1079 ar8327_config_port(struct ar8216_priv
*priv
, unsigned int port
,
1080 struct ar8327_port_cfg
*cfg
)
1084 if (!cfg
|| !cfg
->force_link
) {
1085 priv
->write(priv
, AR8327_REG_PORT_STATUS(port
),
1086 AR8216_PORT_STATUS_LINK_AUTO
);
1090 t
= AR8216_PORT_STATUS_TXMAC
| AR8216_PORT_STATUS_RXMAC
;
1091 t
|= cfg
->duplex
? AR8216_PORT_STATUS_DUPLEX
: 0;
1092 t
|= cfg
->rxpause
? AR8216_PORT_STATUS_RXFLOW
: 0;
1093 t
|= cfg
->txpause
? AR8216_PORT_STATUS_TXFLOW
: 0;
1095 switch (cfg
->speed
) {
1096 case AR8327_PORT_SPEED_10
:
1097 t
|= AR8216_PORT_SPEED_10M
;
1099 case AR8327_PORT_SPEED_100
:
1100 t
|= AR8216_PORT_SPEED_100M
;
1102 case AR8327_PORT_SPEED_1000
:
1103 t
|= AR8216_PORT_SPEED_1000M
;
1107 priv
->write(priv
, AR8327_REG_PORT_STATUS(port
), t
);
1111 ar8327_init_port(struct ar8216_priv
*priv
, int port
)
1113 struct ar8327_platform_data
*pdata
;
1114 struct ar8327_port_cfg
*cfg
;
1117 pdata
= priv
->phy
->dev
.platform_data
;
1119 if (pdata
&& port
== AR8216_PORT_CPU
)
1120 cfg
= &pdata
->port0_cfg
;
1121 else if (pdata
&& port
== 6)
1122 cfg
= &pdata
->port6_cfg
;
1126 ar8327_config_port(priv
, port
, cfg
);
1128 priv
->write(priv
, AR8327_REG_PORT_HEADER(port
), 0);
1130 t
= 1 << AR8327_PORT_VLAN0_DEF_SVID_S
;
1131 t
|= 1 << AR8327_PORT_VLAN0_DEF_CVID_S
;
1132 priv
->write(priv
, AR8327_REG_PORT_VLAN0(port
), t
);
1134 t
= AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH
<< AR8327_PORT_VLAN1_OUT_MODE_S
;
1135 priv
->write(priv
, AR8327_REG_PORT_VLAN1(port
), t
);
1137 t
= AR8327_PORT_LOOKUP_LEARN
;
1138 t
|= AR8216_PORT_STATE_FORWARD
<< AR8327_PORT_LOOKUP_STATE_S
;
1139 priv
->write(priv
, AR8327_REG_PORT_LOOKUP(port
), t
);
1143 ar8327_read_port_status(struct ar8216_priv
*priv
, int port
)
1145 return priv
->read(priv
, AR8327_REG_PORT_STATUS(port
));
1149 ar8327_atu_flush(struct ar8216_priv
*priv
)
1153 ret
= ar8216_wait_bit(priv
, AR8327_REG_ATU_FUNC
,
1154 AR8327_ATU_FUNC_BUSY
, 0);
1156 priv
->write(priv
, AR8327_REG_ATU_FUNC
,
1157 AR8327_ATU_FUNC_OP_FLUSH
);
1163 ar8327_vtu_op(struct ar8216_priv
*priv
, u32 op
, u32 val
)
1165 if (ar8216_wait_bit(priv
, AR8327_REG_VTU_FUNC1
,
1166 AR8327_VTU_FUNC1_BUSY
, 0))
1169 if ((op
& AR8327_VTU_FUNC1_OP
) == AR8327_VTU_FUNC1_OP_LOAD
)
1170 priv
->write(priv
, AR8327_REG_VTU_FUNC0
, val
);
1172 op
|= AR8327_VTU_FUNC1_BUSY
;
1173 priv
->write(priv
, AR8327_REG_VTU_FUNC1
, op
);
1177 ar8327_vtu_flush(struct ar8216_priv
*priv
)
1179 ar8327_vtu_op(priv
, AR8327_VTU_FUNC1_OP_FLUSH
, 0);
1183 ar8327_vtu_load_vlan(struct ar8216_priv
*priv
, u32 vid
, u32 port_mask
)
1189 op
= AR8327_VTU_FUNC1_OP_LOAD
| (vid
<< AR8327_VTU_FUNC1_VID_S
);
1190 val
= AR8327_VTU_FUNC0_VALID
| AR8327_VTU_FUNC0_IVL
;
1191 for (i
= 0; i
< AR8327_NUM_PORTS
; i
++) {
1194 if ((port_mask
& BIT(i
)) == 0)
1195 mode
= AR8327_VTU_FUNC0_EG_MODE_NOT
;
1196 else if (priv
->vlan
== 0)
1197 mode
= AR8327_VTU_FUNC0_EG_MODE_KEEP
;
1198 else if (priv
->vlan_tagged
& BIT(i
))
1199 mode
= AR8327_VTU_FUNC0_EG_MODE_TAG
;
1201 mode
= AR8327_VTU_FUNC0_EG_MODE_UNTAG
;
1203 val
|= mode
<< AR8327_VTU_FUNC0_EG_MODE_S(i
);
1205 ar8327_vtu_op(priv
, op
, val
);
1209 ar8327_setup_port(struct ar8216_priv
*priv
, int port
, u32 egress
, u32 ingress
,
1210 u32 members
, u32 pvid
)
1215 t
= pvid
<< AR8327_PORT_VLAN0_DEF_SVID_S
;
1216 t
|= pvid
<< AR8327_PORT_VLAN0_DEF_CVID_S
;
1217 priv
->write(priv
, AR8327_REG_PORT_VLAN0(port
), t
);
1219 mode
= AR8327_PORT_VLAN1_OUT_MODE_UNMOD
;
1221 case AR8216_OUT_KEEP
:
1222 mode
= AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH
;
1224 case AR8216_OUT_STRIP_VLAN
:
1225 mode
= AR8327_PORT_VLAN1_OUT_MODE_UNTAG
;
1227 case AR8216_OUT_ADD_VLAN
:
1228 mode
= AR8327_PORT_VLAN1_OUT_MODE_TAG
;
1232 t
= AR8327_PORT_VLAN1_PORT_VLAN_PROP
;
1233 t
|= mode
<< AR8327_PORT_VLAN1_OUT_MODE_S
;
1234 priv
->write(priv
, AR8327_REG_PORT_VLAN1(port
), t
);
1237 t
|= AR8327_PORT_LOOKUP_LEARN
;
1238 t
|= ingress
<< AR8327_PORT_LOOKUP_IN_MODE_S
;
1239 t
|= AR8216_PORT_STATE_FORWARD
<< AR8327_PORT_LOOKUP_STATE_S
;
1240 priv
->write(priv
, AR8327_REG_PORT_LOOKUP(port
), t
);
1243 static const struct ar8xxx_chip ar8327_chip
= {
1244 .caps
= AR8XXX_CAP_GIGE
| AR8XXX_CAP_MIB_COUNTERS
,
1245 .hw_init
= ar8327_hw_init
,
1246 .init_globals
= ar8327_init_globals
,
1247 .init_port
= ar8327_init_port
,
1248 .setup_port
= ar8327_setup_port
,
1249 .read_port_status
= ar8327_read_port_status
,
1250 .atu_flush
= ar8327_atu_flush
,
1251 .vtu_flush
= ar8327_vtu_flush
,
1252 .vtu_load_vlan
= ar8327_vtu_load_vlan
,
1254 .num_mibs
= ARRAY_SIZE(ar8236_mibs
),
1255 .mib_decs
= ar8236_mibs
,
1259 ar8216_sw_set_vlan(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1260 struct switch_val
*val
)
1262 struct ar8216_priv
*priv
= to_ar8216(dev
);
1263 priv
->vlan
= !!val
->value
.i
;
1268 ar8216_sw_get_vlan(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1269 struct switch_val
*val
)
1271 struct ar8216_priv
*priv
= to_ar8216(dev
);
1272 val
->value
.i
= priv
->vlan
;
1278 ar8216_sw_set_pvid(struct switch_dev
*dev
, int port
, int vlan
)
1280 struct ar8216_priv
*priv
= to_ar8216(dev
);
1282 /* make sure no invalid PVIDs get set */
1284 if (vlan
>= dev
->vlans
)
1287 priv
->pvid
[port
] = vlan
;
1292 ar8216_sw_get_pvid(struct switch_dev
*dev
, int port
, int *vlan
)
1294 struct ar8216_priv
*priv
= to_ar8216(dev
);
1295 *vlan
= priv
->pvid
[port
];
1300 ar8216_sw_set_vid(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1301 struct switch_val
*val
)
1303 struct ar8216_priv
*priv
= to_ar8216(dev
);
1304 priv
->vlan_id
[val
->port_vlan
] = val
->value
.i
;
1309 ar8216_sw_get_vid(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1310 struct switch_val
*val
)
1312 struct ar8216_priv
*priv
= to_ar8216(dev
);
1313 val
->value
.i
= priv
->vlan_id
[val
->port_vlan
];
1318 ar8216_sw_get_port_link(struct switch_dev
*dev
, int port
,
1319 struct switch_port_link
*link
)
1321 struct ar8216_priv
*priv
= to_ar8216(dev
);
1323 ar8216_read_port_link(priv
, port
, link
);
1328 ar8216_sw_get_ports(struct switch_dev
*dev
, struct switch_val
*val
)
1330 struct ar8216_priv
*priv
= to_ar8216(dev
);
1331 u8 ports
= priv
->vlan_table
[val
->port_vlan
];
1335 for (i
= 0; i
< dev
->ports
; i
++) {
1336 struct switch_port
*p
;
1338 if (!(ports
& (1 << i
)))
1341 p
= &val
->value
.ports
[val
->len
++];
1343 if (priv
->vlan_tagged
& (1 << i
))
1344 p
->flags
= (1 << SWITCH_PORT_FLAG_TAGGED
);
1352 ar8216_sw_set_ports(struct switch_dev
*dev
, struct switch_val
*val
)
1354 struct ar8216_priv
*priv
= to_ar8216(dev
);
1355 u8
*vt
= &priv
->vlan_table
[val
->port_vlan
];
1359 for (i
= 0; i
< val
->len
; i
++) {
1360 struct switch_port
*p
= &val
->value
.ports
[i
];
1362 if (p
->flags
& (1 << SWITCH_PORT_FLAG_TAGGED
)) {
1363 priv
->vlan_tagged
|= (1 << p
->id
);
1365 priv
->vlan_tagged
&= ~(1 << p
->id
);
1366 priv
->pvid
[p
->id
] = val
->port_vlan
;
1368 /* make sure that an untagged port does not
1369 * appear in other vlans */
1370 for (j
= 0; j
< AR8X16_MAX_VLANS
; j
++) {
1371 if (j
== val
->port_vlan
)
1373 priv
->vlan_table
[j
] &= ~(1 << p
->id
);
1383 ar8216_sw_hw_apply(struct switch_dev
*dev
)
1385 struct ar8216_priv
*priv
= to_ar8216(dev
);
1386 u8 portmask
[AR8X16_MAX_PORTS
];
1389 mutex_lock(&priv
->reg_mutex
);
1390 /* flush all vlan translation unit entries */
1391 priv
->chip
->vtu_flush(priv
);
1393 memset(portmask
, 0, sizeof(portmask
));
1395 /* calculate the port destination masks and load vlans
1396 * into the vlan translation unit */
1397 for (j
= 0; j
< AR8X16_MAX_VLANS
; j
++) {
1398 u8 vp
= priv
->vlan_table
[j
];
1403 for (i
= 0; i
< dev
->ports
; i
++) {
1406 portmask
[i
] |= vp
& ~mask
;
1409 priv
->chip
->vtu_load_vlan(priv
, priv
->vlan_id
[j
],
1410 priv
->vlan_table
[j
]);
1414 * isolate all ports, but connect them to the cpu port */
1415 for (i
= 0; i
< dev
->ports
; i
++) {
1416 if (i
== AR8216_PORT_CPU
)
1419 portmask
[i
] = 1 << AR8216_PORT_CPU
;
1420 portmask
[AR8216_PORT_CPU
] |= (1 << i
);
1424 /* update the port destination mask registers and tag settings */
1425 for (i
= 0; i
< dev
->ports
; i
++) {
1426 int egress
, ingress
;
1430 pvid
= priv
->vlan_id
[priv
->pvid
[i
]];
1431 if (priv
->vlan_tagged
& (1 << i
))
1432 egress
= AR8216_OUT_ADD_VLAN
;
1434 egress
= AR8216_OUT_STRIP_VLAN
;
1435 ingress
= AR8216_IN_SECURE
;
1438 egress
= AR8216_OUT_KEEP
;
1439 ingress
= AR8216_IN_PORT_ONLY
;
1442 priv
->chip
->setup_port(priv
, i
, egress
, ingress
, portmask
[i
],
1445 mutex_unlock(&priv
->reg_mutex
);
1450 ar8216_sw_reset_switch(struct switch_dev
*dev
)
1452 struct ar8216_priv
*priv
= to_ar8216(dev
);
1455 mutex_lock(&priv
->reg_mutex
);
1456 memset(&priv
->vlan
, 0, sizeof(struct ar8216_priv
) -
1457 offsetof(struct ar8216_priv
, vlan
));
1459 for (i
= 0; i
< AR8X16_MAX_VLANS
; i
++)
1460 priv
->vlan_id
[i
] = i
;
1462 /* Configure all ports */
1463 for (i
= 0; i
< dev
->ports
; i
++)
1464 priv
->chip
->init_port(priv
, i
);
1466 priv
->chip
->init_globals(priv
);
1467 mutex_unlock(&priv
->reg_mutex
);
1469 return ar8216_sw_hw_apply(dev
);
1473 ar8216_sw_set_reset_mibs(struct switch_dev
*dev
,
1474 const struct switch_attr
*attr
,
1475 struct switch_val
*val
)
1477 struct ar8216_priv
*priv
= to_ar8216(dev
);
1481 if (!ar8xxx_has_mib_counters(priv
))
1484 mutex_lock(&priv
->mib_lock
);
1486 len
= priv
->dev
.ports
* priv
->chip
->num_mibs
*
1487 sizeof(*priv
->mib_stats
);
1488 memset(priv
->mib_stats
, '\0', len
);
1489 ret
= ar8216_mib_flush(priv
);
1496 mutex_unlock(&priv
->mib_lock
);
1501 ar8216_sw_set_port_reset_mib(struct switch_dev
*dev
,
1502 const struct switch_attr
*attr
,
1503 struct switch_val
*val
)
1505 struct ar8216_priv
*priv
= to_ar8216(dev
);
1509 if (!ar8xxx_has_mib_counters(priv
))
1512 port
= val
->port_vlan
;
1513 if (port
>= dev
->ports
)
1516 mutex_lock(&priv
->mib_lock
);
1517 ret
= ar8216_mib_capture(priv
);
1521 ar8216_mib_fetch_port_stat(priv
, port
, true);
1526 mutex_unlock(&priv
->mib_lock
);
1531 ar8216_sw_get_port_mib(struct switch_dev
*dev
,
1532 const struct switch_attr
*attr
,
1533 struct switch_val
*val
)
1535 struct ar8216_priv
*priv
= to_ar8216(dev
);
1536 const struct ar8xxx_chip
*chip
= priv
->chip
;
1540 char *buf
= priv
->buf
;
1543 if (!ar8xxx_has_mib_counters(priv
))
1546 port
= val
->port_vlan
;
1547 if (port
>= dev
->ports
)
1550 mutex_lock(&priv
->mib_lock
);
1551 ret
= ar8216_mib_capture(priv
);
1555 ar8216_mib_fetch_port_stat(priv
, port
, false);
1557 len
+= snprintf(buf
+ len
, sizeof(priv
->buf
) - len
,
1558 "Port %d MIB counters\n",
1561 mib_stats
= &priv
->mib_stats
[port
* chip
->num_mibs
];
1562 for (i
= 0; i
< chip
->num_mibs
; i
++)
1563 len
+= snprintf(buf
+ len
, sizeof(priv
->buf
) - len
,
1565 chip
->mib_decs
[i
].name
,
1574 mutex_unlock(&priv
->mib_lock
);
1578 static struct switch_attr ar8216_globals
[] = {
1580 .type
= SWITCH_TYPE_INT
,
1581 .name
= "enable_vlan",
1582 .description
= "Enable VLAN mode",
1583 .set
= ar8216_sw_set_vlan
,
1584 .get
= ar8216_sw_get_vlan
,
1588 .type
= SWITCH_TYPE_NOVAL
,
1589 .name
= "reset_mibs",
1590 .description
= "Reset all MIB counters",
1591 .set
= ar8216_sw_set_reset_mibs
,
1596 static struct switch_attr ar8216_port
[] = {
1598 .type
= SWITCH_TYPE_NOVAL
,
1599 .name
= "reset_mib",
1600 .description
= "Reset single port MIB counters",
1601 .set
= ar8216_sw_set_port_reset_mib
,
1604 .type
= SWITCH_TYPE_STRING
,
1606 .description
= "Get port's MIB counters",
1608 .get
= ar8216_sw_get_port_mib
,
1612 static struct switch_attr ar8216_vlan
[] = {
1614 .type
= SWITCH_TYPE_INT
,
1616 .description
= "VLAN ID (0-4094)",
1617 .set
= ar8216_sw_set_vid
,
1618 .get
= ar8216_sw_get_vid
,
1623 static const struct switch_dev_ops ar8216_sw_ops
= {
1625 .attr
= ar8216_globals
,
1626 .n_attr
= ARRAY_SIZE(ar8216_globals
),
1629 .attr
= ar8216_port
,
1630 .n_attr
= ARRAY_SIZE(ar8216_port
),
1633 .attr
= ar8216_vlan
,
1634 .n_attr
= ARRAY_SIZE(ar8216_vlan
),
1636 .get_port_pvid
= ar8216_sw_get_pvid
,
1637 .set_port_pvid
= ar8216_sw_set_pvid
,
1638 .get_vlan_ports
= ar8216_sw_get_ports
,
1639 .set_vlan_ports
= ar8216_sw_set_ports
,
1640 .apply_config
= ar8216_sw_hw_apply
,
1641 .reset_switch
= ar8216_sw_reset_switch
,
1642 .get_port_link
= ar8216_sw_get_port_link
,
1646 ar8216_id_chip(struct ar8216_priv
*priv
)
1652 val
= ar8216_mii_read(priv
, AR8216_REG_CTRL
);
1656 id
= val
& (AR8216_CTRL_REVISION
| AR8216_CTRL_VERSION
);
1657 for (i
= 0; i
< AR8X16_PROBE_RETRIES
; i
++) {
1660 val
= ar8216_mii_read(priv
, AR8216_REG_CTRL
);
1664 t
= val
& (AR8216_CTRL_REVISION
| AR8216_CTRL_VERSION
);
1669 priv
->chip_ver
= (id
& AR8216_CTRL_VERSION
) >> AR8216_CTRL_VERSION_S
;
1670 priv
->chip_rev
= (id
& AR8216_CTRL_REVISION
);
1672 switch (priv
->chip_ver
) {
1673 case AR8XXX_VER_AR8216
:
1674 priv
->chip
= &ar8216_chip
;
1676 case AR8XXX_VER_AR8236
:
1677 priv
->chip
= &ar8236_chip
;
1679 case AR8XXX_VER_AR8316
:
1680 priv
->chip
= &ar8316_chip
;
1682 case AR8XXX_VER_AR8327
:
1683 priv
->mii_lo_first
= true;
1684 priv
->chip
= &ar8327_chip
;
1688 "ar8216: Unknown Atheros device [ver=%d, rev=%d, phy_id=%04x%04x]\n",
1689 priv
->chip_ver
, priv
->chip_rev
,
1690 mdiobus_read(priv
->mii_bus
, priv
->phy
->addr
, 2),
1691 mdiobus_read(priv
->mii_bus
, priv
->phy
->addr
, 3));
1700 ar8xxx_mib_work_func(struct work_struct
*work
)
1702 struct ar8216_priv
*priv
;
1705 priv
= container_of(work
, struct ar8216_priv
, mib_work
.work
);
1707 mutex_lock(&priv
->mib_lock
);
1709 err
= ar8216_mib_capture(priv
);
1713 ar8216_mib_fetch_port_stat(priv
, priv
->mib_next_port
, false);
1716 priv
->mib_next_port
++;
1717 if (priv
->mib_next_port
>= priv
->dev
.ports
)
1718 priv
->mib_next_port
= 0;
1720 mutex_unlock(&priv
->mib_lock
);
1721 schedule_delayed_work(&priv
->mib_work
,
1722 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY
));
1726 ar8xxx_mib_init(struct ar8216_priv
*priv
)
1730 if (!ar8xxx_has_mib_counters(priv
))
1733 BUG_ON(!priv
->chip
->mib_decs
|| !priv
->chip
->num_mibs
);
1735 len
= priv
->dev
.ports
* priv
->chip
->num_mibs
*
1736 sizeof(*priv
->mib_stats
);
1737 priv
->mib_stats
= kzalloc(len
, GFP_KERNEL
);
1739 if (!priv
->mib_stats
)
1742 mutex_init(&priv
->mib_lock
);
1743 INIT_DELAYED_WORK(&priv
->mib_work
, ar8xxx_mib_work_func
);
1749 ar8xxx_mib_start(struct ar8216_priv
*priv
)
1751 if (!ar8xxx_has_mib_counters(priv
))
1754 schedule_delayed_work(&priv
->mib_work
,
1755 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY
));
1759 ar8xxx_mib_cleanup(struct ar8216_priv
*priv
)
1761 if (!ar8xxx_has_mib_counters(priv
))
1764 cancel_delayed_work(&priv
->mib_work
);
1765 kfree(priv
->mib_stats
);
1769 ar8216_config_init(struct phy_device
*pdev
)
1771 struct ar8216_priv
*priv
= pdev
->priv
;
1772 struct net_device
*dev
= pdev
->attached_dev
;
1773 struct switch_dev
*swdev
;
1777 priv
= kzalloc(sizeof(struct ar8216_priv
), GFP_KERNEL
);
1782 priv
->mii_bus
= pdev
->bus
;
1785 ret
= ar8216_id_chip(priv
);
1789 if (pdev
->addr
!= 0) {
1790 if (ar8xxx_has_gige(priv
)) {
1791 pdev
->supported
|= SUPPORTED_1000baseT_Full
;
1792 pdev
->advertising
|= ADVERTISED_1000baseT_Full
;
1795 if (chip_is_ar8316(priv
)) {
1796 /* check if we're attaching to the switch twice */
1797 pdev
= pdev
->bus
->phy_map
[0];
1803 /* switch device has not been initialized, reuse priv */
1805 priv
->port4_phy
= true;
1812 /* switch device has been initialized, reinit */
1814 priv
->dev
.ports
= (AR8216_NUM_PORTS
- 1);
1815 priv
->initialized
= false;
1816 priv
->port4_phy
= true;
1817 ar8316_hw_init(priv
);
1825 if (ar8xxx_has_gige(priv
))
1826 pdev
->supported
= SUPPORTED_1000baseT_Full
;
1828 pdev
->supported
= SUPPORTED_100baseT_Full
;
1829 pdev
->advertising
= pdev
->supported
;
1831 mutex_init(&priv
->reg_mutex
);
1832 priv
->read
= ar8216_mii_read
;
1833 priv
->write
= ar8216_mii_write
;
1838 swdev
->cpu_port
= AR8216_PORT_CPU
;
1839 swdev
->ops
= &ar8216_sw_ops
;
1840 swdev
->ports
= AR8216_NUM_PORTS
;
1842 if (chip_is_ar8316(priv
)) {
1843 swdev
->name
= "Atheros AR8316";
1844 swdev
->vlans
= AR8X16_MAX_VLANS
;
1846 if (priv
->port4_phy
) {
1847 /* port 5 connected to the other mac, therefore unusable */
1848 swdev
->ports
= (AR8216_NUM_PORTS
- 1);
1850 } else if (chip_is_ar8236(priv
)) {
1851 swdev
->name
= "Atheros AR8236";
1852 swdev
->vlans
= AR8216_NUM_VLANS
;
1853 swdev
->ports
= AR8216_NUM_PORTS
;
1854 } else if (chip_is_ar8327(priv
)) {
1855 swdev
->name
= "Atheros AR8327";
1856 swdev
->vlans
= AR8X16_MAX_VLANS
;
1857 swdev
->ports
= AR8327_NUM_PORTS
;
1859 swdev
->name
= "Atheros AR8216";
1860 swdev
->vlans
= AR8216_NUM_VLANS
;
1863 ret
= ar8xxx_mib_init(priv
);
1867 ret
= register_switch(swdev
, pdev
->attached_dev
);
1869 goto err_cleanup_mib
;
1871 printk(KERN_INFO
"%s: %s switch driver attached.\n",
1872 pdev
->attached_dev
->name
, swdev
->name
);
1876 ret
= priv
->chip
->hw_init(priv
);
1878 goto err_unregister_switch
;
1880 ret
= ar8216_sw_reset_switch(&priv
->dev
);
1882 goto err_unregister_switch
;
1884 dev
->phy_ptr
= priv
;
1886 /* VID fixup only needed on ar8216 */
1887 if (chip_is_ar8216(priv
) && pdev
->addr
== 0) {
1888 dev
->priv_flags
|= IFF_NO_IP_ALIGN
;
1889 dev
->eth_mangle_rx
= ar8216_mangle_rx
;
1890 dev
->eth_mangle_tx
= ar8216_mangle_tx
;
1895 ar8xxx_mib_start(priv
);
1899 err_unregister_switch
:
1900 unregister_switch(&priv
->dev
);
1902 ar8xxx_mib_cleanup(priv
);
1910 ar8216_read_status(struct phy_device
*phydev
)
1912 struct ar8216_priv
*priv
= phydev
->priv
;
1913 struct switch_port_link link
;
1916 if (phydev
->addr
!= 0)
1917 return genphy_read_status(phydev
);
1919 ar8216_read_port_link(priv
, phydev
->addr
, &link
);
1920 phydev
->link
= !!link
.link
;
1924 switch (link
.speed
) {
1925 case SWITCH_PORT_SPEED_10
:
1926 phydev
->speed
= SPEED_10
;
1928 case SWITCH_PORT_SPEED_100
:
1929 phydev
->speed
= SPEED_100
;
1931 case SWITCH_PORT_SPEED_1000
:
1932 phydev
->speed
= SPEED_1000
;
1937 phydev
->duplex
= link
.duplex
? DUPLEX_FULL
: DUPLEX_HALF
;
1939 /* flush the address translation unit */
1940 mutex_lock(&priv
->reg_mutex
);
1941 ret
= priv
->chip
->atu_flush(priv
);
1942 mutex_unlock(&priv
->reg_mutex
);
1944 phydev
->state
= PHY_RUNNING
;
1945 netif_carrier_on(phydev
->attached_dev
);
1946 phydev
->adjust_link(phydev
->attached_dev
);
1952 ar8216_config_aneg(struct phy_device
*phydev
)
1954 if (phydev
->addr
== 0)
1957 return genphy_config_aneg(phydev
);
1961 ar8216_probe(struct phy_device
*pdev
)
1963 struct ar8216_priv
*priv
;
1966 priv
= kzalloc(sizeof(struct ar8216_priv
), GFP_KERNEL
);
1970 priv
->mii_bus
= pdev
->bus
;
1973 ret
= ar8216_id_chip(priv
);
1980 ar8216_detach(struct phy_device
*pdev
)
1982 struct net_device
*dev
= pdev
->attached_dev
;
1987 dev
->phy_ptr
= NULL
;
1988 dev
->priv_flags
&= ~IFF_NO_IP_ALIGN
;
1989 dev
->eth_mangle_rx
= NULL
;
1990 dev
->eth_mangle_tx
= NULL
;
1994 ar8216_remove(struct phy_device
*pdev
)
1996 struct ar8216_priv
*priv
= pdev
->priv
;
2003 if (pdev
->addr
== 0)
2004 unregister_switch(&priv
->dev
);
2006 ar8xxx_mib_cleanup(priv
);
2010 static struct phy_driver ar8216_driver
= {
2011 .phy_id
= 0x004d0000,
2012 .name
= "Atheros AR8216/AR8236/AR8316",
2013 .phy_id_mask
= 0xffff0000,
2014 .features
= PHY_BASIC_FEATURES
,
2015 .probe
= ar8216_probe
,
2016 .remove
= ar8216_remove
,
2017 .detach
= ar8216_detach
,
2018 .config_init
= &ar8216_config_init
,
2019 .config_aneg
= &ar8216_config_aneg
,
2020 .read_status
= &ar8216_read_status
,
2021 .driver
= { .owner
= THIS_MODULE
},
2027 return phy_driver_register(&ar8216_driver
);
2033 phy_driver_unregister(&ar8216_driver
);
2036 module_init(ar8216_init
);
2037 module_exit(ar8216_exit
);
2038 MODULE_LICENSE("GPL");