2 * ar8216.c: AR8216 switch driver
4 * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/list.h>
22 #include <linux/if_ether.h>
23 #include <linux/skbuff.h>
24 #include <linux/netdevice.h>
25 #include <linux/netlink.h>
26 #include <linux/bitops.h>
27 #include <net/genetlink.h>
28 #include <linux/switch.h>
29 #include <linux/delay.h>
30 #include <linux/phy.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/lockdep.h>
34 #include <linux/ar8216_platform.h>
35 #include <linux/workqueue.h>
36 #include <linux/of_device.h>
37 #include <linux/leds.h>
38 #include <linux/gpio.h>
42 /* size of the vlan table */
43 #define AR8X16_MAX_VLANS 128
44 #define AR8X16_PROBE_RETRIES 10
45 #define AR8X16_MAX_PORTS 8
47 #define AR8XXX_MIB_WORK_DELAY 2000 /* msecs */
51 #define AR8XXX_CAP_GIGE BIT(0)
52 #define AR8XXX_CAP_MIB_COUNTERS BIT(1)
54 #define AR8XXX_NUM_PHYS 5
57 AR8XXX_VER_AR8216
= 0x01,
58 AR8XXX_VER_AR8236
= 0x03,
59 AR8XXX_VER_AR8316
= 0x10,
60 AR8XXX_VER_AR8327
= 0x12,
61 AR8XXX_VER_AR8337
= 0x13,
64 struct ar8xxx_mib_desc
{
73 int (*hw_init
)(struct ar8xxx_priv
*priv
);
74 void (*cleanup
)(struct ar8xxx_priv
*priv
);
76 void (*init_globals
)(struct ar8xxx_priv
*priv
);
77 void (*init_port
)(struct ar8xxx_priv
*priv
, int port
);
78 void (*setup_port
)(struct ar8xxx_priv
*priv
, int port
, u32 members
);
79 u32 (*read_port_status
)(struct ar8xxx_priv
*priv
, int port
);
80 int (*atu_flush
)(struct ar8xxx_priv
*priv
);
81 void (*vtu_flush
)(struct ar8xxx_priv
*priv
);
82 void (*vtu_load_vlan
)(struct ar8xxx_priv
*priv
, u32 vid
, u32 port_mask
);
83 void (*phy_fixup
)(struct ar8xxx_priv
*priv
, int phy
);
85 const struct ar8xxx_mib_desc
*mib_decs
;
89 enum ar8327_led_pattern
{
90 AR8327_LED_PATTERN_OFF
= 0,
91 AR8327_LED_PATTERN_BLINK
,
92 AR8327_LED_PATTERN_ON
,
93 AR8327_LED_PATTERN_RULE
,
96 struct ar8327_led_entry
{
102 struct led_classdev cdev
;
103 struct ar8xxx_priv
*sw_priv
;
108 enum ar8327_led_mode mode
;
112 struct work_struct led_work
;
114 enum ar8327_led_pattern pattern
;
121 struct ar8327_led
**leds
;
122 unsigned int num_leds
;
126 struct switch_dev dev
;
127 struct mii_bus
*mii_bus
;
128 struct phy_device
*phy
;
130 u32 (*read
)(struct ar8xxx_priv
*priv
, int reg
);
131 void (*write
)(struct ar8xxx_priv
*priv
, int reg
, u32 val
);
132 u32 (*rmw
)(struct ar8xxx_priv
*priv
, int reg
, u32 mask
, u32 val
);
134 int (*get_port_link
)(unsigned port
);
136 const struct net_device_ops
*ndo_old
;
137 struct net_device_ops ndo
;
138 struct mutex reg_mutex
;
141 const struct ar8xxx_chip
*chip
;
143 struct ar8327_data ar8327
;
152 struct mutex mib_lock
;
153 struct delayed_work mib_work
;
157 struct list_head list
;
158 unsigned int use_count
;
160 /* all fields below are cleared on reset */
162 u16 vlan_id
[AR8X16_MAX_VLANS
];
163 u8 vlan_table
[AR8X16_MAX_VLANS
];
165 u16 pvid
[AR8X16_MAX_PORTS
];
174 #define MIB_DESC(_s , _o, _n) \
181 static const struct ar8xxx_mib_desc ar8216_mibs
[] = {
182 MIB_DESC(1, AR8216_STATS_RXBROAD
, "RxBroad"),
183 MIB_DESC(1, AR8216_STATS_RXPAUSE
, "RxPause"),
184 MIB_DESC(1, AR8216_STATS_RXMULTI
, "RxMulti"),
185 MIB_DESC(1, AR8216_STATS_RXFCSERR
, "RxFcsErr"),
186 MIB_DESC(1, AR8216_STATS_RXALIGNERR
, "RxAlignErr"),
187 MIB_DESC(1, AR8216_STATS_RXRUNT
, "RxRunt"),
188 MIB_DESC(1, AR8216_STATS_RXFRAGMENT
, "RxFragment"),
189 MIB_DESC(1, AR8216_STATS_RX64BYTE
, "Rx64Byte"),
190 MIB_DESC(1, AR8216_STATS_RX128BYTE
, "Rx128Byte"),
191 MIB_DESC(1, AR8216_STATS_RX256BYTE
, "Rx256Byte"),
192 MIB_DESC(1, AR8216_STATS_RX512BYTE
, "Rx512Byte"),
193 MIB_DESC(1, AR8216_STATS_RX1024BYTE
, "Rx1024Byte"),
194 MIB_DESC(1, AR8216_STATS_RXMAXBYTE
, "RxMaxByte"),
195 MIB_DESC(1, AR8216_STATS_RXTOOLONG
, "RxTooLong"),
196 MIB_DESC(2, AR8216_STATS_RXGOODBYTE
, "RxGoodByte"),
197 MIB_DESC(2, AR8216_STATS_RXBADBYTE
, "RxBadByte"),
198 MIB_DESC(1, AR8216_STATS_RXOVERFLOW
, "RxOverFlow"),
199 MIB_DESC(1, AR8216_STATS_FILTERED
, "Filtered"),
200 MIB_DESC(1, AR8216_STATS_TXBROAD
, "TxBroad"),
201 MIB_DESC(1, AR8216_STATS_TXPAUSE
, "TxPause"),
202 MIB_DESC(1, AR8216_STATS_TXMULTI
, "TxMulti"),
203 MIB_DESC(1, AR8216_STATS_TXUNDERRUN
, "TxUnderRun"),
204 MIB_DESC(1, AR8216_STATS_TX64BYTE
, "Tx64Byte"),
205 MIB_DESC(1, AR8216_STATS_TX128BYTE
, "Tx128Byte"),
206 MIB_DESC(1, AR8216_STATS_TX256BYTE
, "Tx256Byte"),
207 MIB_DESC(1, AR8216_STATS_TX512BYTE
, "Tx512Byte"),
208 MIB_DESC(1, AR8216_STATS_TX1024BYTE
, "Tx1024Byte"),
209 MIB_DESC(1, AR8216_STATS_TXMAXBYTE
, "TxMaxByte"),
210 MIB_DESC(1, AR8216_STATS_TXOVERSIZE
, "TxOverSize"),
211 MIB_DESC(2, AR8216_STATS_TXBYTE
, "TxByte"),
212 MIB_DESC(1, AR8216_STATS_TXCOLLISION
, "TxCollision"),
213 MIB_DESC(1, AR8216_STATS_TXABORTCOL
, "TxAbortCol"),
214 MIB_DESC(1, AR8216_STATS_TXMULTICOL
, "TxMultiCol"),
215 MIB_DESC(1, AR8216_STATS_TXSINGLECOL
, "TxSingleCol"),
216 MIB_DESC(1, AR8216_STATS_TXEXCDEFER
, "TxExcDefer"),
217 MIB_DESC(1, AR8216_STATS_TXDEFER
, "TxDefer"),
218 MIB_DESC(1, AR8216_STATS_TXLATECOL
, "TxLateCol"),
221 static const struct ar8xxx_mib_desc ar8236_mibs
[] = {
222 MIB_DESC(1, AR8236_STATS_RXBROAD
, "RxBroad"),
223 MIB_DESC(1, AR8236_STATS_RXPAUSE
, "RxPause"),
224 MIB_DESC(1, AR8236_STATS_RXMULTI
, "RxMulti"),
225 MIB_DESC(1, AR8236_STATS_RXFCSERR
, "RxFcsErr"),
226 MIB_DESC(1, AR8236_STATS_RXALIGNERR
, "RxAlignErr"),
227 MIB_DESC(1, AR8236_STATS_RXRUNT
, "RxRunt"),
228 MIB_DESC(1, AR8236_STATS_RXFRAGMENT
, "RxFragment"),
229 MIB_DESC(1, AR8236_STATS_RX64BYTE
, "Rx64Byte"),
230 MIB_DESC(1, AR8236_STATS_RX128BYTE
, "Rx128Byte"),
231 MIB_DESC(1, AR8236_STATS_RX256BYTE
, "Rx256Byte"),
232 MIB_DESC(1, AR8236_STATS_RX512BYTE
, "Rx512Byte"),
233 MIB_DESC(1, AR8236_STATS_RX1024BYTE
, "Rx1024Byte"),
234 MIB_DESC(1, AR8236_STATS_RX1518BYTE
, "Rx1518Byte"),
235 MIB_DESC(1, AR8236_STATS_RXMAXBYTE
, "RxMaxByte"),
236 MIB_DESC(1, AR8236_STATS_RXTOOLONG
, "RxTooLong"),
237 MIB_DESC(2, AR8236_STATS_RXGOODBYTE
, "RxGoodByte"),
238 MIB_DESC(2, AR8236_STATS_RXBADBYTE
, "RxBadByte"),
239 MIB_DESC(1, AR8236_STATS_RXOVERFLOW
, "RxOverFlow"),
240 MIB_DESC(1, AR8236_STATS_FILTERED
, "Filtered"),
241 MIB_DESC(1, AR8236_STATS_TXBROAD
, "TxBroad"),
242 MIB_DESC(1, AR8236_STATS_TXPAUSE
, "TxPause"),
243 MIB_DESC(1, AR8236_STATS_TXMULTI
, "TxMulti"),
244 MIB_DESC(1, AR8236_STATS_TXUNDERRUN
, "TxUnderRun"),
245 MIB_DESC(1, AR8236_STATS_TX64BYTE
, "Tx64Byte"),
246 MIB_DESC(1, AR8236_STATS_TX128BYTE
, "Tx128Byte"),
247 MIB_DESC(1, AR8236_STATS_TX256BYTE
, "Tx256Byte"),
248 MIB_DESC(1, AR8236_STATS_TX512BYTE
, "Tx512Byte"),
249 MIB_DESC(1, AR8236_STATS_TX1024BYTE
, "Tx1024Byte"),
250 MIB_DESC(1, AR8236_STATS_TX1518BYTE
, "Tx1518Byte"),
251 MIB_DESC(1, AR8236_STATS_TXMAXBYTE
, "TxMaxByte"),
252 MIB_DESC(1, AR8236_STATS_TXOVERSIZE
, "TxOverSize"),
253 MIB_DESC(2, AR8236_STATS_TXBYTE
, "TxByte"),
254 MIB_DESC(1, AR8236_STATS_TXCOLLISION
, "TxCollision"),
255 MIB_DESC(1, AR8236_STATS_TXABORTCOL
, "TxAbortCol"),
256 MIB_DESC(1, AR8236_STATS_TXMULTICOL
, "TxMultiCol"),
257 MIB_DESC(1, AR8236_STATS_TXSINGLECOL
, "TxSingleCol"),
258 MIB_DESC(1, AR8236_STATS_TXEXCDEFER
, "TxExcDefer"),
259 MIB_DESC(1, AR8236_STATS_TXDEFER
, "TxDefer"),
260 MIB_DESC(1, AR8236_STATS_TXLATECOL
, "TxLateCol"),
263 static DEFINE_MUTEX(ar8xxx_dev_list_lock
);
264 static LIST_HEAD(ar8xxx_dev_list
);
266 static inline struct ar8xxx_priv
*
267 swdev_to_ar8xxx(struct switch_dev
*swdev
)
269 return container_of(swdev
, struct ar8xxx_priv
, dev
);
272 static inline bool ar8xxx_has_gige(struct ar8xxx_priv
*priv
)
274 return priv
->chip
->caps
& AR8XXX_CAP_GIGE
;
277 static inline bool ar8xxx_has_mib_counters(struct ar8xxx_priv
*priv
)
279 return priv
->chip
->caps
& AR8XXX_CAP_MIB_COUNTERS
;
282 static inline bool chip_is_ar8216(struct ar8xxx_priv
*priv
)
284 return priv
->chip_ver
== AR8XXX_VER_AR8216
;
287 static inline bool chip_is_ar8236(struct ar8xxx_priv
*priv
)
289 return priv
->chip_ver
== AR8XXX_VER_AR8236
;
292 static inline bool chip_is_ar8316(struct ar8xxx_priv
*priv
)
294 return priv
->chip_ver
== AR8XXX_VER_AR8316
;
297 static inline bool chip_is_ar8327(struct ar8xxx_priv
*priv
)
299 return priv
->chip_ver
== AR8XXX_VER_AR8327
;
302 static inline bool chip_is_ar8337(struct ar8xxx_priv
*priv
)
304 return priv
->chip_ver
== AR8XXX_VER_AR8337
;
308 split_addr(u32 regaddr
, u16
*r1
, u16
*r2
, u16
*page
)
311 *r1
= regaddr
& 0x1e;
317 *page
= regaddr
& 0x1ff;
320 /* inspired by phy_poll_reset in drivers/net/phy/phy_device.c */
322 ar8xxx_phy_poll_reset(struct mii_bus
*bus
)
324 unsigned int sleep_msecs
= 20;
327 for (elapsed
= sleep_msecs
; elapsed
<= 600;
328 elapsed
+= sleep_msecs
) {
330 for (i
= 0; i
< AR8XXX_NUM_PHYS
; i
++) {
331 ret
= mdiobus_read(bus
, i
, MII_BMCR
);
334 if (ret
& BMCR_RESET
)
336 if (i
== AR8XXX_NUM_PHYS
- 1) {
337 usleep_range(1000, 2000);
346 ar8xxx_phy_init(struct ar8xxx_priv
*priv
)
352 for (i
= 0; i
< AR8XXX_NUM_PHYS
; i
++) {
353 if (priv
->chip
->phy_fixup
)
354 priv
->chip
->phy_fixup(priv
, i
);
356 /* initialize the port itself */
357 mdiobus_write(bus
, i
, MII_ADVERTISE
,
358 ADVERTISE_ALL
| ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
);
359 if (ar8xxx_has_gige(priv
))
360 mdiobus_write(bus
, i
, MII_CTRL1000
, ADVERTISE_1000FULL
);
361 mdiobus_write(bus
, i
, MII_BMCR
, BMCR_RESET
| BMCR_ANENABLE
);
364 ar8xxx_phy_poll_reset(bus
);
368 ar8xxx_mii_read(struct ar8xxx_priv
*priv
, int reg
)
370 struct mii_bus
*bus
= priv
->mii_bus
;
374 split_addr((u32
) reg
, &r1
, &r2
, &page
);
376 mutex_lock(&bus
->mdio_lock
);
378 bus
->write(bus
, 0x18, 0, page
);
379 usleep_range(1000, 2000); /* wait for the page switch to propagate */
380 lo
= bus
->read(bus
, 0x10 | r2
, r1
);
381 hi
= bus
->read(bus
, 0x10 | r2
, r1
+ 1);
383 mutex_unlock(&bus
->mdio_lock
);
385 return (hi
<< 16) | lo
;
389 ar8xxx_mii_write(struct ar8xxx_priv
*priv
, int reg
, u32 val
)
391 struct mii_bus
*bus
= priv
->mii_bus
;
395 split_addr((u32
) reg
, &r1
, &r2
, &r3
);
397 hi
= (u16
) (val
>> 16);
399 mutex_lock(&bus
->mdio_lock
);
401 bus
->write(bus
, 0x18, 0, r3
);
402 usleep_range(1000, 2000); /* wait for the page switch to propagate */
403 if (priv
->mii_lo_first
) {
404 bus
->write(bus
, 0x10 | r2
, r1
, lo
);
405 bus
->write(bus
, 0x10 | r2
, r1
+ 1, hi
);
407 bus
->write(bus
, 0x10 | r2
, r1
+ 1, hi
);
408 bus
->write(bus
, 0x10 | r2
, r1
, lo
);
411 mutex_unlock(&bus
->mdio_lock
);
415 ar8xxx_mii_rmw(struct ar8xxx_priv
*priv
, int reg
, u32 mask
, u32 val
)
417 struct mii_bus
*bus
= priv
->mii_bus
;
422 split_addr((u32
) reg
, &r1
, &r2
, &page
);
424 mutex_lock(&bus
->mdio_lock
);
426 bus
->write(bus
, 0x18, 0, page
);
427 usleep_range(1000, 2000); /* wait for the page switch to propagate */
429 lo
= bus
->read(bus
, 0x10 | r2
, r1
);
430 hi
= bus
->read(bus
, 0x10 | r2
, r1
+ 1);
437 hi
= (u16
) (ret
>> 16);
439 if (priv
->mii_lo_first
) {
440 bus
->write(bus
, 0x10 | r2
, r1
, lo
);
441 bus
->write(bus
, 0x10 | r2
, r1
+ 1, hi
);
443 bus
->write(bus
, 0x10 | r2
, r1
+ 1, hi
);
444 bus
->write(bus
, 0x10 | r2
, r1
, lo
);
447 mutex_unlock(&bus
->mdio_lock
);
454 ar8xxx_phy_dbg_write(struct ar8xxx_priv
*priv
, int phy_addr
,
455 u16 dbg_addr
, u16 dbg_data
)
457 struct mii_bus
*bus
= priv
->mii_bus
;
459 mutex_lock(&bus
->mdio_lock
);
460 bus
->write(bus
, phy_addr
, MII_ATH_DBG_ADDR
, dbg_addr
);
461 bus
->write(bus
, phy_addr
, MII_ATH_DBG_DATA
, dbg_data
);
462 mutex_unlock(&bus
->mdio_lock
);
466 ar8xxx_phy_mmd_write(struct ar8xxx_priv
*priv
, int phy_addr
, u16 addr
, u16 data
)
468 struct mii_bus
*bus
= priv
->mii_bus
;
470 mutex_lock(&bus
->mdio_lock
);
471 bus
->write(bus
, phy_addr
, MII_ATH_MMD_ADDR
, addr
);
472 bus
->write(bus
, phy_addr
, MII_ATH_MMD_DATA
, data
);
473 mutex_unlock(&bus
->mdio_lock
);
477 ar8xxx_rmw(struct ar8xxx_priv
*priv
, int reg
, u32 mask
, u32 val
)
479 return priv
->rmw(priv
, reg
, mask
, val
);
483 ar8xxx_reg_set(struct ar8xxx_priv
*priv
, int reg
, u32 val
)
485 priv
->rmw(priv
, reg
, 0, val
);
489 ar8xxx_reg_wait(struct ar8xxx_priv
*priv
, u32 reg
, u32 mask
, u32 val
,
494 for (i
= 0; i
< timeout
; i
++) {
497 t
= priv
->read(priv
, reg
);
498 if ((t
& mask
) == val
)
501 usleep_range(1000, 2000);
508 ar8xxx_mib_op(struct ar8xxx_priv
*priv
, u32 op
)
513 lockdep_assert_held(&priv
->mib_lock
);
515 if (chip_is_ar8327(priv
) || chip_is_ar8337(priv
))
516 mib_func
= AR8327_REG_MIB_FUNC
;
518 mib_func
= AR8216_REG_MIB_FUNC
;
520 /* Capture the hardware statistics for all ports */
521 ar8xxx_rmw(priv
, mib_func
, AR8216_MIB_FUNC
, (op
<< AR8216_MIB_FUNC_S
));
523 /* Wait for the capturing to complete. */
524 ret
= ar8xxx_reg_wait(priv
, mib_func
, AR8216_MIB_BUSY
, 0, 10);
535 ar8xxx_mib_capture(struct ar8xxx_priv
*priv
)
537 return ar8xxx_mib_op(priv
, AR8216_MIB_FUNC_CAPTURE
);
541 ar8xxx_mib_flush(struct ar8xxx_priv
*priv
)
543 return ar8xxx_mib_op(priv
, AR8216_MIB_FUNC_FLUSH
);
547 ar8xxx_mib_fetch_port_stat(struct ar8xxx_priv
*priv
, int port
, bool flush
)
553 WARN_ON(port
>= priv
->dev
.ports
);
555 lockdep_assert_held(&priv
->mib_lock
);
557 if (chip_is_ar8327(priv
) || chip_is_ar8337(priv
))
558 base
= AR8327_REG_PORT_STATS_BASE(port
);
559 else if (chip_is_ar8236(priv
) ||
560 chip_is_ar8316(priv
))
561 base
= AR8236_REG_PORT_STATS_BASE(port
);
563 base
= AR8216_REG_PORT_STATS_BASE(port
);
565 mib_stats
= &priv
->mib_stats
[port
* priv
->chip
->num_mibs
];
566 for (i
= 0; i
< priv
->chip
->num_mibs
; i
++) {
567 const struct ar8xxx_mib_desc
*mib
;
570 mib
= &priv
->chip
->mib_decs
[i
];
571 t
= priv
->read(priv
, base
+ mib
->offset
);
572 if (mib
->size
== 2) {
575 hi
= priv
->read(priv
, base
+ mib
->offset
+ 4);
587 ar8216_read_port_link(struct ar8xxx_priv
*priv
, int port
,
588 struct switch_port_link
*link
)
593 memset(link
, '\0', sizeof(*link
));
595 status
= priv
->chip
->read_port_status(priv
, port
);
597 link
->aneg
= !!(status
& AR8216_PORT_STATUS_LINK_AUTO
);
599 link
->link
= !!(status
& AR8216_PORT_STATUS_LINK_UP
);
603 if (priv
->get_port_link
) {
606 err
= priv
->get_port_link(port
);
615 link
->duplex
= !!(status
& AR8216_PORT_STATUS_DUPLEX
);
616 link
->tx_flow
= !!(status
& AR8216_PORT_STATUS_TXFLOW
);
617 link
->rx_flow
= !!(status
& AR8216_PORT_STATUS_RXFLOW
);
619 speed
= (status
& AR8216_PORT_STATUS_SPEED
) >>
620 AR8216_PORT_STATUS_SPEED_S
;
623 case AR8216_PORT_SPEED_10M
:
624 link
->speed
= SWITCH_PORT_SPEED_10
;
626 case AR8216_PORT_SPEED_100M
:
627 link
->speed
= SWITCH_PORT_SPEED_100
;
629 case AR8216_PORT_SPEED_1000M
:
630 link
->speed
= SWITCH_PORT_SPEED_1000
;
633 link
->speed
= SWITCH_PORT_SPEED_UNKNOWN
;
638 static struct sk_buff
*
639 ar8216_mangle_tx(struct net_device
*dev
, struct sk_buff
*skb
)
641 struct ar8xxx_priv
*priv
= dev
->phy_ptr
;
650 if (unlikely(skb_headroom(skb
) < 2)) {
651 if (pskb_expand_head(skb
, 2, 0, GFP_ATOMIC
) < 0)
655 buf
= skb_push(skb
, 2);
663 dev_kfree_skb_any(skb
);
668 ar8216_mangle_rx(struct net_device
*dev
, struct sk_buff
*skb
)
670 struct ar8xxx_priv
*priv
;
678 /* don't strip the header if vlan mode is disabled */
682 /* strip header, get vlan id */
686 /* check for vlan header presence */
687 if ((buf
[12 + 2] != 0x81) || (buf
[13 + 2] != 0x00))
692 /* no need to fix up packets coming from a tagged source */
693 if (priv
->vlan_tagged
& (1 << port
))
696 /* lookup port vid from local table, the switch passes an invalid vlan id */
697 vlan
= priv
->vlan_id
[priv
->pvid
[port
]];
700 buf
[14 + 2] |= vlan
>> 8;
701 buf
[15 + 2] = vlan
& 0xff;
705 ar8216_wait_bit(struct ar8xxx_priv
*priv
, int reg
, u32 mask
, u32 val
)
711 t
= priv
->read(priv
, reg
);
712 if ((t
& mask
) == val
)
721 pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
722 (unsigned int) reg
, t
, mask
, val
);
727 ar8216_vtu_op(struct ar8xxx_priv
*priv
, u32 op
, u32 val
)
729 if (ar8216_wait_bit(priv
, AR8216_REG_VTU
, AR8216_VTU_ACTIVE
, 0))
731 if ((op
& AR8216_VTU_OP
) == AR8216_VTU_OP_LOAD
) {
732 val
&= AR8216_VTUDATA_MEMBER
;
733 val
|= AR8216_VTUDATA_VALID
;
734 priv
->write(priv
, AR8216_REG_VTU_DATA
, val
);
736 op
|= AR8216_VTU_ACTIVE
;
737 priv
->write(priv
, AR8216_REG_VTU
, op
);
741 ar8216_vtu_flush(struct ar8xxx_priv
*priv
)
743 ar8216_vtu_op(priv
, AR8216_VTU_OP_FLUSH
, 0);
747 ar8216_vtu_load_vlan(struct ar8xxx_priv
*priv
, u32 vid
, u32 port_mask
)
751 op
= AR8216_VTU_OP_LOAD
| (vid
<< AR8216_VTU_VID_S
);
752 ar8216_vtu_op(priv
, op
, port_mask
);
756 ar8216_atu_flush(struct ar8xxx_priv
*priv
)
760 ret
= ar8216_wait_bit(priv
, AR8216_REG_ATU
, AR8216_ATU_ACTIVE
, 0);
762 priv
->write(priv
, AR8216_REG_ATU
, AR8216_ATU_OP_FLUSH
);
768 ar8216_read_port_status(struct ar8xxx_priv
*priv
, int port
)
770 return priv
->read(priv
, AR8216_REG_PORT_STATUS(port
));
774 ar8216_setup_port(struct ar8xxx_priv
*priv
, int port
, u32 members
)
781 pvid
= priv
->vlan_id
[priv
->pvid
[port
]];
782 if (priv
->vlan_tagged
& (1 << port
))
783 egress
= AR8216_OUT_ADD_VLAN
;
785 egress
= AR8216_OUT_STRIP_VLAN
;
786 ingress
= AR8216_IN_SECURE
;
789 egress
= AR8216_OUT_KEEP
;
790 ingress
= AR8216_IN_PORT_ONLY
;
793 if (chip_is_ar8216(priv
) && priv
->vlan
&& port
== AR8216_PORT_CPU
)
794 header
= AR8216_PORT_CTRL_HEADER
;
798 ar8xxx_rmw(priv
, AR8216_REG_PORT_CTRL(port
),
799 AR8216_PORT_CTRL_LEARN
| AR8216_PORT_CTRL_VLAN_MODE
|
800 AR8216_PORT_CTRL_SINGLE_VLAN
| AR8216_PORT_CTRL_STATE
|
801 AR8216_PORT_CTRL_HEADER
| AR8216_PORT_CTRL_LEARN_LOCK
,
802 AR8216_PORT_CTRL_LEARN
| header
|
803 (egress
<< AR8216_PORT_CTRL_VLAN_MODE_S
) |
804 (AR8216_PORT_STATE_FORWARD
<< AR8216_PORT_CTRL_STATE_S
));
806 ar8xxx_rmw(priv
, AR8216_REG_PORT_VLAN(port
),
807 AR8216_PORT_VLAN_DEST_PORTS
| AR8216_PORT_VLAN_MODE
|
808 AR8216_PORT_VLAN_DEFAULT_ID
,
809 (members
<< AR8216_PORT_VLAN_DEST_PORTS_S
) |
810 (ingress
<< AR8216_PORT_VLAN_MODE_S
) |
811 (pvid
<< AR8216_PORT_VLAN_DEFAULT_ID_S
));
815 ar8216_hw_init(struct ar8xxx_priv
*priv
)
817 if (priv
->initialized
)
820 ar8xxx_phy_init(priv
);
822 priv
->initialized
= true;
827 ar8216_init_globals(struct ar8xxx_priv
*priv
)
829 /* standard atheros magic */
830 priv
->write(priv
, 0x38, 0xc000050e);
832 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
833 AR8216_GCTRL_MTU
, 1518 + 8 + 2);
837 ar8216_init_port(struct ar8xxx_priv
*priv
, int port
)
839 /* Enable port learning and tx */
840 priv
->write(priv
, AR8216_REG_PORT_CTRL(port
),
841 AR8216_PORT_CTRL_LEARN
|
842 (4 << AR8216_PORT_CTRL_STATE_S
));
844 priv
->write(priv
, AR8216_REG_PORT_VLAN(port
), 0);
846 if (port
== AR8216_PORT_CPU
) {
847 priv
->write(priv
, AR8216_REG_PORT_STATUS(port
),
848 AR8216_PORT_STATUS_LINK_UP
|
849 (ar8xxx_has_gige(priv
) ?
850 AR8216_PORT_SPEED_1000M
: AR8216_PORT_SPEED_100M
) |
851 AR8216_PORT_STATUS_TXMAC
|
852 AR8216_PORT_STATUS_RXMAC
|
853 (chip_is_ar8316(priv
) ? AR8216_PORT_STATUS_RXFLOW
: 0) |
854 (chip_is_ar8316(priv
) ? AR8216_PORT_STATUS_TXFLOW
: 0) |
855 AR8216_PORT_STATUS_DUPLEX
);
857 priv
->write(priv
, AR8216_REG_PORT_STATUS(port
),
858 AR8216_PORT_STATUS_LINK_AUTO
);
862 static const struct ar8xxx_chip ar8216_chip
= {
863 .caps
= AR8XXX_CAP_MIB_COUNTERS
,
865 .hw_init
= ar8216_hw_init
,
866 .init_globals
= ar8216_init_globals
,
867 .init_port
= ar8216_init_port
,
868 .setup_port
= ar8216_setup_port
,
869 .read_port_status
= ar8216_read_port_status
,
870 .atu_flush
= ar8216_atu_flush
,
871 .vtu_flush
= ar8216_vtu_flush
,
872 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
874 .num_mibs
= ARRAY_SIZE(ar8216_mibs
),
875 .mib_decs
= ar8216_mibs
,
879 ar8236_setup_port(struct ar8xxx_priv
*priv
, int port
, u32 members
)
885 pvid
= priv
->vlan_id
[priv
->pvid
[port
]];
886 if (priv
->vlan_tagged
& (1 << port
))
887 egress
= AR8216_OUT_ADD_VLAN
;
889 egress
= AR8216_OUT_STRIP_VLAN
;
890 ingress
= AR8216_IN_SECURE
;
893 egress
= AR8216_OUT_KEEP
;
894 ingress
= AR8216_IN_PORT_ONLY
;
897 ar8xxx_rmw(priv
, AR8216_REG_PORT_CTRL(port
),
898 AR8216_PORT_CTRL_LEARN
| AR8216_PORT_CTRL_VLAN_MODE
|
899 AR8216_PORT_CTRL_SINGLE_VLAN
| AR8216_PORT_CTRL_STATE
|
900 AR8216_PORT_CTRL_HEADER
| AR8216_PORT_CTRL_LEARN_LOCK
,
901 AR8216_PORT_CTRL_LEARN
|
902 (egress
<< AR8216_PORT_CTRL_VLAN_MODE_S
) |
903 (AR8216_PORT_STATE_FORWARD
<< AR8216_PORT_CTRL_STATE_S
));
905 ar8xxx_rmw(priv
, AR8236_REG_PORT_VLAN(port
),
906 AR8236_PORT_VLAN_DEFAULT_ID
,
907 (pvid
<< AR8236_PORT_VLAN_DEFAULT_ID_S
));
909 ar8xxx_rmw(priv
, AR8236_REG_PORT_VLAN2(port
),
910 AR8236_PORT_VLAN2_VLAN_MODE
|
911 AR8236_PORT_VLAN2_MEMBER
,
912 (ingress
<< AR8236_PORT_VLAN2_VLAN_MODE_S
) |
913 (members
<< AR8236_PORT_VLAN2_MEMBER_S
));
917 ar8236_init_globals(struct ar8xxx_priv
*priv
)
919 /* enable jumbo frames */
920 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
921 AR8316_GCTRL_MTU
, 9018 + 8 + 2);
923 /* Enable MIB counters */
924 ar8xxx_rmw(priv
, AR8216_REG_MIB_FUNC
, AR8216_MIB_FUNC
| AR8236_MIB_EN
,
925 (AR8216_MIB_FUNC_NO_OP
<< AR8216_MIB_FUNC_S
) |
929 static const struct ar8xxx_chip ar8236_chip
= {
930 .caps
= AR8XXX_CAP_MIB_COUNTERS
,
931 .hw_init
= ar8216_hw_init
,
932 .init_globals
= ar8236_init_globals
,
933 .init_port
= ar8216_init_port
,
934 .setup_port
= ar8236_setup_port
,
935 .read_port_status
= ar8216_read_port_status
,
936 .atu_flush
= ar8216_atu_flush
,
937 .vtu_flush
= ar8216_vtu_flush
,
938 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
940 .num_mibs
= ARRAY_SIZE(ar8236_mibs
),
941 .mib_decs
= ar8236_mibs
,
945 ar8316_hw_init(struct ar8xxx_priv
*priv
)
949 val
= priv
->read(priv
, AR8316_REG_POSTRIP
);
951 if (priv
->phy
->interface
== PHY_INTERFACE_MODE_RGMII
) {
952 if (priv
->port4_phy
) {
953 /* value taken from Ubiquiti RouterStation Pro */
955 pr_info("ar8316: Using port 4 as PHY\n");
958 pr_info("ar8316: Using port 4 as switch port\n");
960 } else if (priv
->phy
->interface
== PHY_INTERFACE_MODE_GMII
) {
961 /* value taken from AVM Fritz!Box 7390 sources */
964 /* no known value for phy interface */
965 pr_err("ar8316: unsupported mii mode: %d.\n",
966 priv
->phy
->interface
);
973 priv
->write(priv
, AR8316_REG_POSTRIP
, newval
);
975 if (priv
->port4_phy
&&
976 priv
->phy
->interface
== PHY_INTERFACE_MODE_RGMII
) {
977 /* work around for phy4 rgmii mode */
978 ar8xxx_phy_dbg_write(priv
, 4, 0x12, 0x480c);
980 ar8xxx_phy_dbg_write(priv
, 4, 0x0, 0x824e);
982 ar8xxx_phy_dbg_write(priv
, 4, 0x5, 0x3d47);
986 ar8xxx_phy_init(priv
);
989 priv
->initialized
= true;
994 ar8316_init_globals(struct ar8xxx_priv
*priv
)
996 /* standard atheros magic */
997 priv
->write(priv
, 0x38, 0xc000050e);
999 /* enable cpu port to receive multicast and broadcast frames */
1000 priv
->write(priv
, AR8216_REG_FLOOD_MASK
, 0x003f003f);
1002 /* enable jumbo frames */
1003 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
1004 AR8316_GCTRL_MTU
, 9018 + 8 + 2);
1006 /* Enable MIB counters */
1007 ar8xxx_rmw(priv
, AR8216_REG_MIB_FUNC
, AR8216_MIB_FUNC
| AR8236_MIB_EN
,
1008 (AR8216_MIB_FUNC_NO_OP
<< AR8216_MIB_FUNC_S
) |
1012 static const struct ar8xxx_chip ar8316_chip
= {
1013 .caps
= AR8XXX_CAP_GIGE
| AR8XXX_CAP_MIB_COUNTERS
,
1014 .hw_init
= ar8316_hw_init
,
1015 .init_globals
= ar8316_init_globals
,
1016 .init_port
= ar8216_init_port
,
1017 .setup_port
= ar8216_setup_port
,
1018 .read_port_status
= ar8216_read_port_status
,
1019 .atu_flush
= ar8216_atu_flush
,
1020 .vtu_flush
= ar8216_vtu_flush
,
1021 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
1023 .num_mibs
= ARRAY_SIZE(ar8236_mibs
),
1024 .mib_decs
= ar8236_mibs
,
1028 ar8327_get_pad_cfg(struct ar8327_pad_cfg
*cfg
)
1036 switch (cfg
->mode
) {
1040 case AR8327_PAD_MAC2MAC_MII
:
1041 t
= AR8327_PAD_MAC_MII_EN
;
1043 t
|= AR8327_PAD_MAC_MII_RXCLK_SEL
;
1045 t
|= AR8327_PAD_MAC_MII_TXCLK_SEL
;
1048 case AR8327_PAD_MAC2MAC_GMII
:
1049 t
= AR8327_PAD_MAC_GMII_EN
;
1051 t
|= AR8327_PAD_MAC_GMII_RXCLK_SEL
;
1053 t
|= AR8327_PAD_MAC_GMII_TXCLK_SEL
;
1056 case AR8327_PAD_MAC_SGMII
:
1057 t
= AR8327_PAD_SGMII_EN
;
1060 * WAR for the QUalcomm Atheros AP136 board.
1061 * It seems that RGMII TX/RX delay settings needs to be
1062 * applied for SGMII mode as well, The ethernet is not
1063 * reliable without this.
1065 t
|= cfg
->txclk_delay_sel
<< AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S
;
1066 t
|= cfg
->rxclk_delay_sel
<< AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S
;
1067 if (cfg
->rxclk_delay_en
)
1068 t
|= AR8327_PAD_RGMII_RXCLK_DELAY_EN
;
1069 if (cfg
->txclk_delay_en
)
1070 t
|= AR8327_PAD_RGMII_TXCLK_DELAY_EN
;
1072 if (cfg
->sgmii_delay_en
)
1073 t
|= AR8327_PAD_SGMII_DELAY_EN
;
1077 case AR8327_PAD_MAC2PHY_MII
:
1078 t
= AR8327_PAD_PHY_MII_EN
;
1080 t
|= AR8327_PAD_PHY_MII_RXCLK_SEL
;
1082 t
|= AR8327_PAD_PHY_MII_TXCLK_SEL
;
1085 case AR8327_PAD_MAC2PHY_GMII
:
1086 t
= AR8327_PAD_PHY_GMII_EN
;
1087 if (cfg
->pipe_rxclk_sel
)
1088 t
|= AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL
;
1090 t
|= AR8327_PAD_PHY_GMII_RXCLK_SEL
;
1092 t
|= AR8327_PAD_PHY_GMII_TXCLK_SEL
;
1095 case AR8327_PAD_MAC_RGMII
:
1096 t
= AR8327_PAD_RGMII_EN
;
1097 t
|= cfg
->txclk_delay_sel
<< AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S
;
1098 t
|= cfg
->rxclk_delay_sel
<< AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S
;
1099 if (cfg
->rxclk_delay_en
)
1100 t
|= AR8327_PAD_RGMII_RXCLK_DELAY_EN
;
1101 if (cfg
->txclk_delay_en
)
1102 t
|= AR8327_PAD_RGMII_TXCLK_DELAY_EN
;
1105 case AR8327_PAD_PHY_GMII
:
1106 t
= AR8327_PAD_PHYX_GMII_EN
;
1109 case AR8327_PAD_PHY_RGMII
:
1110 t
= AR8327_PAD_PHYX_RGMII_EN
;
1113 case AR8327_PAD_PHY_MII
:
1114 t
= AR8327_PAD_PHYX_MII_EN
;
1122 ar8327_phy_fixup(struct ar8xxx_priv
*priv
, int phy
)
1124 switch (priv
->chip_rev
) {
1126 /* For 100M waveform */
1127 ar8xxx_phy_dbg_write(priv
, phy
, 0, 0x02ea);
1128 /* Turn on Gigabit clock */
1129 ar8xxx_phy_dbg_write(priv
, phy
, 0x3d, 0x68a0);
1133 ar8xxx_phy_mmd_write(priv
, phy
, 0x7, 0x3c);
1134 ar8xxx_phy_mmd_write(priv
, phy
, 0x4007, 0x0);
1137 ar8xxx_phy_mmd_write(priv
, phy
, 0x3, 0x800d);
1138 ar8xxx_phy_mmd_write(priv
, phy
, 0x4003, 0x803f);
1140 ar8xxx_phy_dbg_write(priv
, phy
, 0x3d, 0x6860);
1141 ar8xxx_phy_dbg_write(priv
, phy
, 0x5, 0x2c46);
1142 ar8xxx_phy_dbg_write(priv
, phy
, 0x3c, 0x6000);
1148 ar8327_get_port_init_status(struct ar8327_port_cfg
*cfg
)
1152 if (!cfg
->force_link
)
1153 return AR8216_PORT_STATUS_LINK_AUTO
;
1155 t
= AR8216_PORT_STATUS_TXMAC
| AR8216_PORT_STATUS_RXMAC
;
1156 t
|= cfg
->duplex
? AR8216_PORT_STATUS_DUPLEX
: 0;
1157 t
|= cfg
->rxpause
? AR8216_PORT_STATUS_RXFLOW
: 0;
1158 t
|= cfg
->txpause
? AR8216_PORT_STATUS_TXFLOW
: 0;
1160 switch (cfg
->speed
) {
1161 case AR8327_PORT_SPEED_10
:
1162 t
|= AR8216_PORT_SPEED_10M
;
1164 case AR8327_PORT_SPEED_100
:
1165 t
|= AR8216_PORT_SPEED_100M
;
1167 case AR8327_PORT_SPEED_1000
:
1168 t
|= AR8216_PORT_SPEED_1000M
;
1175 #define AR8327_LED_ENTRY(_num, _reg, _shift) \
1176 [_num] = { .reg = (_reg), .shift = (_shift) }
1178 static const struct ar8327_led_entry
1179 ar8327_led_map
[AR8327_NUM_LEDS
] = {
1180 AR8327_LED_ENTRY(AR8327_LED_PHY0_0
, 0, 14),
1181 AR8327_LED_ENTRY(AR8327_LED_PHY0_1
, 1, 14),
1182 AR8327_LED_ENTRY(AR8327_LED_PHY0_2
, 2, 14),
1184 AR8327_LED_ENTRY(AR8327_LED_PHY1_0
, 3, 8),
1185 AR8327_LED_ENTRY(AR8327_LED_PHY1_1
, 3, 10),
1186 AR8327_LED_ENTRY(AR8327_LED_PHY1_2
, 3, 12),
1188 AR8327_LED_ENTRY(AR8327_LED_PHY2_0
, 3, 14),
1189 AR8327_LED_ENTRY(AR8327_LED_PHY2_1
, 3, 16),
1190 AR8327_LED_ENTRY(AR8327_LED_PHY2_2
, 3, 18),
1192 AR8327_LED_ENTRY(AR8327_LED_PHY3_0
, 3, 20),
1193 AR8327_LED_ENTRY(AR8327_LED_PHY3_1
, 3, 22),
1194 AR8327_LED_ENTRY(AR8327_LED_PHY3_2
, 3, 24),
1196 AR8327_LED_ENTRY(AR8327_LED_PHY4_0
, 0, 30),
1197 AR8327_LED_ENTRY(AR8327_LED_PHY4_1
, 1, 30),
1198 AR8327_LED_ENTRY(AR8327_LED_PHY4_2
, 2, 30),
1202 ar8327_set_led_pattern(struct ar8xxx_priv
*priv
, unsigned int led_num
,
1203 enum ar8327_led_pattern pattern
)
1205 const struct ar8327_led_entry
*entry
;
1207 entry
= &ar8327_led_map
[led_num
];
1208 ar8xxx_rmw(priv
, AR8327_REG_LED_CTRL(entry
->reg
),
1209 (3 << entry
->shift
), pattern
<< entry
->shift
);
1213 ar8327_led_work_func(struct work_struct
*work
)
1215 struct ar8327_led
*aled
;
1218 aled
= container_of(work
, struct ar8327_led
, led_work
);
1220 spin_lock(&aled
->lock
);
1221 pattern
= aled
->pattern
;
1222 spin_unlock(&aled
->lock
);
1224 ar8327_set_led_pattern(aled
->sw_priv
, aled
->led_num
,
1229 ar8327_led_schedule_change(struct ar8327_led
*aled
, u8 pattern
)
1231 if (aled
->pattern
== pattern
)
1234 aled
->pattern
= pattern
;
1235 schedule_work(&aled
->led_work
);
1238 static inline struct ar8327_led
*
1239 led_cdev_to_ar8327_led(struct led_classdev
*led_cdev
)
1241 return container_of(led_cdev
, struct ar8327_led
, cdev
);
1245 ar8327_led_blink_set(struct led_classdev
*led_cdev
,
1246 unsigned long *delay_on
,
1247 unsigned long *delay_off
)
1249 struct ar8327_led
*aled
= led_cdev_to_ar8327_led(led_cdev
);
1251 if (*delay_on
== 0 && *delay_off
== 0) {
1256 if (*delay_on
!= 125 || *delay_off
!= 125) {
1258 * The hardware only supports blinking at 4Hz. Fall back
1259 * to software implementation in other cases.
1264 spin_lock(&aled
->lock
);
1266 aled
->enable_hw_mode
= false;
1267 ar8327_led_schedule_change(aled
, AR8327_LED_PATTERN_BLINK
);
1269 spin_unlock(&aled
->lock
);
1275 ar8327_led_set_brightness(struct led_classdev
*led_cdev
,
1276 enum led_brightness brightness
)
1278 struct ar8327_led
*aled
= led_cdev_to_ar8327_led(led_cdev
);
1282 active
= (brightness
!= LED_OFF
);
1283 active
^= aled
->active_low
;
1285 pattern
= (active
) ? AR8327_LED_PATTERN_ON
:
1286 AR8327_LED_PATTERN_OFF
;
1288 spin_lock(&aled
->lock
);
1290 aled
->enable_hw_mode
= false;
1291 ar8327_led_schedule_change(aled
, pattern
);
1293 spin_unlock(&aled
->lock
);
1297 ar8327_led_enable_hw_mode_show(struct device
*dev
,
1298 struct device_attribute
*attr
,
1301 struct led_classdev
*led_cdev
= dev_get_drvdata(dev
);
1302 struct ar8327_led
*aled
= led_cdev_to_ar8327_led(led_cdev
);
1305 spin_lock(&aled
->lock
);
1306 ret
+= sprintf(buf
, "%d\n", aled
->enable_hw_mode
);
1307 spin_unlock(&aled
->lock
);
1313 ar8327_led_enable_hw_mode_store(struct device
*dev
,
1314 struct device_attribute
*attr
,
1318 struct led_classdev
*led_cdev
= dev_get_drvdata(dev
);
1319 struct ar8327_led
*aled
= led_cdev_to_ar8327_led(led_cdev
);
1324 ret
= kstrtou8(buf
, 10, &value
);
1328 spin_lock(&aled
->lock
);
1330 aled
->enable_hw_mode
= !!value
;
1331 if (aled
->enable_hw_mode
)
1332 pattern
= AR8327_LED_PATTERN_RULE
;
1334 pattern
= AR8327_LED_PATTERN_OFF
;
1336 ar8327_led_schedule_change(aled
, pattern
);
1338 spin_unlock(&aled
->lock
);
1343 static DEVICE_ATTR(enable_hw_mode
, S_IRUGO
| S_IWUSR
,
1344 ar8327_led_enable_hw_mode_show
,
1345 ar8327_led_enable_hw_mode_store
);
1348 ar8327_led_register(struct ar8xxx_priv
*priv
, struct ar8327_led
*aled
)
1352 ret
= led_classdev_register(NULL
, &aled
->cdev
);
1356 if (aled
->mode
== AR8327_LED_MODE_HW
) {
1357 ret
= device_create_file(aled
->cdev
.dev
,
1358 &dev_attr_enable_hw_mode
);
1360 goto err_unregister
;
1366 led_classdev_unregister(&aled
->cdev
);
1371 ar8327_led_unregister(struct ar8327_led
*aled
)
1373 if (aled
->mode
== AR8327_LED_MODE_HW
)
1374 device_remove_file(aled
->cdev
.dev
, &dev_attr_enable_hw_mode
);
1376 led_classdev_unregister(&aled
->cdev
);
1377 cancel_work_sync(&aled
->led_work
);
1381 ar8327_led_create(struct ar8xxx_priv
*priv
,
1382 const struct ar8327_led_info
*led_info
)
1384 struct ar8327_data
*data
= &priv
->chip_data
.ar8327
;
1385 struct ar8327_led
*aled
;
1388 if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS
))
1391 if (!led_info
->name
)
1394 if (led_info
->led_num
>= AR8327_NUM_LEDS
)
1397 aled
= kzalloc(sizeof(*aled
) + strlen(led_info
->name
) + 1,
1402 aled
->sw_priv
= priv
;
1403 aled
->led_num
= led_info
->led_num
;
1404 aled
->active_low
= led_info
->active_low
;
1405 aled
->mode
= led_info
->mode
;
1407 if (aled
->mode
== AR8327_LED_MODE_HW
)
1408 aled
->enable_hw_mode
= true;
1410 aled
->name
= (char *)(aled
+ 1);
1411 strcpy(aled
->name
, led_info
->name
);
1413 aled
->cdev
.name
= aled
->name
;
1414 aled
->cdev
.brightness_set
= ar8327_led_set_brightness
;
1415 aled
->cdev
.blink_set
= ar8327_led_blink_set
;
1416 aled
->cdev
.default_trigger
= led_info
->default_trigger
;
1418 spin_lock_init(&aled
->lock
);
1419 mutex_init(&aled
->mutex
);
1420 INIT_WORK(&aled
->led_work
, ar8327_led_work_func
);
1422 ret
= ar8327_led_register(priv
, aled
);
1426 data
->leds
[data
->num_leds
++] = aled
;
1436 ar8327_led_destroy(struct ar8327_led
*aled
)
1438 ar8327_led_unregister(aled
);
1443 ar8327_leds_init(struct ar8xxx_priv
*priv
)
1445 struct ar8327_data
*data
;
1448 if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS
))
1451 data
= &priv
->chip_data
.ar8327
;
1453 for (i
= 0; i
< data
->num_leds
; i
++) {
1454 struct ar8327_led
*aled
;
1456 aled
= data
->leds
[i
];
1458 if (aled
->enable_hw_mode
)
1459 aled
->pattern
= AR8327_LED_PATTERN_RULE
;
1461 aled
->pattern
= AR8327_LED_PATTERN_OFF
;
1463 ar8327_set_led_pattern(priv
, aled
->led_num
, aled
->pattern
);
1468 ar8327_leds_cleanup(struct ar8xxx_priv
*priv
)
1470 struct ar8327_data
*data
= &priv
->chip_data
.ar8327
;
1473 if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS
))
1476 for (i
= 0; i
< data
->num_leds
; i
++) {
1477 struct ar8327_led
*aled
;
1479 aled
= data
->leds
[i
];
1480 ar8327_led_destroy(aled
);
1487 ar8327_hw_config_pdata(struct ar8xxx_priv
*priv
,
1488 struct ar8327_platform_data
*pdata
)
1490 struct ar8327_led_cfg
*led_cfg
;
1491 struct ar8327_data
*data
;
1498 priv
->get_port_link
= pdata
->get_port_link
;
1500 data
= &priv
->chip_data
.ar8327
;
1502 data
->port0_status
= ar8327_get_port_init_status(&pdata
->port0_cfg
);
1503 data
->port6_status
= ar8327_get_port_init_status(&pdata
->port6_cfg
);
1505 t
= ar8327_get_pad_cfg(pdata
->pad0_cfg
);
1506 if (chip_is_ar8337(priv
))
1507 t
|= AR8337_PAD_MAC06_EXCHANGE_EN
;
1509 priv
->write(priv
, AR8327_REG_PAD0_MODE
, t
);
1510 t
= ar8327_get_pad_cfg(pdata
->pad5_cfg
);
1511 priv
->write(priv
, AR8327_REG_PAD5_MODE
, t
);
1512 t
= ar8327_get_pad_cfg(pdata
->pad6_cfg
);
1513 priv
->write(priv
, AR8327_REG_PAD6_MODE
, t
);
1515 pos
= priv
->read(priv
, AR8327_REG_POWER_ON_STRIP
);
1518 led_cfg
= pdata
->led_cfg
;
1520 if (led_cfg
->open_drain
)
1521 new_pos
|= AR8327_POWER_ON_STRIP_LED_OPEN_EN
;
1523 new_pos
&= ~AR8327_POWER_ON_STRIP_LED_OPEN_EN
;
1525 priv
->write(priv
, AR8327_REG_LED_CTRL0
, led_cfg
->led_ctrl0
);
1526 priv
->write(priv
, AR8327_REG_LED_CTRL1
, led_cfg
->led_ctrl1
);
1527 priv
->write(priv
, AR8327_REG_LED_CTRL2
, led_cfg
->led_ctrl2
);
1528 priv
->write(priv
, AR8327_REG_LED_CTRL3
, led_cfg
->led_ctrl3
);
1531 new_pos
|= AR8327_POWER_ON_STRIP_POWER_ON_SEL
;
1534 if (pdata
->sgmii_cfg
) {
1535 t
= pdata
->sgmii_cfg
->sgmii_ctrl
;
1536 if (priv
->chip_rev
== 1)
1537 t
|= AR8327_SGMII_CTRL_EN_PLL
|
1538 AR8327_SGMII_CTRL_EN_RX
|
1539 AR8327_SGMII_CTRL_EN_TX
;
1541 t
&= ~(AR8327_SGMII_CTRL_EN_PLL
|
1542 AR8327_SGMII_CTRL_EN_RX
|
1543 AR8327_SGMII_CTRL_EN_TX
);
1545 priv
->write(priv
, AR8327_REG_SGMII_CTRL
, t
);
1547 if (pdata
->sgmii_cfg
->serdes_aen
)
1548 new_pos
&= ~AR8327_POWER_ON_STRIP_SERDES_AEN
;
1550 new_pos
|= AR8327_POWER_ON_STRIP_SERDES_AEN
;
1553 priv
->write(priv
, AR8327_REG_POWER_ON_STRIP
, new_pos
);
1555 if (pdata
->leds
&& pdata
->num_leds
) {
1558 data
->leds
= kzalloc(pdata
->num_leds
* sizeof(void *),
1563 for (i
= 0; i
< pdata
->num_leds
; i
++)
1564 ar8327_led_create(priv
, &pdata
->leds
[i
]);
1572 ar8327_hw_config_of(struct ar8xxx_priv
*priv
, struct device_node
*np
)
1574 const __be32
*paddr
;
1578 paddr
= of_get_property(np
, "qca,ar8327-initvals", &len
);
1579 if (!paddr
|| len
< (2 * sizeof(*paddr
)))
1582 len
/= sizeof(*paddr
);
1584 for (i
= 0; i
< len
- 1; i
+= 2) {
1588 reg
= be32_to_cpup(paddr
+ i
);
1589 val
= be32_to_cpup(paddr
+ i
+ 1);
1592 case AR8327_REG_PORT_STATUS(0):
1593 priv
->chip_data
.ar8327
.port0_status
= val
;
1595 case AR8327_REG_PORT_STATUS(6):
1596 priv
->chip_data
.ar8327
.port6_status
= val
;
1599 priv
->write(priv
, reg
, val
);
1608 ar8327_hw_config_of(struct ar8xxx_priv
*priv
, struct device_node
*np
)
1615 ar8327_hw_init(struct ar8xxx_priv
*priv
)
1619 if (priv
->phy
->dev
.of_node
)
1620 ret
= ar8327_hw_config_of(priv
, priv
->phy
->dev
.of_node
);
1622 ret
= ar8327_hw_config_pdata(priv
,
1623 priv
->phy
->dev
.platform_data
);
1628 ar8327_leds_init(priv
);
1630 ar8xxx_phy_init(priv
);
1636 ar8327_cleanup(struct ar8xxx_priv
*priv
)
1638 ar8327_leds_cleanup(priv
);
1642 ar8327_init_globals(struct ar8xxx_priv
*priv
)
1646 /* enable CPU port and disable mirror port */
1647 t
= AR8327_FWD_CTRL0_CPU_PORT_EN
|
1648 AR8327_FWD_CTRL0_MIRROR_PORT
;
1649 priv
->write(priv
, AR8327_REG_FWD_CTRL0
, t
);
1651 /* forward multicast and broadcast frames to CPU */
1652 t
= (AR8327_PORTS_ALL
<< AR8327_FWD_CTRL1_UC_FLOOD_S
) |
1653 (AR8327_PORTS_ALL
<< AR8327_FWD_CTRL1_MC_FLOOD_S
) |
1654 (AR8327_PORTS_ALL
<< AR8327_FWD_CTRL1_BC_FLOOD_S
);
1655 priv
->write(priv
, AR8327_REG_FWD_CTRL1
, t
);
1657 /* enable jumbo frames */
1658 ar8xxx_rmw(priv
, AR8327_REG_MAX_FRAME_SIZE
,
1659 AR8327_MAX_FRAME_SIZE_MTU
, 9018 + 8 + 2);
1661 /* Enable MIB counters */
1662 ar8xxx_reg_set(priv
, AR8327_REG_MODULE_EN
,
1663 AR8327_MODULE_EN_MIB
);
1665 /* Disable EEE on all ports due to stability issues */
1666 t
= priv
->read(priv
, AR8327_REG_EEE_CTRL
);
1667 t
|= AR8327_EEE_CTRL_DISABLE_PHY(0) |
1668 AR8327_EEE_CTRL_DISABLE_PHY(1) |
1669 AR8327_EEE_CTRL_DISABLE_PHY(2) |
1670 AR8327_EEE_CTRL_DISABLE_PHY(3) |
1671 AR8327_EEE_CTRL_DISABLE_PHY(4);
1672 priv
->write(priv
, AR8327_REG_EEE_CTRL
, t
);
1676 ar8327_init_port(struct ar8xxx_priv
*priv
, int port
)
1680 if (port
== AR8216_PORT_CPU
)
1681 t
= priv
->chip_data
.ar8327
.port0_status
;
1683 t
= priv
->chip_data
.ar8327
.port6_status
;
1685 t
= AR8216_PORT_STATUS_LINK_AUTO
;
1687 priv
->write(priv
, AR8327_REG_PORT_STATUS(port
), t
);
1688 priv
->write(priv
, AR8327_REG_PORT_HEADER(port
), 0);
1690 t
= 1 << AR8327_PORT_VLAN0_DEF_SVID_S
;
1691 t
|= 1 << AR8327_PORT_VLAN0_DEF_CVID_S
;
1692 priv
->write(priv
, AR8327_REG_PORT_VLAN0(port
), t
);
1694 t
= AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH
<< AR8327_PORT_VLAN1_OUT_MODE_S
;
1695 priv
->write(priv
, AR8327_REG_PORT_VLAN1(port
), t
);
1697 t
= AR8327_PORT_LOOKUP_LEARN
;
1698 t
|= AR8216_PORT_STATE_FORWARD
<< AR8327_PORT_LOOKUP_STATE_S
;
1699 priv
->write(priv
, AR8327_REG_PORT_LOOKUP(port
), t
);
1703 ar8327_read_port_status(struct ar8xxx_priv
*priv
, int port
)
1705 return priv
->read(priv
, AR8327_REG_PORT_STATUS(port
));
1709 ar8327_atu_flush(struct ar8xxx_priv
*priv
)
1713 ret
= ar8216_wait_bit(priv
, AR8327_REG_ATU_FUNC
,
1714 AR8327_ATU_FUNC_BUSY
, 0);
1716 priv
->write(priv
, AR8327_REG_ATU_FUNC
,
1717 AR8327_ATU_FUNC_OP_FLUSH
);
1723 ar8327_vtu_op(struct ar8xxx_priv
*priv
, u32 op
, u32 val
)
1725 if (ar8216_wait_bit(priv
, AR8327_REG_VTU_FUNC1
,
1726 AR8327_VTU_FUNC1_BUSY
, 0))
1729 if ((op
& AR8327_VTU_FUNC1_OP
) == AR8327_VTU_FUNC1_OP_LOAD
)
1730 priv
->write(priv
, AR8327_REG_VTU_FUNC0
, val
);
1732 op
|= AR8327_VTU_FUNC1_BUSY
;
1733 priv
->write(priv
, AR8327_REG_VTU_FUNC1
, op
);
1737 ar8327_vtu_flush(struct ar8xxx_priv
*priv
)
1739 ar8327_vtu_op(priv
, AR8327_VTU_FUNC1_OP_FLUSH
, 0);
1743 ar8327_vtu_load_vlan(struct ar8xxx_priv
*priv
, u32 vid
, u32 port_mask
)
1749 op
= AR8327_VTU_FUNC1_OP_LOAD
| (vid
<< AR8327_VTU_FUNC1_VID_S
);
1750 val
= AR8327_VTU_FUNC0_VALID
| AR8327_VTU_FUNC0_IVL
;
1751 for (i
= 0; i
< AR8327_NUM_PORTS
; i
++) {
1754 if ((port_mask
& BIT(i
)) == 0)
1755 mode
= AR8327_VTU_FUNC0_EG_MODE_NOT
;
1756 else if (priv
->vlan
== 0)
1757 mode
= AR8327_VTU_FUNC0_EG_MODE_KEEP
;
1758 else if ((priv
->vlan_tagged
& BIT(i
)) || (priv
->vlan_id
[priv
->pvid
[i
]] != vid
))
1759 mode
= AR8327_VTU_FUNC0_EG_MODE_TAG
;
1761 mode
= AR8327_VTU_FUNC0_EG_MODE_UNTAG
;
1763 val
|= mode
<< AR8327_VTU_FUNC0_EG_MODE_S(i
);
1765 ar8327_vtu_op(priv
, op
, val
);
1769 ar8327_setup_port(struct ar8xxx_priv
*priv
, int port
, u32 members
)
1772 u32 egress
, ingress
;
1773 u32 pvid
= priv
->vlan_id
[priv
->pvid
[port
]];
1776 egress
= AR8327_PORT_VLAN1_OUT_MODE_UNMOD
;
1777 ingress
= AR8216_IN_SECURE
;
1779 egress
= AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH
;
1780 ingress
= AR8216_IN_PORT_ONLY
;
1783 t
= pvid
<< AR8327_PORT_VLAN0_DEF_SVID_S
;
1784 t
|= pvid
<< AR8327_PORT_VLAN0_DEF_CVID_S
;
1785 priv
->write(priv
, AR8327_REG_PORT_VLAN0(port
), t
);
1787 t
= AR8327_PORT_VLAN1_PORT_VLAN_PROP
;
1788 t
|= egress
<< AR8327_PORT_VLAN1_OUT_MODE_S
;
1789 priv
->write(priv
, AR8327_REG_PORT_VLAN1(port
), t
);
1792 t
|= AR8327_PORT_LOOKUP_LEARN
;
1793 t
|= ingress
<< AR8327_PORT_LOOKUP_IN_MODE_S
;
1794 t
|= AR8216_PORT_STATE_FORWARD
<< AR8327_PORT_LOOKUP_STATE_S
;
1795 priv
->write(priv
, AR8327_REG_PORT_LOOKUP(port
), t
);
1798 static const struct ar8xxx_chip ar8327_chip
= {
1799 .caps
= AR8XXX_CAP_GIGE
| AR8XXX_CAP_MIB_COUNTERS
,
1800 .hw_init
= ar8327_hw_init
,
1801 .cleanup
= ar8327_cleanup
,
1802 .init_globals
= ar8327_init_globals
,
1803 .init_port
= ar8327_init_port
,
1804 .setup_port
= ar8327_setup_port
,
1805 .read_port_status
= ar8327_read_port_status
,
1806 .atu_flush
= ar8327_atu_flush
,
1807 .vtu_flush
= ar8327_vtu_flush
,
1808 .vtu_load_vlan
= ar8327_vtu_load_vlan
,
1809 .phy_fixup
= ar8327_phy_fixup
,
1811 .num_mibs
= ARRAY_SIZE(ar8236_mibs
),
1812 .mib_decs
= ar8236_mibs
,
1816 ar8xxx_sw_set_vlan(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1817 struct switch_val
*val
)
1819 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1820 priv
->vlan
= !!val
->value
.i
;
1825 ar8xxx_sw_get_vlan(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1826 struct switch_val
*val
)
1828 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1829 val
->value
.i
= priv
->vlan
;
1835 ar8xxx_sw_set_pvid(struct switch_dev
*dev
, int port
, int vlan
)
1837 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1839 /* make sure no invalid PVIDs get set */
1841 if (vlan
>= dev
->vlans
)
1844 priv
->pvid
[port
] = vlan
;
1849 ar8xxx_sw_get_pvid(struct switch_dev
*dev
, int port
, int *vlan
)
1851 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1852 *vlan
= priv
->pvid
[port
];
1857 ar8xxx_sw_set_vid(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1858 struct switch_val
*val
)
1860 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1861 priv
->vlan_id
[val
->port_vlan
] = val
->value
.i
;
1866 ar8xxx_sw_get_vid(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1867 struct switch_val
*val
)
1869 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1870 val
->value
.i
= priv
->vlan_id
[val
->port_vlan
];
1875 ar8xxx_sw_get_port_link(struct switch_dev
*dev
, int port
,
1876 struct switch_port_link
*link
)
1878 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1880 ar8216_read_port_link(priv
, port
, link
);
1885 ar8xxx_sw_get_ports(struct switch_dev
*dev
, struct switch_val
*val
)
1887 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1888 u8 ports
= priv
->vlan_table
[val
->port_vlan
];
1892 for (i
= 0; i
< dev
->ports
; i
++) {
1893 struct switch_port
*p
;
1895 if (!(ports
& (1 << i
)))
1898 p
= &val
->value
.ports
[val
->len
++];
1900 if (priv
->vlan_tagged
& (1 << i
))
1901 p
->flags
= (1 << SWITCH_PORT_FLAG_TAGGED
);
1909 ar8327_sw_get_ports(struct switch_dev
*dev
, struct switch_val
*val
)
1911 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1912 u8 ports
= priv
->vlan_table
[val
->port_vlan
];
1916 for (i
= 0; i
< dev
->ports
; i
++) {
1917 struct switch_port
*p
;
1919 if (!(ports
& (1 << i
)))
1922 p
= &val
->value
.ports
[val
->len
++];
1924 if ((priv
->vlan_tagged
& (1 << i
)) || (priv
->pvid
[i
] != val
->port_vlan
))
1925 p
->flags
= (1 << SWITCH_PORT_FLAG_TAGGED
);
1933 ar8xxx_sw_set_ports(struct switch_dev
*dev
, struct switch_val
*val
)
1935 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1936 u8
*vt
= &priv
->vlan_table
[val
->port_vlan
];
1940 for (i
= 0; i
< val
->len
; i
++) {
1941 struct switch_port
*p
= &val
->value
.ports
[i
];
1943 if (p
->flags
& (1 << SWITCH_PORT_FLAG_TAGGED
)) {
1944 priv
->vlan_tagged
|= (1 << p
->id
);
1946 priv
->vlan_tagged
&= ~(1 << p
->id
);
1947 priv
->pvid
[p
->id
] = val
->port_vlan
;
1949 /* make sure that an untagged port does not
1950 * appear in other vlans */
1951 for (j
= 0; j
< AR8X16_MAX_VLANS
; j
++) {
1952 if (j
== val
->port_vlan
)
1954 priv
->vlan_table
[j
] &= ~(1 << p
->id
);
1964 ar8327_sw_set_ports(struct switch_dev
*dev
, struct switch_val
*val
)
1966 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1967 u8
*vt
= &priv
->vlan_table
[val
->port_vlan
];
1971 for (i
= 0; i
< val
->len
; i
++) {
1972 struct switch_port
*p
= &val
->value
.ports
[i
];
1974 if (p
->flags
& (1 << SWITCH_PORT_FLAG_TAGGED
)) {
1975 if (val
->port_vlan
== priv
->pvid
[p
->id
]) {
1976 priv
->vlan_tagged
|= (1 << p
->id
);
1979 priv
->vlan_tagged
&= ~(1 << p
->id
);
1980 priv
->pvid
[p
->id
] = val
->port_vlan
;
1989 ar8327_set_mirror_regs(struct ar8xxx_priv
*priv
)
1993 /* reset all mirror registers */
1994 ar8xxx_rmw(priv
, AR8327_REG_FWD_CTRL0
,
1995 AR8327_FWD_CTRL0_MIRROR_PORT
,
1996 (0xF << AR8327_FWD_CTRL0_MIRROR_PORT_S
));
1997 for (port
= 0; port
< AR8327_NUM_PORTS
; port
++) {
1998 ar8xxx_rmw(priv
, AR8327_REG_PORT_LOOKUP(port
),
1999 AR8327_PORT_LOOKUP_ING_MIRROR_EN
,
2002 ar8xxx_rmw(priv
, AR8327_REG_PORT_HOL_CTRL1(port
),
2003 AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN
,
2007 /* now enable mirroring if necessary */
2008 if (priv
->source_port
>= AR8327_NUM_PORTS
||
2009 priv
->monitor_port
>= AR8327_NUM_PORTS
||
2010 priv
->source_port
== priv
->monitor_port
) {
2014 ar8xxx_rmw(priv
, AR8327_REG_FWD_CTRL0
,
2015 AR8327_FWD_CTRL0_MIRROR_PORT
,
2016 (priv
->monitor_port
<< AR8327_FWD_CTRL0_MIRROR_PORT_S
));
2018 if (priv
->mirror_rx
)
2019 ar8xxx_rmw(priv
, AR8327_REG_PORT_LOOKUP(priv
->source_port
),
2020 AR8327_PORT_LOOKUP_ING_MIRROR_EN
,
2021 AR8327_PORT_LOOKUP_ING_MIRROR_EN
);
2023 if (priv
->mirror_tx
)
2024 ar8xxx_rmw(priv
, AR8327_REG_PORT_HOL_CTRL1(priv
->source_port
),
2025 AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN
,
2026 AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN
);
2030 ar8216_set_mirror_regs(struct ar8xxx_priv
*priv
)
2034 /* reset all mirror registers */
2035 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CPUPORT
,
2036 AR8216_GLOBAL_CPUPORT_MIRROR_PORT
,
2037 (0xF << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S
));
2038 for (port
= 0; port
< AR8216_NUM_PORTS
; port
++) {
2039 ar8xxx_rmw(priv
, AR8216_REG_PORT_CTRL(port
),
2040 AR8216_PORT_CTRL_MIRROR_RX
,
2043 ar8xxx_rmw(priv
, AR8216_REG_PORT_CTRL(port
),
2044 AR8216_PORT_CTRL_MIRROR_TX
,
2048 /* now enable mirroring if necessary */
2049 if (priv
->source_port
>= AR8216_NUM_PORTS
||
2050 priv
->monitor_port
>= AR8216_NUM_PORTS
||
2051 priv
->source_port
== priv
->monitor_port
) {
2055 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CPUPORT
,
2056 AR8216_GLOBAL_CPUPORT_MIRROR_PORT
,
2057 (priv
->monitor_port
<< AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S
));
2059 if (priv
->mirror_rx
)
2060 ar8xxx_rmw(priv
, AR8216_REG_PORT_CTRL(priv
->source_port
),
2061 AR8216_PORT_CTRL_MIRROR_RX
,
2062 AR8216_PORT_CTRL_MIRROR_RX
);
2064 if (priv
->mirror_tx
)
2065 ar8xxx_rmw(priv
, AR8216_REG_PORT_CTRL(priv
->source_port
),
2066 AR8216_PORT_CTRL_MIRROR_TX
,
2067 AR8216_PORT_CTRL_MIRROR_TX
);
2071 ar8xxx_set_mirror_regs(struct ar8xxx_priv
*priv
)
2073 if (chip_is_ar8327(priv
) || chip_is_ar8337(priv
)) {
2074 ar8327_set_mirror_regs(priv
);
2076 ar8216_set_mirror_regs(priv
);
2081 ar8xxx_sw_hw_apply(struct switch_dev
*dev
)
2083 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
2084 u8 portmask
[AR8X16_MAX_PORTS
];
2087 mutex_lock(&priv
->reg_mutex
);
2088 /* flush all vlan translation unit entries */
2089 priv
->chip
->vtu_flush(priv
);
2091 memset(portmask
, 0, sizeof(portmask
));
2093 /* calculate the port destination masks and load vlans
2094 * into the vlan translation unit */
2095 for (j
= 0; j
< AR8X16_MAX_VLANS
; j
++) {
2096 u8 vp
= priv
->vlan_table
[j
];
2101 for (i
= 0; i
< dev
->ports
; i
++) {
2104 portmask
[i
] |= vp
& ~mask
;
2107 priv
->chip
->vtu_load_vlan(priv
, priv
->vlan_id
[j
],
2108 priv
->vlan_table
[j
]);
2112 * isolate all ports, but connect them to the cpu port */
2113 for (i
= 0; i
< dev
->ports
; i
++) {
2114 if (i
== AR8216_PORT_CPU
)
2117 portmask
[i
] = 1 << AR8216_PORT_CPU
;
2118 portmask
[AR8216_PORT_CPU
] |= (1 << i
);
2122 /* update the port destination mask registers and tag settings */
2123 for (i
= 0; i
< dev
->ports
; i
++) {
2124 priv
->chip
->setup_port(priv
, i
, portmask
[i
]);
2127 ar8xxx_set_mirror_regs(priv
);
2129 mutex_unlock(&priv
->reg_mutex
);
2134 ar8xxx_sw_reset_switch(struct switch_dev
*dev
)
2136 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
2139 mutex_lock(&priv
->reg_mutex
);
2140 memset(&priv
->vlan
, 0, sizeof(struct ar8xxx_priv
) -
2141 offsetof(struct ar8xxx_priv
, vlan
));
2143 for (i
= 0; i
< AR8X16_MAX_VLANS
; i
++)
2144 priv
->vlan_id
[i
] = i
;
2146 /* Configure all ports */
2147 for (i
= 0; i
< dev
->ports
; i
++)
2148 priv
->chip
->init_port(priv
, i
);
2150 priv
->mirror_rx
= false;
2151 priv
->mirror_tx
= false;
2152 priv
->source_port
= 0;
2153 priv
->monitor_port
= 0;
2155 priv
->chip
->init_globals(priv
);
2157 mutex_unlock(&priv
->reg_mutex
);
2159 return ar8xxx_sw_hw_apply(dev
);
2163 ar8xxx_sw_set_reset_mibs(struct switch_dev
*dev
,
2164 const struct switch_attr
*attr
,
2165 struct switch_val
*val
)
2167 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
2171 if (!ar8xxx_has_mib_counters(priv
))
2174 mutex_lock(&priv
->mib_lock
);
2176 len
= priv
->dev
.ports
* priv
->chip
->num_mibs
*
2177 sizeof(*priv
->mib_stats
);
2178 memset(priv
->mib_stats
, '\0', len
);
2179 ret
= ar8xxx_mib_flush(priv
);
2186 mutex_unlock(&priv
->mib_lock
);
2191 ar8xxx_sw_set_mirror_rx_enable(struct switch_dev
*dev
,
2192 const struct switch_attr
*attr
,
2193 struct switch_val
*val
)
2195 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
2197 mutex_lock(&priv
->reg_mutex
);
2198 priv
->mirror_rx
= !!val
->value
.i
;
2199 ar8xxx_set_mirror_regs(priv
);
2200 mutex_unlock(&priv
->reg_mutex
);
2206 ar8xxx_sw_get_mirror_rx_enable(struct switch_dev
*dev
,
2207 const struct switch_attr
*attr
,
2208 struct switch_val
*val
)
2210 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
2211 val
->value
.i
= priv
->mirror_rx
;
2216 ar8xxx_sw_set_mirror_tx_enable(struct switch_dev
*dev
,
2217 const struct switch_attr
*attr
,
2218 struct switch_val
*val
)
2220 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
2222 mutex_lock(&priv
->reg_mutex
);
2223 priv
->mirror_tx
= !!val
->value
.i
;
2224 ar8xxx_set_mirror_regs(priv
);
2225 mutex_unlock(&priv
->reg_mutex
);
2231 ar8xxx_sw_get_mirror_tx_enable(struct switch_dev
*dev
,
2232 const struct switch_attr
*attr
,
2233 struct switch_val
*val
)
2235 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
2236 val
->value
.i
= priv
->mirror_tx
;
2241 ar8xxx_sw_set_mirror_monitor_port(struct switch_dev
*dev
,
2242 const struct switch_attr
*attr
,
2243 struct switch_val
*val
)
2245 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
2247 mutex_lock(&priv
->reg_mutex
);
2248 priv
->monitor_port
= val
->value
.i
;
2249 ar8xxx_set_mirror_regs(priv
);
2250 mutex_unlock(&priv
->reg_mutex
);
2256 ar8xxx_sw_get_mirror_monitor_port(struct switch_dev
*dev
,
2257 const struct switch_attr
*attr
,
2258 struct switch_val
*val
)
2260 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
2261 val
->value
.i
= priv
->monitor_port
;
2266 ar8xxx_sw_set_mirror_source_port(struct switch_dev
*dev
,
2267 const struct switch_attr
*attr
,
2268 struct switch_val
*val
)
2270 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
2272 mutex_lock(&priv
->reg_mutex
);
2273 priv
->source_port
= val
->value
.i
;
2274 ar8xxx_set_mirror_regs(priv
);
2275 mutex_unlock(&priv
->reg_mutex
);
2281 ar8xxx_sw_get_mirror_source_port(struct switch_dev
*dev
,
2282 const struct switch_attr
*attr
,
2283 struct switch_val
*val
)
2285 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
2286 val
->value
.i
= priv
->source_port
;
2291 ar8xxx_sw_set_port_reset_mib(struct switch_dev
*dev
,
2292 const struct switch_attr
*attr
,
2293 struct switch_val
*val
)
2295 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
2299 if (!ar8xxx_has_mib_counters(priv
))
2302 port
= val
->port_vlan
;
2303 if (port
>= dev
->ports
)
2306 mutex_lock(&priv
->mib_lock
);
2307 ret
= ar8xxx_mib_capture(priv
);
2311 ar8xxx_mib_fetch_port_stat(priv
, port
, true);
2316 mutex_unlock(&priv
->mib_lock
);
2321 ar8xxx_sw_get_port_mib(struct switch_dev
*dev
,
2322 const struct switch_attr
*attr
,
2323 struct switch_val
*val
)
2325 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
2326 const struct ar8xxx_chip
*chip
= priv
->chip
;
2330 char *buf
= priv
->buf
;
2333 if (!ar8xxx_has_mib_counters(priv
))
2336 port
= val
->port_vlan
;
2337 if (port
>= dev
->ports
)
2340 mutex_lock(&priv
->mib_lock
);
2341 ret
= ar8xxx_mib_capture(priv
);
2345 ar8xxx_mib_fetch_port_stat(priv
, port
, false);
2347 len
+= snprintf(buf
+ len
, sizeof(priv
->buf
) - len
,
2348 "Port %d MIB counters\n",
2351 mib_stats
= &priv
->mib_stats
[port
* chip
->num_mibs
];
2352 for (i
= 0; i
< chip
->num_mibs
; i
++)
2353 len
+= snprintf(buf
+ len
, sizeof(priv
->buf
) - len
,
2355 chip
->mib_decs
[i
].name
,
2364 mutex_unlock(&priv
->mib_lock
);
2368 static struct switch_attr ar8xxx_sw_attr_globals
[] = {
2370 .type
= SWITCH_TYPE_INT
,
2371 .name
= "enable_vlan",
2372 .description
= "Enable VLAN mode",
2373 .set
= ar8xxx_sw_set_vlan
,
2374 .get
= ar8xxx_sw_get_vlan
,
2378 .type
= SWITCH_TYPE_NOVAL
,
2379 .name
= "reset_mibs",
2380 .description
= "Reset all MIB counters",
2381 .set
= ar8xxx_sw_set_reset_mibs
,
2384 .type
= SWITCH_TYPE_INT
,
2385 .name
= "enable_mirror_rx",
2386 .description
= "Enable mirroring of RX packets",
2387 .set
= ar8xxx_sw_set_mirror_rx_enable
,
2388 .get
= ar8xxx_sw_get_mirror_rx_enable
,
2392 .type
= SWITCH_TYPE_INT
,
2393 .name
= "enable_mirror_tx",
2394 .description
= "Enable mirroring of TX packets",
2395 .set
= ar8xxx_sw_set_mirror_tx_enable
,
2396 .get
= ar8xxx_sw_get_mirror_tx_enable
,
2400 .type
= SWITCH_TYPE_INT
,
2401 .name
= "mirror_monitor_port",
2402 .description
= "Mirror monitor port",
2403 .set
= ar8xxx_sw_set_mirror_monitor_port
,
2404 .get
= ar8xxx_sw_get_mirror_monitor_port
,
2405 .max
= AR8216_NUM_PORTS
- 1
2408 .type
= SWITCH_TYPE_INT
,
2409 .name
= "mirror_source_port",
2410 .description
= "Mirror source port",
2411 .set
= ar8xxx_sw_set_mirror_source_port
,
2412 .get
= ar8xxx_sw_get_mirror_source_port
,
2413 .max
= AR8216_NUM_PORTS
- 1
2417 static struct switch_attr ar8327_sw_attr_globals
[] = {
2419 .type
= SWITCH_TYPE_INT
,
2420 .name
= "enable_vlan",
2421 .description
= "Enable VLAN mode",
2422 .set
= ar8xxx_sw_set_vlan
,
2423 .get
= ar8xxx_sw_get_vlan
,
2427 .type
= SWITCH_TYPE_NOVAL
,
2428 .name
= "reset_mibs",
2429 .description
= "Reset all MIB counters",
2430 .set
= ar8xxx_sw_set_reset_mibs
,
2433 .type
= SWITCH_TYPE_INT
,
2434 .name
= "enable_mirror_rx",
2435 .description
= "Enable mirroring of RX packets",
2436 .set
= ar8xxx_sw_set_mirror_rx_enable
,
2437 .get
= ar8xxx_sw_get_mirror_rx_enable
,
2441 .type
= SWITCH_TYPE_INT
,
2442 .name
= "enable_mirror_tx",
2443 .description
= "Enable mirroring of TX packets",
2444 .set
= ar8xxx_sw_set_mirror_tx_enable
,
2445 .get
= ar8xxx_sw_get_mirror_tx_enable
,
2449 .type
= SWITCH_TYPE_INT
,
2450 .name
= "mirror_monitor_port",
2451 .description
= "Mirror monitor port",
2452 .set
= ar8xxx_sw_set_mirror_monitor_port
,
2453 .get
= ar8xxx_sw_get_mirror_monitor_port
,
2454 .max
= AR8327_NUM_PORTS
- 1
2457 .type
= SWITCH_TYPE_INT
,
2458 .name
= "mirror_source_port",
2459 .description
= "Mirror source port",
2460 .set
= ar8xxx_sw_set_mirror_source_port
,
2461 .get
= ar8xxx_sw_get_mirror_source_port
,
2462 .max
= AR8327_NUM_PORTS
- 1
2466 static struct switch_attr ar8xxx_sw_attr_port
[] = {
2468 .type
= SWITCH_TYPE_NOVAL
,
2469 .name
= "reset_mib",
2470 .description
= "Reset single port MIB counters",
2471 .set
= ar8xxx_sw_set_port_reset_mib
,
2474 .type
= SWITCH_TYPE_STRING
,
2476 .description
= "Get port's MIB counters",
2478 .get
= ar8xxx_sw_get_port_mib
,
2482 static struct switch_attr ar8xxx_sw_attr_vlan
[] = {
2484 .type
= SWITCH_TYPE_INT
,
2486 .description
= "VLAN ID (0-4094)",
2487 .set
= ar8xxx_sw_set_vid
,
2488 .get
= ar8xxx_sw_get_vid
,
2493 static const struct switch_dev_ops ar8xxx_sw_ops
= {
2495 .attr
= ar8xxx_sw_attr_globals
,
2496 .n_attr
= ARRAY_SIZE(ar8xxx_sw_attr_globals
),
2499 .attr
= ar8xxx_sw_attr_port
,
2500 .n_attr
= ARRAY_SIZE(ar8xxx_sw_attr_port
),
2503 .attr
= ar8xxx_sw_attr_vlan
,
2504 .n_attr
= ARRAY_SIZE(ar8xxx_sw_attr_vlan
),
2506 .get_port_pvid
= ar8xxx_sw_get_pvid
,
2507 .set_port_pvid
= ar8xxx_sw_set_pvid
,
2508 .get_vlan_ports
= ar8xxx_sw_get_ports
,
2509 .set_vlan_ports
= ar8xxx_sw_set_ports
,
2510 .apply_config
= ar8xxx_sw_hw_apply
,
2511 .reset_switch
= ar8xxx_sw_reset_switch
,
2512 .get_port_link
= ar8xxx_sw_get_port_link
,
2515 static const struct switch_dev_ops ar8327_sw_ops
= {
2517 .attr
= ar8327_sw_attr_globals
,
2518 .n_attr
= ARRAY_SIZE(ar8327_sw_attr_globals
),
2521 .attr
= ar8xxx_sw_attr_port
,
2522 .n_attr
= ARRAY_SIZE(ar8xxx_sw_attr_port
),
2525 .attr
= ar8xxx_sw_attr_vlan
,
2526 .n_attr
= ARRAY_SIZE(ar8xxx_sw_attr_vlan
),
2528 .get_port_pvid
= ar8xxx_sw_get_pvid
,
2529 .set_port_pvid
= ar8xxx_sw_set_pvid
,
2530 .get_vlan_ports
= ar8327_sw_get_ports
,
2531 .set_vlan_ports
= ar8327_sw_set_ports
,
2532 .apply_config
= ar8xxx_sw_hw_apply
,
2533 .reset_switch
= ar8xxx_sw_reset_switch
,
2534 .get_port_link
= ar8xxx_sw_get_port_link
,
2538 ar8xxx_id_chip(struct ar8xxx_priv
*priv
)
2544 val
= priv
->read(priv
, AR8216_REG_CTRL
);
2548 id
= val
& (AR8216_CTRL_REVISION
| AR8216_CTRL_VERSION
);
2549 for (i
= 0; i
< AR8X16_PROBE_RETRIES
; i
++) {
2552 val
= priv
->read(priv
, AR8216_REG_CTRL
);
2556 t
= val
& (AR8216_CTRL_REVISION
| AR8216_CTRL_VERSION
);
2561 priv
->chip_ver
= (id
& AR8216_CTRL_VERSION
) >> AR8216_CTRL_VERSION_S
;
2562 priv
->chip_rev
= (id
& AR8216_CTRL_REVISION
);
2564 switch (priv
->chip_ver
) {
2565 case AR8XXX_VER_AR8216
:
2566 priv
->chip
= &ar8216_chip
;
2568 case AR8XXX_VER_AR8236
:
2569 priv
->chip
= &ar8236_chip
;
2571 case AR8XXX_VER_AR8316
:
2572 priv
->chip
= &ar8316_chip
;
2574 case AR8XXX_VER_AR8327
:
2575 priv
->mii_lo_first
= true;
2576 priv
->chip
= &ar8327_chip
;
2578 case AR8XXX_VER_AR8337
:
2579 priv
->mii_lo_first
= true;
2580 priv
->chip
= &ar8327_chip
;
2583 pr_err("ar8216: Unknown Atheros device [ver=%d, rev=%d]\n",
2584 priv
->chip_ver
, priv
->chip_rev
);
2593 ar8xxx_mib_work_func(struct work_struct
*work
)
2595 struct ar8xxx_priv
*priv
;
2598 priv
= container_of(work
, struct ar8xxx_priv
, mib_work
.work
);
2600 mutex_lock(&priv
->mib_lock
);
2602 err
= ar8xxx_mib_capture(priv
);
2606 ar8xxx_mib_fetch_port_stat(priv
, priv
->mib_next_port
, false);
2609 priv
->mib_next_port
++;
2610 if (priv
->mib_next_port
>= priv
->dev
.ports
)
2611 priv
->mib_next_port
= 0;
2613 mutex_unlock(&priv
->mib_lock
);
2614 schedule_delayed_work(&priv
->mib_work
,
2615 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY
));
2619 ar8xxx_mib_init(struct ar8xxx_priv
*priv
)
2623 if (!ar8xxx_has_mib_counters(priv
))
2626 BUG_ON(!priv
->chip
->mib_decs
|| !priv
->chip
->num_mibs
);
2628 len
= priv
->dev
.ports
* priv
->chip
->num_mibs
*
2629 sizeof(*priv
->mib_stats
);
2630 priv
->mib_stats
= kzalloc(len
, GFP_KERNEL
);
2632 if (!priv
->mib_stats
)
2639 ar8xxx_mib_start(struct ar8xxx_priv
*priv
)
2641 if (!ar8xxx_has_mib_counters(priv
))
2644 schedule_delayed_work(&priv
->mib_work
,
2645 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY
));
2649 ar8xxx_mib_stop(struct ar8xxx_priv
*priv
)
2651 if (!ar8xxx_has_mib_counters(priv
))
2654 cancel_delayed_work(&priv
->mib_work
);
2657 static struct ar8xxx_priv
*
2660 struct ar8xxx_priv
*priv
;
2662 priv
= kzalloc(sizeof(struct ar8xxx_priv
), GFP_KERNEL
);
2666 mutex_init(&priv
->reg_mutex
);
2667 mutex_init(&priv
->mib_lock
);
2668 INIT_DELAYED_WORK(&priv
->mib_work
, ar8xxx_mib_work_func
);
2674 ar8xxx_free(struct ar8xxx_priv
*priv
)
2676 if (priv
->chip
&& priv
->chip
->cleanup
)
2677 priv
->chip
->cleanup(priv
);
2679 kfree(priv
->mib_stats
);
2683 static struct ar8xxx_priv
*
2684 ar8xxx_create_mii(struct mii_bus
*bus
)
2686 struct ar8xxx_priv
*priv
;
2688 priv
= ar8xxx_create();
2690 priv
->mii_bus
= bus
;
2691 priv
->read
= ar8xxx_mii_read
;
2692 priv
->write
= ar8xxx_mii_write
;
2693 priv
->rmw
= ar8xxx_mii_rmw
;
2700 ar8xxx_probe_switch(struct ar8xxx_priv
*priv
)
2702 struct switch_dev
*swdev
;
2705 ret
= ar8xxx_id_chip(priv
);
2710 swdev
->cpu_port
= AR8216_PORT_CPU
;
2711 swdev
->ops
= &ar8xxx_sw_ops
;
2713 if (chip_is_ar8316(priv
)) {
2714 swdev
->name
= "Atheros AR8316";
2715 swdev
->vlans
= AR8X16_MAX_VLANS
;
2716 swdev
->ports
= AR8216_NUM_PORTS
;
2717 } else if (chip_is_ar8236(priv
)) {
2718 swdev
->name
= "Atheros AR8236";
2719 swdev
->vlans
= AR8216_NUM_VLANS
;
2720 swdev
->ports
= AR8216_NUM_PORTS
;
2721 } else if (chip_is_ar8327(priv
)) {
2722 swdev
->name
= "Atheros AR8327";
2723 swdev
->vlans
= AR8X16_MAX_VLANS
;
2724 swdev
->ports
= AR8327_NUM_PORTS
;
2725 swdev
->ops
= &ar8327_sw_ops
;
2726 } else if (chip_is_ar8337(priv
)) {
2727 swdev
->name
= "Atheros AR8337";
2728 swdev
->vlans
= AR8X16_MAX_VLANS
;
2729 swdev
->ports
= AR8327_NUM_PORTS
;
2730 swdev
->ops
= &ar8327_sw_ops
;
2732 swdev
->name
= "Atheros AR8216";
2733 swdev
->vlans
= AR8216_NUM_VLANS
;
2734 swdev
->ports
= AR8216_NUM_PORTS
;
2737 ret
= ar8xxx_mib_init(priv
);
2745 ar8xxx_start(struct ar8xxx_priv
*priv
)
2751 ret
= priv
->chip
->hw_init(priv
);
2755 ret
= ar8xxx_sw_reset_switch(&priv
->dev
);
2761 ar8xxx_mib_start(priv
);
2767 ar8xxx_phy_config_init(struct phy_device
*phydev
)
2769 struct ar8xxx_priv
*priv
= phydev
->priv
;
2770 struct net_device
*dev
= phydev
->attached_dev
;
2776 if (chip_is_ar8327(priv
) || chip_is_ar8337(priv
))
2781 if (phydev
->addr
!= 0) {
2782 if (chip_is_ar8316(priv
)) {
2783 /* switch device has been initialized, reinit */
2784 priv
->dev
.ports
= (AR8216_NUM_PORTS
- 1);
2785 priv
->initialized
= false;
2786 priv
->port4_phy
= true;
2787 ar8316_hw_init(priv
);
2794 ret
= ar8xxx_start(priv
);
2798 /* VID fixup only needed on ar8216 */
2799 if (chip_is_ar8216(priv
)) {
2800 dev
->phy_ptr
= priv
;
2801 dev
->priv_flags
|= IFF_NO_IP_ALIGN
;
2802 dev
->eth_mangle_rx
= ar8216_mangle_rx
;
2803 dev
->eth_mangle_tx
= ar8216_mangle_tx
;
2810 ar8xxx_phy_read_status(struct phy_device
*phydev
)
2812 struct ar8xxx_priv
*priv
= phydev
->priv
;
2813 struct switch_port_link link
;
2816 if (phydev
->addr
!= 0)
2817 return genphy_read_status(phydev
);
2819 ar8216_read_port_link(priv
, phydev
->addr
, &link
);
2820 phydev
->link
= !!link
.link
;
2824 switch (link
.speed
) {
2825 case SWITCH_PORT_SPEED_10
:
2826 phydev
->speed
= SPEED_10
;
2828 case SWITCH_PORT_SPEED_100
:
2829 phydev
->speed
= SPEED_100
;
2831 case SWITCH_PORT_SPEED_1000
:
2832 phydev
->speed
= SPEED_1000
;
2837 phydev
->duplex
= link
.duplex
? DUPLEX_FULL
: DUPLEX_HALF
;
2839 /* flush the address translation unit */
2840 mutex_lock(&priv
->reg_mutex
);
2841 ret
= priv
->chip
->atu_flush(priv
);
2842 mutex_unlock(&priv
->reg_mutex
);
2844 phydev
->state
= PHY_RUNNING
;
2845 netif_carrier_on(phydev
->attached_dev
);
2846 phydev
->adjust_link(phydev
->attached_dev
);
2851 static const u32 ar8xxx_phy_ids
[] = {
2853 0x004dd034, /* AR8327 */
2854 0x004dd036, /* AR8337 */
2857 0x004dd043, /* AR8236 */
2861 ar8xxx_phy_match(u32 phy_id
)
2865 for (i
= 0; i
< ARRAY_SIZE(ar8xxx_phy_ids
); i
++)
2866 if (phy_id
== ar8xxx_phy_ids
[i
])
2873 ar8xxx_is_possible(struct mii_bus
*bus
)
2877 for (i
= 0; i
< 4; i
++) {
2880 phy_id
= mdiobus_read(bus
, i
, MII_PHYSID1
) << 16;
2881 phy_id
|= mdiobus_read(bus
, i
, MII_PHYSID2
);
2882 if (!ar8xxx_phy_match(phy_id
)) {
2883 pr_debug("ar8xxx: unknown PHY at %s:%02x id:%08x\n",
2884 dev_name(&bus
->dev
), i
, phy_id
);
2893 ar8xxx_phy_probe(struct phy_device
*phydev
)
2895 struct ar8xxx_priv
*priv
;
2896 struct switch_dev
*swdev
;
2899 /* skip PHYs at unused adresses */
2900 if (phydev
->addr
!= 0 && phydev
->addr
!= 4)
2903 if (!ar8xxx_is_possible(phydev
->bus
))
2906 mutex_lock(&ar8xxx_dev_list_lock
);
2907 list_for_each_entry(priv
, &ar8xxx_dev_list
, list
)
2908 if (priv
->mii_bus
== phydev
->bus
)
2911 priv
= ar8xxx_create_mii(phydev
->bus
);
2917 ret
= ar8xxx_probe_switch(priv
);
2922 swdev
->alias
= dev_name(&priv
->mii_bus
->dev
);
2923 ret
= register_switch(swdev
, NULL
);
2927 pr_info("%s: %s rev. %u switch registered on %s\n",
2928 swdev
->devname
, swdev
->name
, priv
->chip_rev
,
2929 dev_name(&priv
->mii_bus
->dev
));
2934 if (phydev
->addr
== 0) {
2935 if (ar8xxx_has_gige(priv
)) {
2936 phydev
->supported
= SUPPORTED_1000baseT_Full
;
2937 phydev
->advertising
= ADVERTISED_1000baseT_Full
;
2939 phydev
->supported
= SUPPORTED_100baseT_Full
;
2940 phydev
->advertising
= ADVERTISED_100baseT_Full
;
2943 if (chip_is_ar8327(priv
) || chip_is_ar8337(priv
)) {
2946 ret
= ar8xxx_start(priv
);
2948 goto err_unregister_switch
;
2951 if (ar8xxx_has_gige(priv
)) {
2952 phydev
->supported
|= SUPPORTED_1000baseT_Full
;
2953 phydev
->advertising
|= ADVERTISED_1000baseT_Full
;
2957 phydev
->priv
= priv
;
2959 list_add(&priv
->list
, &ar8xxx_dev_list
);
2961 mutex_unlock(&ar8xxx_dev_list_lock
);
2965 err_unregister_switch
:
2966 if (--priv
->use_count
)
2969 unregister_switch(&priv
->dev
);
2974 mutex_unlock(&ar8xxx_dev_list_lock
);
2979 ar8xxx_phy_detach(struct phy_device
*phydev
)
2981 struct net_device
*dev
= phydev
->attached_dev
;
2986 dev
->phy_ptr
= NULL
;
2987 dev
->priv_flags
&= ~IFF_NO_IP_ALIGN
;
2988 dev
->eth_mangle_rx
= NULL
;
2989 dev
->eth_mangle_tx
= NULL
;
2993 ar8xxx_phy_remove(struct phy_device
*phydev
)
2995 struct ar8xxx_priv
*priv
= phydev
->priv
;
3000 phydev
->priv
= NULL
;
3001 if (--priv
->use_count
> 0)
3004 mutex_lock(&ar8xxx_dev_list_lock
);
3005 list_del(&priv
->list
);
3006 mutex_unlock(&ar8xxx_dev_list_lock
);
3008 unregister_switch(&priv
->dev
);
3009 ar8xxx_mib_stop(priv
);
3013 static struct phy_driver ar8xxx_phy_driver
= {
3014 .phy_id
= 0x004d0000,
3015 .name
= "Atheros AR8216/AR8236/AR8316",
3016 .phy_id_mask
= 0xffff0000,
3017 .features
= PHY_BASIC_FEATURES
,
3018 .probe
= ar8xxx_phy_probe
,
3019 .remove
= ar8xxx_phy_remove
,
3020 .detach
= ar8xxx_phy_detach
,
3021 .config_init
= ar8xxx_phy_config_init
,
3022 .config_aneg
= genphy_config_aneg
,
3023 .read_status
= ar8xxx_phy_read_status
,
3024 .driver
= { .owner
= THIS_MODULE
},
3030 return phy_driver_register(&ar8xxx_phy_driver
);
3036 phy_driver_unregister(&ar8xxx_phy_driver
);
3039 module_init(ar8xxx_init
);
3040 module_exit(ar8xxx_exit
);
3041 MODULE_LICENSE("GPL");