2 * ar8216.c: AR8216 switch driver
4 * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/list.h>
22 #include <linux/if_ether.h>
23 #include <linux/skbuff.h>
24 #include <linux/netdevice.h>
25 #include <linux/netlink.h>
26 #include <linux/bitops.h>
27 #include <net/genetlink.h>
28 #include <linux/switch.h>
29 #include <linux/delay.h>
30 #include <linux/phy.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/lockdep.h>
34 #include <linux/ar8216_platform.h>
37 /* size of the vlan table */
38 #define AR8X16_MAX_VLANS 128
39 #define AR8X16_PROBE_RETRIES 10
40 #define AR8X16_MAX_PORTS 8
44 #define AR8XXX_CAP_GIGE BIT(0)
49 int (*hw_init
)(struct ar8216_priv
*priv
);
50 void (*init_globals
)(struct ar8216_priv
*priv
);
51 void (*init_port
)(struct ar8216_priv
*priv
, int port
);
52 void (*setup_port
)(struct ar8216_priv
*priv
, int port
, u32 egress
,
53 u32 ingress
, u32 members
, u32 pvid
);
54 u32 (*read_port_status
)(struct ar8216_priv
*priv
, int port
);
55 int (*atu_flush
)(struct ar8216_priv
*priv
);
56 void (*vtu_flush
)(struct ar8216_priv
*priv
);
57 void (*vtu_load_vlan
)(struct ar8216_priv
*priv
, u32 vid
, u32 port_mask
);
61 struct switch_dev dev
;
62 struct phy_device
*phy
;
63 u32 (*read
)(struct ar8216_priv
*priv
, int reg
);
64 void (*write
)(struct ar8216_priv
*priv
, int reg
, u32 val
);
65 const struct net_device_ops
*ndo_old
;
66 struct net_device_ops ndo
;
67 struct mutex reg_mutex
;
69 const struct ar8xxx_chip
*chip
;
77 /* all fields below are cleared on reset */
79 u16 vlan_id
[AR8X16_MAX_VLANS
];
80 u8 vlan_table
[AR8X16_MAX_VLANS
];
82 u16 pvid
[AR8X16_MAX_PORTS
];
85 #define to_ar8216(_dev) container_of(_dev, struct ar8216_priv, dev)
87 static inline bool ar8xxx_has_gige(struct ar8216_priv
*priv
)
89 return priv
->chip
->caps
& AR8XXX_CAP_GIGE
;
93 split_addr(u32 regaddr
, u16
*r1
, u16
*r2
, u16
*page
)
102 *page
= regaddr
& 0x1ff;
106 ar8216_mii_read(struct ar8216_priv
*priv
, int reg
)
108 struct phy_device
*phy
= priv
->phy
;
109 struct mii_bus
*bus
= phy
->bus
;
113 split_addr((u32
) reg
, &r1
, &r2
, &page
);
115 mutex_lock(&bus
->mdio_lock
);
117 bus
->write(bus
, 0x18, 0, page
);
118 usleep_range(1000, 2000); /* wait for the page switch to propagate */
119 lo
= bus
->read(bus
, 0x10 | r2
, r1
);
120 hi
= bus
->read(bus
, 0x10 | r2
, r1
+ 1);
122 mutex_unlock(&bus
->mdio_lock
);
124 return (hi
<< 16) | lo
;
128 ar8216_mii_write(struct ar8216_priv
*priv
, int reg
, u32 val
)
130 struct phy_device
*phy
= priv
->phy
;
131 struct mii_bus
*bus
= phy
->bus
;
135 split_addr((u32
) reg
, &r1
, &r2
, &r3
);
137 hi
= (u16
) (val
>> 16);
139 mutex_lock(&bus
->mdio_lock
);
141 bus
->write(bus
, 0x18, 0, r3
);
142 usleep_range(1000, 2000); /* wait for the page switch to propagate */
143 if (priv
->mii_lo_first
) {
144 bus
->write(bus
, 0x10 | r2
, r1
, lo
);
145 bus
->write(bus
, 0x10 | r2
, r1
+ 1, hi
);
147 bus
->write(bus
, 0x10 | r2
, r1
+ 1, hi
);
148 bus
->write(bus
, 0x10 | r2
, r1
, lo
);
151 mutex_unlock(&bus
->mdio_lock
);
155 ar8216_phy_dbg_write(struct ar8216_priv
*priv
, int phy_addr
,
156 u16 dbg_addr
, u16 dbg_data
)
158 struct mii_bus
*bus
= priv
->phy
->bus
;
160 mutex_lock(&bus
->mdio_lock
);
161 bus
->write(bus
, phy_addr
, MII_ATH_DBG_ADDR
, dbg_addr
);
162 bus
->write(bus
, phy_addr
, MII_ATH_DBG_DATA
, dbg_data
);
163 mutex_unlock(&bus
->mdio_lock
);
167 ar8216_rmw(struct ar8216_priv
*priv
, int reg
, u32 mask
, u32 val
)
171 lockdep_assert_held(&priv
->reg_mutex
);
173 v
= priv
->read(priv
, reg
);
176 priv
->write(priv
, reg
, v
);
182 ar8216_read_port_link(struct ar8216_priv
*priv
, int port
,
183 struct switch_port_link
*link
)
188 memset(link
, '\0', sizeof(*link
));
190 status
= priv
->chip
->read_port_status(priv
, port
);
192 link
->aneg
= !!(status
& AR8216_PORT_STATUS_LINK_AUTO
);
194 link
->link
= !!(status
& AR8216_PORT_STATUS_LINK_UP
);
201 link
->duplex
= !!(status
& AR8216_PORT_STATUS_DUPLEX
);
202 link
->tx_flow
= !!(status
& AR8216_PORT_STATUS_TXFLOW
);
203 link
->rx_flow
= !!(status
& AR8216_PORT_STATUS_RXFLOW
);
205 speed
= (status
& AR8216_PORT_STATUS_SPEED
) >>
206 AR8216_PORT_STATUS_SPEED_S
;
209 case AR8216_PORT_SPEED_10M
:
210 link
->speed
= SWITCH_PORT_SPEED_10
;
212 case AR8216_PORT_SPEED_100M
:
213 link
->speed
= SWITCH_PORT_SPEED_100
;
215 case AR8216_PORT_SPEED_1000M
:
216 link
->speed
= SWITCH_PORT_SPEED_1000
;
219 link
->speed
= SWITCH_PORT_SPEED_UNKNOWN
;
224 static struct sk_buff
*
225 ar8216_mangle_tx(struct net_device
*dev
, struct sk_buff
*skb
)
227 struct ar8216_priv
*priv
= dev
->phy_ptr
;
236 if (unlikely(skb_headroom(skb
) < 2)) {
237 if (pskb_expand_head(skb
, 2, 0, GFP_ATOMIC
) < 0)
241 buf
= skb_push(skb
, 2);
249 dev_kfree_skb_any(skb
);
254 ar8216_mangle_rx(struct net_device
*dev
, struct sk_buff
*skb
)
256 struct ar8216_priv
*priv
;
264 /* don't strip the header if vlan mode is disabled */
268 /* strip header, get vlan id */
272 /* check for vlan header presence */
273 if ((buf
[12 + 2] != 0x81) || (buf
[13 + 2] != 0x00))
278 /* no need to fix up packets coming from a tagged source */
279 if (priv
->vlan_tagged
& (1 << port
))
282 /* lookup port vid from local table, the switch passes an invalid vlan id */
283 vlan
= priv
->vlan_id
[priv
->pvid
[port
]];
286 buf
[14 + 2] |= vlan
>> 8;
287 buf
[15 + 2] = vlan
& 0xff;
291 ar8216_wait_bit(struct ar8216_priv
*priv
, int reg
, u32 mask
, u32 val
)
297 t
= priv
->read(priv
, reg
);
298 if ((t
& mask
) == val
)
307 pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
308 (unsigned int) reg
, t
, mask
, val
);
313 ar8216_vtu_op(struct ar8216_priv
*priv
, u32 op
, u32 val
)
315 if (ar8216_wait_bit(priv
, AR8216_REG_VTU
, AR8216_VTU_ACTIVE
, 0))
317 if ((op
& AR8216_VTU_OP
) == AR8216_VTU_OP_LOAD
) {
318 val
&= AR8216_VTUDATA_MEMBER
;
319 val
|= AR8216_VTUDATA_VALID
;
320 priv
->write(priv
, AR8216_REG_VTU_DATA
, val
);
322 op
|= AR8216_VTU_ACTIVE
;
323 priv
->write(priv
, AR8216_REG_VTU
, op
);
327 ar8216_vtu_flush(struct ar8216_priv
*priv
)
329 ar8216_vtu_op(priv
, AR8216_VTU_OP_FLUSH
, 0);
333 ar8216_vtu_load_vlan(struct ar8216_priv
*priv
, u32 vid
, u32 port_mask
)
337 op
= AR8216_VTU_OP_LOAD
| (vid
<< AR8216_VTU_VID_S
);
338 ar8216_vtu_op(priv
, op
, port_mask
);
342 ar8216_atu_flush(struct ar8216_priv
*priv
)
346 ret
= ar8216_wait_bit(priv
, AR8216_REG_ATU
, AR8216_ATU_ACTIVE
, 0);
348 priv
->write(priv
, AR8216_REG_ATU
, AR8216_ATU_OP_FLUSH
);
354 ar8216_read_port_status(struct ar8216_priv
*priv
, int port
)
356 return priv
->read(priv
, AR8216_REG_PORT_STATUS(port
));
360 ar8216_setup_port(struct ar8216_priv
*priv
, int port
, u32 egress
, u32 ingress
,
361 u32 members
, u32 pvid
)
365 if (priv
->vlan
&& port
== AR8216_PORT_CPU
&& priv
->chip_type
== AR8216
)
366 header
= AR8216_PORT_CTRL_HEADER
;
370 ar8216_rmw(priv
, AR8216_REG_PORT_CTRL(port
),
371 AR8216_PORT_CTRL_LEARN
| AR8216_PORT_CTRL_VLAN_MODE
|
372 AR8216_PORT_CTRL_SINGLE_VLAN
| AR8216_PORT_CTRL_STATE
|
373 AR8216_PORT_CTRL_HEADER
| AR8216_PORT_CTRL_LEARN_LOCK
,
374 AR8216_PORT_CTRL_LEARN
| header
|
375 (egress
<< AR8216_PORT_CTRL_VLAN_MODE_S
) |
376 (AR8216_PORT_STATE_FORWARD
<< AR8216_PORT_CTRL_STATE_S
));
378 ar8216_rmw(priv
, AR8216_REG_PORT_VLAN(port
),
379 AR8216_PORT_VLAN_DEST_PORTS
| AR8216_PORT_VLAN_MODE
|
380 AR8216_PORT_VLAN_DEFAULT_ID
,
381 (members
<< AR8216_PORT_VLAN_DEST_PORTS_S
) |
382 (ingress
<< AR8216_PORT_VLAN_MODE_S
) |
383 (pvid
<< AR8216_PORT_VLAN_DEFAULT_ID_S
));
387 ar8216_hw_init(struct ar8216_priv
*priv
)
393 ar8216_init_globals(struct ar8216_priv
*priv
)
395 /* standard atheros magic */
396 priv
->write(priv
, 0x38, 0xc000050e);
398 ar8216_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
399 AR8216_GCTRL_MTU
, 1518 + 8 + 2);
403 ar8216_init_port(struct ar8216_priv
*priv
, int port
)
405 /* Enable port learning and tx */
406 priv
->write(priv
, AR8216_REG_PORT_CTRL(port
),
407 AR8216_PORT_CTRL_LEARN
|
408 (4 << AR8216_PORT_CTRL_STATE_S
));
410 priv
->write(priv
, AR8216_REG_PORT_VLAN(port
), 0);
412 if (port
== AR8216_PORT_CPU
) {
413 priv
->write(priv
, AR8216_REG_PORT_STATUS(port
),
414 AR8216_PORT_STATUS_LINK_UP
|
415 (ar8xxx_has_gige(priv
) ?
416 AR8216_PORT_SPEED_1000M
: AR8216_PORT_SPEED_100M
) |
417 AR8216_PORT_STATUS_TXMAC
|
418 AR8216_PORT_STATUS_RXMAC
|
419 ((priv
->chip_type
== AR8316
) ? AR8216_PORT_STATUS_RXFLOW
: 0) |
420 ((priv
->chip_type
== AR8316
) ? AR8216_PORT_STATUS_TXFLOW
: 0) |
421 AR8216_PORT_STATUS_DUPLEX
);
423 priv
->write(priv
, AR8216_REG_PORT_STATUS(port
),
424 AR8216_PORT_STATUS_LINK_AUTO
);
428 static const struct ar8xxx_chip ar8216_chip
= {
429 .hw_init
= ar8216_hw_init
,
430 .init_globals
= ar8216_init_globals
,
431 .init_port
= ar8216_init_port
,
432 .setup_port
= ar8216_setup_port
,
433 .read_port_status
= ar8216_read_port_status
,
434 .atu_flush
= ar8216_atu_flush
,
435 .vtu_flush
= ar8216_vtu_flush
,
436 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
440 ar8236_setup_port(struct ar8216_priv
*priv
, int port
, u32 egress
, u32 ingress
,
441 u32 members
, u32 pvid
)
443 ar8216_rmw(priv
, AR8216_REG_PORT_CTRL(port
),
444 AR8216_PORT_CTRL_LEARN
| AR8216_PORT_CTRL_VLAN_MODE
|
445 AR8216_PORT_CTRL_SINGLE_VLAN
| AR8216_PORT_CTRL_STATE
|
446 AR8216_PORT_CTRL_HEADER
| AR8216_PORT_CTRL_LEARN_LOCK
,
447 AR8216_PORT_CTRL_LEARN
|
448 (egress
<< AR8216_PORT_CTRL_VLAN_MODE_S
) |
449 (AR8216_PORT_STATE_FORWARD
<< AR8216_PORT_CTRL_STATE_S
));
451 ar8216_rmw(priv
, AR8236_REG_PORT_VLAN(port
),
452 AR8236_PORT_VLAN_DEFAULT_ID
,
453 (pvid
<< AR8236_PORT_VLAN_DEFAULT_ID_S
));
455 ar8216_rmw(priv
, AR8236_REG_PORT_VLAN2(port
),
456 AR8236_PORT_VLAN2_VLAN_MODE
|
457 AR8236_PORT_VLAN2_MEMBER
,
458 (ingress
<< AR8236_PORT_VLAN2_VLAN_MODE_S
) |
459 (members
<< AR8236_PORT_VLAN2_MEMBER_S
));
463 ar8236_hw_init(struct ar8216_priv
*priv
)
468 if (priv
->initialized
)
471 /* Initialize the PHYs */
472 bus
= priv
->phy
->bus
;
473 for (i
= 0; i
< 5; i
++) {
474 mdiobus_write(bus
, i
, MII_ADVERTISE
,
475 ADVERTISE_ALL
| ADVERTISE_PAUSE_CAP
|
476 ADVERTISE_PAUSE_ASYM
);
477 mdiobus_write(bus
, i
, MII_BMCR
, BMCR_RESET
| BMCR_ANENABLE
);
481 priv
->initialized
= true;
486 ar8236_init_globals(struct ar8216_priv
*priv
)
488 /* enable jumbo frames */
489 ar8216_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
490 AR8316_GCTRL_MTU
, 9018 + 8 + 2);
493 static const struct ar8xxx_chip ar8236_chip
= {
494 .hw_init
= ar8236_hw_init
,
495 .init_globals
= ar8236_init_globals
,
496 .init_port
= ar8216_init_port
,
497 .setup_port
= ar8236_setup_port
,
498 .read_port_status
= ar8216_read_port_status
,
499 .atu_flush
= ar8216_atu_flush
,
500 .vtu_flush
= ar8216_vtu_flush
,
501 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
505 ar8316_hw_init(struct ar8216_priv
*priv
)
511 val
= priv
->read(priv
, 0x8);
513 if (priv
->phy
->interface
== PHY_INTERFACE_MODE_RGMII
) {
514 if (priv
->port4_phy
) {
515 /* value taken from Ubiquiti RouterStation Pro */
517 printk(KERN_INFO
"ar8316: Using port 4 as PHY\n");
520 printk(KERN_INFO
"ar8316: Using port 4 as switch port\n");
522 } else if (priv
->phy
->interface
== PHY_INTERFACE_MODE_GMII
) {
523 /* value taken from AVM Fritz!Box 7390 sources */
526 /* no known value for phy interface */
527 printk(KERN_ERR
"ar8316: unsupported mii mode: %d.\n",
528 priv
->phy
->interface
);
535 priv
->write(priv
, 0x8, newval
);
537 /* Initialize the ports */
538 bus
= priv
->phy
->bus
;
539 for (i
= 0; i
< 5; i
++) {
540 if ((i
== 4) && priv
->port4_phy
&&
541 priv
->phy
->interface
== PHY_INTERFACE_MODE_RGMII
) {
542 /* work around for phy4 rgmii mode */
543 ar8216_phy_dbg_write(priv
, i
, 0x12, 0x480c);
545 ar8216_phy_dbg_write(priv
, i
, 0x0, 0x824e);
547 ar8216_phy_dbg_write(priv
, i
, 0x5, 0x3d47);
551 /* initialize the port itself */
552 mdiobus_write(bus
, i
, MII_ADVERTISE
,
553 ADVERTISE_ALL
| ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
);
554 mdiobus_write(bus
, i
, MII_CTRL1000
, ADVERTISE_1000FULL
);
555 mdiobus_write(bus
, i
, MII_BMCR
, BMCR_RESET
| BMCR_ANENABLE
);
560 priv
->initialized
= true;
565 ar8316_init_globals(struct ar8216_priv
*priv
)
567 /* standard atheros magic */
568 priv
->write(priv
, 0x38, 0xc000050e);
570 /* enable cpu port to receive multicast and broadcast frames */
571 priv
->write(priv
, AR8216_REG_FLOOD_MASK
, 0x003f003f);
573 /* enable jumbo frames */
574 ar8216_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
575 AR8316_GCTRL_MTU
, 9018 + 8 + 2);
578 static const struct ar8xxx_chip ar8316_chip
= {
579 .caps
= AR8XXX_CAP_GIGE
,
580 .hw_init
= ar8316_hw_init
,
581 .init_globals
= ar8316_init_globals
,
582 .init_port
= ar8216_init_port
,
583 .setup_port
= ar8216_setup_port
,
584 .read_port_status
= ar8216_read_port_status
,
585 .atu_flush
= ar8216_atu_flush
,
586 .vtu_flush
= ar8216_vtu_flush
,
587 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
591 ar8327_get_pad_cfg(struct ar8327_pad_cfg
*cfg
)
603 case AR8327_PAD_MAC2MAC_MII
:
604 t
= AR8327_PAD_MAC_MII_EN
;
606 t
|= AR8327_PAD_MAC_MII_RXCLK_SEL
;
608 t
|= AR8327_PAD_MAC_MII_TXCLK_SEL
;
611 case AR8327_PAD_MAC2MAC_GMII
:
612 t
= AR8327_PAD_MAC_GMII_EN
;
614 t
|= AR8327_PAD_MAC_GMII_RXCLK_SEL
;
616 t
|= AR8327_PAD_MAC_GMII_TXCLK_SEL
;
619 case AR8327_PAD_MAC_SGMII
:
620 t
= AR8327_PAD_SGMII_EN
;
623 case AR8327_PAD_MAC2PHY_MII
:
624 t
= AR8327_PAD_PHY_MII_EN
;
626 t
|= AR8327_PAD_PHY_MII_RXCLK_SEL
;
628 t
|= AR8327_PAD_PHY_MII_TXCLK_SEL
;
631 case AR8327_PAD_MAC2PHY_GMII
:
632 t
= AR8327_PAD_PHY_GMII_EN
;
633 if (cfg
->pipe_rxclk_sel
)
634 t
|= AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL
;
636 t
|= AR8327_PAD_PHY_GMII_RXCLK_SEL
;
638 t
|= AR8327_PAD_PHY_GMII_TXCLK_SEL
;
641 case AR8327_PAD_MAC_RGMII
:
642 t
= AR8327_PAD_RGMII_EN
;
643 t
|= cfg
->txclk_delay_sel
<< AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S
;
644 t
|= cfg
->rxclk_delay_sel
<< AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S
;
645 if (cfg
->rxclk_delay_en
)
646 t
|= AR8327_PAD_RGMII_RXCLK_DELAY_EN
;
647 if (cfg
->txclk_delay_en
)
648 t
|= AR8327_PAD_RGMII_TXCLK_DELAY_EN
;
651 case AR8327_PAD_PHY_GMII
:
652 t
= AR8327_PAD_PHYX_GMII_EN
;
655 case AR8327_PAD_PHY_RGMII
:
656 t
= AR8327_PAD_PHYX_RGMII_EN
;
659 case AR8327_PAD_PHY_MII
:
660 t
= AR8327_PAD_PHYX_MII_EN
;
668 ar8327_hw_init(struct ar8216_priv
*priv
)
670 struct ar8327_platform_data
*pdata
;
674 pdata
= priv
->phy
->dev
.platform_data
;
678 t
= ar8327_get_pad_cfg(pdata
->pad0_cfg
);
679 priv
->write(priv
, AR8327_REG_PAD0_MODE
, t
);
680 t
= ar8327_get_pad_cfg(pdata
->pad5_cfg
);
681 priv
->write(priv
, AR8327_REG_PAD5_MODE
, t
);
682 t
= ar8327_get_pad_cfg(pdata
->pad6_cfg
);
683 priv
->write(priv
, AR8327_REG_PAD6_MODE
, t
);
685 priv
->write(priv
, AR8327_REG_POWER_ON_STRIP
, 0x40000000);
688 for (i
= 0; i
< AR8327_NUM_PHYS
; i
++) {
689 /* For 100M waveform */
690 ar8216_phy_dbg_write(priv
, i
, 0, 0x02ea);
692 /* Turn on Gigabit clock */
693 ar8216_phy_dbg_write(priv
, i
, 0x3d, 0x68a0);
700 ar8327_init_globals(struct ar8216_priv
*priv
)
704 /* enable CPU port and disable mirror port */
705 t
= AR8327_FWD_CTRL0_CPU_PORT_EN
|
706 AR8327_FWD_CTRL0_MIRROR_PORT
;
707 priv
->write(priv
, AR8327_REG_FWD_CTRL0
, t
);
709 /* forward multicast and broadcast frames to CPU */
710 t
= (AR8327_PORTS_ALL
<< AR8327_FWD_CTRL1_UC_FLOOD_S
) |
711 (AR8327_PORTS_ALL
<< AR8327_FWD_CTRL1_MC_FLOOD_S
) |
712 (AR8327_PORTS_ALL
<< AR8327_FWD_CTRL1_BC_FLOOD_S
);
713 priv
->write(priv
, AR8327_REG_FWD_CTRL1
, t
);
716 ar8216_rmw(priv
, AR8327_REG_MAX_FRAME_SIZE
,
717 AR8327_MAX_FRAME_SIZE_MTU
, 1518 + 8 + 2);
721 ar8327_init_cpuport(struct ar8216_priv
*priv
)
723 struct ar8327_platform_data
*pdata
;
724 struct ar8327_port_cfg
*cfg
;
727 pdata
= priv
->phy
->dev
.platform_data
;
731 cfg
= &pdata
->cpuport_cfg
;
732 if (!cfg
->force_link
) {
733 priv
->write(priv
, AR8327_REG_PORT_STATUS(AR8216_PORT_CPU
),
734 AR8216_PORT_STATUS_LINK_AUTO
);
738 t
= AR8216_PORT_STATUS_TXMAC
| AR8216_PORT_STATUS_RXMAC
;
739 t
|= cfg
->duplex
? AR8216_PORT_STATUS_DUPLEX
: 0;
740 t
|= cfg
->rxpause
? AR8216_PORT_STATUS_RXFLOW
: 0;
741 t
|= cfg
->txpause
? AR8216_PORT_STATUS_TXFLOW
: 0;
742 switch (cfg
->speed
) {
743 case AR8327_PORT_SPEED_10
:
744 t
|= AR8216_PORT_SPEED_10M
;
746 case AR8327_PORT_SPEED_100
:
747 t
|= AR8216_PORT_SPEED_100M
;
749 case AR8327_PORT_SPEED_1000
:
750 t
|= AR8216_PORT_SPEED_1000M
;
754 priv
->write(priv
, AR8327_REG_PORT_STATUS(AR8216_PORT_CPU
), t
);
758 ar8327_init_port(struct ar8216_priv
*priv
, int port
)
762 if (port
== AR8216_PORT_CPU
) {
763 ar8327_init_cpuport(priv
);
765 t
= AR8216_PORT_STATUS_LINK_AUTO
;
766 priv
->write(priv
, AR8327_REG_PORT_STATUS(port
), t
);
769 priv
->write(priv
, AR8327_REG_PORT_HEADER(port
), 0);
771 priv
->write(priv
, AR8327_REG_PORT_VLAN0(port
), 0);
773 t
= AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH
<< AR8327_PORT_VLAN1_OUT_MODE_S
;
774 priv
->write(priv
, AR8327_REG_PORT_VLAN1(port
), t
);
776 t
= AR8327_PORT_LOOKUP_LEARN
;
777 t
|= AR8216_PORT_STATE_FORWARD
<< AR8327_PORT_LOOKUP_STATE_S
;
778 priv
->write(priv
, AR8327_REG_PORT_LOOKUP(port
), t
);
782 ar8327_read_port_status(struct ar8216_priv
*priv
, int port
)
784 return priv
->read(priv
, AR8327_REG_PORT_STATUS(port
));
788 ar8327_atu_flush(struct ar8216_priv
*priv
)
792 ret
= ar8216_wait_bit(priv
, AR8327_REG_ATU_FUNC
,
793 AR8327_ATU_FUNC_BUSY
, 0);
795 priv
->write(priv
, AR8327_REG_ATU_FUNC
,
796 AR8327_ATU_FUNC_OP_FLUSH
);
802 ar8327_vtu_op(struct ar8216_priv
*priv
, u32 op
, u32 val
)
804 if (ar8216_wait_bit(priv
, AR8327_REG_VTU_FUNC1
,
805 AR8327_VTU_FUNC1_BUSY
, 0))
808 if ((op
& AR8327_VTU_FUNC1_OP
) == AR8327_VTU_FUNC1_OP_LOAD
)
809 priv
->write(priv
, AR8327_REG_VTU_FUNC0
, val
);
811 op
|= AR8327_VTU_FUNC1_BUSY
;
812 priv
->write(priv
, AR8327_REG_VTU_FUNC1
, op
);
816 ar8327_vtu_flush(struct ar8216_priv
*priv
)
818 ar8327_vtu_op(priv
, AR8327_VTU_FUNC1_OP_FLUSH
, 0);
822 ar8327_vtu_load_vlan(struct ar8216_priv
*priv
, u32 vid
, u32 port_mask
)
828 op
= AR8327_VTU_FUNC1_OP_LOAD
| (vid
<< AR8327_VTU_FUNC1_VID_S
);
829 val
= AR8327_VTU_FUNC0_VALID
| AR8327_VTU_FUNC0_IVL
;
830 for (i
= 0; i
< AR8327_NUM_PORTS
; i
++) {
833 if ((port_mask
& BIT(i
)) == 0)
834 mode
= AR8327_VTU_FUNC0_EG_MODE_NOT
;
835 else if (priv
->vlan
== 0)
836 mode
= AR8327_VTU_FUNC0_EG_MODE_KEEP
;
837 else if (priv
->vlan_tagged
& BIT(i
))
838 mode
= AR8327_VTU_FUNC0_EG_MODE_TAG
;
840 mode
= AR8327_VTU_FUNC0_EG_MODE_UNTAG
;
842 val
|= mode
<< AR8327_VTU_FUNC0_EG_MODE_S(i
);
844 ar8327_vtu_op(priv
, op
, val
);
848 ar8327_setup_port(struct ar8216_priv
*priv
, int port
, u32 egress
, u32 ingress
,
849 u32 members
, u32 pvid
)
854 t
= pvid
<< AR8327_PORT_VLAN0_DEF_SVID_S
;
855 t
|= pvid
<< AR8327_PORT_VLAN0_DEF_CVID_S
;
856 priv
->write(priv
, AR8327_REG_PORT_VLAN0(port
), t
);
858 mode
= AR8327_PORT_VLAN1_OUT_MODE_UNMOD
;
860 case AR8216_OUT_KEEP
:
861 mode
= AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH
;
863 case AR8216_OUT_STRIP_VLAN
:
864 mode
= AR8327_PORT_VLAN1_OUT_MODE_UNTAG
;
866 case AR8216_OUT_ADD_VLAN
:
867 mode
= AR8327_PORT_VLAN1_OUT_MODE_TAG
;
871 t
= AR8327_PORT_VLAN1_PORT_VLAN_PROP
;
872 t
|= mode
<< AR8327_PORT_VLAN1_OUT_MODE_S
;
873 priv
->write(priv
, AR8327_REG_PORT_VLAN1(port
), t
);
876 t
|= AR8327_PORT_LOOKUP_LEARN
;
877 t
|= ingress
<< AR8327_PORT_LOOKUP_IN_MODE_S
;
878 t
|= AR8216_PORT_STATE_FORWARD
<< AR8327_PORT_LOOKUP_STATE_S
;
879 priv
->write(priv
, AR8327_REG_PORT_LOOKUP(port
), t
);
882 static const struct ar8xxx_chip ar8327_chip
= {
883 .caps
= AR8XXX_CAP_GIGE
,
884 .hw_init
= ar8327_hw_init
,
885 .init_globals
= ar8327_init_globals
,
886 .init_port
= ar8327_init_port
,
887 .setup_port
= ar8327_setup_port
,
888 .read_port_status
= ar8327_read_port_status
,
889 .atu_flush
= ar8327_atu_flush
,
890 .vtu_flush
= ar8327_vtu_flush
,
891 .vtu_load_vlan
= ar8327_vtu_load_vlan
,
895 ar8216_sw_set_vlan(struct switch_dev
*dev
, const struct switch_attr
*attr
,
896 struct switch_val
*val
)
898 struct ar8216_priv
*priv
= to_ar8216(dev
);
899 priv
->vlan
= !!val
->value
.i
;
904 ar8216_sw_get_vlan(struct switch_dev
*dev
, const struct switch_attr
*attr
,
905 struct switch_val
*val
)
907 struct ar8216_priv
*priv
= to_ar8216(dev
);
908 val
->value
.i
= priv
->vlan
;
914 ar8216_sw_set_pvid(struct switch_dev
*dev
, int port
, int vlan
)
916 struct ar8216_priv
*priv
= to_ar8216(dev
);
918 /* make sure no invalid PVIDs get set */
920 if (vlan
>= dev
->vlans
)
923 priv
->pvid
[port
] = vlan
;
928 ar8216_sw_get_pvid(struct switch_dev
*dev
, int port
, int *vlan
)
930 struct ar8216_priv
*priv
= to_ar8216(dev
);
931 *vlan
= priv
->pvid
[port
];
936 ar8216_sw_set_vid(struct switch_dev
*dev
, const struct switch_attr
*attr
,
937 struct switch_val
*val
)
939 struct ar8216_priv
*priv
= to_ar8216(dev
);
940 priv
->vlan_id
[val
->port_vlan
] = val
->value
.i
;
945 ar8216_sw_get_vid(struct switch_dev
*dev
, const struct switch_attr
*attr
,
946 struct switch_val
*val
)
948 struct ar8216_priv
*priv
= to_ar8216(dev
);
949 val
->value
.i
= priv
->vlan_id
[val
->port_vlan
];
954 ar8216_sw_get_port_link(struct switch_dev
*dev
, int port
,
955 struct switch_port_link
*link
)
957 struct ar8216_priv
*priv
= to_ar8216(dev
);
959 ar8216_read_port_link(priv
, port
, link
);
964 ar8216_sw_get_ports(struct switch_dev
*dev
, struct switch_val
*val
)
966 struct ar8216_priv
*priv
= to_ar8216(dev
);
967 u8 ports
= priv
->vlan_table
[val
->port_vlan
];
971 for (i
= 0; i
< dev
->ports
; i
++) {
972 struct switch_port
*p
;
974 if (!(ports
& (1 << i
)))
977 p
= &val
->value
.ports
[val
->len
++];
979 if (priv
->vlan_tagged
& (1 << i
))
980 p
->flags
= (1 << SWITCH_PORT_FLAG_TAGGED
);
988 ar8216_sw_set_ports(struct switch_dev
*dev
, struct switch_val
*val
)
990 struct ar8216_priv
*priv
= to_ar8216(dev
);
991 u8
*vt
= &priv
->vlan_table
[val
->port_vlan
];
995 for (i
= 0; i
< val
->len
; i
++) {
996 struct switch_port
*p
= &val
->value
.ports
[i
];
998 if (p
->flags
& (1 << SWITCH_PORT_FLAG_TAGGED
)) {
999 priv
->vlan_tagged
|= (1 << p
->id
);
1001 priv
->vlan_tagged
&= ~(1 << p
->id
);
1002 priv
->pvid
[p
->id
] = val
->port_vlan
;
1004 /* make sure that an untagged port does not
1005 * appear in other vlans */
1006 for (j
= 0; j
< AR8X16_MAX_VLANS
; j
++) {
1007 if (j
== val
->port_vlan
)
1009 priv
->vlan_table
[j
] &= ~(1 << p
->id
);
1019 ar8216_sw_hw_apply(struct switch_dev
*dev
)
1021 struct ar8216_priv
*priv
= to_ar8216(dev
);
1022 u8 portmask
[AR8X16_MAX_PORTS
];
1025 mutex_lock(&priv
->reg_mutex
);
1026 /* flush all vlan translation unit entries */
1027 priv
->chip
->vtu_flush(priv
);
1029 memset(portmask
, 0, sizeof(portmask
));
1031 /* calculate the port destination masks and load vlans
1032 * into the vlan translation unit */
1033 for (j
= 0; j
< AR8X16_MAX_VLANS
; j
++) {
1034 u8 vp
= priv
->vlan_table
[j
];
1039 for (i
= 0; i
< dev
->ports
; i
++) {
1042 portmask
[i
] |= vp
& ~mask
;
1045 priv
->chip
->vtu_load_vlan(priv
, priv
->vlan_id
[j
],
1046 priv
->vlan_table
[j
]);
1050 * isolate all ports, but connect them to the cpu port */
1051 for (i
= 0; i
< dev
->ports
; i
++) {
1052 if (i
== AR8216_PORT_CPU
)
1055 portmask
[i
] = 1 << AR8216_PORT_CPU
;
1056 portmask
[AR8216_PORT_CPU
] |= (1 << i
);
1060 /* update the port destination mask registers and tag settings */
1061 for (i
= 0; i
< dev
->ports
; i
++) {
1062 int egress
, ingress
;
1066 pvid
= priv
->vlan_id
[priv
->pvid
[i
]];
1067 if (priv
->vlan_tagged
& (1 << i
))
1068 egress
= AR8216_OUT_ADD_VLAN
;
1070 egress
= AR8216_OUT_STRIP_VLAN
;
1071 ingress
= AR8216_IN_SECURE
;
1074 egress
= AR8216_OUT_KEEP
;
1075 ingress
= AR8216_IN_PORT_ONLY
;
1078 priv
->chip
->setup_port(priv
, i
, egress
, ingress
, portmask
[i
],
1081 mutex_unlock(&priv
->reg_mutex
);
1086 ar8216_sw_reset_switch(struct switch_dev
*dev
)
1088 struct ar8216_priv
*priv
= to_ar8216(dev
);
1091 mutex_lock(&priv
->reg_mutex
);
1092 memset(&priv
->vlan
, 0, sizeof(struct ar8216_priv
) -
1093 offsetof(struct ar8216_priv
, vlan
));
1095 for (i
= 0; i
< AR8X16_MAX_VLANS
; i
++)
1096 priv
->vlan_id
[i
] = i
;
1098 /* Configure all ports */
1099 for (i
= 0; i
< dev
->ports
; i
++)
1100 priv
->chip
->init_port(priv
, i
);
1102 priv
->chip
->init_globals(priv
);
1103 mutex_unlock(&priv
->reg_mutex
);
1105 return ar8216_sw_hw_apply(dev
);
1108 static struct switch_attr ar8216_globals
[] = {
1110 .type
= SWITCH_TYPE_INT
,
1111 .name
= "enable_vlan",
1112 .description
= "Enable VLAN mode",
1113 .set
= ar8216_sw_set_vlan
,
1114 .get
= ar8216_sw_get_vlan
,
1119 static struct switch_attr ar8216_port
[] = {
1122 static struct switch_attr ar8216_vlan
[] = {
1124 .type
= SWITCH_TYPE_INT
,
1126 .description
= "VLAN ID (0-4094)",
1127 .set
= ar8216_sw_set_vid
,
1128 .get
= ar8216_sw_get_vid
,
1133 static const struct switch_dev_ops ar8216_sw_ops
= {
1135 .attr
= ar8216_globals
,
1136 .n_attr
= ARRAY_SIZE(ar8216_globals
),
1139 .attr
= ar8216_port
,
1140 .n_attr
= ARRAY_SIZE(ar8216_port
),
1143 .attr
= ar8216_vlan
,
1144 .n_attr
= ARRAY_SIZE(ar8216_vlan
),
1146 .get_port_pvid
= ar8216_sw_get_pvid
,
1147 .set_port_pvid
= ar8216_sw_set_pvid
,
1148 .get_vlan_ports
= ar8216_sw_get_ports
,
1149 .set_vlan_ports
= ar8216_sw_set_ports
,
1150 .apply_config
= ar8216_sw_hw_apply
,
1151 .reset_switch
= ar8216_sw_reset_switch
,
1152 .get_port_link
= ar8216_sw_get_port_link
,
1156 ar8216_id_chip(struct ar8216_priv
*priv
)
1162 priv
->chip_type
= UNKNOWN
;
1164 val
= ar8216_mii_read(priv
, AR8216_REG_CTRL
);
1168 id
= val
& (AR8216_CTRL_REVISION
| AR8216_CTRL_VERSION
);
1169 for (i
= 0; i
< AR8X16_PROBE_RETRIES
; i
++) {
1172 val
= ar8216_mii_read(priv
, AR8216_REG_CTRL
);
1176 t
= val
& (AR8216_CTRL_REVISION
| AR8216_CTRL_VERSION
);
1183 priv
->chip_type
= AR8216
;
1184 priv
->chip
= &ar8216_chip
;
1187 priv
->chip_type
= AR8236
;
1188 priv
->chip
= &ar8236_chip
;
1192 priv
->chip_type
= AR8316
;
1193 priv
->chip
= &ar8316_chip
;
1196 priv
->chip_type
= AR8327
;
1197 priv
->mii_lo_first
= true;
1198 priv
->chip
= &ar8327_chip
;
1202 "ar8216: Unknown Atheros device [ver=%d, rev=%d, phy_id=%04x%04x]\n",
1203 (int)(id
>> AR8216_CTRL_VERSION_S
),
1204 (int)(id
& AR8216_CTRL_REVISION
),
1205 mdiobus_read(priv
->phy
->bus
, priv
->phy
->addr
, 2),
1206 mdiobus_read(priv
->phy
->bus
, priv
->phy
->addr
, 3));
1215 ar8216_config_init(struct phy_device
*pdev
)
1217 struct ar8216_priv
*priv
= pdev
->priv
;
1218 struct net_device
*dev
= pdev
->attached_dev
;
1219 struct switch_dev
*swdev
;
1223 priv
= kzalloc(sizeof(struct ar8216_priv
), GFP_KERNEL
);
1230 ret
= ar8216_id_chip(priv
);
1234 if (pdev
->addr
!= 0) {
1235 if (ar8xxx_has_gige(priv
)) {
1236 pdev
->supported
|= SUPPORTED_1000baseT_Full
;
1237 pdev
->advertising
|= ADVERTISED_1000baseT_Full
;
1240 if (priv
->chip_type
== AR8316
) {
1241 /* check if we're attaching to the switch twice */
1242 pdev
= pdev
->bus
->phy_map
[0];
1248 /* switch device has not been initialized, reuse priv */
1250 priv
->port4_phy
= true;
1257 /* switch device has been initialized, reinit */
1259 priv
->dev
.ports
= (AR8216_NUM_PORTS
- 1);
1260 priv
->initialized
= false;
1261 priv
->port4_phy
= true;
1262 ar8316_hw_init(priv
);
1270 printk(KERN_INFO
"%s: AR%d switch driver attached.\n",
1271 pdev
->attached_dev
->name
, priv
->chip_type
);
1273 if (ar8xxx_has_gige(priv
))
1274 pdev
->supported
= SUPPORTED_1000baseT_Full
;
1276 pdev
->supported
= SUPPORTED_100baseT_Full
;
1277 pdev
->advertising
= pdev
->supported
;
1279 mutex_init(&priv
->reg_mutex
);
1280 priv
->read
= ar8216_mii_read
;
1281 priv
->write
= ar8216_mii_write
;
1286 swdev
->cpu_port
= AR8216_PORT_CPU
;
1287 swdev
->ops
= &ar8216_sw_ops
;
1288 swdev
->ports
= AR8216_NUM_PORTS
;
1290 if (priv
->chip_type
== AR8316
) {
1291 swdev
->name
= "Atheros AR8316";
1292 swdev
->vlans
= AR8X16_MAX_VLANS
;
1294 if (priv
->port4_phy
) {
1295 /* port 5 connected to the other mac, therefore unusable */
1296 swdev
->ports
= (AR8216_NUM_PORTS
- 1);
1298 } else if (priv
->chip_type
== AR8236
) {
1299 swdev
->name
= "Atheros AR8236";
1300 swdev
->vlans
= AR8216_NUM_VLANS
;
1301 swdev
->ports
= AR8216_NUM_PORTS
;
1302 } else if (priv
->chip_type
== AR8327
) {
1303 swdev
->name
= "Atheros AR8327";
1304 swdev
->vlans
= AR8X16_MAX_VLANS
;
1305 swdev
->ports
= AR8327_NUM_PORTS
;
1307 swdev
->name
= "Atheros AR8216";
1308 swdev
->vlans
= AR8216_NUM_VLANS
;
1311 ret
= register_switch(&priv
->dev
, pdev
->attached_dev
);
1317 ret
= priv
->chip
->hw_init(priv
);
1321 ret
= ar8216_sw_reset_switch(&priv
->dev
);
1325 dev
->phy_ptr
= priv
;
1327 /* VID fixup only needed on ar8216 */
1328 if (pdev
->addr
== 0 && priv
->chip_type
== AR8216
) {
1329 dev
->priv_flags
|= IFF_NO_IP_ALIGN
;
1330 dev
->eth_mangle_rx
= ar8216_mangle_rx
;
1331 dev
->eth_mangle_tx
= ar8216_mangle_tx
;
1344 ar8216_read_status(struct phy_device
*phydev
)
1346 struct ar8216_priv
*priv
= phydev
->priv
;
1347 struct switch_port_link link
;
1350 if (phydev
->addr
!= 0)
1351 return genphy_read_status(phydev
);
1353 ar8216_read_port_link(priv
, phydev
->addr
, &link
);
1354 phydev
->link
= !!link
.link
;
1358 switch (link
.speed
) {
1359 case SWITCH_PORT_SPEED_10
:
1360 phydev
->speed
= SPEED_10
;
1362 case SWITCH_PORT_SPEED_100
:
1363 phydev
->speed
= SPEED_100
;
1365 case SWITCH_PORT_SPEED_1000
:
1366 phydev
->speed
= SPEED_1000
;
1371 phydev
->duplex
= link
.duplex
? DUPLEX_FULL
: DUPLEX_HALF
;
1373 /* flush the address translation unit */
1374 mutex_lock(&priv
->reg_mutex
);
1375 ret
= priv
->chip
->atu_flush(priv
);
1376 mutex_unlock(&priv
->reg_mutex
);
1378 phydev
->state
= PHY_RUNNING
;
1379 netif_carrier_on(phydev
->attached_dev
);
1380 phydev
->adjust_link(phydev
->attached_dev
);
1386 ar8216_config_aneg(struct phy_device
*phydev
)
1388 if (phydev
->addr
== 0)
1391 return genphy_config_aneg(phydev
);
1395 ar8216_probe(struct phy_device
*pdev
)
1397 struct ar8216_priv priv
;
1400 return ar8216_id_chip(&priv
);
1404 ar8216_remove(struct phy_device
*pdev
)
1406 struct ar8216_priv
*priv
= pdev
->priv
;
1407 struct net_device
*dev
= pdev
->attached_dev
;
1412 dev
->priv_flags
&= ~IFF_NO_IP_ALIGN
;
1413 dev
->eth_mangle_rx
= NULL
;
1414 dev
->eth_mangle_tx
= NULL
;
1416 if (pdev
->addr
== 0)
1417 unregister_switch(&priv
->dev
);
1421 static struct phy_driver ar8216_driver
= {
1422 .phy_id
= 0x004d0000,
1423 .name
= "Atheros AR8216/AR8236/AR8316",
1424 .phy_id_mask
= 0xffff0000,
1425 .features
= PHY_BASIC_FEATURES
,
1426 .probe
= ar8216_probe
,
1427 .remove
= ar8216_remove
,
1428 .config_init
= &ar8216_config_init
,
1429 .config_aneg
= &ar8216_config_aneg
,
1430 .read_status
= &ar8216_read_status
,
1431 .driver
= { .owner
= THIS_MODULE
},
1437 return phy_driver_register(&ar8216_driver
);
1443 phy_driver_unregister(&ar8216_driver
);
1446 module_init(ar8216_init
);
1447 module_exit(ar8216_exit
);
1448 MODULE_LICENSE("GPL");