2 * ar8216.h: AR8216 switch driver
4 * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
20 #define BITS(_s, _n) (((1UL << (_n)) - 1) << _s)
22 #define AR8XXX_CAP_GIGE BIT(0)
23 #define AR8XXX_CAP_MIB_COUNTERS BIT(1)
25 #define AR8XXX_NUM_PHYS 5
26 #define AR8216_PORT_CPU 0
27 #define AR8216_NUM_PORTS 6
28 #define AR8216_NUM_VLANS 16
29 #define AR8316_NUM_VLANS 4096
31 /* size of the vlan table */
32 #define AR8X16_MAX_VLANS 128
33 #define AR8X16_PROBE_RETRIES 10
34 #define AR8X16_MAX_PORTS 8
36 #define AR8XXX_REG_ARL_CTRL_AGE_TIME_SECS 7
37 #define AR8XXX_DEFAULT_ARL_AGE_TIME 300
39 /* Atheros specific MII registers */
40 #define MII_ATH_MMD_ADDR 0x0d
41 #define MII_ATH_MMD_DATA 0x0e
42 #define MII_ATH_DBG_ADDR 0x1d
43 #define MII_ATH_DBG_DATA 0x1e
45 #define AR8216_REG_CTRL 0x0000
46 #define AR8216_CTRL_REVISION BITS(0, 8)
47 #define AR8216_CTRL_REVISION_S 0
48 #define AR8216_CTRL_VERSION BITS(8, 8)
49 #define AR8216_CTRL_VERSION_S 8
50 #define AR8216_CTRL_RESET BIT(31)
52 #define AR8216_REG_FLOOD_MASK 0x002C
53 #define AR8216_FM_UNI_DEST_PORTS BITS(0, 6)
54 #define AR8216_FM_MULTI_DEST_PORTS BITS(16, 6)
55 #define AR8236_FM_CPU_BROADCAST_EN BIT(26)
56 #define AR8236_FM_CPU_BCAST_FWD_EN BIT(25)
58 #define AR8216_REG_GLOBAL_CTRL 0x0030
59 #define AR8216_GCTRL_MTU BITS(0, 11)
60 #define AR8236_GCTRL_MTU BITS(0, 14)
61 #define AR8316_GCTRL_MTU BITS(0, 14)
63 #define AR8216_REG_VTU 0x0040
64 #define AR8216_VTU_OP BITS(0, 3)
65 #define AR8216_VTU_OP_NOOP 0x0
66 #define AR8216_VTU_OP_FLUSH 0x1
67 #define AR8216_VTU_OP_LOAD 0x2
68 #define AR8216_VTU_OP_PURGE 0x3
69 #define AR8216_VTU_OP_REMOVE_PORT 0x4
70 #define AR8216_VTU_ACTIVE BIT(3)
71 #define AR8216_VTU_FULL BIT(4)
72 #define AR8216_VTU_PORT BITS(8, 4)
73 #define AR8216_VTU_PORT_S 8
74 #define AR8216_VTU_VID BITS(16, 12)
75 #define AR8216_VTU_VID_S 16
76 #define AR8216_VTU_PRIO BITS(28, 3)
77 #define AR8216_VTU_PRIO_S 28
78 #define AR8216_VTU_PRIO_EN BIT(31)
80 #define AR8216_REG_VTU_DATA 0x0044
81 #define AR8216_VTUDATA_MEMBER BITS(0, 10)
82 #define AR8236_VTUDATA_MEMBER BITS(0, 7)
83 #define AR8216_VTUDATA_VALID BIT(11)
85 #define AR8216_REG_ATU_FUNC0 0x0050
86 #define AR8216_ATU_OP BITS(0, 3)
87 #define AR8216_ATU_OP_NOOP 0x0
88 #define AR8216_ATU_OP_FLUSH 0x1
89 #define AR8216_ATU_OP_LOAD 0x2
90 #define AR8216_ATU_OP_PURGE 0x3
91 #define AR8216_ATU_OP_FLUSH_UNLOCKED 0x4
92 #define AR8216_ATU_OP_FLUSH_PORT 0x5
93 #define AR8216_ATU_OP_GET_NEXT 0x6
94 #define AR8216_ATU_ACTIVE BIT(3)
95 #define AR8216_ATU_PORT_NUM BITS(8, 4)
96 #define AR8216_ATU_PORT_NUM_S 8
97 #define AR8216_ATU_FULL_VIO BIT(12)
98 #define AR8216_ATU_ADDR5 BITS(16, 8)
99 #define AR8216_ATU_ADDR5_S 16
100 #define AR8216_ATU_ADDR4 BITS(24, 8)
101 #define AR8216_ATU_ADDR4_S 24
103 #define AR8216_REG_ATU_FUNC1 0x0054
104 #define AR8216_ATU_ADDR3 BITS(0, 8)
105 #define AR8216_ATU_ADDR3_S 0
106 #define AR8216_ATU_ADDR2 BITS(8, 8)
107 #define AR8216_ATU_ADDR2_S 8
108 #define AR8216_ATU_ADDR1 BITS(16, 8)
109 #define AR8216_ATU_ADDR1_S 16
110 #define AR8216_ATU_ADDR0 BITS(24, 8)
111 #define AR8216_ATU_ADDR0_S 24
113 #define AR8216_REG_ATU_FUNC2 0x0058
114 #define AR8216_ATU_PORTS BITS(0, 6)
115 #define AR8216_ATU_PORTS_S 0
116 #define AR8216_ATU_PORT0 BIT(0)
117 #define AR8216_ATU_PORT1 BIT(1)
118 #define AR8216_ATU_PORT2 BIT(2)
119 #define AR8216_ATU_PORT3 BIT(3)
120 #define AR8216_ATU_PORT4 BIT(4)
121 #define AR8216_ATU_PORT5 BIT(5)
122 #define AR8216_ATU_STATUS BITS(16, 4)
123 #define AR8216_ATU_STATUS_S 16
125 #define AR8216_REG_ATU_CTRL 0x005C
126 #define AR8216_ATU_CTRL_AGE_EN BIT(17)
127 #define AR8216_ATU_CTRL_AGE_TIME BITS(0, 16)
128 #define AR8216_ATU_CTRL_AGE_TIME_S 0
129 #define AR8236_ATU_CTRL_RES BIT(20)
131 #define AR8216_REG_MIB_FUNC 0x0080
132 #define AR8216_MIB_TIMER BITS(0, 16)
133 #define AR8216_MIB_AT_HALF_EN BIT(16)
134 #define AR8216_MIB_BUSY BIT(17)
135 #define AR8216_MIB_FUNC BITS(24, 3)
136 #define AR8216_MIB_FUNC_S 24
137 #define AR8216_MIB_FUNC_NO_OP 0x0
138 #define AR8216_MIB_FUNC_FLUSH 0x1
139 #define AR8216_MIB_FUNC_CAPTURE 0x3
140 #define AR8236_MIB_EN BIT(30)
142 #define AR8216_REG_GLOBAL_CPUPORT 0x0078
143 #define AR8216_GLOBAL_CPUPORT_MIRROR_PORT BITS(4, 4)
144 #define AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S 4
146 #define AR8216_PORT_OFFSET(_i) (0x0100 * (_i + 1))
147 #define AR8216_REG_PORT_STATUS(_i) (AR8216_PORT_OFFSET(_i) + 0x0000)
148 #define AR8216_PORT_STATUS_SPEED BITS(0,2)
149 #define AR8216_PORT_STATUS_SPEED_S 0
150 #define AR8216_PORT_STATUS_TXMAC BIT(2)
151 #define AR8216_PORT_STATUS_RXMAC BIT(3)
152 #define AR8216_PORT_STATUS_TXFLOW BIT(4)
153 #define AR8216_PORT_STATUS_RXFLOW BIT(5)
154 #define AR8216_PORT_STATUS_DUPLEX BIT(6)
155 #define AR8216_PORT_STATUS_LINK_UP BIT(8)
156 #define AR8216_PORT_STATUS_LINK_AUTO BIT(9)
157 #define AR8216_PORT_STATUS_LINK_PAUSE BIT(10)
158 #define AR8216_PORT_STATUS_FLOW_CONTROL BIT(12)
160 #define AR8216_REG_PORT_CTRL(_i) (AR8216_PORT_OFFSET(_i) + 0x0004)
162 /* port forwarding state */
163 #define AR8216_PORT_CTRL_STATE BITS(0, 3)
164 #define AR8216_PORT_CTRL_STATE_S 0
166 #define AR8216_PORT_CTRL_LEARN_LOCK BIT(7)
168 /* egress 802.1q mode */
169 #define AR8216_PORT_CTRL_VLAN_MODE BITS(8, 2)
170 #define AR8216_PORT_CTRL_VLAN_MODE_S 8
172 #define AR8216_PORT_CTRL_IGMP_SNOOP BIT(10)
173 #define AR8216_PORT_CTRL_HEADER BIT(11)
174 #define AR8216_PORT_CTRL_MAC_LOOP BIT(12)
175 #define AR8216_PORT_CTRL_SINGLE_VLAN BIT(13)
176 #define AR8216_PORT_CTRL_LEARN BIT(14)
177 #define AR8216_PORT_CTRL_MIRROR_TX BIT(16)
178 #define AR8216_PORT_CTRL_MIRROR_RX BIT(17)
180 #define AR8216_REG_PORT_VLAN(_i) (AR8216_PORT_OFFSET(_i) + 0x0008)
182 #define AR8216_PORT_VLAN_DEFAULT_ID BITS(0, 12)
183 #define AR8216_PORT_VLAN_DEFAULT_ID_S 0
185 #define AR8216_PORT_VLAN_DEST_PORTS BITS(16, 9)
186 #define AR8216_PORT_VLAN_DEST_PORTS_S 16
188 /* bit0 added to the priority field of egress frames */
189 #define AR8216_PORT_VLAN_TX_PRIO BIT(27)
191 /* port default priority */
192 #define AR8216_PORT_VLAN_PRIORITY BITS(28, 2)
193 #define AR8216_PORT_VLAN_PRIORITY_S 28
195 /* ingress 802.1q mode */
196 #define AR8216_PORT_VLAN_MODE BITS(30, 2)
197 #define AR8216_PORT_VLAN_MODE_S 30
199 #define AR8216_REG_PORT_RATE(_i) (AR8216_PORT_OFFSET(_i) + 0x000c)
200 #define AR8216_REG_PORT_PRIO(_i) (AR8216_PORT_OFFSET(_i) + 0x0010)
202 #define AR8216_STATS_RXBROAD 0x00
203 #define AR8216_STATS_RXPAUSE 0x04
204 #define AR8216_STATS_RXMULTI 0x08
205 #define AR8216_STATS_RXFCSERR 0x0c
206 #define AR8216_STATS_RXALIGNERR 0x10
207 #define AR8216_STATS_RXRUNT 0x14
208 #define AR8216_STATS_RXFRAGMENT 0x18
209 #define AR8216_STATS_RX64BYTE 0x1c
210 #define AR8216_STATS_RX128BYTE 0x20
211 #define AR8216_STATS_RX256BYTE 0x24
212 #define AR8216_STATS_RX512BYTE 0x28
213 #define AR8216_STATS_RX1024BYTE 0x2c
214 #define AR8216_STATS_RXMAXBYTE 0x30
215 #define AR8216_STATS_RXTOOLONG 0x34
216 #define AR8216_STATS_RXGOODBYTE 0x38
217 #define AR8216_STATS_RXBADBYTE 0x40
218 #define AR8216_STATS_RXOVERFLOW 0x48
219 #define AR8216_STATS_FILTERED 0x4c
220 #define AR8216_STATS_TXBROAD 0x50
221 #define AR8216_STATS_TXPAUSE 0x54
222 #define AR8216_STATS_TXMULTI 0x58
223 #define AR8216_STATS_TXUNDERRUN 0x5c
224 #define AR8216_STATS_TX64BYTE 0x60
225 #define AR8216_STATS_TX128BYTE 0x64
226 #define AR8216_STATS_TX256BYTE 0x68
227 #define AR8216_STATS_TX512BYTE 0x6c
228 #define AR8216_STATS_TX1024BYTE 0x70
229 #define AR8216_STATS_TXMAXBYTE 0x74
230 #define AR8216_STATS_TXOVERSIZE 0x78
231 #define AR8216_STATS_TXBYTE 0x7c
232 #define AR8216_STATS_TXCOLLISION 0x84
233 #define AR8216_STATS_TXABORTCOL 0x88
234 #define AR8216_STATS_TXMULTICOL 0x8c
235 #define AR8216_STATS_TXSINGLECOL 0x90
236 #define AR8216_STATS_TXEXCDEFER 0x94
237 #define AR8216_STATS_TXDEFER 0x98
238 #define AR8216_STATS_TXLATECOL 0x9c
240 #define AR8236_REG_PORT_VLAN(_i) (AR8216_PORT_OFFSET((_i)) + 0x0008)
241 #define AR8236_PORT_VLAN_DEFAULT_ID BITS(16, 12)
242 #define AR8236_PORT_VLAN_DEFAULT_ID_S 16
243 #define AR8236_PORT_VLAN_PRIORITY BITS(29, 3)
244 #define AR8236_PORT_VLAN_PRIORITY_S 28
246 #define AR8236_REG_PORT_VLAN2(_i) (AR8216_PORT_OFFSET((_i)) + 0x000c)
247 #define AR8236_PORT_VLAN2_MEMBER BITS(16, 7)
248 #define AR8236_PORT_VLAN2_MEMBER_S 16
249 #define AR8236_PORT_VLAN2_TX_PRIO BIT(23)
250 #define AR8236_PORT_VLAN2_VLAN_MODE BITS(30, 2)
251 #define AR8236_PORT_VLAN2_VLAN_MODE_S 30
253 #define AR8236_STATS_RXBROAD 0x00
254 #define AR8236_STATS_RXPAUSE 0x04
255 #define AR8236_STATS_RXMULTI 0x08
256 #define AR8236_STATS_RXFCSERR 0x0c
257 #define AR8236_STATS_RXALIGNERR 0x10
258 #define AR8236_STATS_RXRUNT 0x14
259 #define AR8236_STATS_RXFRAGMENT 0x18
260 #define AR8236_STATS_RX64BYTE 0x1c
261 #define AR8236_STATS_RX128BYTE 0x20
262 #define AR8236_STATS_RX256BYTE 0x24
263 #define AR8236_STATS_RX512BYTE 0x28
264 #define AR8236_STATS_RX1024BYTE 0x2c
265 #define AR8236_STATS_RX1518BYTE 0x30
266 #define AR8236_STATS_RXMAXBYTE 0x34
267 #define AR8236_STATS_RXTOOLONG 0x38
268 #define AR8236_STATS_RXGOODBYTE 0x3c
269 #define AR8236_STATS_RXBADBYTE 0x44
270 #define AR8236_STATS_RXOVERFLOW 0x4c
271 #define AR8236_STATS_FILTERED 0x50
272 #define AR8236_STATS_TXBROAD 0x54
273 #define AR8236_STATS_TXPAUSE 0x58
274 #define AR8236_STATS_TXMULTI 0x5c
275 #define AR8236_STATS_TXUNDERRUN 0x60
276 #define AR8236_STATS_TX64BYTE 0x64
277 #define AR8236_STATS_TX128BYTE 0x68
278 #define AR8236_STATS_TX256BYTE 0x6c
279 #define AR8236_STATS_TX512BYTE 0x70
280 #define AR8236_STATS_TX1024BYTE 0x74
281 #define AR8236_STATS_TX1518BYTE 0x78
282 #define AR8236_STATS_TXMAXBYTE 0x7c
283 #define AR8236_STATS_TXOVERSIZE 0x80
284 #define AR8236_STATS_TXBYTE 0x84
285 #define AR8236_STATS_TXCOLLISION 0x8c
286 #define AR8236_STATS_TXABORTCOL 0x90
287 #define AR8236_STATS_TXMULTICOL 0x94
288 #define AR8236_STATS_TXSINGLECOL 0x98
289 #define AR8236_STATS_TXEXCDEFER 0x9c
290 #define AR8236_STATS_TXDEFER 0xa0
291 #define AR8236_STATS_TXLATECOL 0xa4
293 #define AR8316_REG_POSTRIP 0x0008
294 #define AR8316_POSTRIP_MAC0_GMII_EN BIT(0)
295 #define AR8316_POSTRIP_MAC0_RGMII_EN BIT(1)
296 #define AR8316_POSTRIP_PHY4_GMII_EN BIT(2)
297 #define AR8316_POSTRIP_PHY4_RGMII_EN BIT(3)
298 #define AR8316_POSTRIP_MAC0_MAC_MODE BIT(4)
299 #define AR8316_POSTRIP_RTL_MODE BIT(5)
300 #define AR8316_POSTRIP_RGMII_RXCLK_DELAY_EN BIT(6)
301 #define AR8316_POSTRIP_RGMII_TXCLK_DELAY_EN BIT(7)
302 #define AR8316_POSTRIP_SERDES_EN BIT(8)
303 #define AR8316_POSTRIP_SEL_ANA_RST BIT(9)
304 #define AR8316_POSTRIP_GATE_25M_EN BIT(10)
305 #define AR8316_POSTRIP_SEL_CLK25M BIT(11)
306 #define AR8316_POSTRIP_HIB_PULSE_HW BIT(12)
307 #define AR8316_POSTRIP_DBG_MODE_I BIT(13)
308 #define AR8316_POSTRIP_MAC5_MAC_MODE BIT(14)
309 #define AR8316_POSTRIP_MAC5_PHY_MODE BIT(15)
310 #define AR8316_POSTRIP_POWER_DOWN_HW BIT(16)
311 #define AR8316_POSTRIP_LPW_STATE_EN BIT(17)
312 #define AR8316_POSTRIP_MAN_EN BIT(18)
313 #define AR8316_POSTRIP_PHY_PLL_ON BIT(19)
314 #define AR8316_POSTRIP_LPW_EXIT BIT(20)
315 #define AR8316_POSTRIP_TXDELAY_S0 BIT(21)
316 #define AR8316_POSTRIP_TXDELAY_S1 BIT(22)
317 #define AR8316_POSTRIP_RXDELAY_S0 BIT(23)
318 #define AR8316_POSTRIP_LED_OPEN_EN BIT(24)
319 #define AR8316_POSTRIP_SPI_EN BIT(25)
320 #define AR8316_POSTRIP_RXDELAY_S1 BIT(26)
321 #define AR8316_POSTRIP_POWER_ON_SEL BIT(31)
325 AR8216_PORT_SPEED_10M
= 0,
326 AR8216_PORT_SPEED_100M
= 1,
327 AR8216_PORT_SPEED_1000M
= 2,
328 AR8216_PORT_SPEED_ERR
= 3,
331 /* ingress 802.1q mode */
333 AR8216_IN_PORT_ONLY
= 0,
334 AR8216_IN_PORT_FALLBACK
= 1,
335 AR8216_IN_VLAN_ONLY
= 2,
339 /* egress 802.1q mode */
342 AR8216_OUT_STRIP_VLAN
= 1,
343 AR8216_OUT_ADD_VLAN
= 2
346 /* port forwarding state */
348 AR8216_PORT_STATE_DISABLED
= 0,
349 AR8216_PORT_STATE_BLOCK
= 1,
350 AR8216_PORT_STATE_LISTEN
= 2,
351 AR8216_PORT_STATE_LEARN
= 3,
352 AR8216_PORT_STATE_FORWARD
= 4
356 AR8XXX_VER_AR8216
= 0x01,
357 AR8XXX_VER_AR8236
= 0x03,
358 AR8XXX_VER_AR8316
= 0x10,
359 AR8XXX_VER_AR8327
= 0x12,
360 AR8XXX_VER_AR8337
= 0x13,
363 #define AR8XXX_NUM_ARL_RECORDS 100
366 AR8XXX_ARL_INITIALIZE
,
377 struct ar8xxx_mib_desc
{
385 bool config_at_probe
;
388 /* parameters to calculate REG_PORT_STATS_BASE */
389 unsigned reg_port_stats_start
;
390 unsigned reg_port_stats_length
;
392 unsigned reg_arl_ctrl
;
394 int (*hw_init
)(struct ar8xxx_priv
*priv
);
395 void (*cleanup
)(struct ar8xxx_priv
*priv
);
400 const struct switch_dev_ops
*swops
;
402 void (*init_globals
)(struct ar8xxx_priv
*priv
);
403 void (*init_port
)(struct ar8xxx_priv
*priv
, int port
);
404 void (*setup_port
)(struct ar8xxx_priv
*priv
, int port
, u32 members
);
405 u32 (*read_port_status
)(struct ar8xxx_priv
*priv
, int port
);
406 u32 (*read_port_eee_status
)(struct ar8xxx_priv
*priv
, int port
);
407 int (*atu_flush
)(struct ar8xxx_priv
*priv
);
408 int (*atu_flush_port
)(struct ar8xxx_priv
*priv
, int port
);
409 void (*vtu_flush
)(struct ar8xxx_priv
*priv
);
410 void (*vtu_load_vlan
)(struct ar8xxx_priv
*priv
, u32 vid
, u32 port_mask
);
411 void (*phy_fixup
)(struct ar8xxx_priv
*priv
, int phy
);
412 void (*set_mirror_regs
)(struct ar8xxx_priv
*priv
);
413 void (*get_arl_entry
)(struct ar8xxx_priv
*priv
, struct arl_entry
*a
,
414 u32
*status
, enum arl_op op
);
415 int (*sw_hw_apply
)(struct switch_dev
*dev
);
416 void (*phy_rgmii_set
)(struct ar8xxx_priv
*priv
, struct phy_device
*phydev
);
418 const struct ar8xxx_mib_desc
*mib_decs
;
424 struct switch_dev dev
;
425 struct mii_bus
*mii_bus
;
426 struct phy_device
*phy
;
429 int (*get_port_link
)(unsigned port
);
431 const struct net_device_ops
*ndo_old
;
432 struct net_device_ops ndo
;
433 struct mutex reg_mutex
;
436 const struct ar8xxx_chip
*chip
;
441 struct arl_entry arl_table
[AR8XXX_NUM_ARL_RECORDS
];
442 char arl_buf
[AR8XXX_NUM_ARL_RECORDS
* 32 + 256];
443 bool link_up
[AR8X16_MAX_PORTS
];
447 struct mutex mib_lock
;
448 struct delayed_work mib_work
;
452 struct list_head list
;
453 unsigned int use_count
;
455 /* all fields below are cleared on reset */
457 u16 vlan_id
[AR8X16_MAX_VLANS
];
458 u8 vlan_table
[AR8X16_MAX_VLANS
];
460 u16 pvid
[AR8X16_MAX_PORTS
];
468 u8 port_vlan_prio
[AR8X16_MAX_PORTS
];
472 ar8xxx_mii_read32(struct ar8xxx_priv
*priv
, int phy_id
, int regnum
);
474 ar8xxx_mii_write32(struct ar8xxx_priv
*priv
, int phy_id
, int regnum
, u32 val
);
476 ar8xxx_read(struct ar8xxx_priv
*priv
, int reg
);
478 ar8xxx_write(struct ar8xxx_priv
*priv
, int reg
, u32 val
);
480 ar8xxx_rmw(struct ar8xxx_priv
*priv
, int reg
, u32 mask
, u32 val
);
483 ar8xxx_phy_dbg_read(struct ar8xxx_priv
*priv
, int phy_addr
,
484 u16 dbg_addr
, u16
*dbg_data
);
486 ar8xxx_phy_dbg_write(struct ar8xxx_priv
*priv
, int phy_addr
,
487 u16 dbg_addr
, u16 dbg_data
);
489 ar8xxx_phy_mmd_write(struct ar8xxx_priv
*priv
, int phy_addr
, u16 addr
, u16 reg
, u16 data
);
491 ar8xxx_phy_mmd_read(struct ar8xxx_priv
*priv
, int phy_addr
, u16 addr
, u16 reg
);
493 ar8xxx_phy_init(struct ar8xxx_priv
*priv
);
495 ar8xxx_sw_set_vlan(struct switch_dev
*dev
, const struct switch_attr
*attr
,
496 struct switch_val
*val
);
498 ar8xxx_sw_get_vlan(struct switch_dev
*dev
, const struct switch_attr
*attr
,
499 struct switch_val
*val
);
501 ar8xxx_sw_set_reset_mibs(struct switch_dev
*dev
,
502 const struct switch_attr
*attr
,
503 struct switch_val
*val
);
505 ar8xxx_sw_set_mirror_rx_enable(struct switch_dev
*dev
,
506 const struct switch_attr
*attr
,
507 struct switch_val
*val
);
509 ar8xxx_sw_get_mirror_rx_enable(struct switch_dev
*dev
,
510 const struct switch_attr
*attr
,
511 struct switch_val
*val
);
513 ar8xxx_sw_set_mirror_tx_enable(struct switch_dev
*dev
,
514 const struct switch_attr
*attr
,
515 struct switch_val
*val
);
517 ar8xxx_sw_get_mirror_tx_enable(struct switch_dev
*dev
,
518 const struct switch_attr
*attr
,
519 struct switch_val
*val
);
521 ar8xxx_sw_set_mirror_monitor_port(struct switch_dev
*dev
,
522 const struct switch_attr
*attr
,
523 struct switch_val
*val
);
525 ar8xxx_sw_get_mirror_monitor_port(struct switch_dev
*dev
,
526 const struct switch_attr
*attr
,
527 struct switch_val
*val
);
529 ar8xxx_sw_set_mirror_source_port(struct switch_dev
*dev
,
530 const struct switch_attr
*attr
,
531 struct switch_val
*val
);
533 ar8xxx_sw_get_mirror_source_port(struct switch_dev
*dev
,
534 const struct switch_attr
*attr
,
535 struct switch_val
*val
);
537 ar8xxx_sw_set_pvid(struct switch_dev
*dev
, int port
, int vlan
);
539 ar8xxx_sw_get_pvid(struct switch_dev
*dev
, int port
, int *vlan
);
541 ar8xxx_sw_hw_apply(struct switch_dev
*dev
);
543 ar8xxx_sw_reset_switch(struct switch_dev
*dev
);
545 ar8xxx_sw_get_port_link(struct switch_dev
*dev
, int port
,
546 struct switch_port_link
*link
);
548 ar8xxx_sw_set_port_reset_mib(struct switch_dev
*dev
,
549 const struct switch_attr
*attr
,
550 struct switch_val
*val
);
552 ar8xxx_sw_get_port_mib(struct switch_dev
*dev
,
553 const struct switch_attr
*attr
,
554 struct switch_val
*val
);
556 ar8xxx_sw_get_arl_age_time(struct switch_dev
*dev
,
557 const struct switch_attr
*attr
,
558 struct switch_val
*val
);
560 ar8xxx_sw_set_arl_age_time(struct switch_dev
*dev
,
561 const struct switch_attr
*attr
,
562 struct switch_val
*val
);
564 ar8xxx_sw_get_arl_table(struct switch_dev
*dev
,
565 const struct switch_attr
*attr
,
566 struct switch_val
*val
);
568 ar8xxx_sw_set_flush_arl_table(struct switch_dev
*dev
,
569 const struct switch_attr
*attr
,
570 struct switch_val
*val
);
572 ar8xxx_sw_set_flush_port_arl_table(struct switch_dev
*dev
,
573 const struct switch_attr
*attr
,
574 struct switch_val
*val
);
576 ar8216_wait_bit(struct ar8xxx_priv
*priv
, int reg
, u32 mask
, u32 val
);
578 static inline struct ar8xxx_priv
*
579 swdev_to_ar8xxx(struct switch_dev
*swdev
)
581 return container_of(swdev
, struct ar8xxx_priv
, dev
);
584 static inline bool ar8xxx_has_gige(struct ar8xxx_priv
*priv
)
586 return priv
->chip
->caps
& AR8XXX_CAP_GIGE
;
589 static inline bool ar8xxx_has_mib_counters(struct ar8xxx_priv
*priv
)
591 return priv
->chip
->caps
& AR8XXX_CAP_MIB_COUNTERS
;
594 static inline bool chip_is_ar8216(struct ar8xxx_priv
*priv
)
596 return priv
->chip_ver
== AR8XXX_VER_AR8216
;
599 static inline bool chip_is_ar8236(struct ar8xxx_priv
*priv
)
601 return priv
->chip_ver
== AR8XXX_VER_AR8236
;
604 static inline bool chip_is_ar8316(struct ar8xxx_priv
*priv
)
606 return priv
->chip_ver
== AR8XXX_VER_AR8316
;
609 static inline bool chip_is_ar8327(struct ar8xxx_priv
*priv
)
611 return priv
->chip_ver
== AR8XXX_VER_AR8327
;
614 static inline bool chip_is_ar8337(struct ar8xxx_priv
*priv
)
616 return priv
->chip_ver
== AR8XXX_VER_AR8337
;
620 ar8xxx_reg_set(struct ar8xxx_priv
*priv
, int reg
, u32 val
)
622 ar8xxx_rmw(priv
, reg
, 0, val
);
626 ar8xxx_reg_clear(struct ar8xxx_priv
*priv
, int reg
, u32 val
)
628 ar8xxx_rmw(priv
, reg
, val
, 0);
632 split_addr(u32 regaddr
, u16
*r1
, u16
*r2
, u16
*page
)
635 *r1
= regaddr
& 0x1e;
641 *page
= regaddr
& 0x1ff;
645 wait_for_page_switch(void)