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generic: ar8216: ar8229: add phy_read/phy_write
[openwrt/staging/jow.git] / target / linux / generic / files / drivers / net / phy / ar8216.h
1 /*
2 * ar8216.h: AR8216 switch driver
3 *
4 * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17 #ifndef __AR8216_H
18 #define __AR8216_H
19
20 #define BITS(_s, _n) (((1UL << (_n)) - 1) << _s)
21
22 #define AR8XXX_CAP_GIGE BIT(0)
23 #define AR8XXX_CAP_MIB_COUNTERS BIT(1)
24
25 #define AR8XXX_NUM_PHYS 5
26 #define AR8216_PORT_CPU 0
27 #define AR8216_NUM_PORTS 6
28 #define AR8216_NUM_VLANS 16
29 #define AR8316_NUM_VLANS 4096
30
31 /* size of the vlan table */
32 #define AR8X16_MAX_VLANS 128
33 #define AR8X16_PROBE_RETRIES 10
34 #define AR8X16_MAX_PORTS 8
35
36 #define AR8XXX_REG_ARL_CTRL_AGE_TIME_SECS 7
37 #define AR8XXX_DEFAULT_ARL_AGE_TIME 300
38
39 /* Atheros specific MII registers */
40 #define MII_ATH_MMD_ADDR 0x0d
41 #define MII_ATH_MMD_DATA 0x0e
42 #define MII_ATH_DBG_ADDR 0x1d
43 #define MII_ATH_DBG_DATA 0x1e
44
45 #define AR8216_REG_CTRL 0x0000
46 #define AR8216_CTRL_REVISION BITS(0, 8)
47 #define AR8216_CTRL_REVISION_S 0
48 #define AR8216_CTRL_VERSION BITS(8, 8)
49 #define AR8216_CTRL_VERSION_S 8
50 #define AR8216_CTRL_RESET BIT(31)
51
52 #define AR8216_REG_FLOOD_MASK 0x002C
53 #define AR8216_FM_UNI_DEST_PORTS BITS(0, 6)
54 #define AR8216_FM_MULTI_DEST_PORTS BITS(16, 6)
55 #define AR8229_FLOOD_MASK_MC_DP(_p) BIT(16 + (_p))
56 #define AR8229_FLOOD_MASK_BC_DP(_p) BIT(25 + (_p))
57 #define AR8236_FM_CPU_BROADCAST_EN BIT(26)
58 #define AR8236_FM_CPU_BCAST_FWD_EN BIT(25)
59
60 #define AR8216_REG_GLOBAL_CTRL 0x0030
61 #define AR8216_GCTRL_MTU BITS(0, 11)
62 #define AR8236_GCTRL_MTU BITS(0, 14)
63 #define AR8316_GCTRL_MTU BITS(0, 14)
64
65 #define AR8216_REG_VTU 0x0040
66 #define AR8216_VTU_OP BITS(0, 3)
67 #define AR8216_VTU_OP_NOOP 0x0
68 #define AR8216_VTU_OP_FLUSH 0x1
69 #define AR8216_VTU_OP_LOAD 0x2
70 #define AR8216_VTU_OP_PURGE 0x3
71 #define AR8216_VTU_OP_REMOVE_PORT 0x4
72 #define AR8216_VTU_ACTIVE BIT(3)
73 #define AR8216_VTU_FULL BIT(4)
74 #define AR8216_VTU_PORT BITS(8, 4)
75 #define AR8216_VTU_PORT_S 8
76 #define AR8216_VTU_VID BITS(16, 12)
77 #define AR8216_VTU_VID_S 16
78 #define AR8216_VTU_PRIO BITS(28, 3)
79 #define AR8216_VTU_PRIO_S 28
80 #define AR8216_VTU_PRIO_EN BIT(31)
81
82 #define AR8216_REG_VTU_DATA 0x0044
83 #define AR8216_VTUDATA_MEMBER BITS(0, 10)
84 #define AR8236_VTUDATA_MEMBER BITS(0, 7)
85 #define AR8216_VTUDATA_VALID BIT(11)
86
87 #define AR8216_REG_ATU_FUNC0 0x0050
88 #define AR8216_ATU_OP BITS(0, 3)
89 #define AR8216_ATU_OP_NOOP 0x0
90 #define AR8216_ATU_OP_FLUSH 0x1
91 #define AR8216_ATU_OP_LOAD 0x2
92 #define AR8216_ATU_OP_PURGE 0x3
93 #define AR8216_ATU_OP_FLUSH_UNLOCKED 0x4
94 #define AR8216_ATU_OP_FLUSH_PORT 0x5
95 #define AR8216_ATU_OP_GET_NEXT 0x6
96 #define AR8216_ATU_ACTIVE BIT(3)
97 #define AR8216_ATU_PORT_NUM BITS(8, 4)
98 #define AR8216_ATU_PORT_NUM_S 8
99 #define AR8216_ATU_FULL_VIO BIT(12)
100 #define AR8216_ATU_ADDR5 BITS(16, 8)
101 #define AR8216_ATU_ADDR5_S 16
102 #define AR8216_ATU_ADDR4 BITS(24, 8)
103 #define AR8216_ATU_ADDR4_S 24
104
105 #define AR8216_REG_ATU_FUNC1 0x0054
106 #define AR8216_ATU_ADDR3 BITS(0, 8)
107 #define AR8216_ATU_ADDR3_S 0
108 #define AR8216_ATU_ADDR2 BITS(8, 8)
109 #define AR8216_ATU_ADDR2_S 8
110 #define AR8216_ATU_ADDR1 BITS(16, 8)
111 #define AR8216_ATU_ADDR1_S 16
112 #define AR8216_ATU_ADDR0 BITS(24, 8)
113 #define AR8216_ATU_ADDR0_S 24
114
115 #define AR8216_REG_ATU_FUNC2 0x0058
116 #define AR8216_ATU_PORTS BITS(0, 6)
117 #define AR8216_ATU_PORTS_S 0
118 #define AR8216_ATU_PORT0 BIT(0)
119 #define AR8216_ATU_PORT1 BIT(1)
120 #define AR8216_ATU_PORT2 BIT(2)
121 #define AR8216_ATU_PORT3 BIT(3)
122 #define AR8216_ATU_PORT4 BIT(4)
123 #define AR8216_ATU_PORT5 BIT(5)
124 #define AR8216_ATU_STATUS BITS(16, 4)
125 #define AR8216_ATU_STATUS_S 16
126
127 #define AR8216_REG_ATU_CTRL 0x005C
128 #define AR8216_ATU_CTRL_AGE_EN BIT(17)
129 #define AR8216_ATU_CTRL_AGE_TIME BITS(0, 16)
130 #define AR8216_ATU_CTRL_AGE_TIME_S 0
131 #define AR8236_ATU_CTRL_RES BIT(20)
132 #define AR8216_ATU_CTRL_LEARN_CHANGE BIT(18)
133
134 #define AR8216_REG_TAG_PRIORITY 0x0070
135
136 #define AR8216_REG_SERVICE_TAG 0x0074
137 #define AR8216_SERVICE_TAG_M BITS(0, 16)
138
139 #define AR8216_REG_MIB_FUNC 0x0080
140 #define AR8216_MIB_TIMER BITS(0, 16)
141 #define AR8216_MIB_AT_HALF_EN BIT(16)
142 #define AR8216_MIB_BUSY BIT(17)
143 #define AR8216_MIB_FUNC BITS(24, 3)
144 #define AR8216_MIB_FUNC_S 24
145 #define AR8216_MIB_FUNC_NO_OP 0x0
146 #define AR8216_MIB_FUNC_FLUSH 0x1
147 #define AR8216_MIB_FUNC_CAPTURE 0x3
148 #define AR8236_MIB_EN BIT(30)
149
150 #define AR8216_REG_GLOBAL_CPUPORT 0x0078
151 #define AR8216_GLOBAL_CPUPORT_MIRROR_PORT BITS(4, 4)
152 #define AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S 4
153 #define AR8216_GLOBAL_CPUPORT_EN BIT(8)
154
155 #define AR8216_REG_MDIO_CTRL 0x98
156 #define AR8216_MDIO_CTRL_DATA_M BITS(0, 16)
157 #define AR8216_MDIO_CTRL_REG_ADDR_S 16
158 #define AR8216_MDIO_CTRL_PHY_ADDR_S 21
159 #define AR8216_MDIO_CTRL_CMD_WRITE 0
160 #define AR8216_MDIO_CTRL_CMD_READ BIT(27)
161 #define AR8216_MDIO_CTRL_MASTER_EN BIT(30)
162 #define AR8216_MDIO_CTRL_BUSY BIT(31)
163
164 #define AR8216_PORT_OFFSET(_i) (0x0100 * (_i + 1))
165 #define AR8216_REG_PORT_STATUS(_i) (AR8216_PORT_OFFSET(_i) + 0x0000)
166 #define AR8216_PORT_STATUS_SPEED BITS(0,2)
167 #define AR8216_PORT_STATUS_SPEED_S 0
168 #define AR8216_PORT_STATUS_TXMAC BIT(2)
169 #define AR8216_PORT_STATUS_RXMAC BIT(3)
170 #define AR8216_PORT_STATUS_TXFLOW BIT(4)
171 #define AR8216_PORT_STATUS_RXFLOW BIT(5)
172 #define AR8216_PORT_STATUS_DUPLEX BIT(6)
173 #define AR8216_PORT_STATUS_LINK_UP BIT(8)
174 #define AR8216_PORT_STATUS_LINK_AUTO BIT(9)
175 #define AR8216_PORT_STATUS_LINK_PAUSE BIT(10)
176 #define AR8216_PORT_STATUS_FLOW_CONTROL BIT(12)
177
178 #define AR8216_REG_PORT_CTRL(_i) (AR8216_PORT_OFFSET(_i) + 0x0004)
179
180 /* port forwarding state */
181 #define AR8216_PORT_CTRL_STATE BITS(0, 3)
182 #define AR8216_PORT_CTRL_STATE_S 0
183
184 #define AR8216_PORT_CTRL_LEARN_LOCK BIT(7)
185
186 /* egress 802.1q mode */
187 #define AR8216_PORT_CTRL_VLAN_MODE BITS(8, 2)
188 #define AR8216_PORT_CTRL_VLAN_MODE_S 8
189
190 #define AR8216_PORT_CTRL_IGMP_SNOOP BIT(10)
191 #define AR8216_PORT_CTRL_HEADER BIT(11)
192 #define AR8216_PORT_CTRL_MAC_LOOP BIT(12)
193 #define AR8216_PORT_CTRL_SINGLE_VLAN BIT(13)
194 #define AR8216_PORT_CTRL_LEARN BIT(14)
195 #define AR8216_PORT_CTRL_MIRROR_TX BIT(16)
196 #define AR8216_PORT_CTRL_MIRROR_RX BIT(17)
197
198 #define AR8216_REG_PORT_VLAN(_i) (AR8216_PORT_OFFSET(_i) + 0x0008)
199
200 #define AR8216_PORT_VLAN_DEFAULT_ID BITS(0, 12)
201 #define AR8216_PORT_VLAN_DEFAULT_ID_S 0
202
203 #define AR8216_PORT_VLAN_DEST_PORTS BITS(16, 9)
204 #define AR8216_PORT_VLAN_DEST_PORTS_S 16
205
206 /* bit0 added to the priority field of egress frames */
207 #define AR8216_PORT_VLAN_TX_PRIO BIT(27)
208
209 /* port default priority */
210 #define AR8216_PORT_VLAN_PRIORITY BITS(28, 2)
211 #define AR8216_PORT_VLAN_PRIORITY_S 28
212
213 /* ingress 802.1q mode */
214 #define AR8216_PORT_VLAN_MODE BITS(30, 2)
215 #define AR8216_PORT_VLAN_MODE_S 30
216
217 #define AR8216_REG_PORT_RATE(_i) (AR8216_PORT_OFFSET(_i) + 0x000c)
218 #define AR8216_REG_PORT_PRIO(_i) (AR8216_PORT_OFFSET(_i) + 0x0010)
219
220 #define AR8216_STATS_RXBROAD 0x00
221 #define AR8216_STATS_RXPAUSE 0x04
222 #define AR8216_STATS_RXMULTI 0x08
223 #define AR8216_STATS_RXFCSERR 0x0c
224 #define AR8216_STATS_RXALIGNERR 0x10
225 #define AR8216_STATS_RXRUNT 0x14
226 #define AR8216_STATS_RXFRAGMENT 0x18
227 #define AR8216_STATS_RX64BYTE 0x1c
228 #define AR8216_STATS_RX128BYTE 0x20
229 #define AR8216_STATS_RX256BYTE 0x24
230 #define AR8216_STATS_RX512BYTE 0x28
231 #define AR8216_STATS_RX1024BYTE 0x2c
232 #define AR8216_STATS_RXMAXBYTE 0x30
233 #define AR8216_STATS_RXTOOLONG 0x34
234 #define AR8216_STATS_RXGOODBYTE 0x38
235 #define AR8216_STATS_RXBADBYTE 0x40
236 #define AR8216_STATS_RXOVERFLOW 0x48
237 #define AR8216_STATS_FILTERED 0x4c
238 #define AR8216_STATS_TXBROAD 0x50
239 #define AR8216_STATS_TXPAUSE 0x54
240 #define AR8216_STATS_TXMULTI 0x58
241 #define AR8216_STATS_TXUNDERRUN 0x5c
242 #define AR8216_STATS_TX64BYTE 0x60
243 #define AR8216_STATS_TX128BYTE 0x64
244 #define AR8216_STATS_TX256BYTE 0x68
245 #define AR8216_STATS_TX512BYTE 0x6c
246 #define AR8216_STATS_TX1024BYTE 0x70
247 #define AR8216_STATS_TXMAXBYTE 0x74
248 #define AR8216_STATS_TXOVERSIZE 0x78
249 #define AR8216_STATS_TXBYTE 0x7c
250 #define AR8216_STATS_TXCOLLISION 0x84
251 #define AR8216_STATS_TXABORTCOL 0x88
252 #define AR8216_STATS_TXMULTICOL 0x8c
253 #define AR8216_STATS_TXSINGLECOL 0x90
254 #define AR8216_STATS_TXEXCDEFER 0x94
255 #define AR8216_STATS_TXDEFER 0x98
256 #define AR8216_STATS_TXLATECOL 0x9c
257
258 #define AR8229_REG_OPER_MODE0 0x04
259 #define AR8229_OPER_MODE0_MAC_GMII_EN BIT(6)
260 #define AR8229_OPER_MODE0_PHY_MII_EN BIT(10)
261
262 #define AR8229_REG_OPER_MODE1 0x08
263 #define AR8229_REG_OPER_MODE1_PHY4_MII_EN BIT(28)
264
265 #define AR8229_REG_QM_CTRL 0x3c
266 #define AR8229_QM_CTRL_ARP_EN BIT(15)
267
268 #define AR8236_REG_PORT_VLAN(_i) (AR8216_PORT_OFFSET((_i)) + 0x0008)
269 #define AR8236_PORT_VLAN_DEFAULT_ID BITS(16, 12)
270 #define AR8236_PORT_VLAN_DEFAULT_ID_S 16
271 #define AR8236_PORT_VLAN_PRIORITY BITS(29, 3)
272 #define AR8236_PORT_VLAN_PRIORITY_S 28
273
274 #define AR8236_REG_PORT_VLAN2(_i) (AR8216_PORT_OFFSET((_i)) + 0x000c)
275 #define AR8236_PORT_VLAN2_MEMBER BITS(16, 7)
276 #define AR8236_PORT_VLAN2_MEMBER_S 16
277 #define AR8236_PORT_VLAN2_TX_PRIO BIT(23)
278 #define AR8236_PORT_VLAN2_VLAN_MODE BITS(30, 2)
279 #define AR8236_PORT_VLAN2_VLAN_MODE_S 30
280
281 #define AR8236_STATS_RXBROAD 0x00
282 #define AR8236_STATS_RXPAUSE 0x04
283 #define AR8236_STATS_RXMULTI 0x08
284 #define AR8236_STATS_RXFCSERR 0x0c
285 #define AR8236_STATS_RXALIGNERR 0x10
286 #define AR8236_STATS_RXRUNT 0x14
287 #define AR8236_STATS_RXFRAGMENT 0x18
288 #define AR8236_STATS_RX64BYTE 0x1c
289 #define AR8236_STATS_RX128BYTE 0x20
290 #define AR8236_STATS_RX256BYTE 0x24
291 #define AR8236_STATS_RX512BYTE 0x28
292 #define AR8236_STATS_RX1024BYTE 0x2c
293 #define AR8236_STATS_RX1518BYTE 0x30
294 #define AR8236_STATS_RXMAXBYTE 0x34
295 #define AR8236_STATS_RXTOOLONG 0x38
296 #define AR8236_STATS_RXGOODBYTE 0x3c
297 #define AR8236_STATS_RXBADBYTE 0x44
298 #define AR8236_STATS_RXOVERFLOW 0x4c
299 #define AR8236_STATS_FILTERED 0x50
300 #define AR8236_STATS_TXBROAD 0x54
301 #define AR8236_STATS_TXPAUSE 0x58
302 #define AR8236_STATS_TXMULTI 0x5c
303 #define AR8236_STATS_TXUNDERRUN 0x60
304 #define AR8236_STATS_TX64BYTE 0x64
305 #define AR8236_STATS_TX128BYTE 0x68
306 #define AR8236_STATS_TX256BYTE 0x6c
307 #define AR8236_STATS_TX512BYTE 0x70
308 #define AR8236_STATS_TX1024BYTE 0x74
309 #define AR8236_STATS_TX1518BYTE 0x78
310 #define AR8236_STATS_TXMAXBYTE 0x7c
311 #define AR8236_STATS_TXOVERSIZE 0x80
312 #define AR8236_STATS_TXBYTE 0x84
313 #define AR8236_STATS_TXCOLLISION 0x8c
314 #define AR8236_STATS_TXABORTCOL 0x90
315 #define AR8236_STATS_TXMULTICOL 0x94
316 #define AR8236_STATS_TXSINGLECOL 0x98
317 #define AR8236_STATS_TXEXCDEFER 0x9c
318 #define AR8236_STATS_TXDEFER 0xa0
319 #define AR8236_STATS_TXLATECOL 0xa4
320
321 #define AR8316_REG_POSTRIP 0x0008
322 #define AR8316_POSTRIP_MAC0_GMII_EN BIT(0)
323 #define AR8316_POSTRIP_MAC0_RGMII_EN BIT(1)
324 #define AR8316_POSTRIP_PHY4_GMII_EN BIT(2)
325 #define AR8316_POSTRIP_PHY4_RGMII_EN BIT(3)
326 #define AR8316_POSTRIP_MAC0_MAC_MODE BIT(4)
327 #define AR8316_POSTRIP_RTL_MODE BIT(5)
328 #define AR8316_POSTRIP_RGMII_RXCLK_DELAY_EN BIT(6)
329 #define AR8316_POSTRIP_RGMII_TXCLK_DELAY_EN BIT(7)
330 #define AR8316_POSTRIP_SERDES_EN BIT(8)
331 #define AR8316_POSTRIP_SEL_ANA_RST BIT(9)
332 #define AR8316_POSTRIP_GATE_25M_EN BIT(10)
333 #define AR8316_POSTRIP_SEL_CLK25M BIT(11)
334 #define AR8316_POSTRIP_HIB_PULSE_HW BIT(12)
335 #define AR8316_POSTRIP_DBG_MODE_I BIT(13)
336 #define AR8316_POSTRIP_MAC5_MAC_MODE BIT(14)
337 #define AR8316_POSTRIP_MAC5_PHY_MODE BIT(15)
338 #define AR8316_POSTRIP_POWER_DOWN_HW BIT(16)
339 #define AR8316_POSTRIP_LPW_STATE_EN BIT(17)
340 #define AR8316_POSTRIP_MAN_EN BIT(18)
341 #define AR8316_POSTRIP_PHY_PLL_ON BIT(19)
342 #define AR8316_POSTRIP_LPW_EXIT BIT(20)
343 #define AR8316_POSTRIP_TXDELAY_S0 BIT(21)
344 #define AR8316_POSTRIP_TXDELAY_S1 BIT(22)
345 #define AR8316_POSTRIP_RXDELAY_S0 BIT(23)
346 #define AR8316_POSTRIP_LED_OPEN_EN BIT(24)
347 #define AR8316_POSTRIP_SPI_EN BIT(25)
348 #define AR8316_POSTRIP_RXDELAY_S1 BIT(26)
349 #define AR8316_POSTRIP_POWER_ON_SEL BIT(31)
350
351 /* port speed */
352 enum {
353 AR8216_PORT_SPEED_10M = 0,
354 AR8216_PORT_SPEED_100M = 1,
355 AR8216_PORT_SPEED_1000M = 2,
356 AR8216_PORT_SPEED_ERR = 3,
357 };
358
359 /* ingress 802.1q mode */
360 enum {
361 AR8216_IN_PORT_ONLY = 0,
362 AR8216_IN_PORT_FALLBACK = 1,
363 AR8216_IN_VLAN_ONLY = 2,
364 AR8216_IN_SECURE = 3
365 };
366
367 /* egress 802.1q mode */
368 enum {
369 AR8216_OUT_KEEP = 0,
370 AR8216_OUT_STRIP_VLAN = 1,
371 AR8216_OUT_ADD_VLAN = 2
372 };
373
374 /* port forwarding state */
375 enum {
376 AR8216_PORT_STATE_DISABLED = 0,
377 AR8216_PORT_STATE_BLOCK = 1,
378 AR8216_PORT_STATE_LISTEN = 2,
379 AR8216_PORT_STATE_LEARN = 3,
380 AR8216_PORT_STATE_FORWARD = 4
381 };
382
383 enum {
384 AR8XXX_VER_AR8216 = 0x01,
385 AR8XXX_VER_AR8236 = 0x03,
386 AR8XXX_VER_AR8316 = 0x10,
387 AR8XXX_VER_AR8327 = 0x12,
388 AR8XXX_VER_AR8337 = 0x13,
389 };
390
391 #define AR8XXX_NUM_ARL_RECORDS 100
392
393 enum arl_op {
394 AR8XXX_ARL_INITIALIZE,
395 AR8XXX_ARL_GET_NEXT
396 };
397
398 struct arl_entry {
399 u16 portmap;
400 u8 mac[6];
401 };
402
403 struct ar8xxx_priv;
404
405 struct ar8xxx_mib_desc {
406 unsigned int size;
407 unsigned int offset;
408 const char *name;
409 };
410
411 struct ar8xxx_chip {
412 unsigned long caps;
413 bool config_at_probe;
414 bool mii_lo_first;
415
416 /* parameters to calculate REG_PORT_STATS_BASE */
417 unsigned reg_port_stats_start;
418 unsigned reg_port_stats_length;
419
420 unsigned reg_arl_ctrl;
421
422 int (*hw_init)(struct ar8xxx_priv *priv);
423 void (*cleanup)(struct ar8xxx_priv *priv);
424
425 const char *name;
426 int vlans;
427 int ports;
428 const struct switch_dev_ops *swops;
429
430 void (*init_globals)(struct ar8xxx_priv *priv);
431 void (*init_port)(struct ar8xxx_priv *priv, int port);
432 void (*setup_port)(struct ar8xxx_priv *priv, int port, u32 members);
433 u32 (*read_port_status)(struct ar8xxx_priv *priv, int port);
434 u32 (*read_port_eee_status)(struct ar8xxx_priv *priv, int port);
435 int (*atu_flush)(struct ar8xxx_priv *priv);
436 int (*atu_flush_port)(struct ar8xxx_priv *priv, int port);
437 void (*vtu_flush)(struct ar8xxx_priv *priv);
438 void (*vtu_load_vlan)(struct ar8xxx_priv *priv, u32 vid, u32 port_mask);
439 void (*phy_fixup)(struct ar8xxx_priv *priv, int phy);
440 void (*set_mirror_regs)(struct ar8xxx_priv *priv);
441 void (*get_arl_entry)(struct ar8xxx_priv *priv, struct arl_entry *a,
442 u32 *status, enum arl_op op);
443 int (*sw_hw_apply)(struct switch_dev *dev);
444 void (*phy_rgmii_set)(struct ar8xxx_priv *priv, struct phy_device *phydev);
445 int (*phy_read)(struct ar8xxx_priv *priv, int addr, int regnum);
446 int (*phy_write)(struct ar8xxx_priv *priv, int addr, int regnum, u16 val);
447
448 const struct ar8xxx_mib_desc *mib_decs;
449 unsigned num_mibs;
450 unsigned mib_func;
451 };
452
453 struct ar8xxx_priv {
454 struct switch_dev dev;
455 struct mii_bus *mii_bus;
456 struct mii_bus *sw_mii_bus;
457 struct phy_device *phy;
458 struct device *pdev;
459
460 int (*get_port_link)(unsigned port);
461
462 const struct net_device_ops *ndo_old;
463 struct net_device_ops ndo;
464 struct mutex reg_mutex;
465 u8 chip_ver;
466 u8 chip_rev;
467 const struct ar8xxx_chip *chip;
468 void *chip_data;
469 bool initialized;
470 bool port4_phy;
471 char buf[2048];
472 struct arl_entry arl_table[AR8XXX_NUM_ARL_RECORDS];
473 char arl_buf[AR8XXX_NUM_ARL_RECORDS * 32 + 256];
474 bool link_up[AR8X16_MAX_PORTS];
475
476 bool init;
477
478 struct mutex mib_lock;
479 struct delayed_work mib_work;
480 int mib_next_port;
481 u64 *mib_stats;
482
483 struct list_head list;
484 unsigned int use_count;
485
486 /* all fields below are cleared on reset */
487 bool vlan;
488 u16 vlan_id[AR8X16_MAX_VLANS];
489 u8 vlan_table[AR8X16_MAX_VLANS];
490 u8 vlan_tagged;
491 u16 pvid[AR8X16_MAX_PORTS];
492 int arl_age_time;
493
494 /* mirroring */
495 bool mirror_rx;
496 bool mirror_tx;
497 int source_port;
498 int monitor_port;
499 u8 port_vlan_prio[AR8X16_MAX_PORTS];
500 };
501
502 u32
503 ar8xxx_mii_read32(struct ar8xxx_priv *priv, int phy_id, int regnum);
504 void
505 ar8xxx_mii_write32(struct ar8xxx_priv *priv, int phy_id, int regnum, u32 val);
506 u32
507 ar8xxx_read(struct ar8xxx_priv *priv, int reg);
508 void
509 ar8xxx_write(struct ar8xxx_priv *priv, int reg, u32 val);
510 u32
511 ar8xxx_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val);
512
513 void
514 ar8xxx_phy_dbg_read(struct ar8xxx_priv *priv, int phy_addr,
515 u16 dbg_addr, u16 *dbg_data);
516 void
517 ar8xxx_phy_dbg_write(struct ar8xxx_priv *priv, int phy_addr,
518 u16 dbg_addr, u16 dbg_data);
519 void
520 ar8xxx_phy_mmd_write(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 reg, u16 data);
521 u16
522 ar8xxx_phy_mmd_read(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 reg);
523 void
524 ar8xxx_phy_init(struct ar8xxx_priv *priv);
525 int
526 ar8xxx_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
527 struct switch_val *val);
528 int
529 ar8xxx_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
530 struct switch_val *val);
531 int
532 ar8xxx_sw_set_reset_mibs(struct switch_dev *dev,
533 const struct switch_attr *attr,
534 struct switch_val *val);
535 int
536 ar8xxx_sw_set_mirror_rx_enable(struct switch_dev *dev,
537 const struct switch_attr *attr,
538 struct switch_val *val);
539 int
540 ar8xxx_sw_get_mirror_rx_enable(struct switch_dev *dev,
541 const struct switch_attr *attr,
542 struct switch_val *val);
543 int
544 ar8xxx_sw_set_mirror_tx_enable(struct switch_dev *dev,
545 const struct switch_attr *attr,
546 struct switch_val *val);
547 int
548 ar8xxx_sw_get_mirror_tx_enable(struct switch_dev *dev,
549 const struct switch_attr *attr,
550 struct switch_val *val);
551 int
552 ar8xxx_sw_set_mirror_monitor_port(struct switch_dev *dev,
553 const struct switch_attr *attr,
554 struct switch_val *val);
555 int
556 ar8xxx_sw_get_mirror_monitor_port(struct switch_dev *dev,
557 const struct switch_attr *attr,
558 struct switch_val *val);
559 int
560 ar8xxx_sw_set_mirror_source_port(struct switch_dev *dev,
561 const struct switch_attr *attr,
562 struct switch_val *val);
563 int
564 ar8xxx_sw_get_mirror_source_port(struct switch_dev *dev,
565 const struct switch_attr *attr,
566 struct switch_val *val);
567 int
568 ar8xxx_sw_set_pvid(struct switch_dev *dev, int port, int vlan);
569 int
570 ar8xxx_sw_get_pvid(struct switch_dev *dev, int port, int *vlan);
571 int
572 ar8xxx_sw_hw_apply(struct switch_dev *dev);
573 int
574 ar8xxx_sw_reset_switch(struct switch_dev *dev);
575 int
576 ar8xxx_sw_get_port_link(struct switch_dev *dev, int port,
577 struct switch_port_link *link);
578 int
579 ar8xxx_sw_set_port_reset_mib(struct switch_dev *dev,
580 const struct switch_attr *attr,
581 struct switch_val *val);
582 int
583 ar8xxx_sw_get_port_mib(struct switch_dev *dev,
584 const struct switch_attr *attr,
585 struct switch_val *val);
586 int
587 ar8xxx_sw_get_arl_age_time(struct switch_dev *dev,
588 const struct switch_attr *attr,
589 struct switch_val *val);
590 int
591 ar8xxx_sw_set_arl_age_time(struct switch_dev *dev,
592 const struct switch_attr *attr,
593 struct switch_val *val);
594 int
595 ar8xxx_sw_get_arl_table(struct switch_dev *dev,
596 const struct switch_attr *attr,
597 struct switch_val *val);
598 int
599 ar8xxx_sw_set_flush_arl_table(struct switch_dev *dev,
600 const struct switch_attr *attr,
601 struct switch_val *val);
602 int
603 ar8xxx_sw_set_flush_port_arl_table(struct switch_dev *dev,
604 const struct switch_attr *attr,
605 struct switch_val *val);
606 int
607 ar8216_wait_bit(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val);
608
609 static inline struct ar8xxx_priv *
610 swdev_to_ar8xxx(struct switch_dev *swdev)
611 {
612 return container_of(swdev, struct ar8xxx_priv, dev);
613 }
614
615 static inline bool ar8xxx_has_gige(struct ar8xxx_priv *priv)
616 {
617 return priv->chip->caps & AR8XXX_CAP_GIGE;
618 }
619
620 static inline bool ar8xxx_has_mib_counters(struct ar8xxx_priv *priv)
621 {
622 return priv->chip->caps & AR8XXX_CAP_MIB_COUNTERS;
623 }
624
625 static inline bool chip_is_ar8216(struct ar8xxx_priv *priv)
626 {
627 return priv->chip_ver == AR8XXX_VER_AR8216;
628 }
629
630 static inline bool chip_is_ar8236(struct ar8xxx_priv *priv)
631 {
632 return priv->chip_ver == AR8XXX_VER_AR8236;
633 }
634
635 static inline bool chip_is_ar8316(struct ar8xxx_priv *priv)
636 {
637 return priv->chip_ver == AR8XXX_VER_AR8316;
638 }
639
640 static inline bool chip_is_ar8327(struct ar8xxx_priv *priv)
641 {
642 return priv->chip_ver == AR8XXX_VER_AR8327;
643 }
644
645 static inline bool chip_is_ar8337(struct ar8xxx_priv *priv)
646 {
647 return priv->chip_ver == AR8XXX_VER_AR8337;
648 }
649
650 static inline void
651 ar8xxx_reg_set(struct ar8xxx_priv *priv, int reg, u32 val)
652 {
653 ar8xxx_rmw(priv, reg, 0, val);
654 }
655
656 static inline void
657 ar8xxx_reg_clear(struct ar8xxx_priv *priv, int reg, u32 val)
658 {
659 ar8xxx_rmw(priv, reg, val, 0);
660 }
661
662 static inline void
663 split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
664 {
665 regaddr >>= 1;
666 *r1 = regaddr & 0x1e;
667
668 regaddr >>= 5;
669 *r2 = regaddr & 0x7;
670
671 regaddr >>= 3;
672 *page = regaddr & 0x1ff;
673 }
674
675 static inline void
676 wait_for_page_switch(void)
677 {
678 udelay(5);
679 }
680
681 #endif
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