2 * ar8327.c: AR8216 switch driver
4 * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
18 #include <linux/list.h>
19 #include <linux/bitops.h>
20 #include <linux/switch.h>
21 #include <linux/delay.h>
22 #include <linux/phy.h>
23 #include <linux/lockdep.h>
24 #include <linux/ar8216_platform.h>
25 #include <linux/workqueue.h>
26 #include <linux/of_device.h>
27 #include <linux/leds.h>
28 #include <linux/mdio.h>
33 extern const struct ar8xxx_mib_desc ar8236_mibs
[39];
34 extern const struct switch_attr ar8xxx_sw_attr_vlan
[1];
37 ar8327_get_pad_cfg(struct ar8327_pad_cfg
*cfg
)
49 case AR8327_PAD_MAC2MAC_MII
:
50 t
= AR8327_PAD_MAC_MII_EN
;
52 t
|= AR8327_PAD_MAC_MII_RXCLK_SEL
;
54 t
|= AR8327_PAD_MAC_MII_TXCLK_SEL
;
57 case AR8327_PAD_MAC2MAC_GMII
:
58 t
= AR8327_PAD_MAC_GMII_EN
;
60 t
|= AR8327_PAD_MAC_GMII_RXCLK_SEL
;
62 t
|= AR8327_PAD_MAC_GMII_TXCLK_SEL
;
65 case AR8327_PAD_MAC_SGMII
:
66 t
= AR8327_PAD_SGMII_EN
;
69 * WAR for the QUalcomm Atheros AP136 board.
70 * It seems that RGMII TX/RX delay settings needs to be
71 * applied for SGMII mode as well, The ethernet is not
72 * reliable without this.
74 t
|= cfg
->txclk_delay_sel
<< AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S
;
75 t
|= cfg
->rxclk_delay_sel
<< AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S
;
76 if (cfg
->rxclk_delay_en
)
77 t
|= AR8327_PAD_RGMII_RXCLK_DELAY_EN
;
78 if (cfg
->txclk_delay_en
)
79 t
|= AR8327_PAD_RGMII_TXCLK_DELAY_EN
;
81 if (cfg
->sgmii_delay_en
)
82 t
|= AR8327_PAD_SGMII_DELAY_EN
;
86 case AR8327_PAD_MAC2PHY_MII
:
87 t
= AR8327_PAD_PHY_MII_EN
;
89 t
|= AR8327_PAD_PHY_MII_RXCLK_SEL
;
91 t
|= AR8327_PAD_PHY_MII_TXCLK_SEL
;
94 case AR8327_PAD_MAC2PHY_GMII
:
95 t
= AR8327_PAD_PHY_GMII_EN
;
96 if (cfg
->pipe_rxclk_sel
)
97 t
|= AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL
;
99 t
|= AR8327_PAD_PHY_GMII_RXCLK_SEL
;
101 t
|= AR8327_PAD_PHY_GMII_TXCLK_SEL
;
104 case AR8327_PAD_MAC_RGMII
:
105 t
= AR8327_PAD_RGMII_EN
;
106 t
|= cfg
->txclk_delay_sel
<< AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S
;
107 t
|= cfg
->rxclk_delay_sel
<< AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S
;
108 if (cfg
->rxclk_delay_en
)
109 t
|= AR8327_PAD_RGMII_RXCLK_DELAY_EN
;
110 if (cfg
->txclk_delay_en
)
111 t
|= AR8327_PAD_RGMII_TXCLK_DELAY_EN
;
114 case AR8327_PAD_PHY_GMII
:
115 t
= AR8327_PAD_PHYX_GMII_EN
;
118 case AR8327_PAD_PHY_RGMII
:
119 t
= AR8327_PAD_PHYX_RGMII_EN
;
122 case AR8327_PAD_PHY_MII
:
123 t
= AR8327_PAD_PHYX_MII_EN
;
131 ar8327_phy_fixup(struct ar8xxx_priv
*priv
, int phy
)
133 switch (priv
->chip_rev
) {
135 /* For 100M waveform */
136 ar8xxx_phy_dbg_write(priv
, phy
, 0, 0x02ea);
137 /* Turn on Gigabit clock */
138 ar8xxx_phy_dbg_write(priv
, phy
, 0x3d, 0x68a0);
142 ar8xxx_phy_mmd_write(priv
, phy
, 0x7, 0x3c);
143 ar8xxx_phy_mmd_write(priv
, phy
, 0x4007, 0x0);
146 ar8xxx_phy_mmd_write(priv
, phy
, 0x3, 0x800d);
147 ar8xxx_phy_mmd_write(priv
, phy
, 0x4003, 0x803f);
149 ar8xxx_phy_dbg_write(priv
, phy
, 0x3d, 0x6860);
150 ar8xxx_phy_dbg_write(priv
, phy
, 0x5, 0x2c46);
151 ar8xxx_phy_dbg_write(priv
, phy
, 0x3c, 0x6000);
157 ar8327_get_port_init_status(struct ar8327_port_cfg
*cfg
)
161 if (!cfg
->force_link
)
162 return AR8216_PORT_STATUS_LINK_AUTO
;
164 t
= AR8216_PORT_STATUS_TXMAC
| AR8216_PORT_STATUS_RXMAC
;
165 t
|= cfg
->duplex
? AR8216_PORT_STATUS_DUPLEX
: 0;
166 t
|= cfg
->rxpause
? AR8216_PORT_STATUS_RXFLOW
: 0;
167 t
|= cfg
->txpause
? AR8216_PORT_STATUS_TXFLOW
: 0;
169 switch (cfg
->speed
) {
170 case AR8327_PORT_SPEED_10
:
171 t
|= AR8216_PORT_SPEED_10M
;
173 case AR8327_PORT_SPEED_100
:
174 t
|= AR8216_PORT_SPEED_100M
;
176 case AR8327_PORT_SPEED_1000
:
177 t
|= AR8216_PORT_SPEED_1000M
;
184 #define AR8327_LED_ENTRY(_num, _reg, _shift) \
185 [_num] = { .reg = (_reg), .shift = (_shift) }
187 static const struct ar8327_led_entry
188 ar8327_led_map
[AR8327_NUM_LEDS
] = {
189 AR8327_LED_ENTRY(AR8327_LED_PHY0_0
, 0, 14),
190 AR8327_LED_ENTRY(AR8327_LED_PHY0_1
, 1, 14),
191 AR8327_LED_ENTRY(AR8327_LED_PHY0_2
, 2, 14),
193 AR8327_LED_ENTRY(AR8327_LED_PHY1_0
, 3, 8),
194 AR8327_LED_ENTRY(AR8327_LED_PHY1_1
, 3, 10),
195 AR8327_LED_ENTRY(AR8327_LED_PHY1_2
, 3, 12),
197 AR8327_LED_ENTRY(AR8327_LED_PHY2_0
, 3, 14),
198 AR8327_LED_ENTRY(AR8327_LED_PHY2_1
, 3, 16),
199 AR8327_LED_ENTRY(AR8327_LED_PHY2_2
, 3, 18),
201 AR8327_LED_ENTRY(AR8327_LED_PHY3_0
, 3, 20),
202 AR8327_LED_ENTRY(AR8327_LED_PHY3_1
, 3, 22),
203 AR8327_LED_ENTRY(AR8327_LED_PHY3_2
, 3, 24),
205 AR8327_LED_ENTRY(AR8327_LED_PHY4_0
, 0, 30),
206 AR8327_LED_ENTRY(AR8327_LED_PHY4_1
, 1, 30),
207 AR8327_LED_ENTRY(AR8327_LED_PHY4_2
, 2, 30),
211 ar8327_set_led_pattern(struct ar8xxx_priv
*priv
, unsigned int led_num
,
212 enum ar8327_led_pattern pattern
)
214 const struct ar8327_led_entry
*entry
;
216 entry
= &ar8327_led_map
[led_num
];
217 ar8xxx_rmw(priv
, AR8327_REG_LED_CTRL(entry
->reg
),
218 (3 << entry
->shift
), pattern
<< entry
->shift
);
222 ar8327_led_work_func(struct work_struct
*work
)
224 struct ar8327_led
*aled
;
227 aled
= container_of(work
, struct ar8327_led
, led_work
);
229 spin_lock(&aled
->lock
);
230 pattern
= aled
->pattern
;
231 spin_unlock(&aled
->lock
);
233 ar8327_set_led_pattern(aled
->sw_priv
, aled
->led_num
,
238 ar8327_led_schedule_change(struct ar8327_led
*aled
, u8 pattern
)
240 if (aled
->pattern
== pattern
)
243 aled
->pattern
= pattern
;
244 schedule_work(&aled
->led_work
);
247 static inline struct ar8327_led
*
248 led_cdev_to_ar8327_led(struct led_classdev
*led_cdev
)
250 return container_of(led_cdev
, struct ar8327_led
, cdev
);
254 ar8327_led_blink_set(struct led_classdev
*led_cdev
,
255 unsigned long *delay_on
,
256 unsigned long *delay_off
)
258 struct ar8327_led
*aled
= led_cdev_to_ar8327_led(led_cdev
);
260 if (*delay_on
== 0 && *delay_off
== 0) {
265 if (*delay_on
!= 125 || *delay_off
!= 125) {
267 * The hardware only supports blinking at 4Hz. Fall back
268 * to software implementation in other cases.
273 spin_lock(&aled
->lock
);
275 aled
->enable_hw_mode
= false;
276 ar8327_led_schedule_change(aled
, AR8327_LED_PATTERN_BLINK
);
278 spin_unlock(&aled
->lock
);
284 ar8327_led_set_brightness(struct led_classdev
*led_cdev
,
285 enum led_brightness brightness
)
287 struct ar8327_led
*aled
= led_cdev_to_ar8327_led(led_cdev
);
291 active
= (brightness
!= LED_OFF
);
292 active
^= aled
->active_low
;
294 pattern
= (active
) ? AR8327_LED_PATTERN_ON
:
295 AR8327_LED_PATTERN_OFF
;
297 spin_lock(&aled
->lock
);
299 aled
->enable_hw_mode
= false;
300 ar8327_led_schedule_change(aled
, pattern
);
302 spin_unlock(&aled
->lock
);
306 ar8327_led_enable_hw_mode_show(struct device
*dev
,
307 struct device_attribute
*attr
,
310 struct led_classdev
*led_cdev
= dev_get_drvdata(dev
);
311 struct ar8327_led
*aled
= led_cdev_to_ar8327_led(led_cdev
);
314 spin_lock(&aled
->lock
);
315 ret
+= sprintf(buf
, "%d\n", aled
->enable_hw_mode
);
316 spin_unlock(&aled
->lock
);
322 ar8327_led_enable_hw_mode_store(struct device
*dev
,
323 struct device_attribute
*attr
,
327 struct led_classdev
*led_cdev
= dev_get_drvdata(dev
);
328 struct ar8327_led
*aled
= led_cdev_to_ar8327_led(led_cdev
);
333 ret
= kstrtou8(buf
, 10, &value
);
337 spin_lock(&aled
->lock
);
339 aled
->enable_hw_mode
= !!value
;
340 if (aled
->enable_hw_mode
)
341 pattern
= AR8327_LED_PATTERN_RULE
;
343 pattern
= AR8327_LED_PATTERN_OFF
;
345 ar8327_led_schedule_change(aled
, pattern
);
347 spin_unlock(&aled
->lock
);
352 static DEVICE_ATTR(enable_hw_mode
, S_IRUGO
| S_IWUSR
,
353 ar8327_led_enable_hw_mode_show
,
354 ar8327_led_enable_hw_mode_store
);
357 ar8327_led_register(struct ar8327_led
*aled
)
361 ret
= led_classdev_register(NULL
, &aled
->cdev
);
365 if (aled
->mode
== AR8327_LED_MODE_HW
) {
366 ret
= device_create_file(aled
->cdev
.dev
,
367 &dev_attr_enable_hw_mode
);
375 led_classdev_unregister(&aled
->cdev
);
380 ar8327_led_unregister(struct ar8327_led
*aled
)
382 if (aled
->mode
== AR8327_LED_MODE_HW
)
383 device_remove_file(aled
->cdev
.dev
, &dev_attr_enable_hw_mode
);
385 led_classdev_unregister(&aled
->cdev
);
386 cancel_work_sync(&aled
->led_work
);
390 ar8327_led_create(struct ar8xxx_priv
*priv
,
391 const struct ar8327_led_info
*led_info
)
393 struct ar8327_data
*data
= priv
->chip_data
;
394 struct ar8327_led
*aled
;
397 if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS
))
403 if (led_info
->led_num
>= AR8327_NUM_LEDS
)
406 aled
= kzalloc(sizeof(*aled
) + strlen(led_info
->name
) + 1,
411 aled
->sw_priv
= priv
;
412 aled
->led_num
= led_info
->led_num
;
413 aled
->active_low
= led_info
->active_low
;
414 aled
->mode
= led_info
->mode
;
416 if (aled
->mode
== AR8327_LED_MODE_HW
)
417 aled
->enable_hw_mode
= true;
419 aled
->name
= (char *)(aled
+ 1);
420 strcpy(aled
->name
, led_info
->name
);
422 aled
->cdev
.name
= aled
->name
;
423 aled
->cdev
.brightness_set
= ar8327_led_set_brightness
;
424 aled
->cdev
.blink_set
= ar8327_led_blink_set
;
425 aled
->cdev
.default_trigger
= led_info
->default_trigger
;
427 spin_lock_init(&aled
->lock
);
428 mutex_init(&aled
->mutex
);
429 INIT_WORK(&aled
->led_work
, ar8327_led_work_func
);
431 ret
= ar8327_led_register(aled
);
435 data
->leds
[data
->num_leds
++] = aled
;
445 ar8327_led_destroy(struct ar8327_led
*aled
)
447 ar8327_led_unregister(aled
);
452 ar8327_leds_init(struct ar8xxx_priv
*priv
)
454 struct ar8327_data
*data
= priv
->chip_data
;
457 if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS
))
460 for (i
= 0; i
< data
->num_leds
; i
++) {
461 struct ar8327_led
*aled
;
463 aled
= data
->leds
[i
];
465 if (aled
->enable_hw_mode
)
466 aled
->pattern
= AR8327_LED_PATTERN_RULE
;
468 aled
->pattern
= AR8327_LED_PATTERN_OFF
;
470 ar8327_set_led_pattern(priv
, aled
->led_num
, aled
->pattern
);
475 ar8327_leds_cleanup(struct ar8xxx_priv
*priv
)
477 struct ar8327_data
*data
= priv
->chip_data
;
480 if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS
))
483 for (i
= 0; i
< data
->num_leds
; i
++) {
484 struct ar8327_led
*aled
;
486 aled
= data
->leds
[i
];
487 ar8327_led_destroy(aled
);
494 ar8327_hw_config_pdata(struct ar8xxx_priv
*priv
,
495 struct ar8327_platform_data
*pdata
)
497 struct ar8327_led_cfg
*led_cfg
;
498 struct ar8327_data
*data
= priv
->chip_data
;
505 priv
->get_port_link
= pdata
->get_port_link
;
507 data
->port0_status
= ar8327_get_port_init_status(&pdata
->port0_cfg
);
508 data
->port6_status
= ar8327_get_port_init_status(&pdata
->port6_cfg
);
510 t
= ar8327_get_pad_cfg(pdata
->pad0_cfg
);
511 if (chip_is_ar8337(priv
))
512 t
|= AR8337_PAD_MAC06_EXCHANGE_EN
;
514 ar8xxx_write(priv
, AR8327_REG_PAD0_MODE
, t
);
515 t
= ar8327_get_pad_cfg(pdata
->pad5_cfg
);
516 ar8xxx_write(priv
, AR8327_REG_PAD5_MODE
, t
);
517 t
= ar8327_get_pad_cfg(pdata
->pad6_cfg
);
518 ar8xxx_write(priv
, AR8327_REG_PAD6_MODE
, t
);
520 pos
= ar8xxx_read(priv
, AR8327_REG_POWER_ON_STRIP
);
523 led_cfg
= pdata
->led_cfg
;
525 if (led_cfg
->open_drain
)
526 new_pos
|= AR8327_POWER_ON_STRIP_LED_OPEN_EN
;
528 new_pos
&= ~AR8327_POWER_ON_STRIP_LED_OPEN_EN
;
530 ar8xxx_write(priv
, AR8327_REG_LED_CTRL0
, led_cfg
->led_ctrl0
);
531 ar8xxx_write(priv
, AR8327_REG_LED_CTRL1
, led_cfg
->led_ctrl1
);
532 ar8xxx_write(priv
, AR8327_REG_LED_CTRL2
, led_cfg
->led_ctrl2
);
533 ar8xxx_write(priv
, AR8327_REG_LED_CTRL3
, led_cfg
->led_ctrl3
);
536 new_pos
|= AR8327_POWER_ON_STRIP_POWER_ON_SEL
;
539 if (pdata
->sgmii_cfg
) {
540 t
= pdata
->sgmii_cfg
->sgmii_ctrl
;
541 if (priv
->chip_rev
== 1)
542 t
|= AR8327_SGMII_CTRL_EN_PLL
|
543 AR8327_SGMII_CTRL_EN_RX
|
544 AR8327_SGMII_CTRL_EN_TX
;
546 t
&= ~(AR8327_SGMII_CTRL_EN_PLL
|
547 AR8327_SGMII_CTRL_EN_RX
|
548 AR8327_SGMII_CTRL_EN_TX
);
550 ar8xxx_write(priv
, AR8327_REG_SGMII_CTRL
, t
);
552 if (pdata
->sgmii_cfg
->serdes_aen
)
553 new_pos
&= ~AR8327_POWER_ON_STRIP_SERDES_AEN
;
555 new_pos
|= AR8327_POWER_ON_STRIP_SERDES_AEN
;
558 ar8xxx_write(priv
, AR8327_REG_POWER_ON_STRIP
, new_pos
);
560 if (pdata
->leds
&& pdata
->num_leds
) {
563 data
->leds
= kzalloc(pdata
->num_leds
* sizeof(void *),
568 for (i
= 0; i
< pdata
->num_leds
; i
++)
569 ar8327_led_create(priv
, &pdata
->leds
[i
]);
577 ar8327_hw_config_of(struct ar8xxx_priv
*priv
, struct device_node
*np
)
579 struct ar8327_data
*data
= priv
->chip_data
;
584 paddr
= of_get_property(np
, "qca,ar8327-initvals", &len
);
585 if (!paddr
|| len
< (2 * sizeof(*paddr
)))
588 len
/= sizeof(*paddr
);
590 for (i
= 0; i
< len
- 1; i
+= 2) {
594 reg
= be32_to_cpup(paddr
+ i
);
595 val
= be32_to_cpup(paddr
+ i
+ 1);
598 case AR8327_REG_PORT_STATUS(0):
599 data
->port0_status
= val
;
601 case AR8327_REG_PORT_STATUS(6):
602 data
->port6_status
= val
;
605 ar8xxx_write(priv
, reg
, val
);
614 ar8327_hw_config_of(struct ar8xxx_priv
*priv
, struct device_node
*np
)
621 ar8327_hw_init(struct ar8xxx_priv
*priv
)
625 priv
->chip_data
= kzalloc(sizeof(struct ar8327_data
), GFP_KERNEL
);
626 if (!priv
->chip_data
)
629 if (priv
->phy
->dev
.of_node
)
630 ret
= ar8327_hw_config_of(priv
, priv
->phy
->dev
.of_node
);
632 ret
= ar8327_hw_config_pdata(priv
,
633 priv
->phy
->dev
.platform_data
);
638 ar8327_leds_init(priv
);
640 ar8xxx_phy_init(priv
);
646 ar8327_cleanup(struct ar8xxx_priv
*priv
)
648 ar8327_leds_cleanup(priv
);
652 ar8327_init_globals(struct ar8xxx_priv
*priv
)
654 struct ar8327_data
*data
= priv
->chip_data
;
658 /* enable CPU port and disable mirror port */
659 t
= AR8327_FWD_CTRL0_CPU_PORT_EN
|
660 AR8327_FWD_CTRL0_MIRROR_PORT
;
661 ar8xxx_write(priv
, AR8327_REG_FWD_CTRL0
, t
);
663 /* forward multicast and broadcast frames to CPU */
664 t
= (AR8327_PORTS_ALL
<< AR8327_FWD_CTRL1_UC_FLOOD_S
) |
665 (AR8327_PORTS_ALL
<< AR8327_FWD_CTRL1_MC_FLOOD_S
) |
666 (AR8327_PORTS_ALL
<< AR8327_FWD_CTRL1_BC_FLOOD_S
);
667 ar8xxx_write(priv
, AR8327_REG_FWD_CTRL1
, t
);
669 /* enable jumbo frames */
670 ar8xxx_rmw(priv
, AR8327_REG_MAX_FRAME_SIZE
,
671 AR8327_MAX_FRAME_SIZE_MTU
, 9018 + 8 + 2);
673 /* Enable MIB counters */
674 ar8xxx_reg_set(priv
, AR8327_REG_MODULE_EN
,
675 AR8327_MODULE_EN_MIB
);
677 /* Disable EEE on all phy's due to stability issues */
678 for (i
= 0; i
< AR8XXX_NUM_PHYS
; i
++)
679 data
->eee
[i
] = false;
683 ar8327_init_port(struct ar8xxx_priv
*priv
, int port
)
685 struct ar8327_data
*data
= priv
->chip_data
;
688 if (port
== AR8216_PORT_CPU
)
689 t
= data
->port0_status
;
691 t
= data
->port6_status
;
693 t
= AR8216_PORT_STATUS_LINK_AUTO
;
695 ar8xxx_write(priv
, AR8327_REG_PORT_STATUS(port
), t
);
696 ar8xxx_write(priv
, AR8327_REG_PORT_HEADER(port
), 0);
698 t
= 1 << AR8327_PORT_VLAN0_DEF_SVID_S
;
699 t
|= 1 << AR8327_PORT_VLAN0_DEF_CVID_S
;
700 ar8xxx_write(priv
, AR8327_REG_PORT_VLAN0(port
), t
);
702 t
= AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH
<< AR8327_PORT_VLAN1_OUT_MODE_S
;
703 ar8xxx_write(priv
, AR8327_REG_PORT_VLAN1(port
), t
);
705 t
= AR8327_PORT_LOOKUP_LEARN
;
706 t
|= AR8216_PORT_STATE_FORWARD
<< AR8327_PORT_LOOKUP_STATE_S
;
707 ar8xxx_write(priv
, AR8327_REG_PORT_LOOKUP(port
), t
);
711 ar8327_read_port_status(struct ar8xxx_priv
*priv
, int port
)
715 t
= ar8xxx_read(priv
, AR8327_REG_PORT_STATUS(port
));
716 /* map the flow control autoneg result bits to the flow control bits
717 * used in forced mode to allow ar8216_read_port_link detect
718 * flow control properly if autoneg is used
720 if (t
& AR8216_PORT_STATUS_LINK_UP
&&
721 t
& AR8216_PORT_STATUS_LINK_AUTO
) {
722 t
&= ~(AR8216_PORT_STATUS_TXFLOW
| AR8216_PORT_STATUS_RXFLOW
);
723 if (t
& AR8327_PORT_STATUS_TXFLOW_AUTO
)
724 t
|= AR8216_PORT_STATUS_TXFLOW
;
725 if (t
& AR8327_PORT_STATUS_RXFLOW_AUTO
)
726 t
|= AR8216_PORT_STATUS_RXFLOW
;
733 ar8327_read_port_eee_status(struct ar8xxx_priv
*priv
, int port
)
738 if (port
>= priv
->dev
.ports
)
741 if (port
== 0 || port
== 6)
746 /* EEE Ability Auto-negotiation Result */
747 ar8xxx_phy_mmd_write(priv
, phy
, 0x7, 0x8000);
748 t
= ar8xxx_phy_mmd_read(priv
, phy
, 0x4007);
750 return mmd_eee_adv_to_ethtool_adv_t(t
);
754 ar8327_atu_flush(struct ar8xxx_priv
*priv
)
758 ret
= ar8216_wait_bit(priv
, AR8327_REG_ATU_FUNC
,
759 AR8327_ATU_FUNC_BUSY
, 0);
761 ar8xxx_write(priv
, AR8327_REG_ATU_FUNC
,
762 AR8327_ATU_FUNC_OP_FLUSH
|
763 AR8327_ATU_FUNC_BUSY
);
769 ar8327_vtu_op(struct ar8xxx_priv
*priv
, u32 op
, u32 val
)
771 if (ar8216_wait_bit(priv
, AR8327_REG_VTU_FUNC1
,
772 AR8327_VTU_FUNC1_BUSY
, 0))
775 if ((op
& AR8327_VTU_FUNC1_OP
) == AR8327_VTU_FUNC1_OP_LOAD
)
776 ar8xxx_write(priv
, AR8327_REG_VTU_FUNC0
, val
);
778 op
|= AR8327_VTU_FUNC1_BUSY
;
779 ar8xxx_write(priv
, AR8327_REG_VTU_FUNC1
, op
);
783 ar8327_vtu_flush(struct ar8xxx_priv
*priv
)
785 ar8327_vtu_op(priv
, AR8327_VTU_FUNC1_OP_FLUSH
, 0);
789 ar8327_vtu_load_vlan(struct ar8xxx_priv
*priv
, u32 vid
, u32 port_mask
)
795 op
= AR8327_VTU_FUNC1_OP_LOAD
| (vid
<< AR8327_VTU_FUNC1_VID_S
);
796 val
= AR8327_VTU_FUNC0_VALID
| AR8327_VTU_FUNC0_IVL
;
797 for (i
= 0; i
< AR8327_NUM_PORTS
; i
++) {
800 if ((port_mask
& BIT(i
)) == 0)
801 mode
= AR8327_VTU_FUNC0_EG_MODE_NOT
;
802 else if (priv
->vlan
== 0)
803 mode
= AR8327_VTU_FUNC0_EG_MODE_KEEP
;
804 else if ((priv
->vlan_tagged
& BIT(i
)) || (priv
->vlan_id
[priv
->pvid
[i
]] != vid
))
805 mode
= AR8327_VTU_FUNC0_EG_MODE_TAG
;
807 mode
= AR8327_VTU_FUNC0_EG_MODE_UNTAG
;
809 val
|= mode
<< AR8327_VTU_FUNC0_EG_MODE_S(i
);
811 ar8327_vtu_op(priv
, op
, val
);
815 ar8327_setup_port(struct ar8xxx_priv
*priv
, int port
, u32 members
)
819 u32 pvid
= priv
->vlan_id
[priv
->pvid
[port
]];
822 egress
= AR8327_PORT_VLAN1_OUT_MODE_UNMOD
;
823 ingress
= AR8216_IN_SECURE
;
825 egress
= AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH
;
826 ingress
= AR8216_IN_PORT_ONLY
;
829 t
= pvid
<< AR8327_PORT_VLAN0_DEF_SVID_S
;
830 t
|= pvid
<< AR8327_PORT_VLAN0_DEF_CVID_S
;
831 ar8xxx_write(priv
, AR8327_REG_PORT_VLAN0(port
), t
);
833 t
= AR8327_PORT_VLAN1_PORT_VLAN_PROP
;
834 t
|= egress
<< AR8327_PORT_VLAN1_OUT_MODE_S
;
835 ar8xxx_write(priv
, AR8327_REG_PORT_VLAN1(port
), t
);
838 t
|= AR8327_PORT_LOOKUP_LEARN
;
839 t
|= ingress
<< AR8327_PORT_LOOKUP_IN_MODE_S
;
840 t
|= AR8216_PORT_STATE_FORWARD
<< AR8327_PORT_LOOKUP_STATE_S
;
841 ar8xxx_write(priv
, AR8327_REG_PORT_LOOKUP(port
), t
);
845 ar8327_sw_get_ports(struct switch_dev
*dev
, struct switch_val
*val
)
847 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
848 u8 ports
= priv
->vlan_table
[val
->port_vlan
];
852 for (i
= 0; i
< dev
->ports
; i
++) {
853 struct switch_port
*p
;
855 if (!(ports
& (1 << i
)))
858 p
= &val
->value
.ports
[val
->len
++];
860 if ((priv
->vlan_tagged
& (1 << i
)) || (priv
->pvid
[i
] != val
->port_vlan
))
861 p
->flags
= (1 << SWITCH_PORT_FLAG_TAGGED
);
869 ar8327_sw_set_ports(struct switch_dev
*dev
, struct switch_val
*val
)
871 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
872 u8
*vt
= &priv
->vlan_table
[val
->port_vlan
];
876 for (i
= 0; i
< val
->len
; i
++) {
877 struct switch_port
*p
= &val
->value
.ports
[i
];
879 if (p
->flags
& (1 << SWITCH_PORT_FLAG_TAGGED
)) {
880 if (val
->port_vlan
== priv
->pvid
[p
->id
]) {
881 priv
->vlan_tagged
|= (1 << p
->id
);
884 priv
->vlan_tagged
&= ~(1 << p
->id
);
885 priv
->pvid
[p
->id
] = val
->port_vlan
;
894 ar8327_set_mirror_regs(struct ar8xxx_priv
*priv
)
898 /* reset all mirror registers */
899 ar8xxx_rmw(priv
, AR8327_REG_FWD_CTRL0
,
900 AR8327_FWD_CTRL0_MIRROR_PORT
,
901 (0xF << AR8327_FWD_CTRL0_MIRROR_PORT_S
));
902 for (port
= 0; port
< AR8327_NUM_PORTS
; port
++) {
903 ar8xxx_reg_clear(priv
, AR8327_REG_PORT_LOOKUP(port
),
904 AR8327_PORT_LOOKUP_ING_MIRROR_EN
);
906 ar8xxx_reg_clear(priv
, AR8327_REG_PORT_HOL_CTRL1(port
),
907 AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN
);
910 /* now enable mirroring if necessary */
911 if (priv
->source_port
>= AR8327_NUM_PORTS
||
912 priv
->monitor_port
>= AR8327_NUM_PORTS
||
913 priv
->source_port
== priv
->monitor_port
) {
917 ar8xxx_rmw(priv
, AR8327_REG_FWD_CTRL0
,
918 AR8327_FWD_CTRL0_MIRROR_PORT
,
919 (priv
->monitor_port
<< AR8327_FWD_CTRL0_MIRROR_PORT_S
));
922 ar8xxx_reg_set(priv
, AR8327_REG_PORT_LOOKUP(priv
->source_port
),
923 AR8327_PORT_LOOKUP_ING_MIRROR_EN
);
926 ar8xxx_reg_set(priv
, AR8327_REG_PORT_HOL_CTRL1(priv
->source_port
),
927 AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN
);
931 ar8327_sw_set_eee(struct switch_dev
*dev
,
932 const struct switch_attr
*attr
,
933 struct switch_val
*val
)
935 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
936 struct ar8327_data
*data
= priv
->chip_data
;
937 int port
= val
->port_vlan
;
940 if (port
>= dev
->ports
)
942 if (port
== 0 || port
== 6)
947 data
->eee
[phy
] = !!(val
->value
.i
);
953 ar8327_sw_get_eee(struct switch_dev
*dev
,
954 const struct switch_attr
*attr
,
955 struct switch_val
*val
)
957 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
958 const struct ar8327_data
*data
= priv
->chip_data
;
959 int port
= val
->port_vlan
;
962 if (port
>= dev
->ports
)
964 if (port
== 0 || port
== 6)
969 val
->value
.i
= data
->eee
[phy
];
975 ar8327_wait_atu_ready(struct ar8xxx_priv
*priv
, u16 r2
, u16 r1
)
979 while (mii_read32(priv
, r2
, r1
) & AR8327_ATU_FUNC_BUSY
&& --timeout
)
983 pr_err("ar8327: timeout waiting for atu to become ready\n");
986 static void ar8327_get_arl_entry(struct ar8xxx_priv
*priv
,
987 struct arl_entry
*a
, u32
*status
, enum arl_op op
)
989 struct mii_bus
*bus
= priv
->mii_bus
;
991 u16 r1_data0
, r1_data1
, r1_data2
, r1_func
;
992 u32 t
, val0
, val1
, val2
;
995 split_addr(AR8327_REG_ATU_DATA0
, &r1_data0
, &r2
, &page
);
998 r1_data1
= (AR8327_REG_ATU_DATA1
>> 1) & 0x1e;
999 r1_data2
= (AR8327_REG_ATU_DATA2
>> 1) & 0x1e;
1000 r1_func
= (AR8327_REG_ATU_FUNC
>> 1) & 0x1e;
1003 case AR8XXX_ARL_INITIALIZE
:
1004 /* all ATU registers are on the same page
1005 * therefore set page only once
1007 bus
->write(bus
, 0x18, 0, page
);
1008 wait_for_page_switch();
1010 ar8327_wait_atu_ready(priv
, r2
, r1_func
);
1012 mii_write32(priv
, r2
, r1_data0
, 0);
1013 mii_write32(priv
, r2
, r1_data1
, 0);
1014 mii_write32(priv
, r2
, r1_data2
, 0);
1016 case AR8XXX_ARL_GET_NEXT
:
1017 mii_write32(priv
, r2
, r1_func
,
1018 AR8327_ATU_FUNC_OP_GET_NEXT
|
1019 AR8327_ATU_FUNC_BUSY
);
1020 ar8327_wait_atu_ready(priv
, r2
, r1_func
);
1022 val0
= mii_read32(priv
, r2
, r1_data0
);
1023 val1
= mii_read32(priv
, r2
, r1_data1
);
1024 val2
= mii_read32(priv
, r2
, r1_data2
);
1026 *status
= val2
& AR8327_ATU_STATUS
;
1031 t
= AR8327_ATU_PORT0
;
1032 while (!(val1
& t
) && ++i
< AR8327_NUM_PORTS
)
1036 a
->mac
[0] = (val0
& AR8327_ATU_ADDR0
) >> AR8327_ATU_ADDR0_S
;
1037 a
->mac
[1] = (val0
& AR8327_ATU_ADDR1
) >> AR8327_ATU_ADDR1_S
;
1038 a
->mac
[2] = (val0
& AR8327_ATU_ADDR2
) >> AR8327_ATU_ADDR2_S
;
1039 a
->mac
[3] = (val0
& AR8327_ATU_ADDR3
) >> AR8327_ATU_ADDR3_S
;
1040 a
->mac
[4] = (val1
& AR8327_ATU_ADDR4
) >> AR8327_ATU_ADDR4_S
;
1041 a
->mac
[5] = (val1
& AR8327_ATU_ADDR5
) >> AR8327_ATU_ADDR5_S
;
1047 ar8327_sw_hw_apply(struct switch_dev
*dev
)
1049 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1050 const struct ar8327_data
*data
= priv
->chip_data
;
1053 ret
= ar8xxx_sw_hw_apply(dev
);
1057 for (i
=0; i
< AR8XXX_NUM_PHYS
; i
++) {
1059 ar8xxx_reg_clear(priv
, AR8327_REG_EEE_CTRL
,
1060 AR8327_EEE_CTRL_DISABLE_PHY(i
));
1062 ar8xxx_reg_set(priv
, AR8327_REG_EEE_CTRL
,
1063 AR8327_EEE_CTRL_DISABLE_PHY(i
));
1069 static const struct switch_attr ar8327_sw_attr_globals
[] = {
1071 .type
= SWITCH_TYPE_INT
,
1072 .name
= "enable_vlan",
1073 .description
= "Enable VLAN mode",
1074 .set
= ar8xxx_sw_set_vlan
,
1075 .get
= ar8xxx_sw_get_vlan
,
1079 .type
= SWITCH_TYPE_NOVAL
,
1080 .name
= "reset_mibs",
1081 .description
= "Reset all MIB counters",
1082 .set
= ar8xxx_sw_set_reset_mibs
,
1085 .type
= SWITCH_TYPE_INT
,
1086 .name
= "enable_mirror_rx",
1087 .description
= "Enable mirroring of RX packets",
1088 .set
= ar8xxx_sw_set_mirror_rx_enable
,
1089 .get
= ar8xxx_sw_get_mirror_rx_enable
,
1093 .type
= SWITCH_TYPE_INT
,
1094 .name
= "enable_mirror_tx",
1095 .description
= "Enable mirroring of TX packets",
1096 .set
= ar8xxx_sw_set_mirror_tx_enable
,
1097 .get
= ar8xxx_sw_get_mirror_tx_enable
,
1101 .type
= SWITCH_TYPE_INT
,
1102 .name
= "mirror_monitor_port",
1103 .description
= "Mirror monitor port",
1104 .set
= ar8xxx_sw_set_mirror_monitor_port
,
1105 .get
= ar8xxx_sw_get_mirror_monitor_port
,
1106 .max
= AR8327_NUM_PORTS
- 1
1109 .type
= SWITCH_TYPE_INT
,
1110 .name
= "mirror_source_port",
1111 .description
= "Mirror source port",
1112 .set
= ar8xxx_sw_set_mirror_source_port
,
1113 .get
= ar8xxx_sw_get_mirror_source_port
,
1114 .max
= AR8327_NUM_PORTS
- 1
1117 .type
= SWITCH_TYPE_STRING
,
1118 .name
= "arl_table",
1119 .description
= "Get ARL table",
1121 .get
= ar8xxx_sw_get_arl_table
,
1125 static const struct switch_attr ar8327_sw_attr_port
[] = {
1127 .type
= SWITCH_TYPE_NOVAL
,
1128 .name
= "reset_mib",
1129 .description
= "Reset single port MIB counters",
1130 .set
= ar8xxx_sw_set_port_reset_mib
,
1133 .type
= SWITCH_TYPE_STRING
,
1135 .description
= "Get port's MIB counters",
1137 .get
= ar8xxx_sw_get_port_mib
,
1140 .type
= SWITCH_TYPE_INT
,
1141 .name
= "enable_eee",
1142 .description
= "Enable EEE PHY sleep mode",
1143 .set
= ar8327_sw_set_eee
,
1144 .get
= ar8327_sw_get_eee
,
1149 static const struct switch_dev_ops ar8327_sw_ops
= {
1151 .attr
= ar8327_sw_attr_globals
,
1152 .n_attr
= ARRAY_SIZE(ar8327_sw_attr_globals
),
1155 .attr
= ar8327_sw_attr_port
,
1156 .n_attr
= ARRAY_SIZE(ar8327_sw_attr_port
),
1159 .attr
= ar8xxx_sw_attr_vlan
,
1160 .n_attr
= ARRAY_SIZE(ar8xxx_sw_attr_vlan
),
1162 .get_port_pvid
= ar8xxx_sw_get_pvid
,
1163 .set_port_pvid
= ar8xxx_sw_set_pvid
,
1164 .get_vlan_ports
= ar8327_sw_get_ports
,
1165 .set_vlan_ports
= ar8327_sw_set_ports
,
1166 .apply_config
= ar8327_sw_hw_apply
,
1167 .reset_switch
= ar8xxx_sw_reset_switch
,
1168 .get_port_link
= ar8xxx_sw_get_port_link
,
1171 const struct ar8xxx_chip ar8327_chip
= {
1172 .caps
= AR8XXX_CAP_GIGE
| AR8XXX_CAP_MIB_COUNTERS
,
1173 .config_at_probe
= true,
1174 .mii_lo_first
= true,
1176 .name
= "Atheros AR8327",
1177 .ports
= AR8327_NUM_PORTS
,
1178 .vlans
= AR8X16_MAX_VLANS
,
1179 .swops
= &ar8327_sw_ops
,
1181 .reg_port_stats_start
= 0x1000,
1182 .reg_port_stats_length
= 0x100,
1184 .hw_init
= ar8327_hw_init
,
1185 .cleanup
= ar8327_cleanup
,
1186 .init_globals
= ar8327_init_globals
,
1187 .init_port
= ar8327_init_port
,
1188 .setup_port
= ar8327_setup_port
,
1189 .read_port_status
= ar8327_read_port_status
,
1190 .read_port_eee_status
= ar8327_read_port_eee_status
,
1191 .atu_flush
= ar8327_atu_flush
,
1192 .vtu_flush
= ar8327_vtu_flush
,
1193 .vtu_load_vlan
= ar8327_vtu_load_vlan
,
1194 .phy_fixup
= ar8327_phy_fixup
,
1195 .set_mirror_regs
= ar8327_set_mirror_regs
,
1196 .get_arl_entry
= ar8327_get_arl_entry
,
1197 .sw_hw_apply
= ar8327_sw_hw_apply
,
1199 .num_mibs
= ARRAY_SIZE(ar8236_mibs
),
1200 .mib_decs
= ar8236_mibs
,
1201 .mib_func
= AR8327_REG_MIB_FUNC
1204 const struct ar8xxx_chip ar8337_chip
= {
1205 .caps
= AR8XXX_CAP_GIGE
| AR8XXX_CAP_MIB_COUNTERS
,
1206 .config_at_probe
= true,
1207 .mii_lo_first
= true,
1209 .name
= "Atheros AR8337",
1210 .ports
= AR8327_NUM_PORTS
,
1211 .vlans
= AR8X16_MAX_VLANS
,
1212 .swops
= &ar8327_sw_ops
,
1214 .reg_port_stats_start
= 0x1000,
1215 .reg_port_stats_length
= 0x100,
1217 .hw_init
= ar8327_hw_init
,
1218 .cleanup
= ar8327_cleanup
,
1219 .init_globals
= ar8327_init_globals
,
1220 .init_port
= ar8327_init_port
,
1221 .setup_port
= ar8327_setup_port
,
1222 .read_port_status
= ar8327_read_port_status
,
1223 .read_port_eee_status
= ar8327_read_port_eee_status
,
1224 .atu_flush
= ar8327_atu_flush
,
1225 .vtu_flush
= ar8327_vtu_flush
,
1226 .vtu_load_vlan
= ar8327_vtu_load_vlan
,
1227 .phy_fixup
= ar8327_phy_fixup
,
1228 .set_mirror_regs
= ar8327_set_mirror_regs
,
1229 .get_arl_entry
= ar8327_get_arl_entry
,
1230 .sw_hw_apply
= ar8327_sw_hw_apply
,
1232 .num_mibs
= ARRAY_SIZE(ar8236_mibs
),
1233 .mib_decs
= ar8236_mibs
,
1234 .mib_func
= AR8327_REG_MIB_FUNC