2 * ar8327.c: AR8216 switch driver
4 * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>
5 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
18 #include <linux/list.h>
19 #include <linux/bitops.h>
20 #include <linux/switch.h>
21 #include <linux/delay.h>
22 #include <linux/phy.h>
23 #include <linux/lockdep.h>
24 #include <linux/ar8216_platform.h>
25 #include <linux/workqueue.h>
26 #include <linux/of_device.h>
27 #include <linux/leds.h>
28 #include <linux/mdio.h>
33 extern const struct ar8xxx_mib_desc ar8236_mibs
[39];
34 extern const struct switch_attr ar8xxx_sw_attr_vlan
[1];
37 ar8327_get_pad_cfg(struct ar8327_pad_cfg
*cfg
)
49 case AR8327_PAD_MAC2MAC_MII
:
50 t
= AR8327_PAD_MAC_MII_EN
;
52 t
|= AR8327_PAD_MAC_MII_RXCLK_SEL
;
54 t
|= AR8327_PAD_MAC_MII_TXCLK_SEL
;
57 case AR8327_PAD_MAC2MAC_GMII
:
58 t
= AR8327_PAD_MAC_GMII_EN
;
60 t
|= AR8327_PAD_MAC_GMII_RXCLK_SEL
;
62 t
|= AR8327_PAD_MAC_GMII_TXCLK_SEL
;
65 case AR8327_PAD_MAC_SGMII
:
66 t
= AR8327_PAD_SGMII_EN
;
69 * WAR for the QUalcomm Atheros AP136 board.
70 * It seems that RGMII TX/RX delay settings needs to be
71 * applied for SGMII mode as well, The ethernet is not
72 * reliable without this.
74 t
|= cfg
->txclk_delay_sel
<< AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S
;
75 t
|= cfg
->rxclk_delay_sel
<< AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S
;
76 if (cfg
->rxclk_delay_en
)
77 t
|= AR8327_PAD_RGMII_RXCLK_DELAY_EN
;
78 if (cfg
->txclk_delay_en
)
79 t
|= AR8327_PAD_RGMII_TXCLK_DELAY_EN
;
81 if (cfg
->sgmii_delay_en
)
82 t
|= AR8327_PAD_SGMII_DELAY_EN
;
86 case AR8327_PAD_MAC2PHY_MII
:
87 t
= AR8327_PAD_PHY_MII_EN
;
89 t
|= AR8327_PAD_PHY_MII_RXCLK_SEL
;
91 t
|= AR8327_PAD_PHY_MII_TXCLK_SEL
;
94 case AR8327_PAD_MAC2PHY_GMII
:
95 t
= AR8327_PAD_PHY_GMII_EN
;
96 if (cfg
->pipe_rxclk_sel
)
97 t
|= AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL
;
99 t
|= AR8327_PAD_PHY_GMII_RXCLK_SEL
;
101 t
|= AR8327_PAD_PHY_GMII_TXCLK_SEL
;
104 case AR8327_PAD_MAC_RGMII
:
105 t
= AR8327_PAD_RGMII_EN
;
106 t
|= cfg
->txclk_delay_sel
<< AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S
;
107 t
|= cfg
->rxclk_delay_sel
<< AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S
;
108 if (cfg
->rxclk_delay_en
)
109 t
|= AR8327_PAD_RGMII_RXCLK_DELAY_EN
;
110 if (cfg
->txclk_delay_en
)
111 t
|= AR8327_PAD_RGMII_TXCLK_DELAY_EN
;
114 case AR8327_PAD_PHY_GMII
:
115 t
= AR8327_PAD_PHYX_GMII_EN
;
118 case AR8327_PAD_PHY_RGMII
:
119 t
= AR8327_PAD_PHYX_RGMII_EN
;
122 case AR8327_PAD_PHY_MII
:
123 t
= AR8327_PAD_PHYX_MII_EN
;
131 ar8327_phy_rgmii_set(struct ar8xxx_priv
*priv
, struct phy_device
*phydev
)
134 int phyaddr
= phydev
->mdio
.addr
;
135 struct device_node
*np
= phydev
->mdio
.dev
.of_node
;
140 if (!of_property_read_bool(np
, "qca,phy-rgmii-en")) {
141 pr_err("ar8327: qca,phy-rgmii-en is not specified\n");
144 ar8xxx_phy_dbg_read(priv
, phyaddr
,
145 AR8327_PHY_MODE_SEL
, &phy_val
);
146 phy_val
|= AR8327_PHY_MODE_SEL_RGMII
;
147 ar8xxx_phy_dbg_write(priv
, phyaddr
,
148 AR8327_PHY_MODE_SEL
, phy_val
);
150 /* set rgmii tx clock delay if needed */
151 if (!of_property_read_bool(np
, "qca,txclk-delay-en")) {
152 pr_err("ar8327: qca,txclk-delay-en is not specified\n");
155 ar8xxx_phy_dbg_read(priv
, phyaddr
,
156 AR8327_PHY_SYS_CTRL
, &phy_val
);
157 phy_val
|= AR8327_PHY_SYS_CTRL_RGMII_TX_DELAY
;
158 ar8xxx_phy_dbg_write(priv
, phyaddr
,
159 AR8327_PHY_SYS_CTRL
, phy_val
);
161 /* set rgmii rx clock delay if needed */
162 if (!of_property_read_bool(np
, "qca,rxclk-delay-en")) {
163 pr_err("ar8327: qca,rxclk-delay-en is not specified\n");
166 ar8xxx_phy_dbg_read(priv
, phyaddr
,
167 AR8327_PHY_TEST_CTRL
, &phy_val
);
168 phy_val
|= AR8327_PHY_TEST_CTRL_RGMII_RX_DELAY
;
169 ar8xxx_phy_dbg_write(priv
, phyaddr
,
170 AR8327_PHY_TEST_CTRL
, phy_val
);
174 ar8327_phy_fixup(struct ar8xxx_priv
*priv
, int phy
)
176 switch (priv
->chip_rev
) {
178 /* For 100M waveform */
179 ar8xxx_phy_dbg_write(priv
, phy
, 0, 0x02ea);
180 /* Turn on Gigabit clock */
181 ar8xxx_phy_dbg_write(priv
, phy
, 0x3d, 0x68a0);
185 ar8xxx_phy_mmd_write(priv
, phy
, 0x7, 0x3c, 0x0);
188 ar8xxx_phy_mmd_write(priv
, phy
, 0x3, 0x800d, 0x803f);
189 ar8xxx_phy_dbg_write(priv
, phy
, 0x3d, 0x6860);
190 ar8xxx_phy_dbg_write(priv
, phy
, 0x5, 0x2c46);
191 ar8xxx_phy_dbg_write(priv
, phy
, 0x3c, 0x6000);
197 ar8327_get_port_init_status(struct ar8327_port_cfg
*cfg
)
201 if (!cfg
->force_link
)
202 return AR8216_PORT_STATUS_LINK_AUTO
;
204 t
= AR8216_PORT_STATUS_TXMAC
| AR8216_PORT_STATUS_RXMAC
;
205 t
|= cfg
->duplex
? AR8216_PORT_STATUS_DUPLEX
: 0;
206 t
|= cfg
->rxpause
? AR8216_PORT_STATUS_RXFLOW
: 0;
207 t
|= cfg
->txpause
? AR8216_PORT_STATUS_TXFLOW
: 0;
209 switch (cfg
->speed
) {
210 case AR8327_PORT_SPEED_10
:
211 t
|= AR8216_PORT_SPEED_10M
;
213 case AR8327_PORT_SPEED_100
:
214 t
|= AR8216_PORT_SPEED_100M
;
216 case AR8327_PORT_SPEED_1000
:
217 t
|= AR8216_PORT_SPEED_1000M
;
224 #define AR8327_LED_ENTRY(_num, _reg, _shift) \
225 [_num] = { .reg = (_reg), .shift = (_shift) }
227 static const struct ar8327_led_entry
228 ar8327_led_map
[AR8327_NUM_LEDS
] = {
229 AR8327_LED_ENTRY(AR8327_LED_PHY0_0
, 0, 14),
230 AR8327_LED_ENTRY(AR8327_LED_PHY0_1
, 1, 14),
231 AR8327_LED_ENTRY(AR8327_LED_PHY0_2
, 2, 14),
233 AR8327_LED_ENTRY(AR8327_LED_PHY1_0
, 3, 8),
234 AR8327_LED_ENTRY(AR8327_LED_PHY1_1
, 3, 10),
235 AR8327_LED_ENTRY(AR8327_LED_PHY1_2
, 3, 12),
237 AR8327_LED_ENTRY(AR8327_LED_PHY2_0
, 3, 14),
238 AR8327_LED_ENTRY(AR8327_LED_PHY2_1
, 3, 16),
239 AR8327_LED_ENTRY(AR8327_LED_PHY2_2
, 3, 18),
241 AR8327_LED_ENTRY(AR8327_LED_PHY3_0
, 3, 20),
242 AR8327_LED_ENTRY(AR8327_LED_PHY3_1
, 3, 22),
243 AR8327_LED_ENTRY(AR8327_LED_PHY3_2
, 3, 24),
245 AR8327_LED_ENTRY(AR8327_LED_PHY4_0
, 0, 30),
246 AR8327_LED_ENTRY(AR8327_LED_PHY4_1
, 1, 30),
247 AR8327_LED_ENTRY(AR8327_LED_PHY4_2
, 2, 30),
251 ar8327_set_led_pattern(struct ar8xxx_priv
*priv
, unsigned int led_num
,
252 enum ar8327_led_pattern pattern
)
254 const struct ar8327_led_entry
*entry
;
256 entry
= &ar8327_led_map
[led_num
];
257 ar8xxx_rmw(priv
, AR8327_REG_LED_CTRL(entry
->reg
),
258 (3 << entry
->shift
), pattern
<< entry
->shift
);
262 ar8327_led_work_func(struct work_struct
*work
)
264 struct ar8327_led
*aled
;
267 aled
= container_of(work
, struct ar8327_led
, led_work
);
269 pattern
= aled
->pattern
;
271 ar8327_set_led_pattern(aled
->sw_priv
, aled
->led_num
,
276 ar8327_led_schedule_change(struct ar8327_led
*aled
, u8 pattern
)
278 if (aled
->pattern
== pattern
)
281 aled
->pattern
= pattern
;
282 schedule_work(&aled
->led_work
);
285 static inline struct ar8327_led
*
286 led_cdev_to_ar8327_led(struct led_classdev
*led_cdev
)
288 return container_of(led_cdev
, struct ar8327_led
, cdev
);
292 ar8327_led_blink_set(struct led_classdev
*led_cdev
,
293 unsigned long *delay_on
,
294 unsigned long *delay_off
)
296 struct ar8327_led
*aled
= led_cdev_to_ar8327_led(led_cdev
);
298 if (*delay_on
== 0 && *delay_off
== 0) {
303 if (*delay_on
!= 125 || *delay_off
!= 125) {
305 * The hardware only supports blinking at 4Hz. Fall back
306 * to software implementation in other cases.
311 spin_lock(&aled
->lock
);
313 aled
->enable_hw_mode
= false;
314 ar8327_led_schedule_change(aled
, AR8327_LED_PATTERN_BLINK
);
316 spin_unlock(&aled
->lock
);
322 ar8327_led_set_brightness(struct led_classdev
*led_cdev
,
323 enum led_brightness brightness
)
325 struct ar8327_led
*aled
= led_cdev_to_ar8327_led(led_cdev
);
329 active
= (brightness
!= LED_OFF
);
330 active
^= aled
->active_low
;
332 pattern
= (active
) ? AR8327_LED_PATTERN_ON
:
333 AR8327_LED_PATTERN_OFF
;
335 spin_lock(&aled
->lock
);
337 aled
->enable_hw_mode
= false;
338 ar8327_led_schedule_change(aled
, pattern
);
340 spin_unlock(&aled
->lock
);
344 ar8327_led_enable_hw_mode_show(struct device
*dev
,
345 struct device_attribute
*attr
,
348 struct led_classdev
*led_cdev
= dev_get_drvdata(dev
);
349 struct ar8327_led
*aled
= led_cdev_to_ar8327_led(led_cdev
);
352 ret
+= scnprintf(buf
, PAGE_SIZE
, "%d\n", aled
->enable_hw_mode
);
358 ar8327_led_enable_hw_mode_store(struct device
*dev
,
359 struct device_attribute
*attr
,
363 struct led_classdev
*led_cdev
= dev_get_drvdata(dev
);
364 struct ar8327_led
*aled
= led_cdev_to_ar8327_led(led_cdev
);
369 ret
= kstrtou8(buf
, 10, &value
);
373 spin_lock(&aled
->lock
);
375 aled
->enable_hw_mode
= !!value
;
376 if (aled
->enable_hw_mode
)
377 pattern
= AR8327_LED_PATTERN_RULE
;
379 pattern
= AR8327_LED_PATTERN_OFF
;
381 ar8327_led_schedule_change(aled
, pattern
);
383 spin_unlock(&aled
->lock
);
388 static DEVICE_ATTR(enable_hw_mode
, S_IRUGO
| S_IWUSR
,
389 ar8327_led_enable_hw_mode_show
,
390 ar8327_led_enable_hw_mode_store
);
393 ar8327_led_register(struct ar8327_led
*aled
)
397 ret
= led_classdev_register(NULL
, &aled
->cdev
);
401 if (aled
->mode
== AR8327_LED_MODE_HW
) {
402 ret
= device_create_file(aled
->cdev
.dev
,
403 &dev_attr_enable_hw_mode
);
411 led_classdev_unregister(&aled
->cdev
);
416 ar8327_led_unregister(struct ar8327_led
*aled
)
418 if (aled
->mode
== AR8327_LED_MODE_HW
)
419 device_remove_file(aled
->cdev
.dev
, &dev_attr_enable_hw_mode
);
421 led_classdev_unregister(&aled
->cdev
);
422 cancel_work_sync(&aled
->led_work
);
426 ar8327_led_create(struct ar8xxx_priv
*priv
,
427 const struct ar8327_led_info
*led_info
)
429 struct ar8327_data
*data
= priv
->chip_data
;
430 struct ar8327_led
*aled
;
433 if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS
))
439 if (led_info
->led_num
>= AR8327_NUM_LEDS
)
442 aled
= kzalloc(sizeof(*aled
) + strlen(led_info
->name
) + 1,
447 aled
->sw_priv
= priv
;
448 aled
->led_num
= led_info
->led_num
;
449 aled
->active_low
= led_info
->active_low
;
450 aled
->mode
= led_info
->mode
;
452 if (aled
->mode
== AR8327_LED_MODE_HW
)
453 aled
->enable_hw_mode
= true;
455 aled
->name
= (char *)(aled
+ 1);
456 strcpy(aled
->name
, led_info
->name
);
458 aled
->cdev
.name
= aled
->name
;
459 aled
->cdev
.brightness_set
= ar8327_led_set_brightness
;
460 aled
->cdev
.blink_set
= ar8327_led_blink_set
;
461 aled
->cdev
.default_trigger
= led_info
->default_trigger
;
463 spin_lock_init(&aled
->lock
);
464 mutex_init(&aled
->mutex
);
465 INIT_WORK(&aled
->led_work
, ar8327_led_work_func
);
467 ret
= ar8327_led_register(aled
);
471 data
->leds
[data
->num_leds
++] = aled
;
481 ar8327_led_destroy(struct ar8327_led
*aled
)
483 ar8327_led_unregister(aled
);
488 ar8327_leds_init(struct ar8xxx_priv
*priv
)
490 struct ar8327_data
*data
= priv
->chip_data
;
493 if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS
))
496 for (i
= 0; i
< data
->num_leds
; i
++) {
497 struct ar8327_led
*aled
;
499 aled
= data
->leds
[i
];
501 if (aled
->enable_hw_mode
)
502 aled
->pattern
= AR8327_LED_PATTERN_RULE
;
504 aled
->pattern
= AR8327_LED_PATTERN_OFF
;
506 ar8327_set_led_pattern(priv
, aled
->led_num
, aled
->pattern
);
511 ar8327_leds_cleanup(struct ar8xxx_priv
*priv
)
513 struct ar8327_data
*data
= priv
->chip_data
;
516 if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS
))
519 for (i
= 0; i
< data
->num_leds
; i
++) {
520 struct ar8327_led
*aled
;
522 aled
= data
->leds
[i
];
523 ar8327_led_destroy(aled
);
530 ar8327_hw_config_pdata(struct ar8xxx_priv
*priv
,
531 struct ar8327_platform_data
*pdata
)
533 struct ar8327_led_cfg
*led_cfg
;
534 struct ar8327_data
*data
= priv
->chip_data
;
541 priv
->get_port_link
= pdata
->get_port_link
;
543 data
->port0_status
= ar8327_get_port_init_status(&pdata
->port0_cfg
);
544 data
->port6_status
= ar8327_get_port_init_status(&pdata
->port6_cfg
);
546 t
= ar8327_get_pad_cfg(pdata
->pad0_cfg
);
547 if (chip_is_ar8337(priv
) && !pdata
->pad0_cfg
->mac06_exchange_dis
)
548 t
|= AR8337_PAD_MAC06_EXCHANGE_EN
;
549 ar8xxx_write(priv
, AR8327_REG_PAD0_MODE
, t
);
551 t
= ar8327_get_pad_cfg(pdata
->pad5_cfg
);
552 ar8xxx_write(priv
, AR8327_REG_PAD5_MODE
, t
);
553 t
= ar8327_get_pad_cfg(pdata
->pad6_cfg
);
554 ar8xxx_write(priv
, AR8327_REG_PAD6_MODE
, t
);
556 pos
= ar8xxx_read(priv
, AR8327_REG_POWER_ON_STRIP
);
559 led_cfg
= pdata
->led_cfg
;
561 if (led_cfg
->open_drain
)
562 new_pos
|= AR8327_POWER_ON_STRIP_LED_OPEN_EN
;
564 new_pos
&= ~AR8327_POWER_ON_STRIP_LED_OPEN_EN
;
566 ar8xxx_write(priv
, AR8327_REG_LED_CTRL0
, led_cfg
->led_ctrl0
);
567 ar8xxx_write(priv
, AR8327_REG_LED_CTRL1
, led_cfg
->led_ctrl1
);
568 ar8xxx_write(priv
, AR8327_REG_LED_CTRL2
, led_cfg
->led_ctrl2
);
569 ar8xxx_write(priv
, AR8327_REG_LED_CTRL3
, led_cfg
->led_ctrl3
);
572 new_pos
|= AR8327_POWER_ON_STRIP_POWER_ON_SEL
;
575 if (pdata
->sgmii_cfg
) {
576 t
= pdata
->sgmii_cfg
->sgmii_ctrl
;
577 if (priv
->chip_rev
== 1)
578 t
|= AR8327_SGMII_CTRL_EN_PLL
|
579 AR8327_SGMII_CTRL_EN_RX
|
580 AR8327_SGMII_CTRL_EN_TX
;
582 t
&= ~(AR8327_SGMII_CTRL_EN_PLL
|
583 AR8327_SGMII_CTRL_EN_RX
|
584 AR8327_SGMII_CTRL_EN_TX
);
586 ar8xxx_write(priv
, AR8327_REG_SGMII_CTRL
, t
);
588 if (pdata
->sgmii_cfg
->serdes_aen
)
589 new_pos
&= ~AR8327_POWER_ON_STRIP_SERDES_AEN
;
591 new_pos
|= AR8327_POWER_ON_STRIP_SERDES_AEN
;
594 ar8xxx_write(priv
, AR8327_REG_POWER_ON_STRIP
, new_pos
);
596 if (pdata
->leds
&& pdata
->num_leds
) {
599 data
->leds
= kzalloc(pdata
->num_leds
* sizeof(void *),
604 for (i
= 0; i
< pdata
->num_leds
; i
++)
605 ar8327_led_create(priv
, &pdata
->leds
[i
]);
613 ar8327_hw_config_of(struct ar8xxx_priv
*priv
, struct device_node
*np
)
615 struct ar8327_data
*data
= priv
->chip_data
;
620 paddr
= of_get_property(np
, "qca,ar8327-initvals", &len
);
621 if (!paddr
|| len
< (2 * sizeof(*paddr
)))
624 len
/= sizeof(*paddr
);
626 for (i
= 0; i
< len
- 1; i
+= 2) {
630 reg
= be32_to_cpup(paddr
+ i
);
631 val
= be32_to_cpup(paddr
+ i
+ 1);
634 case AR8327_REG_PORT_STATUS(0):
635 data
->port0_status
= val
;
637 case AR8327_REG_PORT_STATUS(6):
638 data
->port6_status
= val
;
641 ar8xxx_write(priv
, reg
, val
);
650 ar8327_hw_config_of(struct ar8xxx_priv
*priv
, struct device_node
*np
)
657 ar8327_hw_init(struct ar8xxx_priv
*priv
)
661 priv
->chip_data
= kzalloc(sizeof(struct ar8327_data
), GFP_KERNEL
);
662 if (!priv
->chip_data
)
665 if (priv
->phy
->mdio
.dev
.of_node
)
666 ret
= ar8327_hw_config_of(priv
, priv
->phy
->mdio
.dev
.of_node
);
668 ret
= ar8327_hw_config_pdata(priv
,
669 priv
->phy
->mdio
.dev
.platform_data
);
674 ar8327_leds_init(priv
);
676 ar8xxx_phy_init(priv
);
682 ar8327_cleanup(struct ar8xxx_priv
*priv
)
684 ar8327_leds_cleanup(priv
);
688 ar8327_init_globals(struct ar8xxx_priv
*priv
)
690 struct ar8327_data
*data
= priv
->chip_data
;
694 /* enable CPU port and disable mirror port */
695 t
= AR8327_FWD_CTRL0_CPU_PORT_EN
|
696 AR8327_FWD_CTRL0_MIRROR_PORT
;
697 ar8xxx_write(priv
, AR8327_REG_FWD_CTRL0
, t
);
699 /* forward multicast and broadcast frames to CPU */
700 t
= (AR8327_PORTS_ALL
<< AR8327_FWD_CTRL1_UC_FLOOD_S
) |
701 (AR8327_PORTS_ALL
<< AR8327_FWD_CTRL1_MC_FLOOD_S
) |
702 (AR8327_PORTS_ALL
<< AR8327_FWD_CTRL1_BC_FLOOD_S
);
703 ar8xxx_write(priv
, AR8327_REG_FWD_CTRL1
, t
);
705 /* enable jumbo frames */
706 ar8xxx_rmw(priv
, AR8327_REG_MAX_FRAME_SIZE
,
707 AR8327_MAX_FRAME_SIZE_MTU
, 9018 + 8 + 2);
709 /* Enable MIB counters */
710 ar8xxx_reg_set(priv
, AR8327_REG_MODULE_EN
,
711 AR8327_MODULE_EN_MIB
);
713 /* Disable EEE on all phy's due to stability issues */
714 for (i
= 0; i
< AR8XXX_NUM_PHYS
; i
++)
715 data
->eee
[i
] = false;
719 ar8327_init_port(struct ar8xxx_priv
*priv
, int port
)
721 struct ar8327_data
*data
= priv
->chip_data
;
724 if (port
== AR8216_PORT_CPU
)
725 t
= data
->port0_status
;
727 t
= data
->port6_status
;
729 t
= AR8216_PORT_STATUS_LINK_AUTO
;
731 if (port
!= AR8216_PORT_CPU
&& port
!= 6) {
732 /*hw limitation:if configure mac when there is traffic,
733 port MAC may work abnormal. Need disable lan&wan mac at fisrt*/
734 ar8xxx_write(priv
, AR8327_REG_PORT_STATUS(port
), 0);
736 t
|= AR8216_PORT_STATUS_FLOW_CONTROL
;
737 ar8xxx_write(priv
, AR8327_REG_PORT_STATUS(port
), t
);
739 ar8xxx_write(priv
, AR8327_REG_PORT_STATUS(port
), t
);
742 ar8xxx_write(priv
, AR8327_REG_PORT_HEADER(port
), 0);
744 ar8xxx_write(priv
, AR8327_REG_PORT_VLAN0(port
), 0);
746 t
= AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH
<< AR8327_PORT_VLAN1_OUT_MODE_S
;
747 ar8xxx_write(priv
, AR8327_REG_PORT_VLAN1(port
), t
);
749 t
= AR8327_PORT_LOOKUP_LEARN
;
750 t
|= AR8216_PORT_STATE_FORWARD
<< AR8327_PORT_LOOKUP_STATE_S
;
751 ar8xxx_write(priv
, AR8327_REG_PORT_LOOKUP(port
), t
);
755 ar8327_read_port_status(struct ar8xxx_priv
*priv
, int port
)
759 t
= ar8xxx_read(priv
, AR8327_REG_PORT_STATUS(port
));
760 /* map the flow control autoneg result bits to the flow control bits
761 * used in forced mode to allow ar8216_read_port_link detect
762 * flow control properly if autoneg is used
764 if (t
& AR8216_PORT_STATUS_LINK_UP
&&
765 t
& AR8216_PORT_STATUS_LINK_AUTO
) {
766 t
&= ~(AR8216_PORT_STATUS_TXFLOW
| AR8216_PORT_STATUS_RXFLOW
);
767 if (t
& AR8327_PORT_STATUS_TXFLOW_AUTO
)
768 t
|= AR8216_PORT_STATUS_TXFLOW
;
769 if (t
& AR8327_PORT_STATUS_RXFLOW_AUTO
)
770 t
|= AR8216_PORT_STATUS_RXFLOW
;
777 ar8327_read_port_eee_status(struct ar8xxx_priv
*priv
, int port
)
782 if (port
>= priv
->dev
.ports
)
785 if (port
== 0 || port
== 6)
790 /* EEE Ability Auto-negotiation Result */
791 t
= ar8xxx_phy_mmd_read(priv
, phy
, 0x7, 0x8000);
793 return mmd_eee_adv_to_ethtool_adv_t(t
);
797 ar8327_atu_flush(struct ar8xxx_priv
*priv
)
801 ret
= ar8216_wait_bit(priv
, AR8327_REG_ATU_FUNC
,
802 AR8327_ATU_FUNC_BUSY
, 0);
804 ar8xxx_write(priv
, AR8327_REG_ATU_FUNC
,
805 AR8327_ATU_FUNC_OP_FLUSH
|
806 AR8327_ATU_FUNC_BUSY
);
812 ar8327_atu_flush_port(struct ar8xxx_priv
*priv
, int port
)
817 ret
= ar8216_wait_bit(priv
, AR8327_REG_ATU_FUNC
,
818 AR8327_ATU_FUNC_BUSY
, 0);
820 t
= (port
<< AR8327_ATU_PORT_NUM_S
);
821 t
|= AR8327_ATU_FUNC_OP_FLUSH_PORT
;
822 t
|= AR8327_ATU_FUNC_BUSY
;
823 ar8xxx_write(priv
, AR8327_REG_ATU_FUNC
, t
);
830 ar8327_get_port_igmp(struct ar8xxx_priv
*priv
, int port
)
832 u32 fwd_ctrl
, frame_ack
;
834 fwd_ctrl
= (BIT(port
) << AR8327_FWD_CTRL1_IGMP_S
);
835 frame_ack
= ((AR8327_FRAME_ACK_CTRL_IGMP_MLD
|
836 AR8327_FRAME_ACK_CTRL_IGMP_JOIN
|
837 AR8327_FRAME_ACK_CTRL_IGMP_LEAVE
) <<
838 AR8327_FRAME_ACK_CTRL_S(port
));
840 return (ar8xxx_read(priv
, AR8327_REG_FWD_CTRL1
) &
841 fwd_ctrl
) == fwd_ctrl
&&
842 (ar8xxx_read(priv
, AR8327_REG_FRAME_ACK_CTRL(port
)) &
843 frame_ack
) == frame_ack
;
847 ar8327_set_port_igmp(struct ar8xxx_priv
*priv
, int port
, int enable
)
849 int reg_frame_ack
= AR8327_REG_FRAME_ACK_CTRL(port
);
850 u32 val_frame_ack
= (AR8327_FRAME_ACK_CTRL_IGMP_MLD
|
851 AR8327_FRAME_ACK_CTRL_IGMP_JOIN
|
852 AR8327_FRAME_ACK_CTRL_IGMP_LEAVE
) <<
853 AR8327_FRAME_ACK_CTRL_S(port
);
856 ar8xxx_rmw(priv
, AR8327_REG_FWD_CTRL1
,
857 BIT(port
) << AR8327_FWD_CTRL1_MC_FLOOD_S
,
858 BIT(port
) << AR8327_FWD_CTRL1_IGMP_S
);
859 ar8xxx_reg_set(priv
, reg_frame_ack
, val_frame_ack
);
861 ar8xxx_rmw(priv
, AR8327_REG_FWD_CTRL1
,
862 BIT(port
) << AR8327_FWD_CTRL1_IGMP_S
,
863 BIT(port
) << AR8327_FWD_CTRL1_MC_FLOOD_S
);
864 ar8xxx_reg_clear(priv
, reg_frame_ack
, val_frame_ack
);
869 ar8327_vtu_op(struct ar8xxx_priv
*priv
, u32 op
, u32 val
)
871 if (ar8216_wait_bit(priv
, AR8327_REG_VTU_FUNC1
,
872 AR8327_VTU_FUNC1_BUSY
, 0))
875 if ((op
& AR8327_VTU_FUNC1_OP
) == AR8327_VTU_FUNC1_OP_LOAD
)
876 ar8xxx_write(priv
, AR8327_REG_VTU_FUNC0
, val
);
878 op
|= AR8327_VTU_FUNC1_BUSY
;
879 ar8xxx_write(priv
, AR8327_REG_VTU_FUNC1
, op
);
883 ar8327_vtu_flush(struct ar8xxx_priv
*priv
)
885 ar8327_vtu_op(priv
, AR8327_VTU_FUNC1_OP_FLUSH
, 0);
889 ar8327_vtu_load_vlan(struct ar8xxx_priv
*priv
, u32 vid
, u32 port_mask
)
895 op
= AR8327_VTU_FUNC1_OP_LOAD
| (vid
<< AR8327_VTU_FUNC1_VID_S
);
896 val
= AR8327_VTU_FUNC0_VALID
| AR8327_VTU_FUNC0_IVL
;
897 for (i
= 0; i
< AR8327_NUM_PORTS
; i
++) {
900 if ((port_mask
& BIT(i
)) == 0)
901 mode
= AR8327_VTU_FUNC0_EG_MODE_NOT
;
902 else if (priv
->vlan
== 0)
903 mode
= AR8327_VTU_FUNC0_EG_MODE_KEEP
;
904 else if ((priv
->vlan_tagged
& BIT(i
)) || (priv
->vlan_id
[priv
->pvid
[i
]] != vid
))
905 mode
= AR8327_VTU_FUNC0_EG_MODE_TAG
;
907 mode
= AR8327_VTU_FUNC0_EG_MODE_UNTAG
;
909 val
|= mode
<< AR8327_VTU_FUNC0_EG_MODE_S(i
);
911 ar8327_vtu_op(priv
, op
, val
);
915 ar8327_setup_port(struct ar8xxx_priv
*priv
, int port
, u32 members
)
919 u32 pvid
= priv
->vlan_id
[priv
->pvid
[port
]];
922 egress
= AR8327_PORT_VLAN1_OUT_MODE_UNMOD
;
923 ingress
= AR8216_IN_SECURE
;
925 egress
= AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH
;
926 ingress
= AR8216_IN_PORT_ONLY
;
929 t
= pvid
<< AR8327_PORT_VLAN0_DEF_SVID_S
;
930 t
|= pvid
<< AR8327_PORT_VLAN0_DEF_CVID_S
;
931 if (priv
->vlan
&& priv
->port_vlan_prio
[port
]) {
932 u32 prio
= priv
->port_vlan_prio
[port
];
934 t
|= prio
<< AR8327_PORT_VLAN0_DEF_SPRI_S
;
935 t
|= prio
<< AR8327_PORT_VLAN0_DEF_CPRI_S
;
937 ar8xxx_write(priv
, AR8327_REG_PORT_VLAN0(port
), t
);
939 t
= AR8327_PORT_VLAN1_PORT_VLAN_PROP
;
940 t
|= egress
<< AR8327_PORT_VLAN1_OUT_MODE_S
;
941 if (priv
->vlan
&& priv
->port_vlan_prio
[port
])
942 t
|= AR8327_PORT_VLAN1_VLAN_PRI_PROP
;
944 ar8xxx_write(priv
, AR8327_REG_PORT_VLAN1(port
), t
);
947 t
|= AR8327_PORT_LOOKUP_LEARN
;
948 t
|= ingress
<< AR8327_PORT_LOOKUP_IN_MODE_S
;
949 t
|= AR8216_PORT_STATE_FORWARD
<< AR8327_PORT_LOOKUP_STATE_S
;
950 ar8xxx_write(priv
, AR8327_REG_PORT_LOOKUP(port
), t
);
954 ar8327_sw_get_ports(struct switch_dev
*dev
, struct switch_val
*val
)
956 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
957 u8 ports
= priv
->vlan_table
[val
->port_vlan
];
961 for (i
= 0; i
< dev
->ports
; i
++) {
962 struct switch_port
*p
;
964 if (!(ports
& (1 << i
)))
967 p
= &val
->value
.ports
[val
->len
++];
969 if ((priv
->vlan_tagged
& (1 << i
)) || (priv
->pvid
[i
] != val
->port_vlan
))
970 p
->flags
= (1 << SWITCH_PORT_FLAG_TAGGED
);
978 ar8327_sw_set_ports(struct switch_dev
*dev
, struct switch_val
*val
)
980 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
981 u8
*vt
= &priv
->vlan_table
[val
->port_vlan
];
985 for (i
= 0; i
< val
->len
; i
++) {
986 struct switch_port
*p
= &val
->value
.ports
[i
];
988 if (p
->flags
& (1 << SWITCH_PORT_FLAG_TAGGED
)) {
989 if (val
->port_vlan
== priv
->pvid
[p
->id
]) {
990 priv
->vlan_tagged
|= (1 << p
->id
);
993 priv
->vlan_tagged
&= ~(1 << p
->id
);
994 priv
->pvid
[p
->id
] = val
->port_vlan
;
1003 ar8327_set_mirror_regs(struct ar8xxx_priv
*priv
)
1007 /* reset all mirror registers */
1008 ar8xxx_rmw(priv
, AR8327_REG_FWD_CTRL0
,
1009 AR8327_FWD_CTRL0_MIRROR_PORT
,
1010 (0xF << AR8327_FWD_CTRL0_MIRROR_PORT_S
));
1011 for (port
= 0; port
< AR8327_NUM_PORTS
; port
++) {
1012 ar8xxx_reg_clear(priv
, AR8327_REG_PORT_LOOKUP(port
),
1013 AR8327_PORT_LOOKUP_ING_MIRROR_EN
);
1015 ar8xxx_reg_clear(priv
, AR8327_REG_PORT_HOL_CTRL1(port
),
1016 AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN
);
1019 /* now enable mirroring if necessary */
1020 if (priv
->source_port
>= AR8327_NUM_PORTS
||
1021 priv
->monitor_port
>= AR8327_NUM_PORTS
||
1022 priv
->source_port
== priv
->monitor_port
) {
1026 ar8xxx_rmw(priv
, AR8327_REG_FWD_CTRL0
,
1027 AR8327_FWD_CTRL0_MIRROR_PORT
,
1028 (priv
->monitor_port
<< AR8327_FWD_CTRL0_MIRROR_PORT_S
));
1030 if (priv
->mirror_rx
)
1031 ar8xxx_reg_set(priv
, AR8327_REG_PORT_LOOKUP(priv
->source_port
),
1032 AR8327_PORT_LOOKUP_ING_MIRROR_EN
);
1034 if (priv
->mirror_tx
)
1035 ar8xxx_reg_set(priv
, AR8327_REG_PORT_HOL_CTRL1(priv
->source_port
),
1036 AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN
);
1040 ar8327_sw_set_eee(struct switch_dev
*dev
,
1041 const struct switch_attr
*attr
,
1042 struct switch_val
*val
)
1044 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1045 struct ar8327_data
*data
= priv
->chip_data
;
1046 int port
= val
->port_vlan
;
1049 if (port
>= dev
->ports
)
1051 if (port
== 0 || port
== 6)
1056 data
->eee
[phy
] = !!(val
->value
.i
);
1062 ar8327_sw_get_eee(struct switch_dev
*dev
,
1063 const struct switch_attr
*attr
,
1064 struct switch_val
*val
)
1066 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1067 const struct ar8327_data
*data
= priv
->chip_data
;
1068 int port
= val
->port_vlan
;
1071 if (port
>= dev
->ports
)
1073 if (port
== 0 || port
== 6)
1078 val
->value
.i
= data
->eee
[phy
];
1084 ar8327_wait_atu_ready(struct ar8xxx_priv
*priv
, u16 r2
, u16 r1
)
1088 while (ar8xxx_mii_read32(priv
, r2
, r1
) & AR8327_ATU_FUNC_BUSY
&& --timeout
) {
1094 pr_err("ar8327: timeout waiting for atu to become ready\n");
1097 static void ar8327_get_arl_entry(struct ar8xxx_priv
*priv
,
1098 struct arl_entry
*a
, u32
*status
, enum arl_op op
)
1100 struct mii_bus
*bus
= priv
->mii_bus
;
1102 u16 r1_data0
, r1_data1
, r1_data2
, r1_func
;
1103 u32 val0
, val1
, val2
;
1105 split_addr(AR8327_REG_ATU_DATA0
, &r1_data0
, &r2
, &page
);
1108 r1_data1
= (AR8327_REG_ATU_DATA1
>> 1) & 0x1e;
1109 r1_data2
= (AR8327_REG_ATU_DATA2
>> 1) & 0x1e;
1110 r1_func
= (AR8327_REG_ATU_FUNC
>> 1) & 0x1e;
1113 case AR8XXX_ARL_INITIALIZE
:
1114 /* all ATU registers are on the same page
1115 * therefore set page only once
1117 bus
->write(bus
, 0x18, 0, page
);
1118 wait_for_page_switch();
1120 ar8327_wait_atu_ready(priv
, r2
, r1_func
);
1122 ar8xxx_mii_write32(priv
, r2
, r1_data0
, 0);
1123 ar8xxx_mii_write32(priv
, r2
, r1_data1
, 0);
1124 ar8xxx_mii_write32(priv
, r2
, r1_data2
, 0);
1126 case AR8XXX_ARL_GET_NEXT
:
1127 ar8xxx_mii_write32(priv
, r2
, r1_func
,
1128 AR8327_ATU_FUNC_OP_GET_NEXT
|
1129 AR8327_ATU_FUNC_BUSY
);
1130 ar8327_wait_atu_ready(priv
, r2
, r1_func
);
1132 val0
= ar8xxx_mii_read32(priv
, r2
, r1_data0
);
1133 val1
= ar8xxx_mii_read32(priv
, r2
, r1_data1
);
1134 val2
= ar8xxx_mii_read32(priv
, r2
, r1_data2
);
1136 *status
= val2
& AR8327_ATU_STATUS
;
1140 a
->portmap
= (val1
& AR8327_ATU_PORTS
) >> AR8327_ATU_PORTS_S
;
1141 a
->mac
[0] = (val0
& AR8327_ATU_ADDR0
) >> AR8327_ATU_ADDR0_S
;
1142 a
->mac
[1] = (val0
& AR8327_ATU_ADDR1
) >> AR8327_ATU_ADDR1_S
;
1143 a
->mac
[2] = (val0
& AR8327_ATU_ADDR2
) >> AR8327_ATU_ADDR2_S
;
1144 a
->mac
[3] = (val0
& AR8327_ATU_ADDR3
) >> AR8327_ATU_ADDR3_S
;
1145 a
->mac
[4] = (val1
& AR8327_ATU_ADDR4
) >> AR8327_ATU_ADDR4_S
;
1146 a
->mac
[5] = (val1
& AR8327_ATU_ADDR5
) >> AR8327_ATU_ADDR5_S
;
1152 ar8327_sw_hw_apply(struct switch_dev
*dev
)
1154 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1155 const struct ar8327_data
*data
= priv
->chip_data
;
1158 ret
= ar8xxx_sw_hw_apply(dev
);
1162 for (i
=0; i
< AR8XXX_NUM_PHYS
; i
++) {
1164 ar8xxx_reg_clear(priv
, AR8327_REG_EEE_CTRL
,
1165 AR8327_EEE_CTRL_DISABLE_PHY(i
));
1167 ar8xxx_reg_set(priv
, AR8327_REG_EEE_CTRL
,
1168 AR8327_EEE_CTRL_DISABLE_PHY(i
));
1175 ar8327_sw_get_port_igmp_snooping(struct switch_dev
*dev
,
1176 const struct switch_attr
*attr
,
1177 struct switch_val
*val
)
1179 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1180 int port
= val
->port_vlan
;
1182 if (port
>= dev
->ports
)
1185 mutex_lock(&priv
->reg_mutex
);
1186 val
->value
.i
= ar8327_get_port_igmp(priv
, port
);
1187 mutex_unlock(&priv
->reg_mutex
);
1193 ar8327_sw_set_port_igmp_snooping(struct switch_dev
*dev
,
1194 const struct switch_attr
*attr
,
1195 struct switch_val
*val
)
1197 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1198 int port
= val
->port_vlan
;
1200 if (port
>= dev
->ports
)
1203 mutex_lock(&priv
->reg_mutex
);
1204 ar8327_set_port_igmp(priv
, port
, val
->value
.i
);
1205 mutex_unlock(&priv
->reg_mutex
);
1211 ar8327_sw_get_igmp_snooping(struct switch_dev
*dev
,
1212 const struct switch_attr
*attr
,
1213 struct switch_val
*val
)
1217 for (port
= 0; port
< dev
->ports
; port
++) {
1218 val
->port_vlan
= port
;
1219 if (ar8327_sw_get_port_igmp_snooping(dev
, attr
, val
) ||
1228 ar8327_sw_set_igmp_snooping(struct switch_dev
*dev
,
1229 const struct switch_attr
*attr
,
1230 struct switch_val
*val
)
1234 for (port
= 0; port
< dev
->ports
; port
++) {
1235 val
->port_vlan
= port
;
1236 if (ar8327_sw_set_port_igmp_snooping(dev
, attr
, val
))
1244 ar8327_sw_get_igmp_v3(struct switch_dev
*dev
,
1245 const struct switch_attr
*attr
,
1246 struct switch_val
*val
)
1248 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1251 mutex_lock(&priv
->reg_mutex
);
1252 val_reg
= ar8xxx_read(priv
, AR8327_REG_FRAME_ACK_CTRL1
);
1253 val
->value
.i
= ((val_reg
& AR8327_FRAME_ACK_CTRL_IGMP_V3_EN
) != 0);
1254 mutex_unlock(&priv
->reg_mutex
);
1260 ar8327_sw_set_igmp_v3(struct switch_dev
*dev
,
1261 const struct switch_attr
*attr
,
1262 struct switch_val
*val
)
1264 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1266 mutex_lock(&priv
->reg_mutex
);
1268 ar8xxx_reg_set(priv
, AR8327_REG_FRAME_ACK_CTRL1
,
1269 AR8327_FRAME_ACK_CTRL_IGMP_V3_EN
);
1271 ar8xxx_reg_clear(priv
, AR8327_REG_FRAME_ACK_CTRL1
,
1272 AR8327_FRAME_ACK_CTRL_IGMP_V3_EN
);
1273 mutex_unlock(&priv
->reg_mutex
);
1279 ar8327_sw_set_port_vlan_prio(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1280 struct switch_val
*val
)
1282 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1283 int port
= val
->port_vlan
;
1285 if (port
>= dev
->ports
)
1287 if (port
== 0 || port
== 6)
1289 if (val
->value
.i
< 0 || val
->value
.i
> 7)
1292 priv
->port_vlan_prio
[port
] = val
->value
.i
;
1298 ar8327_sw_get_port_vlan_prio(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1299 struct switch_val
*val
)
1301 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1302 int port
= val
->port_vlan
;
1304 val
->value
.i
= priv
->port_vlan_prio
[port
];
1309 static const struct switch_attr ar8327_sw_attr_globals
[] = {
1311 .type
= SWITCH_TYPE_INT
,
1312 .name
= "enable_vlan",
1313 .description
= "Enable VLAN mode",
1314 .set
= ar8xxx_sw_set_vlan
,
1315 .get
= ar8xxx_sw_get_vlan
,
1319 .type
= SWITCH_TYPE_NOVAL
,
1320 .name
= "reset_mibs",
1321 .description
= "Reset all MIB counters",
1322 .set
= ar8xxx_sw_set_reset_mibs
,
1325 .type
= SWITCH_TYPE_INT
,
1326 .name
= "enable_mirror_rx",
1327 .description
= "Enable mirroring of RX packets",
1328 .set
= ar8xxx_sw_set_mirror_rx_enable
,
1329 .get
= ar8xxx_sw_get_mirror_rx_enable
,
1333 .type
= SWITCH_TYPE_INT
,
1334 .name
= "enable_mirror_tx",
1335 .description
= "Enable mirroring of TX packets",
1336 .set
= ar8xxx_sw_set_mirror_tx_enable
,
1337 .get
= ar8xxx_sw_get_mirror_tx_enable
,
1341 .type
= SWITCH_TYPE_INT
,
1342 .name
= "mirror_monitor_port",
1343 .description
= "Mirror monitor port",
1344 .set
= ar8xxx_sw_set_mirror_monitor_port
,
1345 .get
= ar8xxx_sw_get_mirror_monitor_port
,
1346 .max
= AR8327_NUM_PORTS
- 1
1349 .type
= SWITCH_TYPE_INT
,
1350 .name
= "mirror_source_port",
1351 .description
= "Mirror source port",
1352 .set
= ar8xxx_sw_set_mirror_source_port
,
1353 .get
= ar8xxx_sw_get_mirror_source_port
,
1354 .max
= AR8327_NUM_PORTS
- 1
1357 .type
= SWITCH_TYPE_INT
,
1358 .name
= "arl_age_time",
1359 .description
= "ARL age time (secs)",
1360 .set
= ar8xxx_sw_set_arl_age_time
,
1361 .get
= ar8xxx_sw_get_arl_age_time
,
1364 .type
= SWITCH_TYPE_STRING
,
1365 .name
= "arl_table",
1366 .description
= "Get ARL table",
1368 .get
= ar8xxx_sw_get_arl_table
,
1371 .type
= SWITCH_TYPE_NOVAL
,
1372 .name
= "flush_arl_table",
1373 .description
= "Flush ARL table",
1374 .set
= ar8xxx_sw_set_flush_arl_table
,
1377 .type
= SWITCH_TYPE_INT
,
1378 .name
= "igmp_snooping",
1379 .description
= "Enable IGMP Snooping",
1380 .set
= ar8327_sw_set_igmp_snooping
,
1381 .get
= ar8327_sw_get_igmp_snooping
,
1385 .type
= SWITCH_TYPE_INT
,
1387 .description
= "Enable IGMPv3 support",
1388 .set
= ar8327_sw_set_igmp_v3
,
1389 .get
= ar8327_sw_get_igmp_v3
,
1394 static const struct switch_attr ar8327_sw_attr_port
[] = {
1396 .type
= SWITCH_TYPE_NOVAL
,
1397 .name
= "reset_mib",
1398 .description
= "Reset single port MIB counters",
1399 .set
= ar8xxx_sw_set_port_reset_mib
,
1402 .type
= SWITCH_TYPE_STRING
,
1404 .description
= "Get port's MIB counters",
1406 .get
= ar8xxx_sw_get_port_mib
,
1409 .type
= SWITCH_TYPE_INT
,
1410 .name
= "enable_eee",
1411 .description
= "Enable EEE PHY sleep mode",
1412 .set
= ar8327_sw_set_eee
,
1413 .get
= ar8327_sw_get_eee
,
1417 .type
= SWITCH_TYPE_NOVAL
,
1418 .name
= "flush_arl_table",
1419 .description
= "Flush port's ARL table entries",
1420 .set
= ar8xxx_sw_set_flush_port_arl_table
,
1423 .type
= SWITCH_TYPE_INT
,
1424 .name
= "igmp_snooping",
1425 .description
= "Enable port's IGMP Snooping",
1426 .set
= ar8327_sw_set_port_igmp_snooping
,
1427 .get
= ar8327_sw_get_port_igmp_snooping
,
1431 .type
= SWITCH_TYPE_INT
,
1432 .name
= "vlan_prio",
1433 .description
= "Port VLAN default priority (VLAN PCP) (0-7)",
1434 .set
= ar8327_sw_set_port_vlan_prio
,
1435 .get
= ar8327_sw_get_port_vlan_prio
,
1440 static const struct switch_dev_ops ar8327_sw_ops
= {
1442 .attr
= ar8327_sw_attr_globals
,
1443 .n_attr
= ARRAY_SIZE(ar8327_sw_attr_globals
),
1446 .attr
= ar8327_sw_attr_port
,
1447 .n_attr
= ARRAY_SIZE(ar8327_sw_attr_port
),
1450 .attr
= ar8xxx_sw_attr_vlan
,
1451 .n_attr
= ARRAY_SIZE(ar8xxx_sw_attr_vlan
),
1453 .get_port_pvid
= ar8xxx_sw_get_pvid
,
1454 .set_port_pvid
= ar8xxx_sw_set_pvid
,
1455 .get_vlan_ports
= ar8327_sw_get_ports
,
1456 .set_vlan_ports
= ar8327_sw_set_ports
,
1457 .apply_config
= ar8327_sw_hw_apply
,
1458 .reset_switch
= ar8xxx_sw_reset_switch
,
1459 .get_port_link
= ar8xxx_sw_get_port_link
,
1460 /* The following op is disabled as it hogs the CPU and degrades performance.
1461 An implementation has been attempted in 4d8a66d but reading MIB data is slow
1464 The high CPU load has been traced down to the ar8xxx_reg_wait() call in
1465 ar8xxx_mib_op(), which has to usleep_range() till the MIB busy flag set by
1466 the request to update the MIB counter is cleared. */
1468 .get_port_stats
= ar8xxx_sw_get_port_stats
,
1472 const struct ar8xxx_chip ar8327_chip
= {
1473 .caps
= AR8XXX_CAP_GIGE
| AR8XXX_CAP_MIB_COUNTERS
,
1474 .config_at_probe
= true,
1475 .mii_lo_first
= true,
1477 .name
= "Atheros AR8327",
1478 .ports
= AR8327_NUM_PORTS
,
1479 .vlans
= AR8X16_MAX_VLANS
,
1480 .swops
= &ar8327_sw_ops
,
1482 .reg_port_stats_start
= 0x1000,
1483 .reg_port_stats_length
= 0x100,
1484 .reg_arl_ctrl
= AR8327_REG_ARL_CTRL
,
1486 .hw_init
= ar8327_hw_init
,
1487 .cleanup
= ar8327_cleanup
,
1488 .init_globals
= ar8327_init_globals
,
1489 .init_port
= ar8327_init_port
,
1490 .setup_port
= ar8327_setup_port
,
1491 .read_port_status
= ar8327_read_port_status
,
1492 .read_port_eee_status
= ar8327_read_port_eee_status
,
1493 .atu_flush
= ar8327_atu_flush
,
1494 .atu_flush_port
= ar8327_atu_flush_port
,
1495 .vtu_flush
= ar8327_vtu_flush
,
1496 .vtu_load_vlan
= ar8327_vtu_load_vlan
,
1497 .phy_fixup
= ar8327_phy_fixup
,
1498 .set_mirror_regs
= ar8327_set_mirror_regs
,
1499 .get_arl_entry
= ar8327_get_arl_entry
,
1500 .sw_hw_apply
= ar8327_sw_hw_apply
,
1502 .num_mibs
= ARRAY_SIZE(ar8236_mibs
),
1503 .mib_decs
= ar8236_mibs
,
1504 .mib_func
= AR8327_REG_MIB_FUNC
1507 const struct ar8xxx_chip ar8337_chip
= {
1508 .caps
= AR8XXX_CAP_GIGE
| AR8XXX_CAP_MIB_COUNTERS
,
1509 .config_at_probe
= true,
1510 .mii_lo_first
= true,
1512 .name
= "Atheros AR8337",
1513 .ports
= AR8327_NUM_PORTS
,
1514 .vlans
= AR8X16_MAX_VLANS
,
1515 .swops
= &ar8327_sw_ops
,
1517 .reg_port_stats_start
= 0x1000,
1518 .reg_port_stats_length
= 0x100,
1519 .reg_arl_ctrl
= AR8327_REG_ARL_CTRL
,
1521 .hw_init
= ar8327_hw_init
,
1522 .cleanup
= ar8327_cleanup
,
1523 .init_globals
= ar8327_init_globals
,
1524 .init_port
= ar8327_init_port
,
1525 .setup_port
= ar8327_setup_port
,
1526 .read_port_status
= ar8327_read_port_status
,
1527 .read_port_eee_status
= ar8327_read_port_eee_status
,
1528 .atu_flush
= ar8327_atu_flush
,
1529 .atu_flush_port
= ar8327_atu_flush_port
,
1530 .vtu_flush
= ar8327_vtu_flush
,
1531 .vtu_load_vlan
= ar8327_vtu_load_vlan
,
1532 .phy_fixup
= ar8327_phy_fixup
,
1533 .set_mirror_regs
= ar8327_set_mirror_regs
,
1534 .get_arl_entry
= ar8327_get_arl_entry
,
1535 .sw_hw_apply
= ar8327_sw_hw_apply
,
1536 .phy_rgmii_set
= ar8327_phy_rgmii_set
,
1538 .num_mibs
= ARRAY_SIZE(ar8236_mibs
),
1539 .mib_decs
= ar8236_mibs
,
1540 .mib_func
= AR8327_REG_MIB_FUNC