2 * ar8327.c: AR8216 switch driver
4 * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>
5 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
18 #include <linux/list.h>
19 #include <linux/bitops.h>
20 #include <linux/switch.h>
21 #include <linux/delay.h>
22 #include <linux/phy.h>
23 #include <linux/lockdep.h>
24 #include <linux/ar8216_platform.h>
25 #include <linux/workqueue.h>
26 #include <linux/of_device.h>
27 #include <linux/leds.h>
28 #include <linux/mdio.h>
33 extern const struct ar8xxx_mib_desc ar8236_mibs
[39];
34 extern const struct switch_attr ar8xxx_sw_attr_vlan
[1];
37 ar8327_get_pad_cfg(struct ar8327_pad_cfg
*cfg
)
49 case AR8327_PAD_MAC2MAC_MII
:
50 t
= AR8327_PAD_MAC_MII_EN
;
52 t
|= AR8327_PAD_MAC_MII_RXCLK_SEL
;
54 t
|= AR8327_PAD_MAC_MII_TXCLK_SEL
;
57 case AR8327_PAD_MAC2MAC_GMII
:
58 t
= AR8327_PAD_MAC_GMII_EN
;
60 t
|= AR8327_PAD_MAC_GMII_RXCLK_SEL
;
62 t
|= AR8327_PAD_MAC_GMII_TXCLK_SEL
;
65 case AR8327_PAD_MAC_SGMII
:
66 t
= AR8327_PAD_SGMII_EN
;
69 * WAR for the QUalcomm Atheros AP136 board.
70 * It seems that RGMII TX/RX delay settings needs to be
71 * applied for SGMII mode as well, The ethernet is not
72 * reliable without this.
74 t
|= cfg
->txclk_delay_sel
<< AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S
;
75 t
|= cfg
->rxclk_delay_sel
<< AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S
;
76 if (cfg
->rxclk_delay_en
)
77 t
|= AR8327_PAD_RGMII_RXCLK_DELAY_EN
;
78 if (cfg
->txclk_delay_en
)
79 t
|= AR8327_PAD_RGMII_TXCLK_DELAY_EN
;
81 if (cfg
->sgmii_delay_en
)
82 t
|= AR8327_PAD_SGMII_DELAY_EN
;
86 case AR8327_PAD_MAC2PHY_MII
:
87 t
= AR8327_PAD_PHY_MII_EN
;
89 t
|= AR8327_PAD_PHY_MII_RXCLK_SEL
;
91 t
|= AR8327_PAD_PHY_MII_TXCLK_SEL
;
94 case AR8327_PAD_MAC2PHY_GMII
:
95 t
= AR8327_PAD_PHY_GMII_EN
;
96 if (cfg
->pipe_rxclk_sel
)
97 t
|= AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL
;
99 t
|= AR8327_PAD_PHY_GMII_RXCLK_SEL
;
101 t
|= AR8327_PAD_PHY_GMII_TXCLK_SEL
;
104 case AR8327_PAD_MAC_RGMII
:
105 t
= AR8327_PAD_RGMII_EN
;
106 t
|= cfg
->txclk_delay_sel
<< AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S
;
107 t
|= cfg
->rxclk_delay_sel
<< AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S
;
108 if (cfg
->rxclk_delay_en
)
109 t
|= AR8327_PAD_RGMII_RXCLK_DELAY_EN
;
110 if (cfg
->txclk_delay_en
)
111 t
|= AR8327_PAD_RGMII_TXCLK_DELAY_EN
;
114 case AR8327_PAD_PHY_GMII
:
115 t
= AR8327_PAD_PHYX_GMII_EN
;
118 case AR8327_PAD_PHY_RGMII
:
119 t
= AR8327_PAD_PHYX_RGMII_EN
;
122 case AR8327_PAD_PHY_MII
:
123 t
= AR8327_PAD_PHYX_MII_EN
;
131 ar8327_phy_fixup(struct ar8xxx_priv
*priv
, int phy
)
133 switch (priv
->chip_rev
) {
135 /* For 100M waveform */
136 ar8xxx_phy_dbg_write(priv
, phy
, 0, 0x02ea);
137 /* Turn on Gigabit clock */
138 ar8xxx_phy_dbg_write(priv
, phy
, 0x3d, 0x68a0);
142 ar8xxx_phy_mmd_write(priv
, phy
, 0x7, 0x3c, 0x0);
145 ar8xxx_phy_mmd_write(priv
, phy
, 0x3, 0x800d, 0x803f);
146 ar8xxx_phy_dbg_write(priv
, phy
, 0x3d, 0x6860);
147 ar8xxx_phy_dbg_write(priv
, phy
, 0x5, 0x2c46);
148 ar8xxx_phy_dbg_write(priv
, phy
, 0x3c, 0x6000);
154 ar8327_get_port_init_status(struct ar8327_port_cfg
*cfg
)
158 if (!cfg
->force_link
)
159 return AR8216_PORT_STATUS_LINK_AUTO
;
161 t
= AR8216_PORT_STATUS_TXMAC
| AR8216_PORT_STATUS_RXMAC
;
162 t
|= cfg
->duplex
? AR8216_PORT_STATUS_DUPLEX
: 0;
163 t
|= cfg
->rxpause
? AR8216_PORT_STATUS_RXFLOW
: 0;
164 t
|= cfg
->txpause
? AR8216_PORT_STATUS_TXFLOW
: 0;
166 switch (cfg
->speed
) {
167 case AR8327_PORT_SPEED_10
:
168 t
|= AR8216_PORT_SPEED_10M
;
170 case AR8327_PORT_SPEED_100
:
171 t
|= AR8216_PORT_SPEED_100M
;
173 case AR8327_PORT_SPEED_1000
:
174 t
|= AR8216_PORT_SPEED_1000M
;
181 #define AR8327_LED_ENTRY(_num, _reg, _shift) \
182 [_num] = { .reg = (_reg), .shift = (_shift) }
184 static const struct ar8327_led_entry
185 ar8327_led_map
[AR8327_NUM_LEDS
] = {
186 AR8327_LED_ENTRY(AR8327_LED_PHY0_0
, 0, 14),
187 AR8327_LED_ENTRY(AR8327_LED_PHY0_1
, 1, 14),
188 AR8327_LED_ENTRY(AR8327_LED_PHY0_2
, 2, 14),
190 AR8327_LED_ENTRY(AR8327_LED_PHY1_0
, 3, 8),
191 AR8327_LED_ENTRY(AR8327_LED_PHY1_1
, 3, 10),
192 AR8327_LED_ENTRY(AR8327_LED_PHY1_2
, 3, 12),
194 AR8327_LED_ENTRY(AR8327_LED_PHY2_0
, 3, 14),
195 AR8327_LED_ENTRY(AR8327_LED_PHY2_1
, 3, 16),
196 AR8327_LED_ENTRY(AR8327_LED_PHY2_2
, 3, 18),
198 AR8327_LED_ENTRY(AR8327_LED_PHY3_0
, 3, 20),
199 AR8327_LED_ENTRY(AR8327_LED_PHY3_1
, 3, 22),
200 AR8327_LED_ENTRY(AR8327_LED_PHY3_2
, 3, 24),
202 AR8327_LED_ENTRY(AR8327_LED_PHY4_0
, 0, 30),
203 AR8327_LED_ENTRY(AR8327_LED_PHY4_1
, 1, 30),
204 AR8327_LED_ENTRY(AR8327_LED_PHY4_2
, 2, 30),
208 ar8327_set_led_pattern(struct ar8xxx_priv
*priv
, unsigned int led_num
,
209 enum ar8327_led_pattern pattern
)
211 const struct ar8327_led_entry
*entry
;
213 entry
= &ar8327_led_map
[led_num
];
214 ar8xxx_rmw(priv
, AR8327_REG_LED_CTRL(entry
->reg
),
215 (3 << entry
->shift
), pattern
<< entry
->shift
);
219 ar8327_led_work_func(struct work_struct
*work
)
221 struct ar8327_led
*aled
;
224 aled
= container_of(work
, struct ar8327_led
, led_work
);
226 pattern
= aled
->pattern
;
228 ar8327_set_led_pattern(aled
->sw_priv
, aled
->led_num
,
233 ar8327_led_schedule_change(struct ar8327_led
*aled
, u8 pattern
)
235 if (aled
->pattern
== pattern
)
238 aled
->pattern
= pattern
;
239 schedule_work(&aled
->led_work
);
242 static inline struct ar8327_led
*
243 led_cdev_to_ar8327_led(struct led_classdev
*led_cdev
)
245 return container_of(led_cdev
, struct ar8327_led
, cdev
);
249 ar8327_led_blink_set(struct led_classdev
*led_cdev
,
250 unsigned long *delay_on
,
251 unsigned long *delay_off
)
253 struct ar8327_led
*aled
= led_cdev_to_ar8327_led(led_cdev
);
255 if (*delay_on
== 0 && *delay_off
== 0) {
260 if (*delay_on
!= 125 || *delay_off
!= 125) {
262 * The hardware only supports blinking at 4Hz. Fall back
263 * to software implementation in other cases.
268 spin_lock(&aled
->lock
);
270 aled
->enable_hw_mode
= false;
271 ar8327_led_schedule_change(aled
, AR8327_LED_PATTERN_BLINK
);
273 spin_unlock(&aled
->lock
);
279 ar8327_led_set_brightness(struct led_classdev
*led_cdev
,
280 enum led_brightness brightness
)
282 struct ar8327_led
*aled
= led_cdev_to_ar8327_led(led_cdev
);
286 active
= (brightness
!= LED_OFF
);
287 active
^= aled
->active_low
;
289 pattern
= (active
) ? AR8327_LED_PATTERN_ON
:
290 AR8327_LED_PATTERN_OFF
;
292 spin_lock(&aled
->lock
);
294 aled
->enable_hw_mode
= false;
295 ar8327_led_schedule_change(aled
, pattern
);
297 spin_unlock(&aled
->lock
);
301 ar8327_led_enable_hw_mode_show(struct device
*dev
,
302 struct device_attribute
*attr
,
305 struct led_classdev
*led_cdev
= dev_get_drvdata(dev
);
306 struct ar8327_led
*aled
= led_cdev_to_ar8327_led(led_cdev
);
309 ret
+= scnprintf(buf
, PAGE_SIZE
, "%d\n", aled
->enable_hw_mode
);
315 ar8327_led_enable_hw_mode_store(struct device
*dev
,
316 struct device_attribute
*attr
,
320 struct led_classdev
*led_cdev
= dev_get_drvdata(dev
);
321 struct ar8327_led
*aled
= led_cdev_to_ar8327_led(led_cdev
);
326 ret
= kstrtou8(buf
, 10, &value
);
330 spin_lock(&aled
->lock
);
332 aled
->enable_hw_mode
= !!value
;
333 if (aled
->enable_hw_mode
)
334 pattern
= AR8327_LED_PATTERN_RULE
;
336 pattern
= AR8327_LED_PATTERN_OFF
;
338 ar8327_led_schedule_change(aled
, pattern
);
340 spin_unlock(&aled
->lock
);
345 static DEVICE_ATTR(enable_hw_mode
, S_IRUGO
| S_IWUSR
,
346 ar8327_led_enable_hw_mode_show
,
347 ar8327_led_enable_hw_mode_store
);
350 ar8327_led_register(struct ar8327_led
*aled
)
354 ret
= led_classdev_register(NULL
, &aled
->cdev
);
358 if (aled
->mode
== AR8327_LED_MODE_HW
) {
359 ret
= device_create_file(aled
->cdev
.dev
,
360 &dev_attr_enable_hw_mode
);
368 led_classdev_unregister(&aled
->cdev
);
373 ar8327_led_unregister(struct ar8327_led
*aled
)
375 if (aled
->mode
== AR8327_LED_MODE_HW
)
376 device_remove_file(aled
->cdev
.dev
, &dev_attr_enable_hw_mode
);
378 led_classdev_unregister(&aled
->cdev
);
379 cancel_work_sync(&aled
->led_work
);
383 ar8327_led_create(struct ar8xxx_priv
*priv
,
384 const struct ar8327_led_info
*led_info
)
386 struct ar8327_data
*data
= priv
->chip_data
;
387 struct ar8327_led
*aled
;
390 if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS
))
396 if (led_info
->led_num
>= AR8327_NUM_LEDS
)
399 aled
= kzalloc(sizeof(*aled
) + strlen(led_info
->name
) + 1,
404 aled
->sw_priv
= priv
;
405 aled
->led_num
= led_info
->led_num
;
406 aled
->active_low
= led_info
->active_low
;
407 aled
->mode
= led_info
->mode
;
409 if (aled
->mode
== AR8327_LED_MODE_HW
)
410 aled
->enable_hw_mode
= true;
412 aled
->name
= (char *)(aled
+ 1);
413 strcpy(aled
->name
, led_info
->name
);
415 aled
->cdev
.name
= aled
->name
;
416 aled
->cdev
.brightness_set
= ar8327_led_set_brightness
;
417 aled
->cdev
.blink_set
= ar8327_led_blink_set
;
418 aled
->cdev
.default_trigger
= led_info
->default_trigger
;
420 spin_lock_init(&aled
->lock
);
421 mutex_init(&aled
->mutex
);
422 INIT_WORK(&aled
->led_work
, ar8327_led_work_func
);
424 ret
= ar8327_led_register(aled
);
428 data
->leds
[data
->num_leds
++] = aled
;
438 ar8327_led_destroy(struct ar8327_led
*aled
)
440 ar8327_led_unregister(aled
);
445 ar8327_leds_init(struct ar8xxx_priv
*priv
)
447 struct ar8327_data
*data
= priv
->chip_data
;
450 if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS
))
453 for (i
= 0; i
< data
->num_leds
; i
++) {
454 struct ar8327_led
*aled
;
456 aled
= data
->leds
[i
];
458 if (aled
->enable_hw_mode
)
459 aled
->pattern
= AR8327_LED_PATTERN_RULE
;
461 aled
->pattern
= AR8327_LED_PATTERN_OFF
;
463 ar8327_set_led_pattern(priv
, aled
->led_num
, aled
->pattern
);
468 ar8327_leds_cleanup(struct ar8xxx_priv
*priv
)
470 struct ar8327_data
*data
= priv
->chip_data
;
473 if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS
))
476 for (i
= 0; i
< data
->num_leds
; i
++) {
477 struct ar8327_led
*aled
;
479 aled
= data
->leds
[i
];
480 ar8327_led_destroy(aled
);
487 ar8327_hw_config_pdata(struct ar8xxx_priv
*priv
,
488 struct ar8327_platform_data
*pdata
)
490 struct ar8327_led_cfg
*led_cfg
;
491 struct ar8327_data
*data
= priv
->chip_data
;
498 priv
->get_port_link
= pdata
->get_port_link
;
500 data
->port0_status
= ar8327_get_port_init_status(&pdata
->port0_cfg
);
501 data
->port6_status
= ar8327_get_port_init_status(&pdata
->port6_cfg
);
503 t
= ar8327_get_pad_cfg(pdata
->pad0_cfg
);
504 if (chip_is_ar8337(priv
) && !pdata
->pad0_cfg
->mac06_exchange_dis
)
505 t
|= AR8337_PAD_MAC06_EXCHANGE_EN
;
506 ar8xxx_write(priv
, AR8327_REG_PAD0_MODE
, t
);
508 t
= ar8327_get_pad_cfg(pdata
->pad5_cfg
);
509 ar8xxx_write(priv
, AR8327_REG_PAD5_MODE
, t
);
510 t
= ar8327_get_pad_cfg(pdata
->pad6_cfg
);
511 ar8xxx_write(priv
, AR8327_REG_PAD6_MODE
, t
);
513 pos
= ar8xxx_read(priv
, AR8327_REG_POWER_ON_STRIP
);
516 led_cfg
= pdata
->led_cfg
;
518 if (led_cfg
->open_drain
)
519 new_pos
|= AR8327_POWER_ON_STRIP_LED_OPEN_EN
;
521 new_pos
&= ~AR8327_POWER_ON_STRIP_LED_OPEN_EN
;
523 ar8xxx_write(priv
, AR8327_REG_LED_CTRL0
, led_cfg
->led_ctrl0
);
524 ar8xxx_write(priv
, AR8327_REG_LED_CTRL1
, led_cfg
->led_ctrl1
);
525 ar8xxx_write(priv
, AR8327_REG_LED_CTRL2
, led_cfg
->led_ctrl2
);
526 ar8xxx_write(priv
, AR8327_REG_LED_CTRL3
, led_cfg
->led_ctrl3
);
529 new_pos
|= AR8327_POWER_ON_STRIP_POWER_ON_SEL
;
532 if (pdata
->sgmii_cfg
) {
533 t
= pdata
->sgmii_cfg
->sgmii_ctrl
;
534 if (priv
->chip_rev
== 1)
535 t
|= AR8327_SGMII_CTRL_EN_PLL
|
536 AR8327_SGMII_CTRL_EN_RX
|
537 AR8327_SGMII_CTRL_EN_TX
;
539 t
&= ~(AR8327_SGMII_CTRL_EN_PLL
|
540 AR8327_SGMII_CTRL_EN_RX
|
541 AR8327_SGMII_CTRL_EN_TX
);
543 ar8xxx_write(priv
, AR8327_REG_SGMII_CTRL
, t
);
545 if (pdata
->sgmii_cfg
->serdes_aen
)
546 new_pos
&= ~AR8327_POWER_ON_STRIP_SERDES_AEN
;
548 new_pos
|= AR8327_POWER_ON_STRIP_SERDES_AEN
;
551 ar8xxx_write(priv
, AR8327_REG_POWER_ON_STRIP
, new_pos
);
553 if (pdata
->leds
&& pdata
->num_leds
) {
556 data
->leds
= kzalloc(pdata
->num_leds
* sizeof(void *),
561 for (i
= 0; i
< pdata
->num_leds
; i
++)
562 ar8327_led_create(priv
, &pdata
->leds
[i
]);
570 ar8327_hw_config_of(struct ar8xxx_priv
*priv
, struct device_node
*np
)
572 struct ar8327_data
*data
= priv
->chip_data
;
577 paddr
= of_get_property(np
, "qca,ar8327-initvals", &len
);
578 if (!paddr
|| len
< (2 * sizeof(*paddr
)))
581 len
/= sizeof(*paddr
);
583 for (i
= 0; i
< len
- 1; i
+= 2) {
587 reg
= be32_to_cpup(paddr
+ i
);
588 val
= be32_to_cpup(paddr
+ i
+ 1);
591 case AR8327_REG_PORT_STATUS(0):
592 data
->port0_status
= val
;
594 case AR8327_REG_PORT_STATUS(6):
595 data
->port6_status
= val
;
598 ar8xxx_write(priv
, reg
, val
);
607 ar8327_hw_config_of(struct ar8xxx_priv
*priv
, struct device_node
*np
)
614 ar8327_hw_init(struct ar8xxx_priv
*priv
)
618 priv
->chip_data
= kzalloc(sizeof(struct ar8327_data
), GFP_KERNEL
);
619 if (!priv
->chip_data
)
622 if (priv
->phy
->mdio
.dev
.of_node
)
623 ret
= ar8327_hw_config_of(priv
, priv
->phy
->mdio
.dev
.of_node
);
625 ret
= ar8327_hw_config_pdata(priv
,
626 priv
->phy
->mdio
.dev
.platform_data
);
631 ar8327_leds_init(priv
);
633 ar8xxx_phy_init(priv
);
639 ar8327_cleanup(struct ar8xxx_priv
*priv
)
641 ar8327_leds_cleanup(priv
);
645 ar8327_init_globals(struct ar8xxx_priv
*priv
)
647 struct ar8327_data
*data
= priv
->chip_data
;
651 /* enable CPU port and disable mirror port */
652 t
= AR8327_FWD_CTRL0_CPU_PORT_EN
|
653 AR8327_FWD_CTRL0_MIRROR_PORT
;
654 ar8xxx_write(priv
, AR8327_REG_FWD_CTRL0
, t
);
656 /* forward multicast and broadcast frames to CPU */
657 t
= (AR8327_PORTS_ALL
<< AR8327_FWD_CTRL1_UC_FLOOD_S
) |
658 (AR8327_PORTS_ALL
<< AR8327_FWD_CTRL1_MC_FLOOD_S
) |
659 (AR8327_PORTS_ALL
<< AR8327_FWD_CTRL1_BC_FLOOD_S
);
660 ar8xxx_write(priv
, AR8327_REG_FWD_CTRL1
, t
);
662 /* enable jumbo frames */
663 ar8xxx_rmw(priv
, AR8327_REG_MAX_FRAME_SIZE
,
664 AR8327_MAX_FRAME_SIZE_MTU
, 9018 + 8 + 2);
666 /* Enable MIB counters */
667 ar8xxx_reg_set(priv
, AR8327_REG_MODULE_EN
,
668 AR8327_MODULE_EN_MIB
);
670 /* Disable EEE on all phy's due to stability issues */
671 for (i
= 0; i
< AR8XXX_NUM_PHYS
; i
++)
672 data
->eee
[i
] = false;
676 ar8327_init_port(struct ar8xxx_priv
*priv
, int port
)
678 struct ar8327_data
*data
= priv
->chip_data
;
681 if (port
== AR8216_PORT_CPU
)
682 t
= data
->port0_status
;
684 t
= data
->port6_status
;
686 t
= AR8216_PORT_STATUS_LINK_AUTO
;
688 if (port
!= AR8216_PORT_CPU
&& port
!= 6) {
689 /*hw limitation:if configure mac when there is traffic,
690 port MAC may work abnormal. Need disable lan&wan mac at fisrt*/
691 ar8xxx_write(priv
, AR8327_REG_PORT_STATUS(port
), 0);
693 t
|= AR8216_PORT_STATUS_FLOW_CONTROL
;
694 ar8xxx_write(priv
, AR8327_REG_PORT_STATUS(port
), t
);
696 ar8xxx_write(priv
, AR8327_REG_PORT_STATUS(port
), t
);
699 ar8xxx_write(priv
, AR8327_REG_PORT_HEADER(port
), 0);
701 ar8xxx_write(priv
, AR8327_REG_PORT_VLAN0(port
), 0);
703 t
= AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH
<< AR8327_PORT_VLAN1_OUT_MODE_S
;
704 ar8xxx_write(priv
, AR8327_REG_PORT_VLAN1(port
), t
);
706 t
= AR8327_PORT_LOOKUP_LEARN
;
707 t
|= AR8216_PORT_STATE_FORWARD
<< AR8327_PORT_LOOKUP_STATE_S
;
708 ar8xxx_write(priv
, AR8327_REG_PORT_LOOKUP(port
), t
);
712 ar8327_read_port_status(struct ar8xxx_priv
*priv
, int port
)
716 t
= ar8xxx_read(priv
, AR8327_REG_PORT_STATUS(port
));
717 /* map the flow control autoneg result bits to the flow control bits
718 * used in forced mode to allow ar8216_read_port_link detect
719 * flow control properly if autoneg is used
721 if (t
& AR8216_PORT_STATUS_LINK_UP
&&
722 t
& AR8216_PORT_STATUS_LINK_AUTO
) {
723 t
&= ~(AR8216_PORT_STATUS_TXFLOW
| AR8216_PORT_STATUS_RXFLOW
);
724 if (t
& AR8327_PORT_STATUS_TXFLOW_AUTO
)
725 t
|= AR8216_PORT_STATUS_TXFLOW
;
726 if (t
& AR8327_PORT_STATUS_RXFLOW_AUTO
)
727 t
|= AR8216_PORT_STATUS_RXFLOW
;
734 ar8327_read_port_eee_status(struct ar8xxx_priv
*priv
, int port
)
739 if (port
>= priv
->dev
.ports
)
742 if (port
== 0 || port
== 6)
747 /* EEE Ability Auto-negotiation Result */
748 t
= ar8xxx_phy_mmd_read(priv
, phy
, 0x7, 0x8000);
750 return mmd_eee_adv_to_ethtool_adv_t(t
);
754 ar8327_atu_flush(struct ar8xxx_priv
*priv
)
758 ret
= ar8216_wait_bit(priv
, AR8327_REG_ATU_FUNC
,
759 AR8327_ATU_FUNC_BUSY
, 0);
761 ar8xxx_write(priv
, AR8327_REG_ATU_FUNC
,
762 AR8327_ATU_FUNC_OP_FLUSH
|
763 AR8327_ATU_FUNC_BUSY
);
769 ar8327_atu_flush_port(struct ar8xxx_priv
*priv
, int port
)
774 ret
= ar8216_wait_bit(priv
, AR8327_REG_ATU_FUNC
,
775 AR8327_ATU_FUNC_BUSY
, 0);
777 t
= (port
<< AR8327_ATU_PORT_NUM_S
);
778 t
|= AR8327_ATU_FUNC_OP_FLUSH_PORT
;
779 t
|= AR8327_ATU_FUNC_BUSY
;
780 ar8xxx_write(priv
, AR8327_REG_ATU_FUNC
, t
);
787 ar8327_get_port_igmp(struct ar8xxx_priv
*priv
, int port
)
789 u32 fwd_ctrl
, frame_ack
;
791 fwd_ctrl
= (BIT(port
) << AR8327_FWD_CTRL1_IGMP_S
);
792 frame_ack
= ((AR8327_FRAME_ACK_CTRL_IGMP_MLD
|
793 AR8327_FRAME_ACK_CTRL_IGMP_JOIN
|
794 AR8327_FRAME_ACK_CTRL_IGMP_LEAVE
) <<
795 AR8327_FRAME_ACK_CTRL_S(port
));
797 return (ar8xxx_read(priv
, AR8327_REG_FWD_CTRL1
) &
798 fwd_ctrl
) == fwd_ctrl
&&
799 (ar8xxx_read(priv
, AR8327_REG_FRAME_ACK_CTRL(port
)) &
800 frame_ack
) == frame_ack
;
804 ar8327_set_port_igmp(struct ar8xxx_priv
*priv
, int port
, int enable
)
806 int reg_frame_ack
= AR8327_REG_FRAME_ACK_CTRL(port
);
807 u32 val_frame_ack
= (AR8327_FRAME_ACK_CTRL_IGMP_MLD
|
808 AR8327_FRAME_ACK_CTRL_IGMP_JOIN
|
809 AR8327_FRAME_ACK_CTRL_IGMP_LEAVE
) <<
810 AR8327_FRAME_ACK_CTRL_S(port
);
813 ar8xxx_rmw(priv
, AR8327_REG_FWD_CTRL1
,
814 BIT(port
) << AR8327_FWD_CTRL1_MC_FLOOD_S
,
815 BIT(port
) << AR8327_FWD_CTRL1_IGMP_S
);
816 ar8xxx_reg_set(priv
, reg_frame_ack
, val_frame_ack
);
818 ar8xxx_rmw(priv
, AR8327_REG_FWD_CTRL1
,
819 BIT(port
) << AR8327_FWD_CTRL1_IGMP_S
,
820 BIT(port
) << AR8327_FWD_CTRL1_MC_FLOOD_S
);
821 ar8xxx_reg_clear(priv
, reg_frame_ack
, val_frame_ack
);
826 ar8327_vtu_op(struct ar8xxx_priv
*priv
, u32 op
, u32 val
)
828 if (ar8216_wait_bit(priv
, AR8327_REG_VTU_FUNC1
,
829 AR8327_VTU_FUNC1_BUSY
, 0))
832 if ((op
& AR8327_VTU_FUNC1_OP
) == AR8327_VTU_FUNC1_OP_LOAD
)
833 ar8xxx_write(priv
, AR8327_REG_VTU_FUNC0
, val
);
835 op
|= AR8327_VTU_FUNC1_BUSY
;
836 ar8xxx_write(priv
, AR8327_REG_VTU_FUNC1
, op
);
840 ar8327_vtu_flush(struct ar8xxx_priv
*priv
)
842 ar8327_vtu_op(priv
, AR8327_VTU_FUNC1_OP_FLUSH
, 0);
846 ar8327_vtu_load_vlan(struct ar8xxx_priv
*priv
, u32 vid
, u32 port_mask
)
852 op
= AR8327_VTU_FUNC1_OP_LOAD
| (vid
<< AR8327_VTU_FUNC1_VID_S
);
853 val
= AR8327_VTU_FUNC0_VALID
| AR8327_VTU_FUNC0_IVL
;
854 for (i
= 0; i
< AR8327_NUM_PORTS
; i
++) {
857 if ((port_mask
& BIT(i
)) == 0)
858 mode
= AR8327_VTU_FUNC0_EG_MODE_NOT
;
859 else if (priv
->vlan
== 0)
860 mode
= AR8327_VTU_FUNC0_EG_MODE_KEEP
;
861 else if ((priv
->vlan_tagged
& BIT(i
)) || (priv
->vlan_id
[priv
->pvid
[i
]] != vid
))
862 mode
= AR8327_VTU_FUNC0_EG_MODE_TAG
;
864 mode
= AR8327_VTU_FUNC0_EG_MODE_UNTAG
;
866 val
|= mode
<< AR8327_VTU_FUNC0_EG_MODE_S(i
);
868 ar8327_vtu_op(priv
, op
, val
);
872 ar8327_setup_port(struct ar8xxx_priv
*priv
, int port
, u32 members
)
876 u32 pvid
= priv
->vlan_id
[priv
->pvid
[port
]];
879 egress
= AR8327_PORT_VLAN1_OUT_MODE_UNMOD
;
880 ingress
= AR8216_IN_SECURE
;
882 egress
= AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH
;
883 ingress
= AR8216_IN_PORT_ONLY
;
886 t
= pvid
<< AR8327_PORT_VLAN0_DEF_SVID_S
;
887 t
|= pvid
<< AR8327_PORT_VLAN0_DEF_CVID_S
;
888 if (priv
->vlan
&& priv
->port_vlan_prio
[port
]) {
889 u32 prio
= priv
->port_vlan_prio
[port
];
891 t
|= prio
<< AR8327_PORT_VLAN0_DEF_SPRI_S
;
892 t
|= prio
<< AR8327_PORT_VLAN0_DEF_CPRI_S
;
894 ar8xxx_write(priv
, AR8327_REG_PORT_VLAN0(port
), t
);
896 t
= AR8327_PORT_VLAN1_PORT_VLAN_PROP
;
897 t
|= egress
<< AR8327_PORT_VLAN1_OUT_MODE_S
;
898 if (priv
->vlan
&& priv
->port_vlan_prio
[port
])
899 t
|= AR8327_PORT_VLAN1_VLAN_PRI_PROP
;
901 ar8xxx_write(priv
, AR8327_REG_PORT_VLAN1(port
), t
);
904 t
|= AR8327_PORT_LOOKUP_LEARN
;
905 t
|= ingress
<< AR8327_PORT_LOOKUP_IN_MODE_S
;
906 t
|= AR8216_PORT_STATE_FORWARD
<< AR8327_PORT_LOOKUP_STATE_S
;
907 ar8xxx_write(priv
, AR8327_REG_PORT_LOOKUP(port
), t
);
911 ar8327_sw_get_ports(struct switch_dev
*dev
, struct switch_val
*val
)
913 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
914 u8 ports
= priv
->vlan_table
[val
->port_vlan
];
918 for (i
= 0; i
< dev
->ports
; i
++) {
919 struct switch_port
*p
;
921 if (!(ports
& (1 << i
)))
924 p
= &val
->value
.ports
[val
->len
++];
926 if ((priv
->vlan_tagged
& (1 << i
)) || (priv
->pvid
[i
] != val
->port_vlan
))
927 p
->flags
= (1 << SWITCH_PORT_FLAG_TAGGED
);
935 ar8327_sw_set_ports(struct switch_dev
*dev
, struct switch_val
*val
)
937 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
938 u8
*vt
= &priv
->vlan_table
[val
->port_vlan
];
942 for (i
= 0; i
< val
->len
; i
++) {
943 struct switch_port
*p
= &val
->value
.ports
[i
];
945 if (p
->flags
& (1 << SWITCH_PORT_FLAG_TAGGED
)) {
946 if (val
->port_vlan
== priv
->pvid
[p
->id
]) {
947 priv
->vlan_tagged
|= (1 << p
->id
);
950 priv
->vlan_tagged
&= ~(1 << p
->id
);
951 priv
->pvid
[p
->id
] = val
->port_vlan
;
960 ar8327_set_mirror_regs(struct ar8xxx_priv
*priv
)
964 /* reset all mirror registers */
965 ar8xxx_rmw(priv
, AR8327_REG_FWD_CTRL0
,
966 AR8327_FWD_CTRL0_MIRROR_PORT
,
967 (0xF << AR8327_FWD_CTRL0_MIRROR_PORT_S
));
968 for (port
= 0; port
< AR8327_NUM_PORTS
; port
++) {
969 ar8xxx_reg_clear(priv
, AR8327_REG_PORT_LOOKUP(port
),
970 AR8327_PORT_LOOKUP_ING_MIRROR_EN
);
972 ar8xxx_reg_clear(priv
, AR8327_REG_PORT_HOL_CTRL1(port
),
973 AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN
);
976 /* now enable mirroring if necessary */
977 if (priv
->source_port
>= AR8327_NUM_PORTS
||
978 priv
->monitor_port
>= AR8327_NUM_PORTS
||
979 priv
->source_port
== priv
->monitor_port
) {
983 ar8xxx_rmw(priv
, AR8327_REG_FWD_CTRL0
,
984 AR8327_FWD_CTRL0_MIRROR_PORT
,
985 (priv
->monitor_port
<< AR8327_FWD_CTRL0_MIRROR_PORT_S
));
988 ar8xxx_reg_set(priv
, AR8327_REG_PORT_LOOKUP(priv
->source_port
),
989 AR8327_PORT_LOOKUP_ING_MIRROR_EN
);
992 ar8xxx_reg_set(priv
, AR8327_REG_PORT_HOL_CTRL1(priv
->source_port
),
993 AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN
);
997 ar8327_sw_set_eee(struct switch_dev
*dev
,
998 const struct switch_attr
*attr
,
999 struct switch_val
*val
)
1001 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1002 struct ar8327_data
*data
= priv
->chip_data
;
1003 int port
= val
->port_vlan
;
1006 if (port
>= dev
->ports
)
1008 if (port
== 0 || port
== 6)
1013 data
->eee
[phy
] = !!(val
->value
.i
);
1019 ar8327_sw_get_eee(struct switch_dev
*dev
,
1020 const struct switch_attr
*attr
,
1021 struct switch_val
*val
)
1023 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1024 const struct ar8327_data
*data
= priv
->chip_data
;
1025 int port
= val
->port_vlan
;
1028 if (port
>= dev
->ports
)
1030 if (port
== 0 || port
== 6)
1035 val
->value
.i
= data
->eee
[phy
];
1041 ar8327_wait_atu_ready(struct ar8xxx_priv
*priv
, u16 r2
, u16 r1
)
1045 while (ar8xxx_mii_read32(priv
, r2
, r1
) & AR8327_ATU_FUNC_BUSY
&& --timeout
) {
1051 pr_err("ar8327: timeout waiting for atu to become ready\n");
1054 static void ar8327_get_arl_entry(struct ar8xxx_priv
*priv
,
1055 struct arl_entry
*a
, u32
*status
, enum arl_op op
)
1057 struct mii_bus
*bus
= priv
->mii_bus
;
1059 u16 r1_data0
, r1_data1
, r1_data2
, r1_func
;
1060 u32 t
, val0
, val1
, val2
;
1063 split_addr(AR8327_REG_ATU_DATA0
, &r1_data0
, &r2
, &page
);
1066 r1_data1
= (AR8327_REG_ATU_DATA1
>> 1) & 0x1e;
1067 r1_data2
= (AR8327_REG_ATU_DATA2
>> 1) & 0x1e;
1068 r1_func
= (AR8327_REG_ATU_FUNC
>> 1) & 0x1e;
1071 case AR8XXX_ARL_INITIALIZE
:
1072 /* all ATU registers are on the same page
1073 * therefore set page only once
1075 bus
->write(bus
, 0x18, 0, page
);
1076 wait_for_page_switch();
1078 ar8327_wait_atu_ready(priv
, r2
, r1_func
);
1080 ar8xxx_mii_write32(priv
, r2
, r1_data0
, 0);
1081 ar8xxx_mii_write32(priv
, r2
, r1_data1
, 0);
1082 ar8xxx_mii_write32(priv
, r2
, r1_data2
, 0);
1084 case AR8XXX_ARL_GET_NEXT
:
1085 ar8xxx_mii_write32(priv
, r2
, r1_func
,
1086 AR8327_ATU_FUNC_OP_GET_NEXT
|
1087 AR8327_ATU_FUNC_BUSY
);
1088 ar8327_wait_atu_ready(priv
, r2
, r1_func
);
1090 val0
= ar8xxx_mii_read32(priv
, r2
, r1_data0
);
1091 val1
= ar8xxx_mii_read32(priv
, r2
, r1_data1
);
1092 val2
= ar8xxx_mii_read32(priv
, r2
, r1_data2
);
1094 *status
= val2
& AR8327_ATU_STATUS
;
1099 t
= AR8327_ATU_PORT0
;
1100 while (!(val1
& t
) && ++i
< AR8327_NUM_PORTS
)
1104 a
->mac
[0] = (val0
& AR8327_ATU_ADDR0
) >> AR8327_ATU_ADDR0_S
;
1105 a
->mac
[1] = (val0
& AR8327_ATU_ADDR1
) >> AR8327_ATU_ADDR1_S
;
1106 a
->mac
[2] = (val0
& AR8327_ATU_ADDR2
) >> AR8327_ATU_ADDR2_S
;
1107 a
->mac
[3] = (val0
& AR8327_ATU_ADDR3
) >> AR8327_ATU_ADDR3_S
;
1108 a
->mac
[4] = (val1
& AR8327_ATU_ADDR4
) >> AR8327_ATU_ADDR4_S
;
1109 a
->mac
[5] = (val1
& AR8327_ATU_ADDR5
) >> AR8327_ATU_ADDR5_S
;
1115 ar8327_sw_hw_apply(struct switch_dev
*dev
)
1117 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1118 const struct ar8327_data
*data
= priv
->chip_data
;
1121 ret
= ar8xxx_sw_hw_apply(dev
);
1125 for (i
=0; i
< AR8XXX_NUM_PHYS
; i
++) {
1127 ar8xxx_reg_clear(priv
, AR8327_REG_EEE_CTRL
,
1128 AR8327_EEE_CTRL_DISABLE_PHY(i
));
1130 ar8xxx_reg_set(priv
, AR8327_REG_EEE_CTRL
,
1131 AR8327_EEE_CTRL_DISABLE_PHY(i
));
1138 ar8327_sw_get_port_igmp_snooping(struct switch_dev
*dev
,
1139 const struct switch_attr
*attr
,
1140 struct switch_val
*val
)
1142 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1143 int port
= val
->port_vlan
;
1145 if (port
>= dev
->ports
)
1148 mutex_lock(&priv
->reg_mutex
);
1149 val
->value
.i
= ar8327_get_port_igmp(priv
, port
);
1150 mutex_unlock(&priv
->reg_mutex
);
1156 ar8327_sw_set_port_igmp_snooping(struct switch_dev
*dev
,
1157 const struct switch_attr
*attr
,
1158 struct switch_val
*val
)
1160 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1161 int port
= val
->port_vlan
;
1163 if (port
>= dev
->ports
)
1166 mutex_lock(&priv
->reg_mutex
);
1167 ar8327_set_port_igmp(priv
, port
, val
->value
.i
);
1168 mutex_unlock(&priv
->reg_mutex
);
1174 ar8327_sw_get_igmp_snooping(struct switch_dev
*dev
,
1175 const struct switch_attr
*attr
,
1176 struct switch_val
*val
)
1180 for (port
= 0; port
< dev
->ports
; port
++) {
1181 val
->port_vlan
= port
;
1182 if (ar8327_sw_get_port_igmp_snooping(dev
, attr
, val
) ||
1191 ar8327_sw_set_igmp_snooping(struct switch_dev
*dev
,
1192 const struct switch_attr
*attr
,
1193 struct switch_val
*val
)
1197 for (port
= 0; port
< dev
->ports
; port
++) {
1198 val
->port_vlan
= port
;
1199 if (ar8327_sw_set_port_igmp_snooping(dev
, attr
, val
))
1207 ar8327_sw_get_igmp_v3(struct switch_dev
*dev
,
1208 const struct switch_attr
*attr
,
1209 struct switch_val
*val
)
1211 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1214 mutex_lock(&priv
->reg_mutex
);
1215 val_reg
= ar8xxx_read(priv
, AR8327_REG_FRAME_ACK_CTRL1
);
1216 val
->value
.i
= ((val_reg
& AR8327_FRAME_ACK_CTRL_IGMP_V3_EN
) != 0);
1217 mutex_unlock(&priv
->reg_mutex
);
1223 ar8327_sw_set_igmp_v3(struct switch_dev
*dev
,
1224 const struct switch_attr
*attr
,
1225 struct switch_val
*val
)
1227 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1229 mutex_lock(&priv
->reg_mutex
);
1231 ar8xxx_reg_set(priv
, AR8327_REG_FRAME_ACK_CTRL1
,
1232 AR8327_FRAME_ACK_CTRL_IGMP_V3_EN
);
1234 ar8xxx_reg_clear(priv
, AR8327_REG_FRAME_ACK_CTRL1
,
1235 AR8327_FRAME_ACK_CTRL_IGMP_V3_EN
);
1236 mutex_unlock(&priv
->reg_mutex
);
1242 ar8327_sw_set_port_vlan_prio(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1243 struct switch_val
*val
)
1245 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1246 int port
= val
->port_vlan
;
1248 if (port
>= dev
->ports
)
1250 if (port
== 0 || port
== 6)
1252 if (val
->value
.i
< 0 || val
->value
.i
> 7)
1255 priv
->port_vlan_prio
[port
] = val
->value
.i
;
1261 ar8327_sw_get_port_vlan_prio(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1262 struct switch_val
*val
)
1264 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1265 int port
= val
->port_vlan
;
1267 val
->value
.i
= priv
->port_vlan_prio
[port
];
1272 static const struct switch_attr ar8327_sw_attr_globals
[] = {
1274 .type
= SWITCH_TYPE_INT
,
1275 .name
= "enable_vlan",
1276 .description
= "Enable VLAN mode",
1277 .set
= ar8xxx_sw_set_vlan
,
1278 .get
= ar8xxx_sw_get_vlan
,
1282 .type
= SWITCH_TYPE_NOVAL
,
1283 .name
= "reset_mibs",
1284 .description
= "Reset all MIB counters",
1285 .set
= ar8xxx_sw_set_reset_mibs
,
1288 .type
= SWITCH_TYPE_INT
,
1289 .name
= "enable_mirror_rx",
1290 .description
= "Enable mirroring of RX packets",
1291 .set
= ar8xxx_sw_set_mirror_rx_enable
,
1292 .get
= ar8xxx_sw_get_mirror_rx_enable
,
1296 .type
= SWITCH_TYPE_INT
,
1297 .name
= "enable_mirror_tx",
1298 .description
= "Enable mirroring of TX packets",
1299 .set
= ar8xxx_sw_set_mirror_tx_enable
,
1300 .get
= ar8xxx_sw_get_mirror_tx_enable
,
1304 .type
= SWITCH_TYPE_INT
,
1305 .name
= "mirror_monitor_port",
1306 .description
= "Mirror monitor port",
1307 .set
= ar8xxx_sw_set_mirror_monitor_port
,
1308 .get
= ar8xxx_sw_get_mirror_monitor_port
,
1309 .max
= AR8327_NUM_PORTS
- 1
1312 .type
= SWITCH_TYPE_INT
,
1313 .name
= "mirror_source_port",
1314 .description
= "Mirror source port",
1315 .set
= ar8xxx_sw_set_mirror_source_port
,
1316 .get
= ar8xxx_sw_get_mirror_source_port
,
1317 .max
= AR8327_NUM_PORTS
- 1
1320 .type
= SWITCH_TYPE_INT
,
1321 .name
= "arl_age_time",
1322 .description
= "ARL age time (secs)",
1323 .set
= ar8xxx_sw_set_arl_age_time
,
1324 .get
= ar8xxx_sw_get_arl_age_time
,
1327 .type
= SWITCH_TYPE_STRING
,
1328 .name
= "arl_table",
1329 .description
= "Get ARL table",
1331 .get
= ar8xxx_sw_get_arl_table
,
1334 .type
= SWITCH_TYPE_NOVAL
,
1335 .name
= "flush_arl_table",
1336 .description
= "Flush ARL table",
1337 .set
= ar8xxx_sw_set_flush_arl_table
,
1340 .type
= SWITCH_TYPE_INT
,
1341 .name
= "igmp_snooping",
1342 .description
= "Enable IGMP Snooping",
1343 .set
= ar8327_sw_set_igmp_snooping
,
1344 .get
= ar8327_sw_get_igmp_snooping
,
1348 .type
= SWITCH_TYPE_INT
,
1350 .description
= "Enable IGMPv3 support",
1351 .set
= ar8327_sw_set_igmp_v3
,
1352 .get
= ar8327_sw_get_igmp_v3
,
1357 static const struct switch_attr ar8327_sw_attr_port
[] = {
1359 .type
= SWITCH_TYPE_NOVAL
,
1360 .name
= "reset_mib",
1361 .description
= "Reset single port MIB counters",
1362 .set
= ar8xxx_sw_set_port_reset_mib
,
1365 .type
= SWITCH_TYPE_STRING
,
1367 .description
= "Get port's MIB counters",
1369 .get
= ar8xxx_sw_get_port_mib
,
1372 .type
= SWITCH_TYPE_INT
,
1373 .name
= "enable_eee",
1374 .description
= "Enable EEE PHY sleep mode",
1375 .set
= ar8327_sw_set_eee
,
1376 .get
= ar8327_sw_get_eee
,
1380 .type
= SWITCH_TYPE_NOVAL
,
1381 .name
= "flush_arl_table",
1382 .description
= "Flush port's ARL table entries",
1383 .set
= ar8xxx_sw_set_flush_port_arl_table
,
1386 .type
= SWITCH_TYPE_INT
,
1387 .name
= "igmp_snooping",
1388 .description
= "Enable port's IGMP Snooping",
1389 .set
= ar8327_sw_set_port_igmp_snooping
,
1390 .get
= ar8327_sw_get_port_igmp_snooping
,
1394 .type
= SWITCH_TYPE_INT
,
1395 .name
= "vlan_prio",
1396 .description
= "Port VLAN default priority (VLAN PCP) (0-7)",
1397 .set
= ar8327_sw_set_port_vlan_prio
,
1398 .get
= ar8327_sw_get_port_vlan_prio
,
1403 static const struct switch_dev_ops ar8327_sw_ops
= {
1405 .attr
= ar8327_sw_attr_globals
,
1406 .n_attr
= ARRAY_SIZE(ar8327_sw_attr_globals
),
1409 .attr
= ar8327_sw_attr_port
,
1410 .n_attr
= ARRAY_SIZE(ar8327_sw_attr_port
),
1413 .attr
= ar8xxx_sw_attr_vlan
,
1414 .n_attr
= ARRAY_SIZE(ar8xxx_sw_attr_vlan
),
1416 .get_port_pvid
= ar8xxx_sw_get_pvid
,
1417 .set_port_pvid
= ar8xxx_sw_set_pvid
,
1418 .get_vlan_ports
= ar8327_sw_get_ports
,
1419 .set_vlan_ports
= ar8327_sw_set_ports
,
1420 .apply_config
= ar8327_sw_hw_apply
,
1421 .reset_switch
= ar8xxx_sw_reset_switch
,
1422 .get_port_link
= ar8xxx_sw_get_port_link
,
1423 /* The following op is disabled as it hogs the CPU and degrades performance.
1424 An implementation has been attempted in 4d8a66d but reading MIB data is slow
1427 The high CPU load has been traced down to the ar8xxx_reg_wait() call in
1428 ar8xxx_mib_op(), which has to usleep_range() till the MIB busy flag set by
1429 the request to update the MIB counter is cleared. */
1431 .get_port_stats
= ar8xxx_sw_get_port_stats
,
1435 const struct ar8xxx_chip ar8327_chip
= {
1436 .caps
= AR8XXX_CAP_GIGE
| AR8XXX_CAP_MIB_COUNTERS
,
1437 .config_at_probe
= true,
1438 .mii_lo_first
= true,
1440 .name
= "Atheros AR8327",
1441 .ports
= AR8327_NUM_PORTS
,
1442 .vlans
= AR8X16_MAX_VLANS
,
1443 .swops
= &ar8327_sw_ops
,
1445 .reg_port_stats_start
= 0x1000,
1446 .reg_port_stats_length
= 0x100,
1447 .reg_arl_ctrl
= AR8327_REG_ARL_CTRL
,
1449 .hw_init
= ar8327_hw_init
,
1450 .cleanup
= ar8327_cleanup
,
1451 .init_globals
= ar8327_init_globals
,
1452 .init_port
= ar8327_init_port
,
1453 .setup_port
= ar8327_setup_port
,
1454 .read_port_status
= ar8327_read_port_status
,
1455 .read_port_eee_status
= ar8327_read_port_eee_status
,
1456 .atu_flush
= ar8327_atu_flush
,
1457 .atu_flush_port
= ar8327_atu_flush_port
,
1458 .vtu_flush
= ar8327_vtu_flush
,
1459 .vtu_load_vlan
= ar8327_vtu_load_vlan
,
1460 .phy_fixup
= ar8327_phy_fixup
,
1461 .set_mirror_regs
= ar8327_set_mirror_regs
,
1462 .get_arl_entry
= ar8327_get_arl_entry
,
1463 .sw_hw_apply
= ar8327_sw_hw_apply
,
1465 .num_mibs
= ARRAY_SIZE(ar8236_mibs
),
1466 .mib_decs
= ar8236_mibs
,
1467 .mib_func
= AR8327_REG_MIB_FUNC
1470 const struct ar8xxx_chip ar8337_chip
= {
1471 .caps
= AR8XXX_CAP_GIGE
| AR8XXX_CAP_MIB_COUNTERS
,
1472 .config_at_probe
= true,
1473 .mii_lo_first
= true,
1475 .name
= "Atheros AR8337",
1476 .ports
= AR8327_NUM_PORTS
,
1477 .vlans
= AR8X16_MAX_VLANS
,
1478 .swops
= &ar8327_sw_ops
,
1480 .reg_port_stats_start
= 0x1000,
1481 .reg_port_stats_length
= 0x100,
1482 .reg_arl_ctrl
= AR8327_REG_ARL_CTRL
,
1484 .hw_init
= ar8327_hw_init
,
1485 .cleanup
= ar8327_cleanup
,
1486 .init_globals
= ar8327_init_globals
,
1487 .init_port
= ar8327_init_port
,
1488 .setup_port
= ar8327_setup_port
,
1489 .read_port_status
= ar8327_read_port_status
,
1490 .read_port_eee_status
= ar8327_read_port_eee_status
,
1491 .atu_flush
= ar8327_atu_flush
,
1492 .atu_flush_port
= ar8327_atu_flush_port
,
1493 .vtu_flush
= ar8327_vtu_flush
,
1494 .vtu_load_vlan
= ar8327_vtu_load_vlan
,
1495 .phy_fixup
= ar8327_phy_fixup
,
1496 .set_mirror_regs
= ar8327_set_mirror_regs
,
1497 .get_arl_entry
= ar8327_get_arl_entry
,
1498 .sw_hw_apply
= ar8327_sw_hw_apply
,
1500 .num_mibs
= ARRAY_SIZE(ar8236_mibs
),
1501 .mib_decs
= ar8236_mibs
,
1502 .mib_func
= AR8327_REG_MIB_FUNC