2 * ar8327.c: AR8216 switch driver
4 * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
18 #include <linux/list.h>
19 #include <linux/bitops.h>
20 #include <linux/switch.h>
21 #include <linux/delay.h>
22 #include <linux/phy.h>
23 #include <linux/lockdep.h>
24 #include <linux/ar8216_platform.h>
25 #include <linux/workqueue.h>
26 #include <linux/of_device.h>
27 #include <linux/leds.h>
28 #include <linux/mdio.h>
33 extern const struct ar8xxx_mib_desc ar8236_mibs
[39];
34 extern const struct switch_attr ar8xxx_sw_attr_vlan
[1];
37 ar8327_get_pad_cfg(struct ar8327_pad_cfg
*cfg
)
49 case AR8327_PAD_MAC2MAC_MII
:
50 t
= AR8327_PAD_MAC_MII_EN
;
52 t
|= AR8327_PAD_MAC_MII_RXCLK_SEL
;
54 t
|= AR8327_PAD_MAC_MII_TXCLK_SEL
;
57 case AR8327_PAD_MAC2MAC_GMII
:
58 t
= AR8327_PAD_MAC_GMII_EN
;
60 t
|= AR8327_PAD_MAC_GMII_RXCLK_SEL
;
62 t
|= AR8327_PAD_MAC_GMII_TXCLK_SEL
;
65 case AR8327_PAD_MAC_SGMII
:
66 t
= AR8327_PAD_SGMII_EN
;
69 * WAR for the QUalcomm Atheros AP136 board.
70 * It seems that RGMII TX/RX delay settings needs to be
71 * applied for SGMII mode as well, The ethernet is not
72 * reliable without this.
74 t
|= cfg
->txclk_delay_sel
<< AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S
;
75 t
|= cfg
->rxclk_delay_sel
<< AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S
;
76 if (cfg
->rxclk_delay_en
)
77 t
|= AR8327_PAD_RGMII_RXCLK_DELAY_EN
;
78 if (cfg
->txclk_delay_en
)
79 t
|= AR8327_PAD_RGMII_TXCLK_DELAY_EN
;
81 if (cfg
->sgmii_delay_en
)
82 t
|= AR8327_PAD_SGMII_DELAY_EN
;
86 case AR8327_PAD_MAC2PHY_MII
:
87 t
= AR8327_PAD_PHY_MII_EN
;
89 t
|= AR8327_PAD_PHY_MII_RXCLK_SEL
;
91 t
|= AR8327_PAD_PHY_MII_TXCLK_SEL
;
94 case AR8327_PAD_MAC2PHY_GMII
:
95 t
= AR8327_PAD_PHY_GMII_EN
;
96 if (cfg
->pipe_rxclk_sel
)
97 t
|= AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL
;
99 t
|= AR8327_PAD_PHY_GMII_RXCLK_SEL
;
101 t
|= AR8327_PAD_PHY_GMII_TXCLK_SEL
;
104 case AR8327_PAD_MAC_RGMII
:
105 t
= AR8327_PAD_RGMII_EN
;
106 t
|= cfg
->txclk_delay_sel
<< AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S
;
107 t
|= cfg
->rxclk_delay_sel
<< AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S
;
108 if (cfg
->rxclk_delay_en
)
109 t
|= AR8327_PAD_RGMII_RXCLK_DELAY_EN
;
110 if (cfg
->txclk_delay_en
)
111 t
|= AR8327_PAD_RGMII_TXCLK_DELAY_EN
;
114 case AR8327_PAD_PHY_GMII
:
115 t
= AR8327_PAD_PHYX_GMII_EN
;
118 case AR8327_PAD_PHY_RGMII
:
119 t
= AR8327_PAD_PHYX_RGMII_EN
;
122 case AR8327_PAD_PHY_MII
:
123 t
= AR8327_PAD_PHYX_MII_EN
;
131 ar8327_phy_fixup(struct ar8xxx_priv
*priv
, int phy
)
133 switch (priv
->chip_rev
) {
135 /* For 100M waveform */
136 ar8xxx_phy_dbg_write(priv
, phy
, 0, 0x02ea);
137 /* Turn on Gigabit clock */
138 ar8xxx_phy_dbg_write(priv
, phy
, 0x3d, 0x68a0);
142 ar8xxx_phy_mmd_write(priv
, phy
, 0x7, 0x3c, 0x0);
145 ar8xxx_phy_mmd_write(priv
, phy
, 0x3, 0x800d, 0x803f);
146 ar8xxx_phy_dbg_write(priv
, phy
, 0x3d, 0x6860);
147 ar8xxx_phy_dbg_write(priv
, phy
, 0x5, 0x2c46);
148 ar8xxx_phy_dbg_write(priv
, phy
, 0x3c, 0x6000);
154 ar8327_get_port_init_status(struct ar8327_port_cfg
*cfg
)
158 if (!cfg
->force_link
)
159 return AR8216_PORT_STATUS_LINK_AUTO
;
161 t
= AR8216_PORT_STATUS_TXMAC
| AR8216_PORT_STATUS_RXMAC
;
162 t
|= cfg
->duplex
? AR8216_PORT_STATUS_DUPLEX
: 0;
163 t
|= cfg
->rxpause
? AR8216_PORT_STATUS_RXFLOW
: 0;
164 t
|= cfg
->txpause
? AR8216_PORT_STATUS_TXFLOW
: 0;
166 switch (cfg
->speed
) {
167 case AR8327_PORT_SPEED_10
:
168 t
|= AR8216_PORT_SPEED_10M
;
170 case AR8327_PORT_SPEED_100
:
171 t
|= AR8216_PORT_SPEED_100M
;
173 case AR8327_PORT_SPEED_1000
:
174 t
|= AR8216_PORT_SPEED_1000M
;
181 #define AR8327_LED_ENTRY(_num, _reg, _shift) \
182 [_num] = { .reg = (_reg), .shift = (_shift) }
184 static const struct ar8327_led_entry
185 ar8327_led_map
[AR8327_NUM_LEDS
] = {
186 AR8327_LED_ENTRY(AR8327_LED_PHY0_0
, 0, 14),
187 AR8327_LED_ENTRY(AR8327_LED_PHY0_1
, 1, 14),
188 AR8327_LED_ENTRY(AR8327_LED_PHY0_2
, 2, 14),
190 AR8327_LED_ENTRY(AR8327_LED_PHY1_0
, 3, 8),
191 AR8327_LED_ENTRY(AR8327_LED_PHY1_1
, 3, 10),
192 AR8327_LED_ENTRY(AR8327_LED_PHY1_2
, 3, 12),
194 AR8327_LED_ENTRY(AR8327_LED_PHY2_0
, 3, 14),
195 AR8327_LED_ENTRY(AR8327_LED_PHY2_1
, 3, 16),
196 AR8327_LED_ENTRY(AR8327_LED_PHY2_2
, 3, 18),
198 AR8327_LED_ENTRY(AR8327_LED_PHY3_0
, 3, 20),
199 AR8327_LED_ENTRY(AR8327_LED_PHY3_1
, 3, 22),
200 AR8327_LED_ENTRY(AR8327_LED_PHY3_2
, 3, 24),
202 AR8327_LED_ENTRY(AR8327_LED_PHY4_0
, 0, 30),
203 AR8327_LED_ENTRY(AR8327_LED_PHY4_1
, 1, 30),
204 AR8327_LED_ENTRY(AR8327_LED_PHY4_2
, 2, 30),
208 ar8327_set_led_pattern(struct ar8xxx_priv
*priv
, unsigned int led_num
,
209 enum ar8327_led_pattern pattern
)
211 const struct ar8327_led_entry
*entry
;
213 entry
= &ar8327_led_map
[led_num
];
214 ar8xxx_rmw(priv
, AR8327_REG_LED_CTRL(entry
->reg
),
215 (3 << entry
->shift
), pattern
<< entry
->shift
);
219 ar8327_led_work_func(struct work_struct
*work
)
221 struct ar8327_led
*aled
;
224 aled
= container_of(work
, struct ar8327_led
, led_work
);
226 spin_lock(&aled
->lock
);
227 pattern
= aled
->pattern
;
228 spin_unlock(&aled
->lock
);
230 ar8327_set_led_pattern(aled
->sw_priv
, aled
->led_num
,
235 ar8327_led_schedule_change(struct ar8327_led
*aled
, u8 pattern
)
237 if (aled
->pattern
== pattern
)
240 aled
->pattern
= pattern
;
241 schedule_work(&aled
->led_work
);
244 static inline struct ar8327_led
*
245 led_cdev_to_ar8327_led(struct led_classdev
*led_cdev
)
247 return container_of(led_cdev
, struct ar8327_led
, cdev
);
251 ar8327_led_blink_set(struct led_classdev
*led_cdev
,
252 unsigned long *delay_on
,
253 unsigned long *delay_off
)
255 struct ar8327_led
*aled
= led_cdev_to_ar8327_led(led_cdev
);
257 if (*delay_on
== 0 && *delay_off
== 0) {
262 if (*delay_on
!= 125 || *delay_off
!= 125) {
264 * The hardware only supports blinking at 4Hz. Fall back
265 * to software implementation in other cases.
270 spin_lock(&aled
->lock
);
272 aled
->enable_hw_mode
= false;
273 ar8327_led_schedule_change(aled
, AR8327_LED_PATTERN_BLINK
);
275 spin_unlock(&aled
->lock
);
281 ar8327_led_set_brightness(struct led_classdev
*led_cdev
,
282 enum led_brightness brightness
)
284 struct ar8327_led
*aled
= led_cdev_to_ar8327_led(led_cdev
);
288 active
= (brightness
!= LED_OFF
);
289 active
^= aled
->active_low
;
291 pattern
= (active
) ? AR8327_LED_PATTERN_ON
:
292 AR8327_LED_PATTERN_OFF
;
294 spin_lock(&aled
->lock
);
296 aled
->enable_hw_mode
= false;
297 ar8327_led_schedule_change(aled
, pattern
);
299 spin_unlock(&aled
->lock
);
303 ar8327_led_enable_hw_mode_show(struct device
*dev
,
304 struct device_attribute
*attr
,
307 struct led_classdev
*led_cdev
= dev_get_drvdata(dev
);
308 struct ar8327_led
*aled
= led_cdev_to_ar8327_led(led_cdev
);
311 spin_lock(&aled
->lock
);
312 ret
+= sprintf(buf
, "%d\n", aled
->enable_hw_mode
);
313 spin_unlock(&aled
->lock
);
319 ar8327_led_enable_hw_mode_store(struct device
*dev
,
320 struct device_attribute
*attr
,
324 struct led_classdev
*led_cdev
= dev_get_drvdata(dev
);
325 struct ar8327_led
*aled
= led_cdev_to_ar8327_led(led_cdev
);
330 ret
= kstrtou8(buf
, 10, &value
);
334 spin_lock(&aled
->lock
);
336 aled
->enable_hw_mode
= !!value
;
337 if (aled
->enable_hw_mode
)
338 pattern
= AR8327_LED_PATTERN_RULE
;
340 pattern
= AR8327_LED_PATTERN_OFF
;
342 ar8327_led_schedule_change(aled
, pattern
);
344 spin_unlock(&aled
->lock
);
349 static DEVICE_ATTR(enable_hw_mode
, S_IRUGO
| S_IWUSR
,
350 ar8327_led_enable_hw_mode_show
,
351 ar8327_led_enable_hw_mode_store
);
354 ar8327_led_register(struct ar8327_led
*aled
)
358 ret
= led_classdev_register(NULL
, &aled
->cdev
);
362 if (aled
->mode
== AR8327_LED_MODE_HW
) {
363 ret
= device_create_file(aled
->cdev
.dev
,
364 &dev_attr_enable_hw_mode
);
372 led_classdev_unregister(&aled
->cdev
);
377 ar8327_led_unregister(struct ar8327_led
*aled
)
379 if (aled
->mode
== AR8327_LED_MODE_HW
)
380 device_remove_file(aled
->cdev
.dev
, &dev_attr_enable_hw_mode
);
382 led_classdev_unregister(&aled
->cdev
);
383 cancel_work_sync(&aled
->led_work
);
387 ar8327_led_create(struct ar8xxx_priv
*priv
,
388 const struct ar8327_led_info
*led_info
)
390 struct ar8327_data
*data
= priv
->chip_data
;
391 struct ar8327_led
*aled
;
394 if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS
))
400 if (led_info
->led_num
>= AR8327_NUM_LEDS
)
403 aled
= kzalloc(sizeof(*aled
) + strlen(led_info
->name
) + 1,
408 aled
->sw_priv
= priv
;
409 aled
->led_num
= led_info
->led_num
;
410 aled
->active_low
= led_info
->active_low
;
411 aled
->mode
= led_info
->mode
;
413 if (aled
->mode
== AR8327_LED_MODE_HW
)
414 aled
->enable_hw_mode
= true;
416 aled
->name
= (char *)(aled
+ 1);
417 strcpy(aled
->name
, led_info
->name
);
419 aled
->cdev
.name
= aled
->name
;
420 aled
->cdev
.brightness_set
= ar8327_led_set_brightness
;
421 aled
->cdev
.blink_set
= ar8327_led_blink_set
;
422 aled
->cdev
.default_trigger
= led_info
->default_trigger
;
424 spin_lock_init(&aled
->lock
);
425 mutex_init(&aled
->mutex
);
426 INIT_WORK(&aled
->led_work
, ar8327_led_work_func
);
428 ret
= ar8327_led_register(aled
);
432 data
->leds
[data
->num_leds
++] = aled
;
442 ar8327_led_destroy(struct ar8327_led
*aled
)
444 ar8327_led_unregister(aled
);
449 ar8327_leds_init(struct ar8xxx_priv
*priv
)
451 struct ar8327_data
*data
= priv
->chip_data
;
454 if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS
))
457 for (i
= 0; i
< data
->num_leds
; i
++) {
458 struct ar8327_led
*aled
;
460 aled
= data
->leds
[i
];
462 if (aled
->enable_hw_mode
)
463 aled
->pattern
= AR8327_LED_PATTERN_RULE
;
465 aled
->pattern
= AR8327_LED_PATTERN_OFF
;
467 ar8327_set_led_pattern(priv
, aled
->led_num
, aled
->pattern
);
472 ar8327_leds_cleanup(struct ar8xxx_priv
*priv
)
474 struct ar8327_data
*data
= priv
->chip_data
;
477 if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS
))
480 for (i
= 0; i
< data
->num_leds
; i
++) {
481 struct ar8327_led
*aled
;
483 aled
= data
->leds
[i
];
484 ar8327_led_destroy(aled
);
491 ar8327_hw_config_pdata(struct ar8xxx_priv
*priv
,
492 struct ar8327_platform_data
*pdata
)
494 struct ar8327_led_cfg
*led_cfg
;
495 struct ar8327_data
*data
= priv
->chip_data
;
502 priv
->get_port_link
= pdata
->get_port_link
;
504 data
->port0_status
= ar8327_get_port_init_status(&pdata
->port0_cfg
);
505 data
->port6_status
= ar8327_get_port_init_status(&pdata
->port6_cfg
);
507 t
= ar8327_get_pad_cfg(pdata
->pad0_cfg
);
508 if (chip_is_ar8337(priv
) && !pdata
->pad0_cfg
->mac06_exchange_dis
)
509 t
|= AR8337_PAD_MAC06_EXCHANGE_EN
;
510 ar8xxx_write(priv
, AR8327_REG_PAD0_MODE
, t
);
512 t
= ar8327_get_pad_cfg(pdata
->pad5_cfg
);
513 ar8xxx_write(priv
, AR8327_REG_PAD5_MODE
, t
);
514 t
= ar8327_get_pad_cfg(pdata
->pad6_cfg
);
515 ar8xxx_write(priv
, AR8327_REG_PAD6_MODE
, t
);
517 pos
= ar8xxx_read(priv
, AR8327_REG_POWER_ON_STRIP
);
520 led_cfg
= pdata
->led_cfg
;
522 if (led_cfg
->open_drain
)
523 new_pos
|= AR8327_POWER_ON_STRIP_LED_OPEN_EN
;
525 new_pos
&= ~AR8327_POWER_ON_STRIP_LED_OPEN_EN
;
527 ar8xxx_write(priv
, AR8327_REG_LED_CTRL0
, led_cfg
->led_ctrl0
);
528 ar8xxx_write(priv
, AR8327_REG_LED_CTRL1
, led_cfg
->led_ctrl1
);
529 ar8xxx_write(priv
, AR8327_REG_LED_CTRL2
, led_cfg
->led_ctrl2
);
530 ar8xxx_write(priv
, AR8327_REG_LED_CTRL3
, led_cfg
->led_ctrl3
);
533 new_pos
|= AR8327_POWER_ON_STRIP_POWER_ON_SEL
;
536 if (pdata
->sgmii_cfg
) {
537 t
= pdata
->sgmii_cfg
->sgmii_ctrl
;
538 if (priv
->chip_rev
== 1)
539 t
|= AR8327_SGMII_CTRL_EN_PLL
|
540 AR8327_SGMII_CTRL_EN_RX
|
541 AR8327_SGMII_CTRL_EN_TX
;
543 t
&= ~(AR8327_SGMII_CTRL_EN_PLL
|
544 AR8327_SGMII_CTRL_EN_RX
|
545 AR8327_SGMII_CTRL_EN_TX
);
547 ar8xxx_write(priv
, AR8327_REG_SGMII_CTRL
, t
);
549 if (pdata
->sgmii_cfg
->serdes_aen
)
550 new_pos
&= ~AR8327_POWER_ON_STRIP_SERDES_AEN
;
552 new_pos
|= AR8327_POWER_ON_STRIP_SERDES_AEN
;
555 ar8xxx_write(priv
, AR8327_REG_POWER_ON_STRIP
, new_pos
);
557 if (pdata
->leds
&& pdata
->num_leds
) {
560 data
->leds
= kzalloc(pdata
->num_leds
* sizeof(void *),
565 for (i
= 0; i
< pdata
->num_leds
; i
++)
566 ar8327_led_create(priv
, &pdata
->leds
[i
]);
574 ar8327_hw_config_of(struct ar8xxx_priv
*priv
, struct device_node
*np
)
576 struct ar8327_data
*data
= priv
->chip_data
;
581 paddr
= of_get_property(np
, "qca,ar8327-initvals", &len
);
582 if (!paddr
|| len
< (2 * sizeof(*paddr
)))
585 len
/= sizeof(*paddr
);
587 for (i
= 0; i
< len
- 1; i
+= 2) {
591 reg
= be32_to_cpup(paddr
+ i
);
592 val
= be32_to_cpup(paddr
+ i
+ 1);
595 case AR8327_REG_PORT_STATUS(0):
596 data
->port0_status
= val
;
598 case AR8327_REG_PORT_STATUS(6):
599 data
->port6_status
= val
;
602 ar8xxx_write(priv
, reg
, val
);
611 ar8327_hw_config_of(struct ar8xxx_priv
*priv
, struct device_node
*np
)
618 ar8327_hw_init(struct ar8xxx_priv
*priv
)
622 priv
->chip_data
= kzalloc(sizeof(struct ar8327_data
), GFP_KERNEL
);
623 if (!priv
->chip_data
)
626 if (priv
->phy
->dev
.of_node
)
627 ret
= ar8327_hw_config_of(priv
, priv
->phy
->dev
.of_node
);
629 ret
= ar8327_hw_config_pdata(priv
,
630 priv
->phy
->dev
.platform_data
);
635 ar8327_leds_init(priv
);
637 ar8xxx_phy_init(priv
);
643 ar8327_cleanup(struct ar8xxx_priv
*priv
)
645 ar8327_leds_cleanup(priv
);
649 ar8327_init_globals(struct ar8xxx_priv
*priv
)
651 struct ar8327_data
*data
= priv
->chip_data
;
655 /* enable CPU port and disable mirror port */
656 t
= AR8327_FWD_CTRL0_CPU_PORT_EN
|
657 AR8327_FWD_CTRL0_MIRROR_PORT
;
658 ar8xxx_write(priv
, AR8327_REG_FWD_CTRL0
, t
);
660 /* forward multicast and broadcast frames to CPU */
661 t
= (AR8327_PORTS_ALL
<< AR8327_FWD_CTRL1_UC_FLOOD_S
) |
662 (AR8327_PORTS_ALL
<< AR8327_FWD_CTRL1_MC_FLOOD_S
) |
663 (AR8327_PORTS_ALL
<< AR8327_FWD_CTRL1_BC_FLOOD_S
);
664 ar8xxx_write(priv
, AR8327_REG_FWD_CTRL1
, t
);
666 /* enable jumbo frames */
667 ar8xxx_rmw(priv
, AR8327_REG_MAX_FRAME_SIZE
,
668 AR8327_MAX_FRAME_SIZE_MTU
, 9018 + 8 + 2);
670 /* Enable MIB counters */
671 ar8xxx_reg_set(priv
, AR8327_REG_MODULE_EN
,
672 AR8327_MODULE_EN_MIB
);
674 /* Disable EEE on all phy's due to stability issues */
675 for (i
= 0; i
< AR8XXX_NUM_PHYS
; i
++)
676 data
->eee
[i
] = false;
680 ar8327_init_port(struct ar8xxx_priv
*priv
, int port
)
682 struct ar8327_data
*data
= priv
->chip_data
;
685 if (port
== AR8216_PORT_CPU
)
686 t
= data
->port0_status
;
688 t
= data
->port6_status
;
690 t
= AR8216_PORT_STATUS_LINK_AUTO
;
692 ar8xxx_write(priv
, AR8327_REG_PORT_STATUS(port
), t
);
693 ar8xxx_write(priv
, AR8327_REG_PORT_HEADER(port
), 0);
695 t
= 1 << AR8327_PORT_VLAN0_DEF_SVID_S
;
696 t
|= 1 << AR8327_PORT_VLAN0_DEF_CVID_S
;
697 ar8xxx_write(priv
, AR8327_REG_PORT_VLAN0(port
), t
);
699 t
= AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH
<< AR8327_PORT_VLAN1_OUT_MODE_S
;
700 ar8xxx_write(priv
, AR8327_REG_PORT_VLAN1(port
), t
);
702 t
= AR8327_PORT_LOOKUP_LEARN
;
703 t
|= AR8216_PORT_STATE_FORWARD
<< AR8327_PORT_LOOKUP_STATE_S
;
704 ar8xxx_write(priv
, AR8327_REG_PORT_LOOKUP(port
), t
);
708 ar8327_read_port_status(struct ar8xxx_priv
*priv
, int port
)
712 t
= ar8xxx_read(priv
, AR8327_REG_PORT_STATUS(port
));
713 /* map the flow control autoneg result bits to the flow control bits
714 * used in forced mode to allow ar8216_read_port_link detect
715 * flow control properly if autoneg is used
717 if (t
& AR8216_PORT_STATUS_LINK_UP
&&
718 t
& AR8216_PORT_STATUS_LINK_AUTO
) {
719 t
&= ~(AR8216_PORT_STATUS_TXFLOW
| AR8216_PORT_STATUS_RXFLOW
);
720 if (t
& AR8327_PORT_STATUS_TXFLOW_AUTO
)
721 t
|= AR8216_PORT_STATUS_TXFLOW
;
722 if (t
& AR8327_PORT_STATUS_RXFLOW_AUTO
)
723 t
|= AR8216_PORT_STATUS_RXFLOW
;
730 ar8327_read_port_eee_status(struct ar8xxx_priv
*priv
, int port
)
735 if (port
>= priv
->dev
.ports
)
738 if (port
== 0 || port
== 6)
743 /* EEE Ability Auto-negotiation Result */
744 t
= ar8xxx_phy_mmd_read(priv
, phy
, 0x7, 0x8000);
746 return mmd_eee_adv_to_ethtool_adv_t(t
);
750 ar8327_atu_flush(struct ar8xxx_priv
*priv
)
754 ret
= ar8216_wait_bit(priv
, AR8327_REG_ATU_FUNC
,
755 AR8327_ATU_FUNC_BUSY
, 0);
757 ar8xxx_write(priv
, AR8327_REG_ATU_FUNC
,
758 AR8327_ATU_FUNC_OP_FLUSH
|
759 AR8327_ATU_FUNC_BUSY
);
765 ar8327_atu_flush_port(struct ar8xxx_priv
*priv
, int port
)
770 ret
= ar8216_wait_bit(priv
, AR8327_REG_ATU_FUNC
,
771 AR8327_ATU_FUNC_BUSY
, 0);
773 t
= (port
<< AR8327_ATU_PORT_NUM_S
);
774 t
|= AR8327_ATU_FUNC_OP_FLUSH_PORT
;
775 t
|= AR8327_ATU_FUNC_BUSY
;
776 ar8xxx_write(priv
, AR8327_REG_ATU_FUNC
, t
);
783 ar8327_get_port_igmp(struct ar8xxx_priv
*priv
, int port
)
785 u32 fwd_ctrl
, frame_ack
;
787 fwd_ctrl
= (BIT(port
) << AR8327_FWD_CTRL1_IGMP_S
);
788 frame_ack
= ((AR8327_FRAME_ACK_CTRL_IGMP_MLD
|
789 AR8327_FRAME_ACK_CTRL_IGMP_JOIN
|
790 AR8327_FRAME_ACK_CTRL_IGMP_LEAVE
) <<
791 AR8327_FRAME_ACK_CTRL_S(port
));
793 return (ar8xxx_read(priv
, AR8327_REG_FWD_CTRL1
) &
794 fwd_ctrl
) == fwd_ctrl
&&
795 (ar8xxx_read(priv
, AR8327_REG_FRAME_ACK_CTRL(port
)) &
796 frame_ack
) == frame_ack
;
800 ar8327_set_port_igmp(struct ar8xxx_priv
*priv
, int port
, int enable
)
802 int reg_frame_ack
= AR8327_REG_FRAME_ACK_CTRL(port
);
803 u32 val_frame_ack
= (AR8327_FRAME_ACK_CTRL_IGMP_MLD
|
804 AR8327_FRAME_ACK_CTRL_IGMP_JOIN
|
805 AR8327_FRAME_ACK_CTRL_IGMP_LEAVE
) <<
806 AR8327_FRAME_ACK_CTRL_S(port
);
809 ar8xxx_rmw(priv
, AR8327_REG_FWD_CTRL1
,
810 BIT(port
) << AR8327_FWD_CTRL1_MC_FLOOD_S
,
811 BIT(port
) << AR8327_FWD_CTRL1_IGMP_S
);
812 ar8xxx_reg_set(priv
, reg_frame_ack
, val_frame_ack
);
814 ar8xxx_rmw(priv
, AR8327_REG_FWD_CTRL1
,
815 BIT(port
) << AR8327_FWD_CTRL1_IGMP_S
,
816 BIT(port
) << AR8327_FWD_CTRL1_MC_FLOOD_S
);
817 ar8xxx_reg_clear(priv
, reg_frame_ack
, val_frame_ack
);
822 ar8327_vtu_op(struct ar8xxx_priv
*priv
, u32 op
, u32 val
)
824 if (ar8216_wait_bit(priv
, AR8327_REG_VTU_FUNC1
,
825 AR8327_VTU_FUNC1_BUSY
, 0))
828 if ((op
& AR8327_VTU_FUNC1_OP
) == AR8327_VTU_FUNC1_OP_LOAD
)
829 ar8xxx_write(priv
, AR8327_REG_VTU_FUNC0
, val
);
831 op
|= AR8327_VTU_FUNC1_BUSY
;
832 ar8xxx_write(priv
, AR8327_REG_VTU_FUNC1
, op
);
836 ar8327_vtu_flush(struct ar8xxx_priv
*priv
)
838 ar8327_vtu_op(priv
, AR8327_VTU_FUNC1_OP_FLUSH
, 0);
842 ar8327_vtu_load_vlan(struct ar8xxx_priv
*priv
, u32 vid
, u32 port_mask
)
848 op
= AR8327_VTU_FUNC1_OP_LOAD
| (vid
<< AR8327_VTU_FUNC1_VID_S
);
849 val
= AR8327_VTU_FUNC0_VALID
| AR8327_VTU_FUNC0_IVL
;
850 for (i
= 0; i
< AR8327_NUM_PORTS
; i
++) {
853 if ((port_mask
& BIT(i
)) == 0)
854 mode
= AR8327_VTU_FUNC0_EG_MODE_NOT
;
855 else if (priv
->vlan
== 0)
856 mode
= AR8327_VTU_FUNC0_EG_MODE_KEEP
;
857 else if ((priv
->vlan_tagged
& BIT(i
)) || (priv
->vlan_id
[priv
->pvid
[i
]] != vid
))
858 mode
= AR8327_VTU_FUNC0_EG_MODE_TAG
;
860 mode
= AR8327_VTU_FUNC0_EG_MODE_UNTAG
;
862 val
|= mode
<< AR8327_VTU_FUNC0_EG_MODE_S(i
);
864 ar8327_vtu_op(priv
, op
, val
);
868 ar8327_setup_port(struct ar8xxx_priv
*priv
, int port
, u32 members
)
872 u32 pvid
= priv
->vlan_id
[priv
->pvid
[port
]];
875 egress
= AR8327_PORT_VLAN1_OUT_MODE_UNMOD
;
876 ingress
= AR8216_IN_SECURE
;
878 egress
= AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH
;
879 ingress
= AR8216_IN_PORT_ONLY
;
882 t
= pvid
<< AR8327_PORT_VLAN0_DEF_SVID_S
;
883 t
|= pvid
<< AR8327_PORT_VLAN0_DEF_CVID_S
;
884 ar8xxx_write(priv
, AR8327_REG_PORT_VLAN0(port
), t
);
886 t
= AR8327_PORT_VLAN1_PORT_VLAN_PROP
;
887 t
|= egress
<< AR8327_PORT_VLAN1_OUT_MODE_S
;
888 ar8xxx_write(priv
, AR8327_REG_PORT_VLAN1(port
), t
);
891 t
|= AR8327_PORT_LOOKUP_LEARN
;
892 t
|= ingress
<< AR8327_PORT_LOOKUP_IN_MODE_S
;
893 t
|= AR8216_PORT_STATE_FORWARD
<< AR8327_PORT_LOOKUP_STATE_S
;
894 ar8xxx_write(priv
, AR8327_REG_PORT_LOOKUP(port
), t
);
898 ar8327_sw_get_ports(struct switch_dev
*dev
, struct switch_val
*val
)
900 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
901 u8 ports
= priv
->vlan_table
[val
->port_vlan
];
905 for (i
= 0; i
< dev
->ports
; i
++) {
906 struct switch_port
*p
;
908 if (!(ports
& (1 << i
)))
911 p
= &val
->value
.ports
[val
->len
++];
913 if ((priv
->vlan_tagged
& (1 << i
)) || (priv
->pvid
[i
] != val
->port_vlan
))
914 p
->flags
= (1 << SWITCH_PORT_FLAG_TAGGED
);
922 ar8327_sw_set_ports(struct switch_dev
*dev
, struct switch_val
*val
)
924 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
925 u8
*vt
= &priv
->vlan_table
[val
->port_vlan
];
929 for (i
= 0; i
< val
->len
; i
++) {
930 struct switch_port
*p
= &val
->value
.ports
[i
];
932 if (p
->flags
& (1 << SWITCH_PORT_FLAG_TAGGED
)) {
933 if (val
->port_vlan
== priv
->pvid
[p
->id
]) {
934 priv
->vlan_tagged
|= (1 << p
->id
);
937 priv
->vlan_tagged
&= ~(1 << p
->id
);
938 priv
->pvid
[p
->id
] = val
->port_vlan
;
947 ar8327_set_mirror_regs(struct ar8xxx_priv
*priv
)
951 /* reset all mirror registers */
952 ar8xxx_rmw(priv
, AR8327_REG_FWD_CTRL0
,
953 AR8327_FWD_CTRL0_MIRROR_PORT
,
954 (0xF << AR8327_FWD_CTRL0_MIRROR_PORT_S
));
955 for (port
= 0; port
< AR8327_NUM_PORTS
; port
++) {
956 ar8xxx_reg_clear(priv
, AR8327_REG_PORT_LOOKUP(port
),
957 AR8327_PORT_LOOKUP_ING_MIRROR_EN
);
959 ar8xxx_reg_clear(priv
, AR8327_REG_PORT_HOL_CTRL1(port
),
960 AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN
);
963 /* now enable mirroring if necessary */
964 if (priv
->source_port
>= AR8327_NUM_PORTS
||
965 priv
->monitor_port
>= AR8327_NUM_PORTS
||
966 priv
->source_port
== priv
->monitor_port
) {
970 ar8xxx_rmw(priv
, AR8327_REG_FWD_CTRL0
,
971 AR8327_FWD_CTRL0_MIRROR_PORT
,
972 (priv
->monitor_port
<< AR8327_FWD_CTRL0_MIRROR_PORT_S
));
975 ar8xxx_reg_set(priv
, AR8327_REG_PORT_LOOKUP(priv
->source_port
),
976 AR8327_PORT_LOOKUP_ING_MIRROR_EN
);
979 ar8xxx_reg_set(priv
, AR8327_REG_PORT_HOL_CTRL1(priv
->source_port
),
980 AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN
);
984 ar8327_sw_set_eee(struct switch_dev
*dev
,
985 const struct switch_attr
*attr
,
986 struct switch_val
*val
)
988 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
989 struct ar8327_data
*data
= priv
->chip_data
;
990 int port
= val
->port_vlan
;
993 if (port
>= dev
->ports
)
995 if (port
== 0 || port
== 6)
1000 data
->eee
[phy
] = !!(val
->value
.i
);
1006 ar8327_sw_get_eee(struct switch_dev
*dev
,
1007 const struct switch_attr
*attr
,
1008 struct switch_val
*val
)
1010 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1011 const struct ar8327_data
*data
= priv
->chip_data
;
1012 int port
= val
->port_vlan
;
1015 if (port
>= dev
->ports
)
1017 if (port
== 0 || port
== 6)
1022 val
->value
.i
= data
->eee
[phy
];
1028 ar8327_wait_atu_ready(struct ar8xxx_priv
*priv
, u16 r2
, u16 r1
)
1032 while (ar8xxx_mii_read32(priv
, r2
, r1
) & AR8327_ATU_FUNC_BUSY
&& --timeout
)
1036 pr_err("ar8327: timeout waiting for atu to become ready\n");
1039 static void ar8327_get_arl_entry(struct ar8xxx_priv
*priv
,
1040 struct arl_entry
*a
, u32
*status
, enum arl_op op
)
1042 struct mii_bus
*bus
= priv
->mii_bus
;
1044 u16 r1_data0
, r1_data1
, r1_data2
, r1_func
;
1045 u32 t
, val0
, val1
, val2
;
1048 split_addr(AR8327_REG_ATU_DATA0
, &r1_data0
, &r2
, &page
);
1051 r1_data1
= (AR8327_REG_ATU_DATA1
>> 1) & 0x1e;
1052 r1_data2
= (AR8327_REG_ATU_DATA2
>> 1) & 0x1e;
1053 r1_func
= (AR8327_REG_ATU_FUNC
>> 1) & 0x1e;
1056 case AR8XXX_ARL_INITIALIZE
:
1057 /* all ATU registers are on the same page
1058 * therefore set page only once
1060 bus
->write(bus
, 0x18, 0, page
);
1061 wait_for_page_switch();
1063 ar8327_wait_atu_ready(priv
, r2
, r1_func
);
1065 ar8xxx_mii_write32(priv
, r2
, r1_data0
, 0);
1066 ar8xxx_mii_write32(priv
, r2
, r1_data1
, 0);
1067 ar8xxx_mii_write32(priv
, r2
, r1_data2
, 0);
1069 case AR8XXX_ARL_GET_NEXT
:
1070 ar8xxx_mii_write32(priv
, r2
, r1_func
,
1071 AR8327_ATU_FUNC_OP_GET_NEXT
|
1072 AR8327_ATU_FUNC_BUSY
);
1073 ar8327_wait_atu_ready(priv
, r2
, r1_func
);
1075 val0
= ar8xxx_mii_read32(priv
, r2
, r1_data0
);
1076 val1
= ar8xxx_mii_read32(priv
, r2
, r1_data1
);
1077 val2
= ar8xxx_mii_read32(priv
, r2
, r1_data2
);
1079 *status
= val2
& AR8327_ATU_STATUS
;
1084 t
= AR8327_ATU_PORT0
;
1085 while (!(val1
& t
) && ++i
< AR8327_NUM_PORTS
)
1089 a
->mac
[0] = (val0
& AR8327_ATU_ADDR0
) >> AR8327_ATU_ADDR0_S
;
1090 a
->mac
[1] = (val0
& AR8327_ATU_ADDR1
) >> AR8327_ATU_ADDR1_S
;
1091 a
->mac
[2] = (val0
& AR8327_ATU_ADDR2
) >> AR8327_ATU_ADDR2_S
;
1092 a
->mac
[3] = (val0
& AR8327_ATU_ADDR3
) >> AR8327_ATU_ADDR3_S
;
1093 a
->mac
[4] = (val1
& AR8327_ATU_ADDR4
) >> AR8327_ATU_ADDR4_S
;
1094 a
->mac
[5] = (val1
& AR8327_ATU_ADDR5
) >> AR8327_ATU_ADDR5_S
;
1100 ar8327_sw_hw_apply(struct switch_dev
*dev
)
1102 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1103 const struct ar8327_data
*data
= priv
->chip_data
;
1106 ret
= ar8xxx_sw_hw_apply(dev
);
1110 for (i
=0; i
< AR8XXX_NUM_PHYS
; i
++) {
1112 ar8xxx_reg_clear(priv
, AR8327_REG_EEE_CTRL
,
1113 AR8327_EEE_CTRL_DISABLE_PHY(i
));
1115 ar8xxx_reg_set(priv
, AR8327_REG_EEE_CTRL
,
1116 AR8327_EEE_CTRL_DISABLE_PHY(i
));
1123 ar8327_sw_get_port_igmp_snooping(struct switch_dev
*dev
,
1124 const struct switch_attr
*attr
,
1125 struct switch_val
*val
)
1127 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1128 int port
= val
->port_vlan
;
1130 if (port
>= dev
->ports
)
1133 mutex_lock(&priv
->reg_mutex
);
1134 val
->value
.i
= ar8327_get_port_igmp(priv
, port
);
1135 mutex_unlock(&priv
->reg_mutex
);
1141 ar8327_sw_set_port_igmp_snooping(struct switch_dev
*dev
,
1142 const struct switch_attr
*attr
,
1143 struct switch_val
*val
)
1145 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1146 int port
= val
->port_vlan
;
1148 if (port
>= dev
->ports
)
1151 mutex_lock(&priv
->reg_mutex
);
1152 ar8327_set_port_igmp(priv
, port
, val
->value
.i
);
1153 mutex_unlock(&priv
->reg_mutex
);
1159 ar8327_sw_get_igmp_snooping(struct switch_dev
*dev
,
1160 const struct switch_attr
*attr
,
1161 struct switch_val
*val
)
1165 for (port
= 0; port
< dev
->ports
; port
++) {
1166 val
->port_vlan
= port
;
1167 if (ar8327_sw_get_port_igmp_snooping(dev
, attr
, val
) ||
1176 ar8327_sw_set_igmp_snooping(struct switch_dev
*dev
,
1177 const struct switch_attr
*attr
,
1178 struct switch_val
*val
)
1182 for (port
= 0; port
< dev
->ports
; port
++) {
1183 val
->port_vlan
= port
;
1184 if (ar8327_sw_set_port_igmp_snooping(dev
, attr
, val
))
1192 ar8327_sw_get_igmp_v3(struct switch_dev
*dev
,
1193 const struct switch_attr
*attr
,
1194 struct switch_val
*val
)
1196 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1199 mutex_lock(&priv
->reg_mutex
);
1200 val_reg
= ar8xxx_read(priv
, AR8327_REG_FRAME_ACK_CTRL1
);
1201 val
->value
.i
= ((val_reg
& AR8327_FRAME_ACK_CTRL_IGMP_V3_EN
) != 0);
1202 mutex_unlock(&priv
->reg_mutex
);
1208 ar8327_sw_set_igmp_v3(struct switch_dev
*dev
,
1209 const struct switch_attr
*attr
,
1210 struct switch_val
*val
)
1212 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1214 mutex_lock(&priv
->reg_mutex
);
1216 ar8xxx_reg_set(priv
, AR8327_REG_FRAME_ACK_CTRL1
,
1217 AR8327_FRAME_ACK_CTRL_IGMP_V3_EN
);
1219 ar8xxx_reg_clear(priv
, AR8327_REG_FRAME_ACK_CTRL1
,
1220 AR8327_FRAME_ACK_CTRL_IGMP_V3_EN
);
1221 mutex_unlock(&priv
->reg_mutex
);
1226 static const struct switch_attr ar8327_sw_attr_globals
[] = {
1228 .type
= SWITCH_TYPE_INT
,
1229 .name
= "enable_vlan",
1230 .description
= "Enable VLAN mode",
1231 .set
= ar8xxx_sw_set_vlan
,
1232 .get
= ar8xxx_sw_get_vlan
,
1236 .type
= SWITCH_TYPE_NOVAL
,
1237 .name
= "reset_mibs",
1238 .description
= "Reset all MIB counters",
1239 .set
= ar8xxx_sw_set_reset_mibs
,
1242 .type
= SWITCH_TYPE_INT
,
1243 .name
= "enable_mirror_rx",
1244 .description
= "Enable mirroring of RX packets",
1245 .set
= ar8xxx_sw_set_mirror_rx_enable
,
1246 .get
= ar8xxx_sw_get_mirror_rx_enable
,
1250 .type
= SWITCH_TYPE_INT
,
1251 .name
= "enable_mirror_tx",
1252 .description
= "Enable mirroring of TX packets",
1253 .set
= ar8xxx_sw_set_mirror_tx_enable
,
1254 .get
= ar8xxx_sw_get_mirror_tx_enable
,
1258 .type
= SWITCH_TYPE_INT
,
1259 .name
= "mirror_monitor_port",
1260 .description
= "Mirror monitor port",
1261 .set
= ar8xxx_sw_set_mirror_monitor_port
,
1262 .get
= ar8xxx_sw_get_mirror_monitor_port
,
1263 .max
= AR8327_NUM_PORTS
- 1
1266 .type
= SWITCH_TYPE_INT
,
1267 .name
= "mirror_source_port",
1268 .description
= "Mirror source port",
1269 .set
= ar8xxx_sw_set_mirror_source_port
,
1270 .get
= ar8xxx_sw_get_mirror_source_port
,
1271 .max
= AR8327_NUM_PORTS
- 1
1274 .type
= SWITCH_TYPE_INT
,
1275 .name
= "arl_age_time",
1276 .description
= "ARL age time (secs)",
1277 .set
= ar8xxx_sw_set_arl_age_time
,
1278 .get
= ar8xxx_sw_get_arl_age_time
,
1281 .type
= SWITCH_TYPE_STRING
,
1282 .name
= "arl_table",
1283 .description
= "Get ARL table",
1285 .get
= ar8xxx_sw_get_arl_table
,
1288 .type
= SWITCH_TYPE_NOVAL
,
1289 .name
= "flush_arl_table",
1290 .description
= "Flush ARL table",
1291 .set
= ar8xxx_sw_set_flush_arl_table
,
1294 .type
= SWITCH_TYPE_INT
,
1295 .name
= "igmp_snooping",
1296 .description
= "Enable IGMP Snooping",
1297 .set
= ar8327_sw_set_igmp_snooping
,
1298 .get
= ar8327_sw_get_igmp_snooping
,
1302 .type
= SWITCH_TYPE_INT
,
1304 .description
= "Enable IGMPv3 support",
1305 .set
= ar8327_sw_set_igmp_v3
,
1306 .get
= ar8327_sw_get_igmp_v3
,
1311 static const struct switch_attr ar8327_sw_attr_port
[] = {
1313 .type
= SWITCH_TYPE_NOVAL
,
1314 .name
= "reset_mib",
1315 .description
= "Reset single port MIB counters",
1316 .set
= ar8xxx_sw_set_port_reset_mib
,
1319 .type
= SWITCH_TYPE_STRING
,
1321 .description
= "Get port's MIB counters",
1323 .get
= ar8xxx_sw_get_port_mib
,
1326 .type
= SWITCH_TYPE_INT
,
1327 .name
= "enable_eee",
1328 .description
= "Enable EEE PHY sleep mode",
1329 .set
= ar8327_sw_set_eee
,
1330 .get
= ar8327_sw_get_eee
,
1334 .type
= SWITCH_TYPE_NOVAL
,
1335 .name
= "flush_arl_table",
1336 .description
= "Flush port's ARL table entries",
1337 .set
= ar8xxx_sw_set_flush_port_arl_table
,
1340 .type
= SWITCH_TYPE_INT
,
1341 .name
= "igmp_snooping",
1342 .description
= "Enable port's IGMP Snooping",
1343 .set
= ar8327_sw_set_port_igmp_snooping
,
1344 .get
= ar8327_sw_get_port_igmp_snooping
,
1349 static const struct switch_dev_ops ar8327_sw_ops
= {
1351 .attr
= ar8327_sw_attr_globals
,
1352 .n_attr
= ARRAY_SIZE(ar8327_sw_attr_globals
),
1355 .attr
= ar8327_sw_attr_port
,
1356 .n_attr
= ARRAY_SIZE(ar8327_sw_attr_port
),
1359 .attr
= ar8xxx_sw_attr_vlan
,
1360 .n_attr
= ARRAY_SIZE(ar8xxx_sw_attr_vlan
),
1362 .get_port_pvid
= ar8xxx_sw_get_pvid
,
1363 .set_port_pvid
= ar8xxx_sw_set_pvid
,
1364 .get_vlan_ports
= ar8327_sw_get_ports
,
1365 .set_vlan_ports
= ar8327_sw_set_ports
,
1366 .apply_config
= ar8327_sw_hw_apply
,
1367 .reset_switch
= ar8xxx_sw_reset_switch
,
1368 .get_port_link
= ar8xxx_sw_get_port_link
,
1371 const struct ar8xxx_chip ar8327_chip
= {
1372 .caps
= AR8XXX_CAP_GIGE
| AR8XXX_CAP_MIB_COUNTERS
,
1373 .config_at_probe
= true,
1374 .mii_lo_first
= true,
1376 .name
= "Atheros AR8327",
1377 .ports
= AR8327_NUM_PORTS
,
1378 .vlans
= AR8X16_MAX_VLANS
,
1379 .swops
= &ar8327_sw_ops
,
1381 .reg_port_stats_start
= 0x1000,
1382 .reg_port_stats_length
= 0x100,
1383 .reg_arl_ctrl
= AR8327_REG_ARL_CTRL
,
1385 .hw_init
= ar8327_hw_init
,
1386 .cleanup
= ar8327_cleanup
,
1387 .init_globals
= ar8327_init_globals
,
1388 .init_port
= ar8327_init_port
,
1389 .setup_port
= ar8327_setup_port
,
1390 .read_port_status
= ar8327_read_port_status
,
1391 .read_port_eee_status
= ar8327_read_port_eee_status
,
1392 .atu_flush
= ar8327_atu_flush
,
1393 .atu_flush_port
= ar8327_atu_flush_port
,
1394 .vtu_flush
= ar8327_vtu_flush
,
1395 .vtu_load_vlan
= ar8327_vtu_load_vlan
,
1396 .phy_fixup
= ar8327_phy_fixup
,
1397 .set_mirror_regs
= ar8327_set_mirror_regs
,
1398 .get_arl_entry
= ar8327_get_arl_entry
,
1399 .sw_hw_apply
= ar8327_sw_hw_apply
,
1401 .num_mibs
= ARRAY_SIZE(ar8236_mibs
),
1402 .mib_decs
= ar8236_mibs
,
1403 .mib_func
= AR8327_REG_MIB_FUNC
1406 const struct ar8xxx_chip ar8337_chip
= {
1407 .caps
= AR8XXX_CAP_GIGE
| AR8XXX_CAP_MIB_COUNTERS
,
1408 .config_at_probe
= true,
1409 .mii_lo_first
= true,
1411 .name
= "Atheros AR8337",
1412 .ports
= AR8327_NUM_PORTS
,
1413 .vlans
= AR8X16_MAX_VLANS
,
1414 .swops
= &ar8327_sw_ops
,
1416 .reg_port_stats_start
= 0x1000,
1417 .reg_port_stats_length
= 0x100,
1418 .reg_arl_ctrl
= AR8327_REG_ARL_CTRL
,
1420 .hw_init
= ar8327_hw_init
,
1421 .cleanup
= ar8327_cleanup
,
1422 .init_globals
= ar8327_init_globals
,
1423 .init_port
= ar8327_init_port
,
1424 .setup_port
= ar8327_setup_port
,
1425 .read_port_status
= ar8327_read_port_status
,
1426 .read_port_eee_status
= ar8327_read_port_eee_status
,
1427 .atu_flush
= ar8327_atu_flush
,
1428 .atu_flush_port
= ar8327_atu_flush_port
,
1429 .vtu_flush
= ar8327_vtu_flush
,
1430 .vtu_load_vlan
= ar8327_vtu_load_vlan
,
1431 .phy_fixup
= ar8327_phy_fixup
,
1432 .set_mirror_regs
= ar8327_set_mirror_regs
,
1433 .get_arl_entry
= ar8327_get_arl_entry
,
1434 .sw_hw_apply
= ar8327_sw_hw_apply
,
1436 .num_mibs
= ARRAY_SIZE(ar8236_mibs
),
1437 .mib_decs
= ar8236_mibs
,
1438 .mib_func
= AR8327_REG_MIB_FUNC