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b53: allow configuration through device tree
[openwrt/staging/dedeckeh.git] / target / linux / generic / files / drivers / net / phy / b53 / b53_common.c
1 /*
2 * B53 switch driver main logic
3 *
4 * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 */
18
19 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
20
21 #include <linux/delay.h>
22 #include <linux/export.h>
23 #include <linux/gpio.h>
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/switch.h>
27 #include <linux/of.h>
28 #include <linux/of_net.h>
29 #include <linux/platform_data/b53.h>
30
31 #include "b53_regs.h"
32 #include "b53_priv.h"
33
34 /* buffer size needed for displaying all MIBs with max'd values */
35 #define B53_BUF_SIZE 1188
36
37 struct b53_mib_desc {
38 u8 size;
39 u8 offset;
40 const char *name;
41 };
42
43
44 /* BCM5365 MIB counters */
45 static const struct b53_mib_desc b53_mibs_65[] = {
46 { 8, 0x00, "TxOctets" },
47 { 4, 0x08, "TxDropPkts" },
48 { 4, 0x10, "TxBroadcastPkts" },
49 { 4, 0x14, "TxMulticastPkts" },
50 { 4, 0x18, "TxUnicastPkts" },
51 { 4, 0x1c, "TxCollisions" },
52 { 4, 0x20, "TxSingleCollision" },
53 { 4, 0x24, "TxMultipleCollision" },
54 { 4, 0x28, "TxDeferredTransmit" },
55 { 4, 0x2c, "TxLateCollision" },
56 { 4, 0x30, "TxExcessiveCollision" },
57 { 4, 0x38, "TxPausePkts" },
58 { 8, 0x44, "RxOctets" },
59 { 4, 0x4c, "RxUndersizePkts" },
60 { 4, 0x50, "RxPausePkts" },
61 { 4, 0x54, "Pkts64Octets" },
62 { 4, 0x58, "Pkts65to127Octets" },
63 { 4, 0x5c, "Pkts128to255Octets" },
64 { 4, 0x60, "Pkts256to511Octets" },
65 { 4, 0x64, "Pkts512to1023Octets" },
66 { 4, 0x68, "Pkts1024to1522Octets" },
67 { 4, 0x6c, "RxOversizePkts" },
68 { 4, 0x70, "RxJabbers" },
69 { 4, 0x74, "RxAlignmentErrors" },
70 { 4, 0x78, "RxFCSErrors" },
71 { 8, 0x7c, "RxGoodOctets" },
72 { 4, 0x84, "RxDropPkts" },
73 { 4, 0x88, "RxUnicastPkts" },
74 { 4, 0x8c, "RxMulticastPkts" },
75 { 4, 0x90, "RxBroadcastPkts" },
76 { 4, 0x94, "RxSAChanges" },
77 { 4, 0x98, "RxFragments" },
78 { },
79 };
80
81 /* BCM63xx MIB counters */
82 static const struct b53_mib_desc b53_mibs_63xx[] = {
83 { 8, 0x00, "TxOctets" },
84 { 4, 0x08, "TxDropPkts" },
85 { 4, 0x0c, "TxQoSPkts" },
86 { 4, 0x10, "TxBroadcastPkts" },
87 { 4, 0x14, "TxMulticastPkts" },
88 { 4, 0x18, "TxUnicastPkts" },
89 { 4, 0x1c, "TxCollisions" },
90 { 4, 0x20, "TxSingleCollision" },
91 { 4, 0x24, "TxMultipleCollision" },
92 { 4, 0x28, "TxDeferredTransmit" },
93 { 4, 0x2c, "TxLateCollision" },
94 { 4, 0x30, "TxExcessiveCollision" },
95 { 4, 0x38, "TxPausePkts" },
96 { 8, 0x3c, "TxQoSOctets" },
97 { 8, 0x44, "RxOctets" },
98 { 4, 0x4c, "RxUndersizePkts" },
99 { 4, 0x50, "RxPausePkts" },
100 { 4, 0x54, "Pkts64Octets" },
101 { 4, 0x58, "Pkts65to127Octets" },
102 { 4, 0x5c, "Pkts128to255Octets" },
103 { 4, 0x60, "Pkts256to511Octets" },
104 { 4, 0x64, "Pkts512to1023Octets" },
105 { 4, 0x68, "Pkts1024to1522Octets" },
106 { 4, 0x6c, "RxOversizePkts" },
107 { 4, 0x70, "RxJabbers" },
108 { 4, 0x74, "RxAlignmentErrors" },
109 { 4, 0x78, "RxFCSErrors" },
110 { 8, 0x7c, "RxGoodOctets" },
111 { 4, 0x84, "RxDropPkts" },
112 { 4, 0x88, "RxUnicastPkts" },
113 { 4, 0x8c, "RxMulticastPkts" },
114 { 4, 0x90, "RxBroadcastPkts" },
115 { 4, 0x94, "RxSAChanges" },
116 { 4, 0x98, "RxFragments" },
117 { 4, 0xa0, "RxSymbolErrors" },
118 { 4, 0xa4, "RxQoSPkts" },
119 { 8, 0xa8, "RxQoSOctets" },
120 { 4, 0xb0, "Pkts1523to2047Octets" },
121 { 4, 0xb4, "Pkts2048to4095Octets" },
122 { 4, 0xb8, "Pkts4096to8191Octets" },
123 { 4, 0xbc, "Pkts8192to9728Octets" },
124 { 4, 0xc0, "RxDiscarded" },
125 { }
126 };
127
128 /* MIB counters */
129 static const struct b53_mib_desc b53_mibs[] = {
130 { 8, 0x00, "TxOctets" },
131 { 4, 0x08, "TxDropPkts" },
132 { 4, 0x10, "TxBroadcastPkts" },
133 { 4, 0x14, "TxMulticastPkts" },
134 { 4, 0x18, "TxUnicastPkts" },
135 { 4, 0x1c, "TxCollisions" },
136 { 4, 0x20, "TxSingleCollision" },
137 { 4, 0x24, "TxMultipleCollision" },
138 { 4, 0x28, "TxDeferredTransmit" },
139 { 4, 0x2c, "TxLateCollision" },
140 { 4, 0x30, "TxExcessiveCollision" },
141 { 4, 0x38, "TxPausePkts" },
142 { 8, 0x50, "RxOctets" },
143 { 4, 0x58, "RxUndersizePkts" },
144 { 4, 0x5c, "RxPausePkts" },
145 { 4, 0x60, "Pkts64Octets" },
146 { 4, 0x64, "Pkts65to127Octets" },
147 { 4, 0x68, "Pkts128to255Octets" },
148 { 4, 0x6c, "Pkts256to511Octets" },
149 { 4, 0x70, "Pkts512to1023Octets" },
150 { 4, 0x74, "Pkts1024to1522Octets" },
151 { 4, 0x78, "RxOversizePkts" },
152 { 4, 0x7c, "RxJabbers" },
153 { 4, 0x80, "RxAlignmentErrors" },
154 { 4, 0x84, "RxFCSErrors" },
155 { 8, 0x88, "RxGoodOctets" },
156 { 4, 0x90, "RxDropPkts" },
157 { 4, 0x94, "RxUnicastPkts" },
158 { 4, 0x98, "RxMulticastPkts" },
159 { 4, 0x9c, "RxBroadcastPkts" },
160 { 4, 0xa0, "RxSAChanges" },
161 { 4, 0xa4, "RxFragments" },
162 { 4, 0xa8, "RxJumboPkts" },
163 { 4, 0xac, "RxSymbolErrors" },
164 { 4, 0xc0, "RxDiscarded" },
165 { }
166 };
167
168 static int b53_do_vlan_op(struct b53_device *dev, u8 op)
169 {
170 unsigned int i;
171
172 b53_write8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], VTA_START_CMD | op);
173
174 for (i = 0; i < 10; i++) {
175 u8 vta;
176
177 b53_read8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], &vta);
178 if (!(vta & VTA_START_CMD))
179 return 0;
180
181 usleep_range(100, 200);
182 }
183
184 return -EIO;
185 }
186
187 static void b53_set_vlan_entry(struct b53_device *dev, u16 vid, u16 members,
188 u16 untag)
189 {
190 if (is5325(dev)) {
191 u32 entry = 0;
192
193 if (members) {
194 entry = ((untag & VA_UNTAG_MASK_25) << VA_UNTAG_S_25) |
195 members;
196 if (dev->core_rev >= 3)
197 entry |= VA_VALID_25_R4 | vid << VA_VID_HIGH_S;
198 else
199 entry |= VA_VALID_25;
200 }
201
202 b53_write32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, entry);
203 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
204 VTA_RW_STATE_WR | VTA_RW_OP_EN);
205 } else if (is5365(dev)) {
206 u16 entry = 0;
207
208 if (members)
209 entry = ((untag & VA_UNTAG_MASK_65) << VA_UNTAG_S_65) |
210 members | VA_VALID_65;
211
212 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, entry);
213 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
214 VTA_RW_STATE_WR | VTA_RW_OP_EN);
215 } else {
216 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
217 b53_write32(dev, B53_ARLIO_PAGE, dev->vta_regs[2],
218 (untag << VTE_UNTAG_S) | members);
219
220 b53_do_vlan_op(dev, VTA_CMD_WRITE);
221 }
222 }
223
224 void b53_set_forwarding(struct b53_device *dev, int enable)
225 {
226 u8 mgmt;
227
228 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
229
230 if (enable)
231 mgmt |= SM_SW_FWD_EN;
232 else
233 mgmt &= ~SM_SW_FWD_EN;
234
235 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
236 }
237
238 static void b53_enable_vlan(struct b53_device *dev, int enable)
239 {
240 u8 mgmt, vc0, vc1, vc4 = 0, vc5;
241
242 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
243 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, &vc0);
244 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, &vc1);
245
246 if (is5325(dev) || is5365(dev)) {
247 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
248 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, &vc5);
249 } else if (is63xx(dev)) {
250 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, &vc4);
251 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, &vc5);
252 } else {
253 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, &vc4);
254 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, &vc5);
255 }
256
257 mgmt &= ~SM_SW_FWD_MODE;
258
259 if (enable) {
260 vc0 |= VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID;
261 vc1 |= VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN;
262 vc4 &= ~VC4_ING_VID_CHECK_MASK;
263 vc4 |= VC4_ING_VID_VIO_DROP << VC4_ING_VID_CHECK_S;
264 vc5 |= VC5_DROP_VTABLE_MISS;
265
266 if (is5325(dev))
267 vc0 &= ~VC0_RESERVED_1;
268
269 if (is5325(dev) || is5365(dev))
270 vc1 |= VC1_RX_MCST_TAG_EN;
271
272 if (!is5325(dev) && !is5365(dev)) {
273 if (dev->allow_vid_4095)
274 vc5 |= VC5_VID_FFF_EN;
275 else
276 vc5 &= ~VC5_VID_FFF_EN;
277 }
278 } else {
279 vc0 &= ~(VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID);
280 vc1 &= ~(VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN);
281 vc4 &= ~VC4_ING_VID_CHECK_MASK;
282 vc5 &= ~VC5_DROP_VTABLE_MISS;
283
284 if (is5325(dev) || is5365(dev))
285 vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S;
286 else
287 vc4 |= VC4_ING_VID_VIO_TO_IMP << VC4_ING_VID_CHECK_S;
288
289 if (is5325(dev) || is5365(dev))
290 vc1 &= ~VC1_RX_MCST_TAG_EN;
291
292 if (!is5325(dev) && !is5365(dev))
293 vc5 &= ~VC5_VID_FFF_EN;
294 }
295
296 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, vc0);
297 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, vc1);
298
299 if (is5325(dev) || is5365(dev)) {
300 /* enable the high 8 bit vid check on 5325 */
301 if (is5325(dev) && enable)
302 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3,
303 VC3_HIGH_8BIT_EN);
304 else
305 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
306
307 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, vc4);
308 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, vc5);
309 } else if (is63xx(dev)) {
310 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3_63XX, 0);
311 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, vc4);
312 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, vc5);
313 } else {
314 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
315 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, vc4);
316 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, vc5);
317 }
318
319 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
320 }
321
322 static int b53_set_jumbo(struct b53_device *dev, int enable, int allow_10_100)
323 {
324 u32 port_mask = 0;
325 u16 max_size = JMS_MIN_SIZE;
326
327 if (is5325(dev) || is5365(dev))
328 return -EINVAL;
329
330 if (enable) {
331 port_mask = dev->enabled_ports;
332 max_size = JMS_MAX_SIZE;
333 if (allow_10_100)
334 port_mask |= JPM_10_100_JUMBO_EN;
335 }
336
337 b53_write32(dev, B53_JUMBO_PAGE, dev->jumbo_pm_reg, port_mask);
338 return b53_write16(dev, B53_JUMBO_PAGE, dev->jumbo_size_reg, max_size);
339 }
340
341 static int b53_flush_arl(struct b53_device *dev)
342 {
343 unsigned int i;
344
345 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
346 FAST_AGE_DONE | FAST_AGE_DYNAMIC | FAST_AGE_STATIC);
347
348 for (i = 0; i < 10; i++) {
349 u8 fast_age_ctrl;
350
351 b53_read8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
352 &fast_age_ctrl);
353
354 if (!(fast_age_ctrl & FAST_AGE_DONE))
355 return 0;
356
357 mdelay(1);
358 }
359
360 pr_warn("time out while flushing ARL\n");
361
362 return -EINVAL;
363 }
364
365 static void b53_enable_ports(struct b53_device *dev)
366 {
367 unsigned i;
368
369 b53_for_each_port(dev, i) {
370 u8 port_ctrl;
371 u16 pvlan_mask;
372
373 /*
374 * prevent leaking packets between wan and lan in unmanaged
375 * mode through port vlans.
376 */
377 if (dev->enable_vlan || is_cpu_port(dev, i))
378 pvlan_mask = 0x1ff;
379 else if (is531x5(dev) || is5301x(dev))
380 /* BCM53115 may use a different port as cpu port */
381 pvlan_mask = BIT(dev->sw_dev.cpu_port);
382 else
383 pvlan_mask = BIT(B53_CPU_PORT);
384
385 /* BCM5325 CPU port is at 8 */
386 if ((is5325(dev) || is5365(dev)) && i == B53_CPU_PORT_25)
387 i = B53_CPU_PORT;
388
389 if (dev->chip_id == BCM5398_DEVICE_ID && (i == 6 || i == 7))
390 /* disable unused ports 6 & 7 */
391 port_ctrl = PORT_CTRL_RX_DISABLE | PORT_CTRL_TX_DISABLE;
392 else if (i == B53_CPU_PORT)
393 port_ctrl = PORT_CTRL_RX_BCST_EN |
394 PORT_CTRL_RX_MCST_EN |
395 PORT_CTRL_RX_UCST_EN;
396 else
397 port_ctrl = 0;
398
399 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i),
400 pvlan_mask);
401
402 /* port state is handled by bcm63xx_enet driver */
403 if (!is63xx(dev) && !(is5301x(dev) && i == 6))
404 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(i),
405 port_ctrl);
406 }
407 }
408
409 static void b53_enable_mib(struct b53_device *dev)
410 {
411 u8 gc;
412
413 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
414
415 gc &= ~(GC_RESET_MIB | GC_MIB_AC_EN);
416
417 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc);
418 }
419
420 static int b53_apply(struct b53_device *dev)
421 {
422 int i;
423
424 /* clear all vlan entries */
425 if (is5325(dev) || is5365(dev)) {
426 for (i = 1; i < dev->sw_dev.vlans; i++)
427 b53_set_vlan_entry(dev, i, 0, 0);
428 } else {
429 b53_do_vlan_op(dev, VTA_CMD_CLEAR);
430 }
431
432 b53_enable_vlan(dev, dev->enable_vlan);
433
434 /* fill VLAN table */
435 if (dev->enable_vlan) {
436 for (i = 0; i < dev->sw_dev.vlans; i++) {
437 struct b53_vlan *vlan = &dev->vlans[i];
438
439 if (!vlan->members)
440 continue;
441
442 b53_set_vlan_entry(dev, i, vlan->members, vlan->untag);
443 }
444
445 b53_for_each_port(dev, i)
446 b53_write16(dev, B53_VLAN_PAGE,
447 B53_VLAN_PORT_DEF_TAG(i),
448 dev->ports[i].pvid);
449 } else {
450 b53_for_each_port(dev, i)
451 b53_write16(dev, B53_VLAN_PAGE,
452 B53_VLAN_PORT_DEF_TAG(i), 1);
453
454 }
455
456 b53_enable_ports(dev);
457
458 if (!is5325(dev) && !is5365(dev))
459 b53_set_jumbo(dev, dev->enable_jumbo, 1);
460
461 return 0;
462 }
463
464 static void b53_switch_reset_gpio(struct b53_device *dev)
465 {
466 int gpio = dev->reset_gpio;
467
468 if (gpio < 0)
469 return;
470
471 /*
472 * Reset sequence: RESET low(50ms)->high(20ms)
473 */
474 gpio_set_value(gpio, 0);
475 mdelay(50);
476
477 gpio_set_value(gpio, 1);
478 mdelay(20);
479
480 dev->current_page = 0xff;
481 }
482
483 static int b53_configure_ports_of(struct b53_device *dev)
484 {
485 struct device_node *dn, *pn;
486 u32 port_num;
487
488 dn = of_get_child_by_name(dev_of_node(dev->dev), "ports");
489
490 for_each_available_child_of_node(dn, pn) {
491 struct device_node *fixed_link;
492
493 if (of_property_read_u32(pn, "reg", &port_num))
494 continue;
495
496 if (port_num > B53_CPU_PORT)
497 continue;
498
499 fixed_link = of_get_child_by_name(pn, "fixed-link");
500 if (fixed_link) {
501 u32 spd;
502 u8 po = GMII_PO_LINK;
503 int mode = of_get_phy_mode(pn);
504
505 if (!of_property_read_u32(fixed_link, "speed", &spd)) {
506 switch (spd) {
507 case 10:
508 po |= GMII_PO_SPEED_10M;
509 break;
510 case 100:
511 po |= GMII_PO_SPEED_100M;
512 break;
513 case 2000:
514 if (is_imp_port(dev, port_num))
515 po |= PORT_OVERRIDE_SPEED_2000M;
516 else
517 po |= GMII_PO_SPEED_2000M;
518 /* fall through */
519 case 1000:
520 po |= GMII_PO_SPEED_1000M;
521 break;
522 }
523 }
524
525 if (of_property_read_bool(fixed_link, "full-duplex"))
526 po |= PORT_OVERRIDE_FULL_DUPLEX;
527 if (of_property_read_bool(fixed_link, "pause"))
528 po |= GMII_PO_RX_FLOW;
529 if (of_property_read_bool(fixed_link, "asym-pause"))
530 po |= GMII_PO_TX_FLOW;
531
532 if (is_imp_port(dev, port_num)) {
533 po |= PORT_OVERRIDE_EN;
534
535 if (is5325(dev) &&
536 mode == PHY_INTERFACE_MODE_REVMII)
537 po |= PORT_OVERRIDE_RV_MII_25;
538
539 b53_write8(dev, B53_CTRL_PAGE,
540 B53_PORT_OVERRIDE_CTRL, po);
541
542 if (is5325(dev) &&
543 mode == PHY_INTERFACE_MODE_REVMII) {
544 b53_read8(dev, B53_CTRL_PAGE,
545 B53_PORT_OVERRIDE_CTRL, &po);
546 if (!(po & PORT_OVERRIDE_RV_MII_25))
547 pr_err("Failed to enable reverse MII mode\n");
548 return -EINVAL;
549 }
550 } else {
551 po |= GMII_PO_EN;
552 b53_write8(dev, B53_CTRL_PAGE,
553 B53_GMII_PORT_OVERRIDE_CTRL(port_num),
554 po);
555 }
556 }
557 }
558
559 return 0;
560 }
561
562 static int b53_configure_ports(struct b53_device *dev)
563 {
564 u8 cpu_port = dev->sw_dev.cpu_port;
565
566 /* configure MII port if necessary */
567 if (is5325(dev)) {
568 u8 mii_port_override;
569
570 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
571 &mii_port_override);
572 /* reverse mii needs to be enabled */
573 if (!(mii_port_override & PORT_OVERRIDE_RV_MII_25)) {
574 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
575 mii_port_override | PORT_OVERRIDE_RV_MII_25);
576 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
577 &mii_port_override);
578
579 if (!(mii_port_override & PORT_OVERRIDE_RV_MII_25)) {
580 pr_err("Failed to enable reverse MII mode\n");
581 return -EINVAL;
582 }
583 }
584 } else if (is531x5(dev) && cpu_port == B53_CPU_PORT) {
585 u8 mii_port_override;
586
587 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
588 &mii_port_override);
589 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
590 mii_port_override | PORT_OVERRIDE_EN |
591 PORT_OVERRIDE_LINK);
592
593 /* BCM47189 has another interface connected to the port 5 */
594 if (dev->enabled_ports & BIT(5)) {
595 u8 po_reg = B53_GMII_PORT_OVERRIDE_CTRL(5);
596 u8 gmii_po;
597
598 b53_read8(dev, B53_CTRL_PAGE, po_reg, &gmii_po);
599 gmii_po |= GMII_PO_LINK |
600 GMII_PO_RX_FLOW |
601 GMII_PO_TX_FLOW |
602 GMII_PO_EN;
603 b53_write8(dev, B53_CTRL_PAGE, po_reg, gmii_po);
604 }
605 } else if (is5301x(dev)) {
606 if (cpu_port == 8) {
607 u8 mii_port_override;
608
609 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
610 &mii_port_override);
611 mii_port_override |= PORT_OVERRIDE_LINK |
612 PORT_OVERRIDE_RX_FLOW |
613 PORT_OVERRIDE_TX_FLOW |
614 PORT_OVERRIDE_SPEED_2000M |
615 PORT_OVERRIDE_EN;
616 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
617 mii_port_override);
618
619 /* TODO: Ports 5 & 7 require some extra handling */
620 } else {
621 u8 po_reg = B53_GMII_PORT_OVERRIDE_CTRL(cpu_port);
622 u8 gmii_po;
623
624 b53_read8(dev, B53_CTRL_PAGE, po_reg, &gmii_po);
625 gmii_po |= GMII_PO_LINK |
626 GMII_PO_RX_FLOW |
627 GMII_PO_TX_FLOW |
628 GMII_PO_EN |
629 GMII_PO_SPEED_2000M;
630 b53_write8(dev, B53_CTRL_PAGE, po_reg, gmii_po);
631 }
632 }
633
634 return 0;
635 }
636
637 static int b53_switch_reset(struct b53_device *dev)
638 {
639 int ret = 0;
640 u8 mgmt;
641
642 b53_switch_reset_gpio(dev);
643
644 if (is539x(dev)) {
645 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x83);
646 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x00);
647 }
648
649 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
650
651 if (!(mgmt & SM_SW_FWD_EN)) {
652 mgmt &= ~SM_SW_FWD_MODE;
653 mgmt |= SM_SW_FWD_EN;
654
655 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
656 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
657
658 if (!(mgmt & SM_SW_FWD_EN)) {
659 pr_err("Failed to enable switch!\n");
660 return -EINVAL;
661 }
662 }
663
664 /* enable all ports */
665 b53_enable_ports(dev);
666
667 if (dev->dev->of_node)
668 ret = b53_configure_ports_of(dev);
669 else
670 ret = b53_configure_ports(dev);
671
672 if (ret)
673 return ret;
674
675 b53_enable_mib(dev);
676
677 return b53_flush_arl(dev);
678 }
679
680 /*
681 * Swconfig glue functions
682 */
683
684 static int b53_global_get_vlan_enable(struct switch_dev *dev,
685 const struct switch_attr *attr,
686 struct switch_val *val)
687 {
688 struct b53_device *priv = sw_to_b53(dev);
689
690 val->value.i = priv->enable_vlan;
691
692 return 0;
693 }
694
695 static int b53_global_set_vlan_enable(struct switch_dev *dev,
696 const struct switch_attr *attr,
697 struct switch_val *val)
698 {
699 struct b53_device *priv = sw_to_b53(dev);
700
701 priv->enable_vlan = val->value.i;
702
703 return 0;
704 }
705
706 static int b53_global_get_jumbo_enable(struct switch_dev *dev,
707 const struct switch_attr *attr,
708 struct switch_val *val)
709 {
710 struct b53_device *priv = sw_to_b53(dev);
711
712 val->value.i = priv->enable_jumbo;
713
714 return 0;
715 }
716
717 static int b53_global_set_jumbo_enable(struct switch_dev *dev,
718 const struct switch_attr *attr,
719 struct switch_val *val)
720 {
721 struct b53_device *priv = sw_to_b53(dev);
722
723 priv->enable_jumbo = val->value.i;
724
725 return 0;
726 }
727
728 static int b53_global_get_4095_enable(struct switch_dev *dev,
729 const struct switch_attr *attr,
730 struct switch_val *val)
731 {
732 struct b53_device *priv = sw_to_b53(dev);
733
734 val->value.i = priv->allow_vid_4095;
735
736 return 0;
737 }
738
739 static int b53_global_set_4095_enable(struct switch_dev *dev,
740 const struct switch_attr *attr,
741 struct switch_val *val)
742 {
743 struct b53_device *priv = sw_to_b53(dev);
744
745 priv->allow_vid_4095 = val->value.i;
746
747 return 0;
748 }
749
750 static int b53_global_get_ports(struct switch_dev *dev,
751 const struct switch_attr *attr,
752 struct switch_val *val)
753 {
754 struct b53_device *priv = sw_to_b53(dev);
755
756 val->len = snprintf(priv->buf, B53_BUF_SIZE, "0x%04x",
757 priv->enabled_ports);
758 val->value.s = priv->buf;
759
760 return 0;
761 }
762
763 static int b53_port_get_pvid(struct switch_dev *dev, int port, int *val)
764 {
765 struct b53_device *priv = sw_to_b53(dev);
766
767 *val = priv->ports[port].pvid;
768
769 return 0;
770 }
771
772 static int b53_port_set_pvid(struct switch_dev *dev, int port, int val)
773 {
774 struct b53_device *priv = sw_to_b53(dev);
775
776 if (val > 15 && is5325(priv))
777 return -EINVAL;
778 if (val == 4095 && !priv->allow_vid_4095)
779 return -EINVAL;
780
781 priv->ports[port].pvid = val;
782
783 return 0;
784 }
785
786 static int b53_vlan_get_ports(struct switch_dev *dev, struct switch_val *val)
787 {
788 struct b53_device *priv = sw_to_b53(dev);
789 struct switch_port *port = &val->value.ports[0];
790 struct b53_vlan *vlan = &priv->vlans[val->port_vlan];
791 int i;
792
793 val->len = 0;
794
795 if (!vlan->members)
796 return 0;
797
798 for (i = 0; i < dev->ports; i++) {
799 if (!(vlan->members & BIT(i)))
800 continue;
801
802
803 if (!(vlan->untag & BIT(i)))
804 port->flags = BIT(SWITCH_PORT_FLAG_TAGGED);
805 else
806 port->flags = 0;
807
808 port->id = i;
809 val->len++;
810 port++;
811 }
812
813 return 0;
814 }
815
816 static int b53_vlan_set_ports(struct switch_dev *dev, struct switch_val *val)
817 {
818 struct b53_device *priv = sw_to_b53(dev);
819 struct switch_port *port;
820 struct b53_vlan *vlan = &priv->vlans[val->port_vlan];
821 int i;
822
823 /* only BCM5325 and BCM5365 supports VID 0 */
824 if (val->port_vlan == 0 && !is5325(priv) && !is5365(priv))
825 return -EINVAL;
826
827 /* VLAN 4095 needs special handling */
828 if (val->port_vlan == 4095 && !priv->allow_vid_4095)
829 return -EINVAL;
830
831 port = &val->value.ports[0];
832 vlan->members = 0;
833 vlan->untag = 0;
834 for (i = 0; i < val->len; i++, port++) {
835 vlan->members |= BIT(port->id);
836
837 if (!(port->flags & BIT(SWITCH_PORT_FLAG_TAGGED))) {
838 vlan->untag |= BIT(port->id);
839 priv->ports[port->id].pvid = val->port_vlan;
840 };
841 }
842
843 /* ignore disabled ports */
844 vlan->members &= priv->enabled_ports;
845 vlan->untag &= priv->enabled_ports;
846
847 return 0;
848 }
849
850 static int b53_port_get_link(struct switch_dev *dev, int port,
851 struct switch_port_link *link)
852 {
853 struct b53_device *priv = sw_to_b53(dev);
854
855 if (is_cpu_port(priv, port)) {
856 link->link = 1;
857 link->duplex = 1;
858 link->speed = is5325(priv) || is5365(priv) ?
859 SWITCH_PORT_SPEED_100 : SWITCH_PORT_SPEED_1000;
860 link->aneg = 0;
861 } else if (priv->enabled_ports & BIT(port)) {
862 u32 speed;
863 u16 lnk, duplex;
864
865 b53_read16(priv, B53_STAT_PAGE, B53_LINK_STAT, &lnk);
866 b53_read16(priv, B53_STAT_PAGE, priv->duplex_reg, &duplex);
867
868 lnk = (lnk >> port) & 1;
869 duplex = (duplex >> port) & 1;
870
871 if (is5325(priv) || is5365(priv)) {
872 u16 tmp;
873
874 b53_read16(priv, B53_STAT_PAGE, B53_SPEED_STAT, &tmp);
875 speed = SPEED_PORT_FE(tmp, port);
876 } else {
877 b53_read32(priv, B53_STAT_PAGE, B53_SPEED_STAT, &speed);
878 speed = SPEED_PORT_GE(speed, port);
879 }
880
881 link->link = lnk;
882 if (lnk) {
883 link->duplex = duplex;
884 switch (speed) {
885 case SPEED_STAT_10M:
886 link->speed = SWITCH_PORT_SPEED_10;
887 break;
888 case SPEED_STAT_100M:
889 link->speed = SWITCH_PORT_SPEED_100;
890 break;
891 case SPEED_STAT_1000M:
892 link->speed = SWITCH_PORT_SPEED_1000;
893 break;
894 }
895 }
896
897 link->aneg = 1;
898 } else {
899 link->link = 0;
900 }
901
902 return 0;
903
904 }
905
906 static int b53_port_set_link(struct switch_dev *sw_dev, int port,
907 struct switch_port_link *link)
908 {
909 struct b53_device *dev = sw_to_b53(sw_dev);
910
911 /*
912 * TODO: BCM63XX requires special handling as it can have external phys
913 * and ports might be GE or only FE
914 */
915 if (is63xx(dev))
916 return -ENOTSUPP;
917
918 if (port == sw_dev->cpu_port)
919 return -EINVAL;
920
921 if (!(BIT(port) & dev->enabled_ports))
922 return -EINVAL;
923
924 if (link->speed == SWITCH_PORT_SPEED_1000 &&
925 (is5325(dev) || is5365(dev)))
926 return -EINVAL;
927
928 if (link->speed == SWITCH_PORT_SPEED_1000 && !link->duplex)
929 return -EINVAL;
930
931 return switch_generic_set_link(sw_dev, port, link);
932 }
933
934 static int b53_phy_read16(struct switch_dev *dev, int addr, u8 reg, u16 *value)
935 {
936 struct b53_device *priv = sw_to_b53(dev);
937
938 if (priv->ops->phy_read16)
939 return priv->ops->phy_read16(priv, addr, reg, value);
940
941 return b53_read16(priv, B53_PORT_MII_PAGE(addr), reg, value);
942 }
943
944 static int b53_phy_write16(struct switch_dev *dev, int addr, u8 reg, u16 value)
945 {
946 struct b53_device *priv = sw_to_b53(dev);
947
948 if (priv->ops->phy_write16)
949 return priv->ops->phy_write16(priv, addr, reg, value);
950
951 return b53_write16(priv, B53_PORT_MII_PAGE(addr), reg, value);
952 }
953
954 static int b53_global_reset_switch(struct switch_dev *dev)
955 {
956 struct b53_device *priv = sw_to_b53(dev);
957
958 /* reset vlans */
959 priv->enable_vlan = 0;
960 priv->enable_jumbo = 0;
961 priv->allow_vid_4095 = 0;
962
963 memset(priv->vlans, 0, sizeof(*priv->vlans) * dev->vlans);
964 memset(priv->ports, 0, sizeof(*priv->ports) * dev->ports);
965
966 return b53_switch_reset(priv);
967 }
968
969 static int b53_global_apply_config(struct switch_dev *dev)
970 {
971 struct b53_device *priv = sw_to_b53(dev);
972
973 /* disable switching */
974 b53_set_forwarding(priv, 0);
975
976 b53_apply(priv);
977
978 /* enable switching */
979 b53_set_forwarding(priv, 1);
980
981 return 0;
982 }
983
984
985 static int b53_global_reset_mib(struct switch_dev *dev,
986 const struct switch_attr *attr,
987 struct switch_val *val)
988 {
989 struct b53_device *priv = sw_to_b53(dev);
990 u8 gc;
991
992 b53_read8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
993
994 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc | GC_RESET_MIB);
995 mdelay(1);
996 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc & ~GC_RESET_MIB);
997 mdelay(1);
998
999 return 0;
1000 }
1001
1002 static int b53_port_get_mib(struct switch_dev *sw_dev,
1003 const struct switch_attr *attr,
1004 struct switch_val *val)
1005 {
1006 struct b53_device *dev = sw_to_b53(sw_dev);
1007 const struct b53_mib_desc *mibs;
1008 int port = val->port_vlan;
1009 int len = 0;
1010
1011 if (!(BIT(port) & dev->enabled_ports))
1012 return -1;
1013
1014 if (is5365(dev)) {
1015 if (port == 5)
1016 port = 8;
1017
1018 mibs = b53_mibs_65;
1019 } else if (is63xx(dev)) {
1020 mibs = b53_mibs_63xx;
1021 } else {
1022 mibs = b53_mibs;
1023 }
1024
1025 dev->buf[0] = 0;
1026
1027 for (; mibs->size > 0; mibs++) {
1028 u64 val;
1029
1030 if (mibs->size == 8) {
1031 b53_read64(dev, B53_MIB_PAGE(port), mibs->offset, &val);
1032 } else {
1033 u32 val32;
1034
1035 b53_read32(dev, B53_MIB_PAGE(port), mibs->offset,
1036 &val32);
1037 val = val32;
1038 }
1039
1040 len += snprintf(dev->buf + len, B53_BUF_SIZE - len,
1041 "%-20s: %llu\n", mibs->name, val);
1042 }
1043
1044 val->len = len;
1045 val->value.s = dev->buf;
1046
1047 return 0;
1048 }
1049
1050 static struct switch_attr b53_global_ops_25[] = {
1051 {
1052 .type = SWITCH_TYPE_INT,
1053 .name = "enable_vlan",
1054 .description = "Enable VLAN mode",
1055 .set = b53_global_set_vlan_enable,
1056 .get = b53_global_get_vlan_enable,
1057 .max = 1,
1058 },
1059 {
1060 .type = SWITCH_TYPE_STRING,
1061 .name = "ports",
1062 .description = "Available ports (as bitmask)",
1063 .get = b53_global_get_ports,
1064 },
1065 };
1066
1067 static struct switch_attr b53_global_ops_65[] = {
1068 {
1069 .type = SWITCH_TYPE_INT,
1070 .name = "enable_vlan",
1071 .description = "Enable VLAN mode",
1072 .set = b53_global_set_vlan_enable,
1073 .get = b53_global_get_vlan_enable,
1074 .max = 1,
1075 },
1076 {
1077 .type = SWITCH_TYPE_STRING,
1078 .name = "ports",
1079 .description = "Available ports (as bitmask)",
1080 .get = b53_global_get_ports,
1081 },
1082 {
1083 .type = SWITCH_TYPE_INT,
1084 .name = "reset_mib",
1085 .description = "Reset MIB counters",
1086 .set = b53_global_reset_mib,
1087 },
1088 };
1089
1090 static struct switch_attr b53_global_ops[] = {
1091 {
1092 .type = SWITCH_TYPE_INT,
1093 .name = "enable_vlan",
1094 .description = "Enable VLAN mode",
1095 .set = b53_global_set_vlan_enable,
1096 .get = b53_global_get_vlan_enable,
1097 .max = 1,
1098 },
1099 {
1100 .type = SWITCH_TYPE_STRING,
1101 .name = "ports",
1102 .description = "Available Ports (as bitmask)",
1103 .get = b53_global_get_ports,
1104 },
1105 {
1106 .type = SWITCH_TYPE_INT,
1107 .name = "reset_mib",
1108 .description = "Reset MIB counters",
1109 .set = b53_global_reset_mib,
1110 },
1111 {
1112 .type = SWITCH_TYPE_INT,
1113 .name = "enable_jumbo",
1114 .description = "Enable Jumbo Frames",
1115 .set = b53_global_set_jumbo_enable,
1116 .get = b53_global_get_jumbo_enable,
1117 .max = 1,
1118 },
1119 {
1120 .type = SWITCH_TYPE_INT,
1121 .name = "allow_vid_4095",
1122 .description = "Allow VID 4095",
1123 .set = b53_global_set_4095_enable,
1124 .get = b53_global_get_4095_enable,
1125 .max = 1,
1126 },
1127 };
1128
1129 static struct switch_attr b53_port_ops[] = {
1130 {
1131 .type = SWITCH_TYPE_STRING,
1132 .name = "mib",
1133 .description = "Get port's MIB counters",
1134 .get = b53_port_get_mib,
1135 },
1136 };
1137
1138 static struct switch_attr b53_no_ops[] = {
1139 };
1140
1141 static const struct switch_dev_ops b53_switch_ops_25 = {
1142 .attr_global = {
1143 .attr = b53_global_ops_25,
1144 .n_attr = ARRAY_SIZE(b53_global_ops_25),
1145 },
1146 .attr_port = {
1147 .attr = b53_no_ops,
1148 .n_attr = ARRAY_SIZE(b53_no_ops),
1149 },
1150 .attr_vlan = {
1151 .attr = b53_no_ops,
1152 .n_attr = ARRAY_SIZE(b53_no_ops),
1153 },
1154
1155 .get_vlan_ports = b53_vlan_get_ports,
1156 .set_vlan_ports = b53_vlan_set_ports,
1157 .get_port_pvid = b53_port_get_pvid,
1158 .set_port_pvid = b53_port_set_pvid,
1159 .apply_config = b53_global_apply_config,
1160 .reset_switch = b53_global_reset_switch,
1161 .get_port_link = b53_port_get_link,
1162 .set_port_link = b53_port_set_link,
1163 .phy_read16 = b53_phy_read16,
1164 .phy_write16 = b53_phy_write16,
1165 };
1166
1167 static const struct switch_dev_ops b53_switch_ops_65 = {
1168 .attr_global = {
1169 .attr = b53_global_ops_65,
1170 .n_attr = ARRAY_SIZE(b53_global_ops_65),
1171 },
1172 .attr_port = {
1173 .attr = b53_port_ops,
1174 .n_attr = ARRAY_SIZE(b53_port_ops),
1175 },
1176 .attr_vlan = {
1177 .attr = b53_no_ops,
1178 .n_attr = ARRAY_SIZE(b53_no_ops),
1179 },
1180
1181 .get_vlan_ports = b53_vlan_get_ports,
1182 .set_vlan_ports = b53_vlan_set_ports,
1183 .get_port_pvid = b53_port_get_pvid,
1184 .set_port_pvid = b53_port_set_pvid,
1185 .apply_config = b53_global_apply_config,
1186 .reset_switch = b53_global_reset_switch,
1187 .get_port_link = b53_port_get_link,
1188 .set_port_link = b53_port_set_link,
1189 .phy_read16 = b53_phy_read16,
1190 .phy_write16 = b53_phy_write16,
1191 };
1192
1193 static const struct switch_dev_ops b53_switch_ops = {
1194 .attr_global = {
1195 .attr = b53_global_ops,
1196 .n_attr = ARRAY_SIZE(b53_global_ops),
1197 },
1198 .attr_port = {
1199 .attr = b53_port_ops,
1200 .n_attr = ARRAY_SIZE(b53_port_ops),
1201 },
1202 .attr_vlan = {
1203 .attr = b53_no_ops,
1204 .n_attr = ARRAY_SIZE(b53_no_ops),
1205 },
1206
1207 .get_vlan_ports = b53_vlan_get_ports,
1208 .set_vlan_ports = b53_vlan_set_ports,
1209 .get_port_pvid = b53_port_get_pvid,
1210 .set_port_pvid = b53_port_set_pvid,
1211 .apply_config = b53_global_apply_config,
1212 .reset_switch = b53_global_reset_switch,
1213 .get_port_link = b53_port_get_link,
1214 .set_port_link = b53_port_set_link,
1215 .phy_read16 = b53_phy_read16,
1216 .phy_write16 = b53_phy_write16,
1217 };
1218
1219 struct b53_chip_data {
1220 u32 chip_id;
1221 const char *dev_name;
1222 const char *alias;
1223 u16 vlans;
1224 u16 enabled_ports;
1225 u8 cpu_port;
1226 u8 vta_regs[3];
1227 u8 duplex_reg;
1228 u8 jumbo_pm_reg;
1229 u8 jumbo_size_reg;
1230 const struct switch_dev_ops *sw_ops;
1231 };
1232
1233 #define B53_VTA_REGS \
1234 { B53_VT_ACCESS, B53_VT_INDEX, B53_VT_ENTRY }
1235 #define B53_VTA_REGS_9798 \
1236 { B53_VT_ACCESS_9798, B53_VT_INDEX_9798, B53_VT_ENTRY_9798 }
1237 #define B53_VTA_REGS_63XX \
1238 { B53_VT_ACCESS_63XX, B53_VT_INDEX_63XX, B53_VT_ENTRY_63XX }
1239
1240 static const struct b53_chip_data b53_switch_chips[] = {
1241 {
1242 .chip_id = BCM5325_DEVICE_ID,
1243 .dev_name = "BCM5325",
1244 .alias = "bcm5325",
1245 .vlans = 16,
1246 .enabled_ports = 0x1f,
1247 .cpu_port = B53_CPU_PORT_25,
1248 .duplex_reg = B53_DUPLEX_STAT_FE,
1249 .sw_ops = &b53_switch_ops_25,
1250 },
1251 {
1252 .chip_id = BCM5365_DEVICE_ID,
1253 .dev_name = "BCM5365",
1254 .alias = "bcm5365",
1255 .vlans = 256,
1256 .enabled_ports = 0x1f,
1257 .cpu_port = B53_CPU_PORT_25,
1258 .duplex_reg = B53_DUPLEX_STAT_FE,
1259 .sw_ops = &b53_switch_ops_65,
1260 },
1261 {
1262 .chip_id = BCM5395_DEVICE_ID,
1263 .dev_name = "BCM5395",
1264 .alias = "bcm5395",
1265 .vlans = 4096,
1266 .enabled_ports = 0x1f,
1267 .cpu_port = B53_CPU_PORT,
1268 .vta_regs = B53_VTA_REGS,
1269 .duplex_reg = B53_DUPLEX_STAT_GE,
1270 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1271 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1272 .sw_ops = &b53_switch_ops,
1273 },
1274 {
1275 .chip_id = BCM5397_DEVICE_ID,
1276 .dev_name = "BCM5397",
1277 .alias = "bcm5397",
1278 .vlans = 4096,
1279 .enabled_ports = 0x1f,
1280 .cpu_port = B53_CPU_PORT,
1281 .vta_regs = B53_VTA_REGS_9798,
1282 .duplex_reg = B53_DUPLEX_STAT_GE,
1283 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1284 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1285 .sw_ops = &b53_switch_ops,
1286 },
1287 {
1288 .chip_id = BCM5398_DEVICE_ID,
1289 .dev_name = "BCM5398",
1290 .alias = "bcm5398",
1291 .vlans = 4096,
1292 .enabled_ports = 0x7f,
1293 .cpu_port = B53_CPU_PORT,
1294 .vta_regs = B53_VTA_REGS_9798,
1295 .duplex_reg = B53_DUPLEX_STAT_GE,
1296 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1297 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1298 .sw_ops = &b53_switch_ops,
1299 },
1300 {
1301 .chip_id = BCM53115_DEVICE_ID,
1302 .dev_name = "BCM53115",
1303 .alias = "bcm53115",
1304 .vlans = 4096,
1305 .enabled_ports = 0x1f,
1306 .vta_regs = B53_VTA_REGS,
1307 .cpu_port = B53_CPU_PORT,
1308 .duplex_reg = B53_DUPLEX_STAT_GE,
1309 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1310 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1311 .sw_ops = &b53_switch_ops,
1312 },
1313 {
1314 .chip_id = BCM53125_DEVICE_ID,
1315 .dev_name = "BCM53125",
1316 .alias = "bcm53125",
1317 .vlans = 4096,
1318 .enabled_ports = 0x1f,
1319 .cpu_port = B53_CPU_PORT,
1320 .vta_regs = B53_VTA_REGS,
1321 .duplex_reg = B53_DUPLEX_STAT_GE,
1322 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1323 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1324 .sw_ops = &b53_switch_ops,
1325 },
1326 {
1327 .chip_id = BCM53128_DEVICE_ID,
1328 .dev_name = "BCM53128",
1329 .alias = "bcm53128",
1330 .vlans = 4096,
1331 .enabled_ports = 0x1ff,
1332 .cpu_port = B53_CPU_PORT,
1333 .vta_regs = B53_VTA_REGS,
1334 .duplex_reg = B53_DUPLEX_STAT_GE,
1335 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1336 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1337 .sw_ops = &b53_switch_ops,
1338 },
1339 {
1340 .chip_id = BCM63XX_DEVICE_ID,
1341 .dev_name = "BCM63xx",
1342 .alias = "bcm63xx",
1343 .vlans = 4096,
1344 .enabled_ports = 0, /* pdata must provide them */
1345 .cpu_port = B53_CPU_PORT,
1346 .vta_regs = B53_VTA_REGS_63XX,
1347 .duplex_reg = B53_DUPLEX_STAT_63XX,
1348 .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX,
1349 .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX,
1350 .sw_ops = &b53_switch_ops,
1351 },
1352 {
1353 .chip_id = BCM53010_DEVICE_ID,
1354 .dev_name = "BCM53010",
1355 .alias = "bcm53011",
1356 .vlans = 4096,
1357 .enabled_ports = 0x1f,
1358 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1359 .vta_regs = B53_VTA_REGS,
1360 .duplex_reg = B53_DUPLEX_STAT_GE,
1361 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1362 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1363 .sw_ops = &b53_switch_ops,
1364 },
1365 {
1366 .chip_id = BCM53011_DEVICE_ID,
1367 .dev_name = "BCM53011",
1368 .alias = "bcm53011",
1369 .vlans = 4096,
1370 .enabled_ports = 0x1bf,
1371 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1372 .vta_regs = B53_VTA_REGS,
1373 .duplex_reg = B53_DUPLEX_STAT_GE,
1374 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1375 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1376 .sw_ops = &b53_switch_ops,
1377 },
1378 {
1379 .chip_id = BCM53012_DEVICE_ID,
1380 .dev_name = "BCM53012",
1381 .alias = "bcm53011",
1382 .vlans = 4096,
1383 .enabled_ports = 0x1bf,
1384 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1385 .vta_regs = B53_VTA_REGS,
1386 .duplex_reg = B53_DUPLEX_STAT_GE,
1387 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1388 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1389 .sw_ops = &b53_switch_ops,
1390 },
1391 {
1392 .chip_id = BCM53018_DEVICE_ID,
1393 .dev_name = "BCM53018",
1394 .alias = "bcm53018",
1395 .vlans = 4096,
1396 .enabled_ports = 0x1f,
1397 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1398 .vta_regs = B53_VTA_REGS,
1399 .duplex_reg = B53_DUPLEX_STAT_GE,
1400 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1401 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1402 .sw_ops = &b53_switch_ops,
1403 },
1404 {
1405 .chip_id = BCM53019_DEVICE_ID,
1406 .dev_name = "BCM53019",
1407 .alias = "bcm53019",
1408 .vlans = 4096,
1409 .enabled_ports = 0x1f,
1410 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1411 .vta_regs = B53_VTA_REGS,
1412 .duplex_reg = B53_DUPLEX_STAT_GE,
1413 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1414 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1415 .sw_ops = &b53_switch_ops,
1416 },
1417 };
1418
1419 static int b53_switch_init_of(struct b53_device *dev)
1420 {
1421 struct device_node *dn, *pn;
1422 const char *alias;
1423 u32 port_num;
1424 u16 ports = 0;
1425
1426 dn = of_get_child_by_name(dev_of_node(dev->dev), "ports");
1427 if (!dn)
1428 return -EINVAL;
1429
1430 for_each_available_child_of_node(dn, pn) {
1431 const char *label;
1432 int len;
1433
1434 if (of_property_read_u32(pn, "reg", &port_num))
1435 continue;
1436
1437 if (port_num > B53_CPU_PORT)
1438 continue;
1439
1440 ports |= BIT(port_num);
1441
1442 label = of_get_property(pn, "label", &len);
1443 if (label && !strcmp(label, "cpu"))
1444 dev->sw_dev.cpu_port = port_num;
1445 }
1446
1447 dev->enabled_ports = ports;
1448
1449 if (!of_property_read_string(dev_of_node(dev->dev), "lede,alias",
1450 &alias))
1451 dev->sw_dev.alias = devm_kstrdup(dev->dev, alias, GFP_KERNEL);
1452
1453 return 0;
1454 }
1455
1456 static int b53_switch_init(struct b53_device *dev)
1457 {
1458 struct switch_dev *sw_dev = &dev->sw_dev;
1459 unsigned i;
1460 int ret;
1461
1462 for (i = 0; i < ARRAY_SIZE(b53_switch_chips); i++) {
1463 const struct b53_chip_data *chip = &b53_switch_chips[i];
1464
1465 if (chip->chip_id == dev->chip_id) {
1466 sw_dev->name = chip->dev_name;
1467 if (!sw_dev->alias)
1468 sw_dev->alias = chip->alias;
1469 if (!dev->enabled_ports)
1470 dev->enabled_ports = chip->enabled_ports;
1471 dev->duplex_reg = chip->duplex_reg;
1472 dev->vta_regs[0] = chip->vta_regs[0];
1473 dev->vta_regs[1] = chip->vta_regs[1];
1474 dev->vta_regs[2] = chip->vta_regs[2];
1475 dev->jumbo_pm_reg = chip->jumbo_pm_reg;
1476 sw_dev->ops = chip->sw_ops;
1477 sw_dev->cpu_port = chip->cpu_port;
1478 sw_dev->vlans = chip->vlans;
1479 break;
1480 }
1481 }
1482
1483 if (!sw_dev->name)
1484 return -EINVAL;
1485
1486 /* check which BCM5325x version we have */
1487 if (is5325(dev)) {
1488 u8 vc4;
1489
1490 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
1491
1492 /* check reserved bits */
1493 switch (vc4 & 3) {
1494 case 1:
1495 /* BCM5325E */
1496 break;
1497 case 3:
1498 /* BCM5325F - do not use port 4 */
1499 dev->enabled_ports &= ~BIT(4);
1500 break;
1501 default:
1502 /* On the BCM47XX SoCs this is the supported internal switch.*/
1503 #ifndef CONFIG_BCM47XX
1504 /* BCM5325M */
1505 return -EINVAL;
1506 #else
1507 break;
1508 #endif
1509 }
1510 } else if (dev->chip_id == BCM53115_DEVICE_ID) {
1511 u64 strap_value;
1512
1513 b53_read48(dev, B53_STAT_PAGE, B53_STRAP_VALUE, &strap_value);
1514 /* use second IMP port if GMII is enabled */
1515 if (strap_value & SV_GMII_CTRL_115)
1516 sw_dev->cpu_port = 5;
1517 }
1518
1519 if (dev_of_node(dev->dev)) {
1520 ret = b53_switch_init_of(dev);
1521 if (ret)
1522 return ret;
1523 }
1524
1525 dev->enabled_ports |= BIT(sw_dev->cpu_port);
1526 sw_dev->ports = fls(dev->enabled_ports);
1527
1528 dev->ports = devm_kzalloc(dev->dev,
1529 sizeof(struct b53_port) * sw_dev->ports,
1530 GFP_KERNEL);
1531 if (!dev->ports)
1532 return -ENOMEM;
1533
1534 dev->vlans = devm_kzalloc(dev->dev,
1535 sizeof(struct b53_vlan) * sw_dev->vlans,
1536 GFP_KERNEL);
1537 if (!dev->vlans)
1538 return -ENOMEM;
1539
1540 dev->buf = devm_kzalloc(dev->dev, B53_BUF_SIZE, GFP_KERNEL);
1541 if (!dev->buf)
1542 return -ENOMEM;
1543
1544 dev->reset_gpio = b53_switch_get_reset_gpio(dev);
1545 if (dev->reset_gpio >= 0) {
1546 ret = devm_gpio_request_one(dev->dev, dev->reset_gpio,
1547 GPIOF_OUT_INIT_HIGH, "robo_reset");
1548 if (ret)
1549 return ret;
1550 }
1551
1552 return b53_switch_reset(dev);
1553 }
1554
1555 struct b53_device *b53_switch_alloc(struct device *base, struct b53_io_ops *ops,
1556 void *priv)
1557 {
1558 struct b53_device *dev;
1559
1560 dev = devm_kzalloc(base, sizeof(*dev), GFP_KERNEL);
1561 if (!dev)
1562 return NULL;
1563
1564 dev->dev = base;
1565 dev->ops = ops;
1566 dev->priv = priv;
1567 mutex_init(&dev->reg_mutex);
1568
1569 return dev;
1570 }
1571 EXPORT_SYMBOL(b53_switch_alloc);
1572
1573 int b53_switch_detect(struct b53_device *dev)
1574 {
1575 u32 id32;
1576 u16 tmp;
1577 u8 id8;
1578 int ret;
1579
1580 ret = b53_read8(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id8);
1581 if (ret)
1582 return ret;
1583
1584 switch (id8) {
1585 case 0:
1586 /*
1587 * BCM5325 and BCM5365 do not have this register so reads
1588 * return 0. But the read operation did succeed, so assume
1589 * this is one of them.
1590 *
1591 * Next check if we can write to the 5325's VTA register; for
1592 * 5365 it is read only.
1593 */
1594
1595 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, 0xf);
1596 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, &tmp);
1597
1598 if (tmp == 0xf)
1599 dev->chip_id = BCM5325_DEVICE_ID;
1600 else
1601 dev->chip_id = BCM5365_DEVICE_ID;
1602 break;
1603 case BCM5395_DEVICE_ID:
1604 case BCM5397_DEVICE_ID:
1605 case BCM5398_DEVICE_ID:
1606 dev->chip_id = id8;
1607 break;
1608 default:
1609 ret = b53_read32(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id32);
1610 if (ret)
1611 return ret;
1612
1613 switch (id32) {
1614 case BCM53115_DEVICE_ID:
1615 case BCM53125_DEVICE_ID:
1616 case BCM53128_DEVICE_ID:
1617 case BCM53010_DEVICE_ID:
1618 case BCM53011_DEVICE_ID:
1619 case BCM53012_DEVICE_ID:
1620 case BCM53018_DEVICE_ID:
1621 case BCM53019_DEVICE_ID:
1622 dev->chip_id = id32;
1623 break;
1624 default:
1625 pr_err("unsupported switch detected (BCM53%02x/BCM%x)\n",
1626 id8, id32);
1627 return -ENODEV;
1628 }
1629 }
1630
1631 if (dev->chip_id == BCM5325_DEVICE_ID)
1632 return b53_read8(dev, B53_STAT_PAGE, B53_REV_ID_25,
1633 &dev->core_rev);
1634 else
1635 return b53_read8(dev, B53_MGMT_PAGE, B53_REV_ID,
1636 &dev->core_rev);
1637 }
1638 EXPORT_SYMBOL(b53_switch_detect);
1639
1640 int b53_switch_register(struct b53_device *dev)
1641 {
1642 int ret;
1643
1644 if (dev->pdata) {
1645 dev->chip_id = dev->pdata->chip_id;
1646 dev->enabled_ports = dev->pdata->enabled_ports;
1647 dev->sw_dev.alias = dev->pdata->alias;
1648 }
1649
1650 if (!dev->chip_id && b53_switch_detect(dev))
1651 return -EINVAL;
1652
1653 ret = b53_switch_init(dev);
1654 if (ret)
1655 return ret;
1656
1657 pr_info("found switch: %s, rev %i\n", dev->sw_dev.name, dev->core_rev);
1658
1659 return register_switch(&dev->sw_dev, NULL);
1660 }
1661 EXPORT_SYMBOL(b53_switch_register);
1662
1663 MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>");
1664 MODULE_DESCRIPTION("B53 switch library");
1665 MODULE_LICENSE("Dual BSD/GPL");
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