2 * B53 switch driver main logic
4 * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
21 #include <linux/delay.h>
22 #include <linux/export.h>
23 #include <linux/gpio.h>
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/switch.h>
28 #include <linux/of_net.h>
29 #include <linux/platform_data/b53.h>
34 /* buffer size needed for displaying all MIBs with max'd values */
35 #define B53_BUF_SIZE 1188
43 /* BCM5365 MIB counters */
44 static const struct b53_mib_desc b53_mibs_65
[] = {
45 { 8, 0x00, "TxOctets" },
46 { 4, 0x08, "TxDropPkts" },
47 { 4, 0x10, "TxBroadcastPkts" },
48 { 4, 0x14, "TxMulticastPkts" },
49 { 4, 0x18, "TxUnicastPkts" },
50 { 4, 0x1c, "TxCollisions" },
51 { 4, 0x20, "TxSingleCollision" },
52 { 4, 0x24, "TxMultipleCollision" },
53 { 4, 0x28, "TxDeferredTransmit" },
54 { 4, 0x2c, "TxLateCollision" },
55 { 4, 0x30, "TxExcessiveCollision" },
56 { 4, 0x38, "TxPausePkts" },
57 { 8, 0x44, "RxOctets" },
58 { 4, 0x4c, "RxUndersizePkts" },
59 { 4, 0x50, "RxPausePkts" },
60 { 4, 0x54, "Pkts64Octets" },
61 { 4, 0x58, "Pkts65to127Octets" },
62 { 4, 0x5c, "Pkts128to255Octets" },
63 { 4, 0x60, "Pkts256to511Octets" },
64 { 4, 0x64, "Pkts512to1023Octets" },
65 { 4, 0x68, "Pkts1024to1522Octets" },
66 { 4, 0x6c, "RxOversizePkts" },
67 { 4, 0x70, "RxJabbers" },
68 { 4, 0x74, "RxAlignmentErrors" },
69 { 4, 0x78, "RxFCSErrors" },
70 { 8, 0x7c, "RxGoodOctets" },
71 { 4, 0x84, "RxDropPkts" },
72 { 4, 0x88, "RxUnicastPkts" },
73 { 4, 0x8c, "RxMulticastPkts" },
74 { 4, 0x90, "RxBroadcastPkts" },
75 { 4, 0x94, "RxSAChanges" },
76 { 4, 0x98, "RxFragments" },
80 #define B63XX_MIB_TXB_ID 0 /* TxOctets */
81 #define B63XX_MIB_RXB_ID 14 /* RxOctets */
83 /* BCM63xx MIB counters */
84 static const struct b53_mib_desc b53_mibs_63xx
[] = {
85 { 8, 0x00, "TxOctets" },
86 { 4, 0x08, "TxDropPkts" },
87 { 4, 0x0c, "TxQoSPkts" },
88 { 4, 0x10, "TxBroadcastPkts" },
89 { 4, 0x14, "TxMulticastPkts" },
90 { 4, 0x18, "TxUnicastPkts" },
91 { 4, 0x1c, "TxCollisions" },
92 { 4, 0x20, "TxSingleCollision" },
93 { 4, 0x24, "TxMultipleCollision" },
94 { 4, 0x28, "TxDeferredTransmit" },
95 { 4, 0x2c, "TxLateCollision" },
96 { 4, 0x30, "TxExcessiveCollision" },
97 { 4, 0x38, "TxPausePkts" },
98 { 8, 0x3c, "TxQoSOctets" },
99 { 8, 0x44, "RxOctets" },
100 { 4, 0x4c, "RxUndersizePkts" },
101 { 4, 0x50, "RxPausePkts" },
102 { 4, 0x54, "Pkts64Octets" },
103 { 4, 0x58, "Pkts65to127Octets" },
104 { 4, 0x5c, "Pkts128to255Octets" },
105 { 4, 0x60, "Pkts256to511Octets" },
106 { 4, 0x64, "Pkts512to1023Octets" },
107 { 4, 0x68, "Pkts1024to1522Octets" },
108 { 4, 0x6c, "RxOversizePkts" },
109 { 4, 0x70, "RxJabbers" },
110 { 4, 0x74, "RxAlignmentErrors" },
111 { 4, 0x78, "RxFCSErrors" },
112 { 8, 0x7c, "RxGoodOctets" },
113 { 4, 0x84, "RxDropPkts" },
114 { 4, 0x88, "RxUnicastPkts" },
115 { 4, 0x8c, "RxMulticastPkts" },
116 { 4, 0x90, "RxBroadcastPkts" },
117 { 4, 0x94, "RxSAChanges" },
118 { 4, 0x98, "RxFragments" },
119 { 4, 0xa0, "RxSymbolErrors" },
120 { 4, 0xa4, "RxQoSPkts" },
121 { 8, 0xa8, "RxQoSOctets" },
122 { 4, 0xb0, "Pkts1523to2047Octets" },
123 { 4, 0xb4, "Pkts2048to4095Octets" },
124 { 4, 0xb8, "Pkts4096to8191Octets" },
125 { 4, 0xbc, "Pkts8192to9728Octets" },
126 { 4, 0xc0, "RxDiscarded" },
130 #define B53XX_MIB_TXB_ID 0 /* TxOctets */
131 #define B53XX_MIB_RXB_ID 12 /* RxOctets */
134 static const struct b53_mib_desc b53_mibs
[] = {
135 { 8, 0x00, "TxOctets" },
136 { 4, 0x08, "TxDropPkts" },
137 { 4, 0x10, "TxBroadcastPkts" },
138 { 4, 0x14, "TxMulticastPkts" },
139 { 4, 0x18, "TxUnicastPkts" },
140 { 4, 0x1c, "TxCollisions" },
141 { 4, 0x20, "TxSingleCollision" },
142 { 4, 0x24, "TxMultipleCollision" },
143 { 4, 0x28, "TxDeferredTransmit" },
144 { 4, 0x2c, "TxLateCollision" },
145 { 4, 0x30, "TxExcessiveCollision" },
146 { 4, 0x38, "TxPausePkts" },
147 { 8, 0x50, "RxOctets" },
148 { 4, 0x58, "RxUndersizePkts" },
149 { 4, 0x5c, "RxPausePkts" },
150 { 4, 0x60, "Pkts64Octets" },
151 { 4, 0x64, "Pkts65to127Octets" },
152 { 4, 0x68, "Pkts128to255Octets" },
153 { 4, 0x6c, "Pkts256to511Octets" },
154 { 4, 0x70, "Pkts512to1023Octets" },
155 { 4, 0x74, "Pkts1024to1522Octets" },
156 { 4, 0x78, "RxOversizePkts" },
157 { 4, 0x7c, "RxJabbers" },
158 { 4, 0x80, "RxAlignmentErrors" },
159 { 4, 0x84, "RxFCSErrors" },
160 { 8, 0x88, "RxGoodOctets" },
161 { 4, 0x90, "RxDropPkts" },
162 { 4, 0x94, "RxUnicastPkts" },
163 { 4, 0x98, "RxMulticastPkts" },
164 { 4, 0x9c, "RxBroadcastPkts" },
165 { 4, 0xa0, "RxSAChanges" },
166 { 4, 0xa4, "RxFragments" },
167 { 4, 0xa8, "RxJumboPkts" },
168 { 4, 0xac, "RxSymbolErrors" },
169 { 4, 0xc0, "RxDiscarded" },
173 static int b53_do_vlan_op(struct b53_device
*dev
, u8 op
)
177 b53_write8(dev
, B53_ARLIO_PAGE
, dev
->vta_regs
[0], VTA_START_CMD
| op
);
179 for (i
= 0; i
< 10; i
++) {
182 b53_read8(dev
, B53_ARLIO_PAGE
, dev
->vta_regs
[0], &vta
);
183 if (!(vta
& VTA_START_CMD
))
186 usleep_range(100, 200);
192 static void b53_set_vlan_entry(struct b53_device
*dev
, u16 vid
, u16 members
,
199 entry
= ((untag
& VA_UNTAG_MASK_25
) << VA_UNTAG_S_25
) |
201 if (dev
->core_rev
>= 3)
202 entry
|= VA_VALID_25_R4
| vid
<< VA_VID_HIGH_S
;
204 entry
|= VA_VALID_25
;
207 b53_write32(dev
, B53_VLAN_PAGE
, B53_VLAN_WRITE_25
, entry
);
208 b53_write16(dev
, B53_VLAN_PAGE
, B53_VLAN_TABLE_ACCESS_25
, vid
|
209 VTA_RW_STATE_WR
| VTA_RW_OP_EN
);
210 } else if (is5365(dev
)) {
214 entry
= ((untag
& VA_UNTAG_MASK_65
) << VA_UNTAG_S_65
) |
215 members
| VA_VALID_65
;
217 b53_write16(dev
, B53_VLAN_PAGE
, B53_VLAN_WRITE_65
, entry
);
218 b53_write16(dev
, B53_VLAN_PAGE
, B53_VLAN_TABLE_ACCESS_65
, vid
|
219 VTA_RW_STATE_WR
| VTA_RW_OP_EN
);
221 b53_write16(dev
, B53_ARLIO_PAGE
, dev
->vta_regs
[1], vid
);
222 b53_write32(dev
, B53_ARLIO_PAGE
, dev
->vta_regs
[2],
223 (untag
<< VTE_UNTAG_S
) | members
);
225 b53_do_vlan_op(dev
, VTA_CMD_WRITE
);
229 void b53_set_forwarding(struct b53_device
*dev
, int enable
)
233 b53_read8(dev
, B53_CTRL_PAGE
, B53_SWITCH_MODE
, &mgmt
);
236 mgmt
|= SM_SW_FWD_EN
;
238 mgmt
&= ~SM_SW_FWD_EN
;
240 b53_write8(dev
, B53_CTRL_PAGE
, B53_SWITCH_MODE
, mgmt
);
243 static void b53_enable_vlan(struct b53_device
*dev
, int enable
)
245 u8 mgmt
, vc0
, vc1
, vc4
= 0, vc5
;
247 b53_read8(dev
, B53_CTRL_PAGE
, B53_SWITCH_MODE
, &mgmt
);
248 b53_read8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL0
, &vc0
);
249 b53_read8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL1
, &vc1
);
251 if (is5325(dev
) || is5365(dev
)) {
252 b53_read8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL4_25
, &vc4
);
253 b53_read8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL5_25
, &vc5
);
254 } else if (is63xx(dev
)) {
255 b53_read8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL4_63XX
, &vc4
);
256 b53_read8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL5_63XX
, &vc5
);
258 b53_read8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL4
, &vc4
);
259 b53_read8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL5
, &vc5
);
262 mgmt
&= ~SM_SW_FWD_MODE
;
265 vc0
|= VC0_VLAN_EN
| VC0_VID_CHK_EN
| VC0_VID_HASH_VID
;
266 vc1
|= VC1_RX_MCST_UNTAG_EN
| VC1_RX_MCST_FWD_EN
;
267 vc4
&= ~VC4_ING_VID_CHECK_MASK
;
268 vc4
|= VC4_ING_VID_VIO_DROP
<< VC4_ING_VID_CHECK_S
;
269 vc5
|= VC5_DROP_VTABLE_MISS
;
272 vc0
&= ~VC0_RESERVED_1
;
274 if (is5325(dev
) || is5365(dev
))
275 vc1
|= VC1_RX_MCST_TAG_EN
;
277 if (!is5325(dev
) && !is5365(dev
)) {
278 if (dev
->allow_vid_4095
)
279 vc5
|= VC5_VID_FFF_EN
;
281 vc5
&= ~VC5_VID_FFF_EN
;
284 vc0
&= ~(VC0_VLAN_EN
| VC0_VID_CHK_EN
| VC0_VID_HASH_VID
);
285 vc1
&= ~(VC1_RX_MCST_UNTAG_EN
| VC1_RX_MCST_FWD_EN
);
286 vc4
&= ~VC4_ING_VID_CHECK_MASK
;
287 vc5
&= ~VC5_DROP_VTABLE_MISS
;
289 if (is5325(dev
) || is5365(dev
))
290 vc4
|= VC4_ING_VID_VIO_FWD
<< VC4_ING_VID_CHECK_S
;
292 vc4
|= VC4_ING_VID_VIO_TO_IMP
<< VC4_ING_VID_CHECK_S
;
294 if (is5325(dev
) || is5365(dev
))
295 vc1
&= ~VC1_RX_MCST_TAG_EN
;
297 if (!is5325(dev
) && !is5365(dev
))
298 vc5
&= ~VC5_VID_FFF_EN
;
301 b53_write8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL0
, vc0
);
302 b53_write8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL1
, vc1
);
304 if (is5325(dev
) || is5365(dev
)) {
305 /* enable the high 8 bit vid check on 5325 */
306 if (is5325(dev
) && enable
)
307 b53_write8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL3
,
310 b53_write8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL3
, 0);
312 b53_write8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL4_25
, vc4
);
313 b53_write8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL5_25
, vc5
);
314 } else if (is63xx(dev
)) {
315 b53_write16(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL3_63XX
, 0);
316 b53_write8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL4_63XX
, vc4
);
317 b53_write8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL5_63XX
, vc5
);
319 b53_write16(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL3
, 0);
320 b53_write8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL4
, vc4
);
321 b53_write8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL5
, vc5
);
324 b53_write8(dev
, B53_CTRL_PAGE
, B53_SWITCH_MODE
, mgmt
);
327 static int b53_set_jumbo(struct b53_device
*dev
, int enable
, int allow_10_100
)
330 u16 max_size
= JMS_MIN_SIZE
;
332 if (is5325(dev
) || is5365(dev
))
336 port_mask
= dev
->enabled_ports
;
337 max_size
= JMS_MAX_SIZE
;
339 port_mask
|= JPM_10_100_JUMBO_EN
;
342 b53_write32(dev
, B53_JUMBO_PAGE
, dev
->jumbo_pm_reg
, port_mask
);
343 return b53_write16(dev
, B53_JUMBO_PAGE
, dev
->jumbo_size_reg
, max_size
);
346 static int b53_flush_arl(struct b53_device
*dev
)
350 b53_write8(dev
, B53_CTRL_PAGE
, B53_FAST_AGE_CTRL
,
351 FAST_AGE_DONE
| FAST_AGE_DYNAMIC
| FAST_AGE_STATIC
);
353 for (i
= 0; i
< 10; i
++) {
356 b53_read8(dev
, B53_CTRL_PAGE
, B53_FAST_AGE_CTRL
,
359 if (!(fast_age_ctrl
& FAST_AGE_DONE
))
365 pr_warn("time out while flushing ARL\n");
370 static void b53_enable_ports(struct b53_device
*dev
)
374 b53_for_each_port(dev
, i
) {
379 * prevent leaking packets between wan and lan in unmanaged
380 * mode through port vlans.
382 if (dev
->enable_vlan
|| is_cpu_port(dev
, i
))
384 else if (is531x5(dev
) || is5301x(dev
))
385 /* BCM53115 may use a different port as cpu port */
386 pvlan_mask
= BIT(dev
->sw_dev
.cpu_port
);
388 pvlan_mask
= BIT(B53_CPU_PORT
);
390 /* BCM5325 CPU port is at 8 */
391 if ((is5325(dev
) || is5365(dev
)) && i
== B53_CPU_PORT_25
)
394 if (dev
->chip_id
== BCM5398_DEVICE_ID
&& (i
== 6 || i
== 7))
395 /* disable unused ports 6 & 7 */
396 port_ctrl
= PORT_CTRL_RX_DISABLE
| PORT_CTRL_TX_DISABLE
;
397 else if (i
== B53_CPU_PORT
)
398 port_ctrl
= PORT_CTRL_RX_BCST_EN
|
399 PORT_CTRL_RX_MCST_EN
|
400 PORT_CTRL_RX_UCST_EN
;
404 b53_write16(dev
, B53_PVLAN_PAGE
, B53_PVLAN_PORT_MASK(i
),
407 /* port state is handled by bcm63xx_enet driver */
408 if (!is63xx(dev
) && !(is5301x(dev
) && i
== 6))
409 b53_write8(dev
, B53_CTRL_PAGE
, B53_PORT_CTRL(i
),
414 static void b53_enable_mib(struct b53_device
*dev
)
418 b53_read8(dev
, B53_MGMT_PAGE
, B53_GLOBAL_CONFIG
, &gc
);
420 gc
&= ~(GC_RESET_MIB
| GC_MIB_AC_EN
);
422 b53_write8(dev
, B53_MGMT_PAGE
, B53_GLOBAL_CONFIG
, gc
);
425 static int b53_apply(struct b53_device
*dev
)
429 /* clear all vlan entries */
430 if (is5325(dev
) || is5365(dev
)) {
431 for (i
= 1; i
< dev
->sw_dev
.vlans
; i
++)
432 b53_set_vlan_entry(dev
, i
, 0, 0);
434 b53_do_vlan_op(dev
, VTA_CMD_CLEAR
);
437 b53_enable_vlan(dev
, dev
->enable_vlan
);
439 /* fill VLAN table */
440 if (dev
->enable_vlan
) {
441 for (i
= 0; i
< dev
->sw_dev
.vlans
; i
++) {
442 struct b53_vlan
*vlan
= &dev
->vlans
[i
];
447 b53_set_vlan_entry(dev
, i
, vlan
->members
, vlan
->untag
);
450 b53_for_each_port(dev
, i
)
451 b53_write16(dev
, B53_VLAN_PAGE
,
452 B53_VLAN_PORT_DEF_TAG(i
),
455 b53_for_each_port(dev
, i
)
456 b53_write16(dev
, B53_VLAN_PAGE
,
457 B53_VLAN_PORT_DEF_TAG(i
), 1);
461 b53_enable_ports(dev
);
463 if (!is5325(dev
) && !is5365(dev
))
464 b53_set_jumbo(dev
, dev
->enable_jumbo
, 1);
469 static void b53_switch_reset_gpio(struct b53_device
*dev
)
471 int gpio
= dev
->reset_gpio
;
477 * Reset sequence: RESET low(50ms)->high(20ms)
479 gpio_set_value(gpio
, 0);
482 gpio_set_value(gpio
, 1);
485 dev
->current_page
= 0xff;
488 static int b53_configure_ports_of(struct b53_device
*dev
)
490 struct device_node
*dn
, *pn
;
493 dn
= of_get_child_by_name(dev_of_node(dev
->dev
), "ports");
495 for_each_available_child_of_node(dn
, pn
) {
496 struct device_node
*fixed_link
;
498 if (of_property_read_u32(pn
, "reg", &port_num
))
501 if (port_num
> B53_CPU_PORT
)
504 fixed_link
= of_get_child_by_name(pn
, "fixed-link");
507 u8 po
= GMII_PO_LINK
;
508 int mode
= of_get_phy_mode(pn
);
510 if (!of_property_read_u32(fixed_link
, "speed", &spd
)) {
513 po
|= GMII_PO_SPEED_10M
;
516 po
|= GMII_PO_SPEED_100M
;
519 if (is_imp_port(dev
, port_num
))
520 po
|= PORT_OVERRIDE_SPEED_2000M
;
522 po
|= GMII_PO_SPEED_2000M
;
525 po
|= GMII_PO_SPEED_1000M
;
530 if (of_property_read_bool(fixed_link
, "full-duplex"))
531 po
|= PORT_OVERRIDE_FULL_DUPLEX
;
532 if (of_property_read_bool(fixed_link
, "pause"))
533 po
|= GMII_PO_RX_FLOW
;
534 if (of_property_read_bool(fixed_link
, "asym-pause"))
535 po
|= GMII_PO_TX_FLOW
;
537 if (is_imp_port(dev
, port_num
)) {
538 po
|= PORT_OVERRIDE_EN
;
541 mode
== PHY_INTERFACE_MODE_REVMII
)
542 po
|= PORT_OVERRIDE_RV_MII_25
;
544 b53_write8(dev
, B53_CTRL_PAGE
,
545 B53_PORT_OVERRIDE_CTRL
, po
);
548 mode
== PHY_INTERFACE_MODE_REVMII
) {
549 b53_read8(dev
, B53_CTRL_PAGE
,
550 B53_PORT_OVERRIDE_CTRL
, &po
);
551 if (!(po
& PORT_OVERRIDE_RV_MII_25
))
552 pr_err("Failed to enable reverse MII mode\n");
557 b53_write8(dev
, B53_CTRL_PAGE
,
558 B53_GMII_PORT_OVERRIDE_CTRL(port_num
),
567 static int b53_configure_ports(struct b53_device
*dev
)
569 u8 cpu_port
= dev
->sw_dev
.cpu_port
;
571 /* configure MII port if necessary */
573 u8 mii_port_override
;
575 b53_read8(dev
, B53_CTRL_PAGE
, B53_PORT_OVERRIDE_CTRL
,
577 /* reverse mii needs to be enabled */
578 if (!(mii_port_override
& PORT_OVERRIDE_RV_MII_25
)) {
579 b53_write8(dev
, B53_CTRL_PAGE
, B53_PORT_OVERRIDE_CTRL
,
580 mii_port_override
| PORT_OVERRIDE_RV_MII_25
);
581 b53_read8(dev
, B53_CTRL_PAGE
, B53_PORT_OVERRIDE_CTRL
,
584 if (!(mii_port_override
& PORT_OVERRIDE_RV_MII_25
)) {
585 pr_err("Failed to enable reverse MII mode\n");
589 } else if (is531x5(dev
) && cpu_port
== B53_CPU_PORT
) {
590 u8 mii_port_override
;
592 b53_read8(dev
, B53_CTRL_PAGE
, B53_PORT_OVERRIDE_CTRL
,
594 b53_write8(dev
, B53_CTRL_PAGE
, B53_PORT_OVERRIDE_CTRL
,
595 mii_port_override
| PORT_OVERRIDE_EN
|
598 /* BCM47189 has another interface connected to the port 5 */
599 if (dev
->enabled_ports
& BIT(5)) {
600 u8 po_reg
= B53_GMII_PORT_OVERRIDE_CTRL(5);
603 b53_read8(dev
, B53_CTRL_PAGE
, po_reg
, &gmii_po
);
604 gmii_po
|= GMII_PO_LINK
|
608 b53_write8(dev
, B53_CTRL_PAGE
, po_reg
, gmii_po
);
610 } else if (is5301x(dev
)) {
612 u8 mii_port_override
;
614 b53_read8(dev
, B53_CTRL_PAGE
, B53_PORT_OVERRIDE_CTRL
,
616 mii_port_override
|= PORT_OVERRIDE_LINK
|
617 PORT_OVERRIDE_RX_FLOW
|
618 PORT_OVERRIDE_TX_FLOW
|
619 PORT_OVERRIDE_SPEED_2000M
|
621 b53_write8(dev
, B53_CTRL_PAGE
, B53_PORT_OVERRIDE_CTRL
,
624 /* TODO: Ports 5 & 7 require some extra handling */
626 u8 po_reg
= B53_GMII_PORT_OVERRIDE_CTRL(cpu_port
);
629 b53_read8(dev
, B53_CTRL_PAGE
, po_reg
, &gmii_po
);
630 gmii_po
|= GMII_PO_LINK
|
635 b53_write8(dev
, B53_CTRL_PAGE
, po_reg
, gmii_po
);
642 static int b53_switch_reset(struct b53_device
*dev
)
647 b53_switch_reset_gpio(dev
);
650 b53_write8(dev
, B53_CTRL_PAGE
, B53_SOFTRESET
, 0x83);
651 b53_write8(dev
, B53_CTRL_PAGE
, B53_SOFTRESET
, 0x00);
654 b53_read8(dev
, B53_CTRL_PAGE
, B53_SWITCH_MODE
, &mgmt
);
656 if (!(mgmt
& SM_SW_FWD_EN
)) {
657 mgmt
&= ~SM_SW_FWD_MODE
;
658 mgmt
|= SM_SW_FWD_EN
;
660 b53_write8(dev
, B53_CTRL_PAGE
, B53_SWITCH_MODE
, mgmt
);
661 b53_read8(dev
, B53_CTRL_PAGE
, B53_SWITCH_MODE
, &mgmt
);
663 if (!(mgmt
& SM_SW_FWD_EN
)) {
664 pr_err("Failed to enable switch!\n");
669 /* enable all ports */
670 b53_enable_ports(dev
);
672 if (dev
->dev
->of_node
)
673 ret
= b53_configure_ports_of(dev
);
675 ret
= b53_configure_ports(dev
);
682 return b53_flush_arl(dev
);
686 * Swconfig glue functions
689 static int b53_global_get_vlan_enable(struct switch_dev
*dev
,
690 const struct switch_attr
*attr
,
691 struct switch_val
*val
)
693 struct b53_device
*priv
= sw_to_b53(dev
);
695 val
->value
.i
= priv
->enable_vlan
;
700 static int b53_global_set_vlan_enable(struct switch_dev
*dev
,
701 const struct switch_attr
*attr
,
702 struct switch_val
*val
)
704 struct b53_device
*priv
= sw_to_b53(dev
);
706 priv
->enable_vlan
= val
->value
.i
;
711 static int b53_global_get_jumbo_enable(struct switch_dev
*dev
,
712 const struct switch_attr
*attr
,
713 struct switch_val
*val
)
715 struct b53_device
*priv
= sw_to_b53(dev
);
717 val
->value
.i
= priv
->enable_jumbo
;
722 static int b53_global_set_jumbo_enable(struct switch_dev
*dev
,
723 const struct switch_attr
*attr
,
724 struct switch_val
*val
)
726 struct b53_device
*priv
= sw_to_b53(dev
);
728 priv
->enable_jumbo
= val
->value
.i
;
733 static int b53_global_get_4095_enable(struct switch_dev
*dev
,
734 const struct switch_attr
*attr
,
735 struct switch_val
*val
)
737 struct b53_device
*priv
= sw_to_b53(dev
);
739 val
->value
.i
= priv
->allow_vid_4095
;
744 static int b53_global_set_4095_enable(struct switch_dev
*dev
,
745 const struct switch_attr
*attr
,
746 struct switch_val
*val
)
748 struct b53_device
*priv
= sw_to_b53(dev
);
750 priv
->allow_vid_4095
= val
->value
.i
;
755 static int b53_global_get_ports(struct switch_dev
*dev
,
756 const struct switch_attr
*attr
,
757 struct switch_val
*val
)
759 struct b53_device
*priv
= sw_to_b53(dev
);
761 val
->len
= snprintf(priv
->buf
, B53_BUF_SIZE
, "0x%04x",
762 priv
->enabled_ports
);
763 val
->value
.s
= priv
->buf
;
768 static int b53_port_get_pvid(struct switch_dev
*dev
, int port
, int *val
)
770 struct b53_device
*priv
= sw_to_b53(dev
);
772 *val
= priv
->ports
[port
].pvid
;
777 static int b53_port_set_pvid(struct switch_dev
*dev
, int port
, int val
)
779 struct b53_device
*priv
= sw_to_b53(dev
);
781 if (val
> 15 && is5325(priv
))
783 if (val
== 4095 && !priv
->allow_vid_4095
)
786 priv
->ports
[port
].pvid
= val
;
791 static int b53_vlan_get_ports(struct switch_dev
*dev
, struct switch_val
*val
)
793 struct b53_device
*priv
= sw_to_b53(dev
);
794 struct switch_port
*port
= &val
->value
.ports
[0];
795 struct b53_vlan
*vlan
= &priv
->vlans
[val
->port_vlan
];
803 for (i
= 0; i
< dev
->ports
; i
++) {
804 if (!(vlan
->members
& BIT(i
)))
808 if (!(vlan
->untag
& BIT(i
)))
809 port
->flags
= BIT(SWITCH_PORT_FLAG_TAGGED
);
821 static int b53_vlan_set_ports(struct switch_dev
*dev
, struct switch_val
*val
)
823 struct b53_device
*priv
= sw_to_b53(dev
);
824 struct switch_port
*port
;
825 struct b53_vlan
*vlan
= &priv
->vlans
[val
->port_vlan
];
828 /* only BCM5325 and BCM5365 supports VID 0 */
829 if (val
->port_vlan
== 0 && !is5325(priv
) && !is5365(priv
))
832 /* VLAN 4095 needs special handling */
833 if (val
->port_vlan
== 4095 && !priv
->allow_vid_4095
)
836 port
= &val
->value
.ports
[0];
839 for (i
= 0; i
< val
->len
; i
++, port
++) {
840 vlan
->members
|= BIT(port
->id
);
842 if (!(port
->flags
& BIT(SWITCH_PORT_FLAG_TAGGED
))) {
843 vlan
->untag
|= BIT(port
->id
);
844 priv
->ports
[port
->id
].pvid
= val
->port_vlan
;
848 /* ignore disabled ports */
849 vlan
->members
&= priv
->enabled_ports
;
850 vlan
->untag
&= priv
->enabled_ports
;
855 static int b53_port_get_link(struct switch_dev
*dev
, int port
,
856 struct switch_port_link
*link
)
858 struct b53_device
*priv
= sw_to_b53(dev
);
860 if (is_cpu_port(priv
, port
)) {
863 link
->speed
= is5325(priv
) || is5365(priv
) ?
864 SWITCH_PORT_SPEED_100
: SWITCH_PORT_SPEED_1000
;
866 } else if (priv
->enabled_ports
& BIT(port
)) {
870 b53_read16(priv
, B53_STAT_PAGE
, B53_LINK_STAT
, &lnk
);
871 b53_read16(priv
, B53_STAT_PAGE
, priv
->duplex_reg
, &duplex
);
873 lnk
= (lnk
>> port
) & 1;
874 duplex
= (duplex
>> port
) & 1;
876 if (is5325(priv
) || is5365(priv
)) {
879 b53_read16(priv
, B53_STAT_PAGE
, B53_SPEED_STAT
, &tmp
);
880 speed
= SPEED_PORT_FE(tmp
, port
);
882 b53_read32(priv
, B53_STAT_PAGE
, B53_SPEED_STAT
, &speed
);
883 speed
= SPEED_PORT_GE(speed
, port
);
888 link
->duplex
= duplex
;
891 link
->speed
= SWITCH_PORT_SPEED_10
;
893 case SPEED_STAT_100M
:
894 link
->speed
= SWITCH_PORT_SPEED_100
;
896 case SPEED_STAT_1000M
:
897 link
->speed
= SWITCH_PORT_SPEED_1000
;
911 static int b53_port_set_link(struct switch_dev
*sw_dev
, int port
,
912 struct switch_port_link
*link
)
914 struct b53_device
*dev
= sw_to_b53(sw_dev
);
917 * TODO: BCM63XX requires special handling as it can have external phys
918 * and ports might be GE or only FE
923 if (port
== sw_dev
->cpu_port
)
926 if (!(BIT(port
) & dev
->enabled_ports
))
929 if (link
->speed
== SWITCH_PORT_SPEED_1000
&&
930 (is5325(dev
) || is5365(dev
)))
933 if (link
->speed
== SWITCH_PORT_SPEED_1000
&& !link
->duplex
)
936 return switch_generic_set_link(sw_dev
, port
, link
);
939 static int b53_phy_read16(struct switch_dev
*dev
, int addr
, u8 reg
, u16
*value
)
941 struct b53_device
*priv
= sw_to_b53(dev
);
943 if (priv
->ops
->phy_read16
)
944 return priv
->ops
->phy_read16(priv
, addr
, reg
, value
);
946 return b53_read16(priv
, B53_PORT_MII_PAGE(addr
), reg
, value
);
949 static int b53_phy_write16(struct switch_dev
*dev
, int addr
, u8 reg
, u16 value
)
951 struct b53_device
*priv
= sw_to_b53(dev
);
953 if (priv
->ops
->phy_write16
)
954 return priv
->ops
->phy_write16(priv
, addr
, reg
, value
);
956 return b53_write16(priv
, B53_PORT_MII_PAGE(addr
), reg
, value
);
959 static int b53_global_reset_switch(struct switch_dev
*dev
)
961 struct b53_device
*priv
= sw_to_b53(dev
);
964 priv
->enable_vlan
= 0;
965 priv
->enable_jumbo
= 0;
966 priv
->allow_vid_4095
= 0;
968 memset(priv
->vlans
, 0, sizeof(*priv
->vlans
) * dev
->vlans
);
969 memset(priv
->ports
, 0, sizeof(*priv
->ports
) * dev
->ports
);
971 return b53_switch_reset(priv
);
974 static int b53_global_apply_config(struct switch_dev
*dev
)
976 struct b53_device
*priv
= sw_to_b53(dev
);
978 /* disable switching */
979 b53_set_forwarding(priv
, 0);
983 /* enable switching */
984 b53_set_forwarding(priv
, 1);
990 static int b53_global_reset_mib(struct switch_dev
*dev
,
991 const struct switch_attr
*attr
,
992 struct switch_val
*val
)
994 struct b53_device
*priv
= sw_to_b53(dev
);
997 b53_read8(priv
, B53_MGMT_PAGE
, B53_GLOBAL_CONFIG
, &gc
);
999 b53_write8(priv
, B53_MGMT_PAGE
, B53_GLOBAL_CONFIG
, gc
| GC_RESET_MIB
);
1001 b53_write8(priv
, B53_MGMT_PAGE
, B53_GLOBAL_CONFIG
, gc
& ~GC_RESET_MIB
);
1007 static int b53_port_get_mib(struct switch_dev
*sw_dev
,
1008 const struct switch_attr
*attr
,
1009 struct switch_val
*val
)
1011 struct b53_device
*dev
= sw_to_b53(sw_dev
);
1012 const struct b53_mib_desc
*mibs
;
1013 int port
= val
->port_vlan
;
1016 if (!(BIT(port
) & dev
->enabled_ports
))
1024 } else if (is63xx(dev
)) {
1025 mibs
= b53_mibs_63xx
;
1032 for (; mibs
->size
> 0; mibs
++) {
1035 if (mibs
->size
== 8) {
1036 b53_read64(dev
, B53_MIB_PAGE(port
), mibs
->offset
, &val
);
1040 b53_read32(dev
, B53_MIB_PAGE(port
), mibs
->offset
,
1045 len
+= snprintf(dev
->buf
+ len
, B53_BUF_SIZE
- len
,
1046 "%-20s: %llu\n", mibs
->name
, val
);
1050 val
->value
.s
= dev
->buf
;
1055 static int b53_port_get_stats(struct switch_dev
*sw_dev
, int port
,
1056 struct switch_port_stats
*stats
)
1058 struct b53_device
*dev
= sw_to_b53(sw_dev
);
1059 const struct b53_mib_desc
*mibs
;
1063 if (!(BIT(port
) & dev
->enabled_ports
))
1066 txb_id
= B53XX_MIB_TXB_ID
;
1067 rxb_id
= B53XX_MIB_RXB_ID
;
1074 } else if (is63xx(dev
)) {
1075 mibs
= b53_mibs_63xx
;
1076 txb_id
= B63XX_MIB_TXB_ID
;
1077 rxb_id
= B63XX_MIB_RXB_ID
;
1084 if (mibs
->size
== 8) {
1085 b53_read64(dev
, B53_MIB_PAGE(port
), mibs
[txb_id
].offset
, &txb
);
1086 b53_read64(dev
, B53_MIB_PAGE(port
), mibs
[rxb_id
].offset
, &rxb
);
1090 b53_read32(dev
, B53_MIB_PAGE(port
), mibs
[txb_id
].offset
, &val32
);
1093 b53_read32(dev
, B53_MIB_PAGE(port
), mibs
[rxb_id
].offset
, &val32
);
1097 stats
->tx_bytes
= txb
;
1098 stats
->rx_bytes
= rxb
;
1103 static struct switch_attr b53_global_ops_25
[] = {
1105 .type
= SWITCH_TYPE_INT
,
1106 .name
= "enable_vlan",
1107 .description
= "Enable VLAN mode",
1108 .set
= b53_global_set_vlan_enable
,
1109 .get
= b53_global_get_vlan_enable
,
1113 .type
= SWITCH_TYPE_STRING
,
1115 .description
= "Available ports (as bitmask)",
1116 .get
= b53_global_get_ports
,
1120 static struct switch_attr b53_global_ops_65
[] = {
1122 .type
= SWITCH_TYPE_INT
,
1123 .name
= "enable_vlan",
1124 .description
= "Enable VLAN mode",
1125 .set
= b53_global_set_vlan_enable
,
1126 .get
= b53_global_get_vlan_enable
,
1130 .type
= SWITCH_TYPE_STRING
,
1132 .description
= "Available ports (as bitmask)",
1133 .get
= b53_global_get_ports
,
1136 .type
= SWITCH_TYPE_INT
,
1137 .name
= "reset_mib",
1138 .description
= "Reset MIB counters",
1139 .set
= b53_global_reset_mib
,
1143 static struct switch_attr b53_global_ops
[] = {
1145 .type
= SWITCH_TYPE_INT
,
1146 .name
= "enable_vlan",
1147 .description
= "Enable VLAN mode",
1148 .set
= b53_global_set_vlan_enable
,
1149 .get
= b53_global_get_vlan_enable
,
1153 .type
= SWITCH_TYPE_STRING
,
1155 .description
= "Available Ports (as bitmask)",
1156 .get
= b53_global_get_ports
,
1159 .type
= SWITCH_TYPE_INT
,
1160 .name
= "reset_mib",
1161 .description
= "Reset MIB counters",
1162 .set
= b53_global_reset_mib
,
1165 .type
= SWITCH_TYPE_INT
,
1166 .name
= "enable_jumbo",
1167 .description
= "Enable Jumbo Frames",
1168 .set
= b53_global_set_jumbo_enable
,
1169 .get
= b53_global_get_jumbo_enable
,
1173 .type
= SWITCH_TYPE_INT
,
1174 .name
= "allow_vid_4095",
1175 .description
= "Allow VID 4095",
1176 .set
= b53_global_set_4095_enable
,
1177 .get
= b53_global_get_4095_enable
,
1182 static struct switch_attr b53_port_ops
[] = {
1184 .type
= SWITCH_TYPE_STRING
,
1186 .description
= "Get port's MIB counters",
1187 .get
= b53_port_get_mib
,
1191 static struct switch_attr b53_no_ops
[] = {
1194 static const struct switch_dev_ops b53_switch_ops_25
= {
1196 .attr
= b53_global_ops_25
,
1197 .n_attr
= ARRAY_SIZE(b53_global_ops_25
),
1201 .n_attr
= ARRAY_SIZE(b53_no_ops
),
1205 .n_attr
= ARRAY_SIZE(b53_no_ops
),
1208 .get_vlan_ports
= b53_vlan_get_ports
,
1209 .set_vlan_ports
= b53_vlan_set_ports
,
1210 .get_port_pvid
= b53_port_get_pvid
,
1211 .set_port_pvid
= b53_port_set_pvid
,
1212 .apply_config
= b53_global_apply_config
,
1213 .reset_switch
= b53_global_reset_switch
,
1214 .get_port_link
= b53_port_get_link
,
1215 .set_port_link
= b53_port_set_link
,
1216 .get_port_stats
= b53_port_get_stats
,
1217 .phy_read16
= b53_phy_read16
,
1218 .phy_write16
= b53_phy_write16
,
1221 static const struct switch_dev_ops b53_switch_ops_65
= {
1223 .attr
= b53_global_ops_65
,
1224 .n_attr
= ARRAY_SIZE(b53_global_ops_65
),
1227 .attr
= b53_port_ops
,
1228 .n_attr
= ARRAY_SIZE(b53_port_ops
),
1232 .n_attr
= ARRAY_SIZE(b53_no_ops
),
1235 .get_vlan_ports
= b53_vlan_get_ports
,
1236 .set_vlan_ports
= b53_vlan_set_ports
,
1237 .get_port_pvid
= b53_port_get_pvid
,
1238 .set_port_pvid
= b53_port_set_pvid
,
1239 .apply_config
= b53_global_apply_config
,
1240 .reset_switch
= b53_global_reset_switch
,
1241 .get_port_link
= b53_port_get_link
,
1242 .set_port_link
= b53_port_set_link
,
1243 .get_port_stats
= b53_port_get_stats
,
1244 .phy_read16
= b53_phy_read16
,
1245 .phy_write16
= b53_phy_write16
,
1248 static const struct switch_dev_ops b53_switch_ops
= {
1250 .attr
= b53_global_ops
,
1251 .n_attr
= ARRAY_SIZE(b53_global_ops
),
1254 .attr
= b53_port_ops
,
1255 .n_attr
= ARRAY_SIZE(b53_port_ops
),
1259 .n_attr
= ARRAY_SIZE(b53_no_ops
),
1262 .get_vlan_ports
= b53_vlan_get_ports
,
1263 .set_vlan_ports
= b53_vlan_set_ports
,
1264 .get_port_pvid
= b53_port_get_pvid
,
1265 .set_port_pvid
= b53_port_set_pvid
,
1266 .apply_config
= b53_global_apply_config
,
1267 .reset_switch
= b53_global_reset_switch
,
1268 .get_port_link
= b53_port_get_link
,
1269 .set_port_link
= b53_port_set_link
,
1270 .get_port_stats
= b53_port_get_stats
,
1271 .phy_read16
= b53_phy_read16
,
1272 .phy_write16
= b53_phy_write16
,
1275 struct b53_chip_data
{
1277 const char *dev_name
;
1286 const struct switch_dev_ops
*sw_ops
;
1289 #define B53_VTA_REGS \
1290 { B53_VT_ACCESS, B53_VT_INDEX, B53_VT_ENTRY }
1291 #define B53_VTA_REGS_9798 \
1292 { B53_VT_ACCESS_9798, B53_VT_INDEX_9798, B53_VT_ENTRY_9798 }
1293 #define B53_VTA_REGS_63XX \
1294 { B53_VT_ACCESS_63XX, B53_VT_INDEX_63XX, B53_VT_ENTRY_63XX }
1296 static const struct b53_chip_data b53_switch_chips
[] = {
1298 .chip_id
= BCM5325_DEVICE_ID
,
1299 .dev_name
= "BCM5325",
1302 .enabled_ports
= 0x1f,
1303 .cpu_port
= B53_CPU_PORT_25
,
1304 .duplex_reg
= B53_DUPLEX_STAT_FE
,
1305 .sw_ops
= &b53_switch_ops_25
,
1308 .chip_id
= BCM5365_DEVICE_ID
,
1309 .dev_name
= "BCM5365",
1312 .enabled_ports
= 0x1f,
1313 .cpu_port
= B53_CPU_PORT_25
,
1314 .duplex_reg
= B53_DUPLEX_STAT_FE
,
1315 .sw_ops
= &b53_switch_ops_65
,
1318 .chip_id
= BCM5395_DEVICE_ID
,
1319 .dev_name
= "BCM5395",
1322 .enabled_ports
= 0x1f,
1323 .cpu_port
= B53_CPU_PORT
,
1324 .vta_regs
= B53_VTA_REGS
,
1325 .duplex_reg
= B53_DUPLEX_STAT_GE
,
1326 .jumbo_pm_reg
= B53_JUMBO_PORT_MASK
,
1327 .jumbo_size_reg
= B53_JUMBO_MAX_SIZE
,
1328 .sw_ops
= &b53_switch_ops
,
1331 .chip_id
= BCM5397_DEVICE_ID
,
1332 .dev_name
= "BCM5397",
1335 .enabled_ports
= 0x1f,
1336 .cpu_port
= B53_CPU_PORT
,
1337 .vta_regs
= B53_VTA_REGS_9798
,
1338 .duplex_reg
= B53_DUPLEX_STAT_GE
,
1339 .jumbo_pm_reg
= B53_JUMBO_PORT_MASK
,
1340 .jumbo_size_reg
= B53_JUMBO_MAX_SIZE
,
1341 .sw_ops
= &b53_switch_ops
,
1344 .chip_id
= BCM5398_DEVICE_ID
,
1345 .dev_name
= "BCM5398",
1348 .enabled_ports
= 0x7f,
1349 .cpu_port
= B53_CPU_PORT
,
1350 .vta_regs
= B53_VTA_REGS_9798
,
1351 .duplex_reg
= B53_DUPLEX_STAT_GE
,
1352 .jumbo_pm_reg
= B53_JUMBO_PORT_MASK
,
1353 .jumbo_size_reg
= B53_JUMBO_MAX_SIZE
,
1354 .sw_ops
= &b53_switch_ops
,
1357 .chip_id
= BCM53115_DEVICE_ID
,
1358 .dev_name
= "BCM53115",
1359 .alias
= "bcm53115",
1361 .enabled_ports
= 0x1f,
1362 .vta_regs
= B53_VTA_REGS
,
1363 .cpu_port
= B53_CPU_PORT
,
1364 .duplex_reg
= B53_DUPLEX_STAT_GE
,
1365 .jumbo_pm_reg
= B53_JUMBO_PORT_MASK
,
1366 .jumbo_size_reg
= B53_JUMBO_MAX_SIZE
,
1367 .sw_ops
= &b53_switch_ops
,
1370 .chip_id
= BCM53125_DEVICE_ID
,
1371 .dev_name
= "BCM53125",
1372 .alias
= "bcm53125",
1374 .enabled_ports
= 0x1f,
1375 .cpu_port
= B53_CPU_PORT
,
1376 .vta_regs
= B53_VTA_REGS
,
1377 .duplex_reg
= B53_DUPLEX_STAT_GE
,
1378 .jumbo_pm_reg
= B53_JUMBO_PORT_MASK
,
1379 .jumbo_size_reg
= B53_JUMBO_MAX_SIZE
,
1380 .sw_ops
= &b53_switch_ops
,
1383 .chip_id
= BCM53128_DEVICE_ID
,
1384 .dev_name
= "BCM53128",
1385 .alias
= "bcm53128",
1387 .enabled_ports
= 0x1ff,
1388 .cpu_port
= B53_CPU_PORT
,
1389 .vta_regs
= B53_VTA_REGS
,
1390 .duplex_reg
= B53_DUPLEX_STAT_GE
,
1391 .jumbo_pm_reg
= B53_JUMBO_PORT_MASK
,
1392 .jumbo_size_reg
= B53_JUMBO_MAX_SIZE
,
1393 .sw_ops
= &b53_switch_ops
,
1396 .chip_id
= BCM63XX_DEVICE_ID
,
1397 .dev_name
= "BCM63xx",
1400 .enabled_ports
= 0, /* pdata must provide them */
1401 .cpu_port
= B53_CPU_PORT
,
1402 .vta_regs
= B53_VTA_REGS_63XX
,
1403 .duplex_reg
= B53_DUPLEX_STAT_63XX
,
1404 .jumbo_pm_reg
= B53_JUMBO_PORT_MASK_63XX
,
1405 .jumbo_size_reg
= B53_JUMBO_MAX_SIZE_63XX
,
1406 .sw_ops
= &b53_switch_ops
,
1409 .chip_id
= BCM53010_DEVICE_ID
,
1410 .dev_name
= "BCM53010",
1411 .alias
= "bcm53011",
1413 .enabled_ports
= 0x1f,
1414 .cpu_port
= B53_CPU_PORT_25
, /* TODO: auto detect */
1415 .vta_regs
= B53_VTA_REGS
,
1416 .duplex_reg
= B53_DUPLEX_STAT_GE
,
1417 .jumbo_pm_reg
= B53_JUMBO_PORT_MASK
,
1418 .jumbo_size_reg
= B53_JUMBO_MAX_SIZE
,
1419 .sw_ops
= &b53_switch_ops
,
1422 .chip_id
= BCM53011_DEVICE_ID
,
1423 .dev_name
= "BCM53011",
1424 .alias
= "bcm53011",
1426 .enabled_ports
= 0x1bf,
1427 .cpu_port
= B53_CPU_PORT_25
, /* TODO: auto detect */
1428 .vta_regs
= B53_VTA_REGS
,
1429 .duplex_reg
= B53_DUPLEX_STAT_GE
,
1430 .jumbo_pm_reg
= B53_JUMBO_PORT_MASK
,
1431 .jumbo_size_reg
= B53_JUMBO_MAX_SIZE
,
1432 .sw_ops
= &b53_switch_ops
,
1435 .chip_id
= BCM53012_DEVICE_ID
,
1436 .dev_name
= "BCM53012",
1437 .alias
= "bcm53011",
1439 .enabled_ports
= 0x1bf,
1440 .cpu_port
= B53_CPU_PORT_25
, /* TODO: auto detect */
1441 .vta_regs
= B53_VTA_REGS
,
1442 .duplex_reg
= B53_DUPLEX_STAT_GE
,
1443 .jumbo_pm_reg
= B53_JUMBO_PORT_MASK
,
1444 .jumbo_size_reg
= B53_JUMBO_MAX_SIZE
,
1445 .sw_ops
= &b53_switch_ops
,
1448 .chip_id
= BCM53018_DEVICE_ID
,
1449 .dev_name
= "BCM53018",
1450 .alias
= "bcm53018",
1452 .enabled_ports
= 0x1f,
1453 .cpu_port
= B53_CPU_PORT_25
, /* TODO: auto detect */
1454 .vta_regs
= B53_VTA_REGS
,
1455 .duplex_reg
= B53_DUPLEX_STAT_GE
,
1456 .jumbo_pm_reg
= B53_JUMBO_PORT_MASK
,
1457 .jumbo_size_reg
= B53_JUMBO_MAX_SIZE
,
1458 .sw_ops
= &b53_switch_ops
,
1461 .chip_id
= BCM53019_DEVICE_ID
,
1462 .dev_name
= "BCM53019",
1463 .alias
= "bcm53019",
1465 .enabled_ports
= 0x1f,
1466 .cpu_port
= B53_CPU_PORT_25
, /* TODO: auto detect */
1467 .vta_regs
= B53_VTA_REGS
,
1468 .duplex_reg
= B53_DUPLEX_STAT_GE
,
1469 .jumbo_pm_reg
= B53_JUMBO_PORT_MASK
,
1470 .jumbo_size_reg
= B53_JUMBO_MAX_SIZE
,
1471 .sw_ops
= &b53_switch_ops
,
1475 static int b53_switch_init_of(struct b53_device
*dev
)
1477 struct device_node
*dn
, *pn
;
1482 dn
= of_get_child_by_name(dev_of_node(dev
->dev
), "ports");
1486 for_each_available_child_of_node(dn
, pn
) {
1490 if (of_property_read_u32(pn
, "reg", &port_num
))
1493 if (port_num
> B53_CPU_PORT
)
1496 ports
|= BIT(port_num
);
1498 label
= of_get_property(pn
, "label", &len
);
1499 if (label
&& !strcmp(label
, "cpu"))
1500 dev
->sw_dev
.cpu_port
= port_num
;
1503 dev
->enabled_ports
= ports
;
1505 if (!of_property_read_string(dev_of_node(dev
->dev
), "lede,alias",
1507 dev
->sw_dev
.alias
= devm_kstrdup(dev
->dev
, alias
, GFP_KERNEL
);
1512 static int b53_switch_init(struct b53_device
*dev
)
1514 struct switch_dev
*sw_dev
= &dev
->sw_dev
;
1518 for (i
= 0; i
< ARRAY_SIZE(b53_switch_chips
); i
++) {
1519 const struct b53_chip_data
*chip
= &b53_switch_chips
[i
];
1521 if (chip
->chip_id
== dev
->chip_id
) {
1522 sw_dev
->name
= chip
->dev_name
;
1524 sw_dev
->alias
= chip
->alias
;
1525 if (!dev
->enabled_ports
)
1526 dev
->enabled_ports
= chip
->enabled_ports
;
1527 dev
->duplex_reg
= chip
->duplex_reg
;
1528 dev
->vta_regs
[0] = chip
->vta_regs
[0];
1529 dev
->vta_regs
[1] = chip
->vta_regs
[1];
1530 dev
->vta_regs
[2] = chip
->vta_regs
[2];
1531 dev
->jumbo_pm_reg
= chip
->jumbo_pm_reg
;
1532 sw_dev
->ops
= chip
->sw_ops
;
1533 sw_dev
->cpu_port
= chip
->cpu_port
;
1534 sw_dev
->vlans
= chip
->vlans
;
1542 /* check which BCM5325x version we have */
1546 b53_read8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL4_25
, &vc4
);
1548 /* check reserved bits */
1554 /* BCM5325F - do not use port 4 */
1555 dev
->enabled_ports
&= ~BIT(4);
1558 /* On the BCM47XX SoCs this is the supported internal switch.*/
1559 #ifndef CONFIG_BCM47XX
1566 } else if (dev
->chip_id
== BCM53115_DEVICE_ID
) {
1569 b53_read48(dev
, B53_STAT_PAGE
, B53_STRAP_VALUE
, &strap_value
);
1570 /* use second IMP port if GMII is enabled */
1571 if (strap_value
& SV_GMII_CTRL_115
)
1572 sw_dev
->cpu_port
= 5;
1575 if (dev_of_node(dev
->dev
)) {
1576 ret
= b53_switch_init_of(dev
);
1581 dev
->enabled_ports
|= BIT(sw_dev
->cpu_port
);
1582 sw_dev
->ports
= fls(dev
->enabled_ports
);
1584 dev
->ports
= devm_kzalloc(dev
->dev
,
1585 sizeof(struct b53_port
) * sw_dev
->ports
,
1590 dev
->vlans
= devm_kzalloc(dev
->dev
,
1591 sizeof(struct b53_vlan
) * sw_dev
->vlans
,
1596 dev
->buf
= devm_kzalloc(dev
->dev
, B53_BUF_SIZE
, GFP_KERNEL
);
1600 dev
->reset_gpio
= b53_switch_get_reset_gpio(dev
);
1601 if (dev
->reset_gpio
>= 0) {
1602 ret
= devm_gpio_request_one(dev
->dev
, dev
->reset_gpio
,
1603 GPIOF_OUT_INIT_HIGH
, "robo_reset");
1608 return b53_switch_reset(dev
);
1611 struct b53_device
*b53_switch_alloc(struct device
*base
, struct b53_io_ops
*ops
,
1614 struct b53_device
*dev
;
1616 dev
= devm_kzalloc(base
, sizeof(*dev
), GFP_KERNEL
);
1623 mutex_init(&dev
->reg_mutex
);
1627 EXPORT_SYMBOL(b53_switch_alloc
);
1629 int b53_switch_detect(struct b53_device
*dev
)
1636 ret
= b53_read8(dev
, B53_MGMT_PAGE
, B53_DEVICE_ID
, &id8
);
1643 * BCM5325 and BCM5365 do not have this register so reads
1644 * return 0. But the read operation did succeed, so assume
1645 * this is one of them.
1647 * Next check if we can write to the 5325's VTA register; for
1648 * 5365 it is read only.
1651 b53_write16(dev
, B53_VLAN_PAGE
, B53_VLAN_TABLE_ACCESS_25
, 0xf);
1652 b53_read16(dev
, B53_VLAN_PAGE
, B53_VLAN_TABLE_ACCESS_25
, &tmp
);
1655 dev
->chip_id
= BCM5325_DEVICE_ID
;
1657 dev
->chip_id
= BCM5365_DEVICE_ID
;
1659 case BCM5395_DEVICE_ID
:
1660 case BCM5397_DEVICE_ID
:
1661 case BCM5398_DEVICE_ID
:
1665 ret
= b53_read32(dev
, B53_MGMT_PAGE
, B53_DEVICE_ID
, &id32
);
1670 case BCM53115_DEVICE_ID
:
1671 case BCM53125_DEVICE_ID
:
1672 case BCM53128_DEVICE_ID
:
1673 case BCM53010_DEVICE_ID
:
1674 case BCM53011_DEVICE_ID
:
1675 case BCM53012_DEVICE_ID
:
1676 case BCM53018_DEVICE_ID
:
1677 case BCM53019_DEVICE_ID
:
1678 dev
->chip_id
= id32
;
1681 pr_err("unsupported switch detected (BCM53%02x/BCM%x)\n",
1687 if (dev
->chip_id
== BCM5325_DEVICE_ID
)
1688 return b53_read8(dev
, B53_STAT_PAGE
, B53_REV_ID_25
,
1691 return b53_read8(dev
, B53_MGMT_PAGE
, B53_REV_ID
,
1694 EXPORT_SYMBOL(b53_switch_detect
);
1696 int b53_switch_register(struct b53_device
*dev
)
1701 dev
->chip_id
= dev
->pdata
->chip_id
;
1702 dev
->enabled_ports
= dev
->pdata
->enabled_ports
;
1703 dev
->sw_dev
.alias
= dev
->pdata
->alias
;
1706 if (!dev
->chip_id
&& b53_switch_detect(dev
))
1709 ret
= b53_switch_init(dev
);
1713 pr_info("found switch: %s, rev %i\n", dev
->sw_dev
.name
, dev
->core_rev
);
1715 return register_switch(&dev
->sw_dev
, NULL
);
1717 EXPORT_SYMBOL(b53_switch_register
);
1719 MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>");
1720 MODULE_DESCRIPTION("B53 switch library");
1721 MODULE_LICENSE("Dual BSD/GPL");