2 * B53 switch driver main logic
4 * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
21 #include <linux/delay.h>
22 #include <linux/export.h>
23 #include <linux/gpio.h>
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/switch.h>
27 #include <linux/phy.h>
29 #include <linux/of_net.h>
30 #include <linux/platform_data/b53.h>
35 /* buffer size needed for displaying all MIBs with max'd values */
36 #define B53_BUF_SIZE 1188
44 /* BCM5365 MIB counters */
45 static const struct b53_mib_desc b53_mibs_65
[] = {
46 { 8, 0x00, "TxOctets" },
47 { 4, 0x08, "TxDropPkts" },
48 { 4, 0x10, "TxBroadcastPkts" },
49 { 4, 0x14, "TxMulticastPkts" },
50 { 4, 0x18, "TxUnicastPkts" },
51 { 4, 0x1c, "TxCollisions" },
52 { 4, 0x20, "TxSingleCollision" },
53 { 4, 0x24, "TxMultipleCollision" },
54 { 4, 0x28, "TxDeferredTransmit" },
55 { 4, 0x2c, "TxLateCollision" },
56 { 4, 0x30, "TxExcessiveCollision" },
57 { 4, 0x38, "TxPausePkts" },
58 { 8, 0x44, "RxOctets" },
59 { 4, 0x4c, "RxUndersizePkts" },
60 { 4, 0x50, "RxPausePkts" },
61 { 4, 0x54, "Pkts64Octets" },
62 { 4, 0x58, "Pkts65to127Octets" },
63 { 4, 0x5c, "Pkts128to255Octets" },
64 { 4, 0x60, "Pkts256to511Octets" },
65 { 4, 0x64, "Pkts512to1023Octets" },
66 { 4, 0x68, "Pkts1024to1522Octets" },
67 { 4, 0x6c, "RxOversizePkts" },
68 { 4, 0x70, "RxJabbers" },
69 { 4, 0x74, "RxAlignmentErrors" },
70 { 4, 0x78, "RxFCSErrors" },
71 { 8, 0x7c, "RxGoodOctets" },
72 { 4, 0x84, "RxDropPkts" },
73 { 4, 0x88, "RxUnicastPkts" },
74 { 4, 0x8c, "RxMulticastPkts" },
75 { 4, 0x90, "RxBroadcastPkts" },
76 { 4, 0x94, "RxSAChanges" },
77 { 4, 0x98, "RxFragments" },
81 #define B63XX_MIB_TXB_ID 0 /* TxOctets */
82 #define B63XX_MIB_RXB_ID 14 /* RxOctets */
84 /* BCM63xx MIB counters */
85 static const struct b53_mib_desc b53_mibs_63xx
[] = {
86 { 8, 0x00, "TxOctets" },
87 { 4, 0x08, "TxDropPkts" },
88 { 4, 0x0c, "TxQoSPkts" },
89 { 4, 0x10, "TxBroadcastPkts" },
90 { 4, 0x14, "TxMulticastPkts" },
91 { 4, 0x18, "TxUnicastPkts" },
92 { 4, 0x1c, "TxCollisions" },
93 { 4, 0x20, "TxSingleCollision" },
94 { 4, 0x24, "TxMultipleCollision" },
95 { 4, 0x28, "TxDeferredTransmit" },
96 { 4, 0x2c, "TxLateCollision" },
97 { 4, 0x30, "TxExcessiveCollision" },
98 { 4, 0x38, "TxPausePkts" },
99 { 8, 0x3c, "TxQoSOctets" },
100 { 8, 0x44, "RxOctets" },
101 { 4, 0x4c, "RxUndersizePkts" },
102 { 4, 0x50, "RxPausePkts" },
103 { 4, 0x54, "Pkts64Octets" },
104 { 4, 0x58, "Pkts65to127Octets" },
105 { 4, 0x5c, "Pkts128to255Octets" },
106 { 4, 0x60, "Pkts256to511Octets" },
107 { 4, 0x64, "Pkts512to1023Octets" },
108 { 4, 0x68, "Pkts1024to1522Octets" },
109 { 4, 0x6c, "RxOversizePkts" },
110 { 4, 0x70, "RxJabbers" },
111 { 4, 0x74, "RxAlignmentErrors" },
112 { 4, 0x78, "RxFCSErrors" },
113 { 8, 0x7c, "RxGoodOctets" },
114 { 4, 0x84, "RxDropPkts" },
115 { 4, 0x88, "RxUnicastPkts" },
116 { 4, 0x8c, "RxMulticastPkts" },
117 { 4, 0x90, "RxBroadcastPkts" },
118 { 4, 0x94, "RxSAChanges" },
119 { 4, 0x98, "RxFragments" },
120 { 4, 0xa0, "RxSymbolErrors" },
121 { 4, 0xa4, "RxQoSPkts" },
122 { 8, 0xa8, "RxQoSOctets" },
123 { 4, 0xb0, "Pkts1523to2047Octets" },
124 { 4, 0xb4, "Pkts2048to4095Octets" },
125 { 4, 0xb8, "Pkts4096to8191Octets" },
126 { 4, 0xbc, "Pkts8192to9728Octets" },
127 { 4, 0xc0, "RxDiscarded" },
131 #define B53XX_MIB_TXB_ID 0 /* TxOctets */
132 #define B53XX_MIB_RXB_ID 12 /* RxOctets */
135 static const struct b53_mib_desc b53_mibs
[] = {
136 { 8, 0x00, "TxOctets" },
137 { 4, 0x08, "TxDropPkts" },
138 { 4, 0x10, "TxBroadcastPkts" },
139 { 4, 0x14, "TxMulticastPkts" },
140 { 4, 0x18, "TxUnicastPkts" },
141 { 4, 0x1c, "TxCollisions" },
142 { 4, 0x20, "TxSingleCollision" },
143 { 4, 0x24, "TxMultipleCollision" },
144 { 4, 0x28, "TxDeferredTransmit" },
145 { 4, 0x2c, "TxLateCollision" },
146 { 4, 0x30, "TxExcessiveCollision" },
147 { 4, 0x38, "TxPausePkts" },
148 { 8, 0x50, "RxOctets" },
149 { 4, 0x58, "RxUndersizePkts" },
150 { 4, 0x5c, "RxPausePkts" },
151 { 4, 0x60, "Pkts64Octets" },
152 { 4, 0x64, "Pkts65to127Octets" },
153 { 4, 0x68, "Pkts128to255Octets" },
154 { 4, 0x6c, "Pkts256to511Octets" },
155 { 4, 0x70, "Pkts512to1023Octets" },
156 { 4, 0x74, "Pkts1024to1522Octets" },
157 { 4, 0x78, "RxOversizePkts" },
158 { 4, 0x7c, "RxJabbers" },
159 { 4, 0x80, "RxAlignmentErrors" },
160 { 4, 0x84, "RxFCSErrors" },
161 { 8, 0x88, "RxGoodOctets" },
162 { 4, 0x90, "RxDropPkts" },
163 { 4, 0x94, "RxUnicastPkts" },
164 { 4, 0x98, "RxMulticastPkts" },
165 { 4, 0x9c, "RxBroadcastPkts" },
166 { 4, 0xa0, "RxSAChanges" },
167 { 4, 0xa4, "RxFragments" },
168 { 4, 0xa8, "RxJumboPkts" },
169 { 4, 0xac, "RxSymbolErrors" },
170 { 4, 0xc0, "RxDiscarded" },
174 static int b53_do_vlan_op(struct b53_device
*dev
, u8 op
)
178 b53_write8(dev
, B53_ARLIO_PAGE
, dev
->vta_regs
[0], VTA_START_CMD
| op
);
180 for (i
= 0; i
< 10; i
++) {
183 b53_read8(dev
, B53_ARLIO_PAGE
, dev
->vta_regs
[0], &vta
);
184 if (!(vta
& VTA_START_CMD
))
187 usleep_range(100, 200);
193 static void b53_set_vlan_entry(struct b53_device
*dev
, u16 vid
, u16 members
,
200 entry
= ((untag
& VA_UNTAG_MASK_25
) << VA_UNTAG_S_25
) |
202 if (dev
->core_rev
>= 3)
203 entry
|= VA_VALID_25_R4
| vid
<< VA_VID_HIGH_S
;
205 entry
|= VA_VALID_25
;
208 b53_write32(dev
, B53_VLAN_PAGE
, B53_VLAN_WRITE_25
, entry
);
209 b53_write16(dev
, B53_VLAN_PAGE
, B53_VLAN_TABLE_ACCESS_25
, vid
|
210 VTA_RW_STATE_WR
| VTA_RW_OP_EN
);
211 } else if (is5365(dev
)) {
215 entry
= ((untag
& VA_UNTAG_MASK_65
) << VA_UNTAG_S_65
) |
216 members
| VA_VALID_65
;
218 b53_write16(dev
, B53_VLAN_PAGE
, B53_VLAN_WRITE_65
, entry
);
219 b53_write16(dev
, B53_VLAN_PAGE
, B53_VLAN_TABLE_ACCESS_65
, vid
|
220 VTA_RW_STATE_WR
| VTA_RW_OP_EN
);
222 b53_write16(dev
, B53_ARLIO_PAGE
, dev
->vta_regs
[1], vid
);
223 b53_write32(dev
, B53_ARLIO_PAGE
, dev
->vta_regs
[2],
224 (untag
<< VTE_UNTAG_S
) | members
);
226 b53_do_vlan_op(dev
, VTA_CMD_WRITE
);
230 void b53_set_forwarding(struct b53_device
*dev
, int enable
)
234 b53_read8(dev
, B53_CTRL_PAGE
, B53_SWITCH_MODE
, &mgmt
);
237 mgmt
|= SM_SW_FWD_EN
;
239 mgmt
&= ~SM_SW_FWD_EN
;
241 b53_write8(dev
, B53_CTRL_PAGE
, B53_SWITCH_MODE
, mgmt
);
244 static void b53_enable_vlan(struct b53_device
*dev
, int enable
)
246 u8 mgmt
, vc0
, vc1
, vc4
= 0, vc5
;
248 b53_read8(dev
, B53_CTRL_PAGE
, B53_SWITCH_MODE
, &mgmt
);
249 b53_read8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL0
, &vc0
);
250 b53_read8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL1
, &vc1
);
252 if (is5325(dev
) || is5365(dev
)) {
253 b53_read8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL4_25
, &vc4
);
254 b53_read8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL5_25
, &vc5
);
255 } else if (is63xx(dev
)) {
256 b53_read8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL4_63XX
, &vc4
);
257 b53_read8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL5_63XX
, &vc5
);
259 b53_read8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL4
, &vc4
);
260 b53_read8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL5
, &vc5
);
263 mgmt
&= ~SM_SW_FWD_MODE
;
266 vc0
|= VC0_VLAN_EN
| VC0_VID_CHK_EN
| VC0_VID_HASH_VID
;
267 vc1
|= VC1_RX_MCST_UNTAG_EN
| VC1_RX_MCST_FWD_EN
;
268 vc4
&= ~VC4_ING_VID_CHECK_MASK
;
269 vc4
|= VC4_ING_VID_VIO_DROP
<< VC4_ING_VID_CHECK_S
;
270 vc5
|= VC5_DROP_VTABLE_MISS
;
273 vc0
&= ~VC0_RESERVED_1
;
275 if (is5325(dev
) || is5365(dev
))
276 vc1
|= VC1_RX_MCST_TAG_EN
;
278 if (!is5325(dev
) && !is5365(dev
)) {
279 if (dev
->allow_vid_4095
)
280 vc5
|= VC5_VID_FFF_EN
;
282 vc5
&= ~VC5_VID_FFF_EN
;
285 vc0
&= ~(VC0_VLAN_EN
| VC0_VID_CHK_EN
| VC0_VID_HASH_VID
);
286 vc1
&= ~(VC1_RX_MCST_UNTAG_EN
| VC1_RX_MCST_FWD_EN
);
287 vc4
&= ~VC4_ING_VID_CHECK_MASK
;
288 vc5
&= ~VC5_DROP_VTABLE_MISS
;
290 if (is5325(dev
) || is5365(dev
))
291 vc4
|= VC4_ING_VID_VIO_FWD
<< VC4_ING_VID_CHECK_S
;
293 vc4
|= VC4_ING_VID_VIO_TO_IMP
<< VC4_ING_VID_CHECK_S
;
295 if (is5325(dev
) || is5365(dev
))
296 vc1
&= ~VC1_RX_MCST_TAG_EN
;
298 if (!is5325(dev
) && !is5365(dev
))
299 vc5
&= ~VC5_VID_FFF_EN
;
302 b53_write8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL0
, vc0
);
303 b53_write8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL1
, vc1
);
305 if (is5325(dev
) || is5365(dev
)) {
306 /* enable the high 8 bit vid check on 5325 */
307 if (is5325(dev
) && enable
)
308 b53_write8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL3
,
311 b53_write8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL3
, 0);
313 b53_write8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL4_25
, vc4
);
314 b53_write8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL5_25
, vc5
);
315 } else if (is63xx(dev
)) {
316 b53_write16(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL3_63XX
, 0);
317 b53_write8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL4_63XX
, vc4
);
318 b53_write8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL5_63XX
, vc5
);
320 b53_write16(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL3
, 0);
321 b53_write8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL4
, vc4
);
322 b53_write8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL5
, vc5
);
325 b53_write8(dev
, B53_CTRL_PAGE
, B53_SWITCH_MODE
, mgmt
);
328 static int b53_set_jumbo(struct b53_device
*dev
, int enable
, int allow_10_100
)
331 u16 max_size
= JMS_MIN_SIZE
;
333 if (is5325(dev
) || is5365(dev
))
337 port_mask
= dev
->enabled_ports
;
338 max_size
= JMS_MAX_SIZE
;
340 port_mask
|= JPM_10_100_JUMBO_EN
;
343 b53_write32(dev
, B53_JUMBO_PAGE
, dev
->jumbo_pm_reg
, port_mask
);
344 return b53_write16(dev
, B53_JUMBO_PAGE
, dev
->jumbo_size_reg
, max_size
);
347 static int b53_flush_arl(struct b53_device
*dev
)
351 b53_write8(dev
, B53_CTRL_PAGE
, B53_FAST_AGE_CTRL
,
352 FAST_AGE_DONE
| FAST_AGE_DYNAMIC
| FAST_AGE_STATIC
);
354 for (i
= 0; i
< 10; i
++) {
357 b53_read8(dev
, B53_CTRL_PAGE
, B53_FAST_AGE_CTRL
,
360 if (!(fast_age_ctrl
& FAST_AGE_DONE
))
366 pr_warn("time out while flushing ARL\n");
371 static void b53_enable_ports(struct b53_device
*dev
)
375 b53_for_each_port(dev
, i
) {
380 * prevent leaking packets between wan and lan in unmanaged
381 * mode through port vlans.
383 if (dev
->enable_vlan
|| is_cpu_port(dev
, i
))
385 else if (is531x5(dev
) || is5301x(dev
))
386 /* BCM53115 may use a different port as cpu port */
387 pvlan_mask
= BIT(dev
->sw_dev
.cpu_port
);
389 pvlan_mask
= BIT(B53_CPU_PORT
);
391 /* BCM5325 CPU port is at 8 */
392 if ((is5325(dev
) || is5365(dev
)) && i
== B53_CPU_PORT_25
)
395 if (dev
->chip_id
== BCM5398_DEVICE_ID
&& (i
== 6 || i
== 7))
396 /* disable unused ports 6 & 7 */
397 port_ctrl
= PORT_CTRL_RX_DISABLE
| PORT_CTRL_TX_DISABLE
;
398 else if (i
== B53_CPU_PORT
)
399 port_ctrl
= PORT_CTRL_RX_BCST_EN
|
400 PORT_CTRL_RX_MCST_EN
|
401 PORT_CTRL_RX_UCST_EN
;
405 b53_write16(dev
, B53_PVLAN_PAGE
, B53_PVLAN_PORT_MASK(i
),
408 /* port state is handled by bcm63xx_enet driver */
409 if (!is63xx(dev
) && !(is5301x(dev
) && i
== 6))
410 b53_write8(dev
, B53_CTRL_PAGE
, B53_PORT_CTRL(i
),
415 static void b53_enable_mib(struct b53_device
*dev
)
419 b53_read8(dev
, B53_MGMT_PAGE
, B53_GLOBAL_CONFIG
, &gc
);
421 gc
&= ~(GC_RESET_MIB
| GC_MIB_AC_EN
);
423 b53_write8(dev
, B53_MGMT_PAGE
, B53_GLOBAL_CONFIG
, gc
);
426 static int b53_apply(struct b53_device
*dev
)
430 /* clear all vlan entries */
431 if (is5325(dev
) || is5365(dev
)) {
432 for (i
= 1; i
< dev
->sw_dev
.vlans
; i
++)
433 b53_set_vlan_entry(dev
, i
, 0, 0);
435 b53_do_vlan_op(dev
, VTA_CMD_CLEAR
);
438 b53_enable_vlan(dev
, dev
->enable_vlan
);
440 /* fill VLAN table */
441 if (dev
->enable_vlan
) {
442 for (i
= 0; i
< dev
->sw_dev
.vlans
; i
++) {
443 struct b53_vlan
*vlan
= &dev
->vlans
[i
];
448 b53_set_vlan_entry(dev
, i
, vlan
->members
, vlan
->untag
);
451 b53_for_each_port(dev
, i
)
452 b53_write16(dev
, B53_VLAN_PAGE
,
453 B53_VLAN_PORT_DEF_TAG(i
),
456 b53_for_each_port(dev
, i
)
457 b53_write16(dev
, B53_VLAN_PAGE
,
458 B53_VLAN_PORT_DEF_TAG(i
), 1);
462 b53_enable_ports(dev
);
464 if (!is5325(dev
) && !is5365(dev
))
465 b53_set_jumbo(dev
, dev
->enable_jumbo
, 1);
470 static void b53_switch_reset_gpio(struct b53_device
*dev
)
472 int gpio
= dev
->reset_gpio
;
478 * Reset sequence: RESET low(50ms)->high(20ms)
480 gpio_set_value(gpio
, 0);
483 gpio_set_value(gpio
, 1);
486 dev
->current_page
= 0xff;
489 static int b53_configure_ports_of(struct b53_device
*dev
)
491 struct device_node
*dn
, *pn
;
494 dn
= of_get_child_by_name(dev_of_node(dev
->dev
), "ports");
496 for_each_available_child_of_node(dn
, pn
) {
497 struct device_node
*fixed_link
;
499 if (of_property_read_u32(pn
, "reg", &port_num
))
502 if (port_num
> B53_CPU_PORT
)
505 fixed_link
= of_get_child_by_name(pn
, "fixed-link");
508 u8 po
= GMII_PO_LINK
;
509 int mode
= of_get_phy_mode(pn
);
511 if (!of_property_read_u32(fixed_link
, "speed", &spd
)) {
514 po
|= GMII_PO_SPEED_10M
;
517 po
|= GMII_PO_SPEED_100M
;
520 if (is_imp_port(dev
, port_num
))
521 po
|= PORT_OVERRIDE_SPEED_2000M
;
523 po
|= GMII_PO_SPEED_2000M
;
526 po
|= GMII_PO_SPEED_1000M
;
531 if (of_property_read_bool(fixed_link
, "full-duplex"))
532 po
|= PORT_OVERRIDE_FULL_DUPLEX
;
533 if (of_property_read_bool(fixed_link
, "pause"))
534 po
|= GMII_PO_RX_FLOW
;
535 if (of_property_read_bool(fixed_link
, "asym-pause"))
536 po
|= GMII_PO_TX_FLOW
;
538 if (is_imp_port(dev
, port_num
)) {
539 po
|= PORT_OVERRIDE_EN
;
542 mode
== PHY_INTERFACE_MODE_REVMII
)
543 po
|= PORT_OVERRIDE_RV_MII_25
;
545 b53_write8(dev
, B53_CTRL_PAGE
,
546 B53_PORT_OVERRIDE_CTRL
, po
);
549 mode
== PHY_INTERFACE_MODE_REVMII
) {
550 b53_read8(dev
, B53_CTRL_PAGE
,
551 B53_PORT_OVERRIDE_CTRL
, &po
);
552 if (!(po
& PORT_OVERRIDE_RV_MII_25
))
553 pr_err("Failed to enable reverse MII mode\n");
558 b53_write8(dev
, B53_CTRL_PAGE
,
559 B53_GMII_PORT_OVERRIDE_CTRL(port_num
),
568 static int b53_configure_ports(struct b53_device
*dev
)
570 u8 cpu_port
= dev
->sw_dev
.cpu_port
;
572 /* configure MII port if necessary */
574 u8 mii_port_override
;
576 b53_read8(dev
, B53_CTRL_PAGE
, B53_PORT_OVERRIDE_CTRL
,
578 /* reverse mii needs to be enabled */
579 if (!(mii_port_override
& PORT_OVERRIDE_RV_MII_25
)) {
580 b53_write8(dev
, B53_CTRL_PAGE
, B53_PORT_OVERRIDE_CTRL
,
581 mii_port_override
| PORT_OVERRIDE_RV_MII_25
);
582 b53_read8(dev
, B53_CTRL_PAGE
, B53_PORT_OVERRIDE_CTRL
,
585 if (!(mii_port_override
& PORT_OVERRIDE_RV_MII_25
)) {
586 pr_err("Failed to enable reverse MII mode\n");
590 } else if (is531x5(dev
) && cpu_port
== B53_CPU_PORT
) {
591 u8 mii_port_override
;
593 b53_read8(dev
, B53_CTRL_PAGE
, B53_PORT_OVERRIDE_CTRL
,
595 b53_write8(dev
, B53_CTRL_PAGE
, B53_PORT_OVERRIDE_CTRL
,
596 mii_port_override
| PORT_OVERRIDE_EN
|
599 /* BCM47189 has another interface connected to the port 5 */
600 if (dev
->enabled_ports
& BIT(5)) {
601 u8 po_reg
= B53_GMII_PORT_OVERRIDE_CTRL(5);
604 b53_read8(dev
, B53_CTRL_PAGE
, po_reg
, &gmii_po
);
605 gmii_po
|= GMII_PO_LINK
|
609 b53_write8(dev
, B53_CTRL_PAGE
, po_reg
, gmii_po
);
611 } else if (is5301x(dev
)) {
613 u8 mii_port_override
;
615 b53_read8(dev
, B53_CTRL_PAGE
, B53_PORT_OVERRIDE_CTRL
,
617 mii_port_override
|= PORT_OVERRIDE_LINK
|
618 PORT_OVERRIDE_RX_FLOW
|
619 PORT_OVERRIDE_TX_FLOW
|
620 PORT_OVERRIDE_SPEED_2000M
|
622 b53_write8(dev
, B53_CTRL_PAGE
, B53_PORT_OVERRIDE_CTRL
,
625 /* TODO: Ports 5 & 7 require some extra handling */
627 u8 po_reg
= B53_GMII_PORT_OVERRIDE_CTRL(cpu_port
);
630 b53_read8(dev
, B53_CTRL_PAGE
, po_reg
, &gmii_po
);
631 gmii_po
|= GMII_PO_LINK
|
636 b53_write8(dev
, B53_CTRL_PAGE
, po_reg
, gmii_po
);
643 static int b53_switch_reset(struct b53_device
*dev
)
648 b53_switch_reset_gpio(dev
);
651 b53_write8(dev
, B53_CTRL_PAGE
, B53_SOFTRESET
, 0x83);
652 b53_write8(dev
, B53_CTRL_PAGE
, B53_SOFTRESET
, 0x00);
655 b53_read8(dev
, B53_CTRL_PAGE
, B53_SWITCH_MODE
, &mgmt
);
657 if (!(mgmt
& SM_SW_FWD_EN
)) {
658 mgmt
&= ~SM_SW_FWD_MODE
;
659 mgmt
|= SM_SW_FWD_EN
;
661 b53_write8(dev
, B53_CTRL_PAGE
, B53_SWITCH_MODE
, mgmt
);
662 b53_read8(dev
, B53_CTRL_PAGE
, B53_SWITCH_MODE
, &mgmt
);
664 if (!(mgmt
& SM_SW_FWD_EN
)) {
665 pr_err("Failed to enable switch!\n");
670 /* enable all ports */
671 b53_enable_ports(dev
);
673 if (dev
->dev
->of_node
)
674 ret
= b53_configure_ports_of(dev
);
676 ret
= b53_configure_ports(dev
);
683 return b53_flush_arl(dev
);
687 * Swconfig glue functions
690 static int b53_global_get_vlan_enable(struct switch_dev
*dev
,
691 const struct switch_attr
*attr
,
692 struct switch_val
*val
)
694 struct b53_device
*priv
= sw_to_b53(dev
);
696 val
->value
.i
= priv
->enable_vlan
;
701 static int b53_global_set_vlan_enable(struct switch_dev
*dev
,
702 const struct switch_attr
*attr
,
703 struct switch_val
*val
)
705 struct b53_device
*priv
= sw_to_b53(dev
);
707 priv
->enable_vlan
= val
->value
.i
;
712 static int b53_global_get_jumbo_enable(struct switch_dev
*dev
,
713 const struct switch_attr
*attr
,
714 struct switch_val
*val
)
716 struct b53_device
*priv
= sw_to_b53(dev
);
718 val
->value
.i
= priv
->enable_jumbo
;
723 static int b53_global_set_jumbo_enable(struct switch_dev
*dev
,
724 const struct switch_attr
*attr
,
725 struct switch_val
*val
)
727 struct b53_device
*priv
= sw_to_b53(dev
);
729 priv
->enable_jumbo
= val
->value
.i
;
734 static int b53_global_get_4095_enable(struct switch_dev
*dev
,
735 const struct switch_attr
*attr
,
736 struct switch_val
*val
)
738 struct b53_device
*priv
= sw_to_b53(dev
);
740 val
->value
.i
= priv
->allow_vid_4095
;
745 static int b53_global_set_4095_enable(struct switch_dev
*dev
,
746 const struct switch_attr
*attr
,
747 struct switch_val
*val
)
749 struct b53_device
*priv
= sw_to_b53(dev
);
751 priv
->allow_vid_4095
= val
->value
.i
;
756 static int b53_global_get_ports(struct switch_dev
*dev
,
757 const struct switch_attr
*attr
,
758 struct switch_val
*val
)
760 struct b53_device
*priv
= sw_to_b53(dev
);
762 val
->len
= snprintf(priv
->buf
, B53_BUF_SIZE
, "0x%04x",
763 priv
->enabled_ports
);
764 val
->value
.s
= priv
->buf
;
769 static int b53_port_get_pvid(struct switch_dev
*dev
, int port
, int *val
)
771 struct b53_device
*priv
= sw_to_b53(dev
);
773 *val
= priv
->ports
[port
].pvid
;
778 static int b53_port_set_pvid(struct switch_dev
*dev
, int port
, int val
)
780 struct b53_device
*priv
= sw_to_b53(dev
);
782 if (val
> 15 && is5325(priv
))
784 if (val
== 4095 && !priv
->allow_vid_4095
)
787 priv
->ports
[port
].pvid
= val
;
792 static int b53_vlan_get_ports(struct switch_dev
*dev
, struct switch_val
*val
)
794 struct b53_device
*priv
= sw_to_b53(dev
);
795 struct switch_port
*port
= &val
->value
.ports
[0];
796 struct b53_vlan
*vlan
= &priv
->vlans
[val
->port_vlan
];
804 for (i
= 0; i
< dev
->ports
; i
++) {
805 if (!(vlan
->members
& BIT(i
)))
809 if (!(vlan
->untag
& BIT(i
)))
810 port
->flags
= BIT(SWITCH_PORT_FLAG_TAGGED
);
822 static int b53_vlan_set_ports(struct switch_dev
*dev
, struct switch_val
*val
)
824 struct b53_device
*priv
= sw_to_b53(dev
);
825 struct switch_port
*port
;
826 struct b53_vlan
*vlan
= &priv
->vlans
[val
->port_vlan
];
829 /* only BCM5325 and BCM5365 supports VID 0 */
830 if (val
->port_vlan
== 0 && !is5325(priv
) && !is5365(priv
))
833 /* VLAN 4095 needs special handling */
834 if (val
->port_vlan
== 4095 && !priv
->allow_vid_4095
)
837 port
= &val
->value
.ports
[0];
840 for (i
= 0; i
< val
->len
; i
++, port
++) {
841 vlan
->members
|= BIT(port
->id
);
843 if (!(port
->flags
& BIT(SWITCH_PORT_FLAG_TAGGED
))) {
844 vlan
->untag
|= BIT(port
->id
);
845 priv
->ports
[port
->id
].pvid
= val
->port_vlan
;
849 /* ignore disabled ports */
850 vlan
->members
&= priv
->enabled_ports
;
851 vlan
->untag
&= priv
->enabled_ports
;
856 static int b53_port_get_link(struct switch_dev
*dev
, int port
,
857 struct switch_port_link
*link
)
859 struct b53_device
*priv
= sw_to_b53(dev
);
861 if (is_cpu_port(priv
, port
)) {
864 link
->speed
= is5325(priv
) || is5365(priv
) ?
865 SWITCH_PORT_SPEED_100
: SWITCH_PORT_SPEED_1000
;
867 } else if (priv
->enabled_ports
& BIT(port
)) {
871 b53_read16(priv
, B53_STAT_PAGE
, B53_LINK_STAT
, &lnk
);
872 b53_read16(priv
, B53_STAT_PAGE
, priv
->duplex_reg
, &duplex
);
874 lnk
= (lnk
>> port
) & 1;
875 duplex
= (duplex
>> port
) & 1;
877 if (is5325(priv
) || is5365(priv
)) {
880 b53_read16(priv
, B53_STAT_PAGE
, B53_SPEED_STAT
, &tmp
);
881 speed
= SPEED_PORT_FE(tmp
, port
);
883 b53_read32(priv
, B53_STAT_PAGE
, B53_SPEED_STAT
, &speed
);
884 speed
= SPEED_PORT_GE(speed
, port
);
889 link
->duplex
= duplex
;
892 link
->speed
= SWITCH_PORT_SPEED_10
;
894 case SPEED_STAT_100M
:
895 link
->speed
= SWITCH_PORT_SPEED_100
;
897 case SPEED_STAT_1000M
:
898 link
->speed
= SWITCH_PORT_SPEED_1000
;
912 static int b53_port_set_link(struct switch_dev
*sw_dev
, int port
,
913 struct switch_port_link
*link
)
915 struct b53_device
*dev
= sw_to_b53(sw_dev
);
918 * TODO: BCM63XX requires special handling as it can have external phys
919 * and ports might be GE or only FE
924 if (port
== sw_dev
->cpu_port
)
927 if (!(BIT(port
) & dev
->enabled_ports
))
930 if (link
->speed
== SWITCH_PORT_SPEED_1000
&&
931 (is5325(dev
) || is5365(dev
)))
934 if (link
->speed
== SWITCH_PORT_SPEED_1000
&& !link
->duplex
)
937 return switch_generic_set_link(sw_dev
, port
, link
);
940 static int b53_phy_read16(struct switch_dev
*dev
, int addr
, u8 reg
, u16
*value
)
942 struct b53_device
*priv
= sw_to_b53(dev
);
944 if (priv
->ops
->phy_read16
)
945 return priv
->ops
->phy_read16(priv
, addr
, reg
, value
);
947 return b53_read16(priv
, B53_PORT_MII_PAGE(addr
), reg
, value
);
950 static int b53_phy_write16(struct switch_dev
*dev
, int addr
, u8 reg
, u16 value
)
952 struct b53_device
*priv
= sw_to_b53(dev
);
954 if (priv
->ops
->phy_write16
)
955 return priv
->ops
->phy_write16(priv
, addr
, reg
, value
);
957 return b53_write16(priv
, B53_PORT_MII_PAGE(addr
), reg
, value
);
960 static int b53_global_reset_switch(struct switch_dev
*dev
)
962 struct b53_device
*priv
= sw_to_b53(dev
);
965 priv
->enable_vlan
= 0;
966 priv
->enable_jumbo
= 0;
967 priv
->allow_vid_4095
= 0;
969 memset(priv
->vlans
, 0, sizeof(*priv
->vlans
) * dev
->vlans
);
970 memset(priv
->ports
, 0, sizeof(*priv
->ports
) * dev
->ports
);
972 return b53_switch_reset(priv
);
975 static int b53_global_apply_config(struct switch_dev
*dev
)
977 struct b53_device
*priv
= sw_to_b53(dev
);
979 /* disable switching */
980 b53_set_forwarding(priv
, 0);
984 /* enable switching */
985 b53_set_forwarding(priv
, 1);
991 static int b53_global_reset_mib(struct switch_dev
*dev
,
992 const struct switch_attr
*attr
,
993 struct switch_val
*val
)
995 struct b53_device
*priv
= sw_to_b53(dev
);
998 b53_read8(priv
, B53_MGMT_PAGE
, B53_GLOBAL_CONFIG
, &gc
);
1000 b53_write8(priv
, B53_MGMT_PAGE
, B53_GLOBAL_CONFIG
, gc
| GC_RESET_MIB
);
1002 b53_write8(priv
, B53_MGMT_PAGE
, B53_GLOBAL_CONFIG
, gc
& ~GC_RESET_MIB
);
1008 static int b53_port_get_mib(struct switch_dev
*sw_dev
,
1009 const struct switch_attr
*attr
,
1010 struct switch_val
*val
)
1012 struct b53_device
*dev
= sw_to_b53(sw_dev
);
1013 const struct b53_mib_desc
*mibs
;
1014 int port
= val
->port_vlan
;
1017 if (!(BIT(port
) & dev
->enabled_ports
))
1025 } else if (is63xx(dev
)) {
1026 mibs
= b53_mibs_63xx
;
1033 for (; mibs
->size
> 0; mibs
++) {
1036 if (mibs
->size
== 8) {
1037 b53_read64(dev
, B53_MIB_PAGE(port
), mibs
->offset
, &val
);
1041 b53_read32(dev
, B53_MIB_PAGE(port
), mibs
->offset
,
1046 len
+= snprintf(dev
->buf
+ len
, B53_BUF_SIZE
- len
,
1047 "%-20s: %llu\n", mibs
->name
, val
);
1051 val
->value
.s
= dev
->buf
;
1056 static int b53_port_get_stats(struct switch_dev
*sw_dev
, int port
,
1057 struct switch_port_stats
*stats
)
1059 struct b53_device
*dev
= sw_to_b53(sw_dev
);
1060 const struct b53_mib_desc
*mibs
;
1064 if (!(BIT(port
) & dev
->enabled_ports
))
1067 txb_id
= B53XX_MIB_TXB_ID
;
1068 rxb_id
= B53XX_MIB_RXB_ID
;
1075 } else if (is63xx(dev
)) {
1076 mibs
= b53_mibs_63xx
;
1077 txb_id
= B63XX_MIB_TXB_ID
;
1078 rxb_id
= B63XX_MIB_RXB_ID
;
1085 if (mibs
->size
== 8) {
1086 b53_read64(dev
, B53_MIB_PAGE(port
), mibs
[txb_id
].offset
, &txb
);
1087 b53_read64(dev
, B53_MIB_PAGE(port
), mibs
[rxb_id
].offset
, &rxb
);
1091 b53_read32(dev
, B53_MIB_PAGE(port
), mibs
[txb_id
].offset
, &val32
);
1094 b53_read32(dev
, B53_MIB_PAGE(port
), mibs
[rxb_id
].offset
, &val32
);
1098 stats
->tx_bytes
= txb
;
1099 stats
->rx_bytes
= rxb
;
1104 static struct switch_attr b53_global_ops_25
[] = {
1106 .type
= SWITCH_TYPE_INT
,
1107 .name
= "enable_vlan",
1108 .description
= "Enable VLAN mode",
1109 .set
= b53_global_set_vlan_enable
,
1110 .get
= b53_global_get_vlan_enable
,
1114 .type
= SWITCH_TYPE_STRING
,
1116 .description
= "Available ports (as bitmask)",
1117 .get
= b53_global_get_ports
,
1121 static struct switch_attr b53_global_ops_65
[] = {
1123 .type
= SWITCH_TYPE_INT
,
1124 .name
= "enable_vlan",
1125 .description
= "Enable VLAN mode",
1126 .set
= b53_global_set_vlan_enable
,
1127 .get
= b53_global_get_vlan_enable
,
1131 .type
= SWITCH_TYPE_STRING
,
1133 .description
= "Available ports (as bitmask)",
1134 .get
= b53_global_get_ports
,
1137 .type
= SWITCH_TYPE_INT
,
1138 .name
= "reset_mib",
1139 .description
= "Reset MIB counters",
1140 .set
= b53_global_reset_mib
,
1144 static struct switch_attr b53_global_ops
[] = {
1146 .type
= SWITCH_TYPE_INT
,
1147 .name
= "enable_vlan",
1148 .description
= "Enable VLAN mode",
1149 .set
= b53_global_set_vlan_enable
,
1150 .get
= b53_global_get_vlan_enable
,
1154 .type
= SWITCH_TYPE_STRING
,
1156 .description
= "Available Ports (as bitmask)",
1157 .get
= b53_global_get_ports
,
1160 .type
= SWITCH_TYPE_INT
,
1161 .name
= "reset_mib",
1162 .description
= "Reset MIB counters",
1163 .set
= b53_global_reset_mib
,
1166 .type
= SWITCH_TYPE_INT
,
1167 .name
= "enable_jumbo",
1168 .description
= "Enable Jumbo Frames",
1169 .set
= b53_global_set_jumbo_enable
,
1170 .get
= b53_global_get_jumbo_enable
,
1174 .type
= SWITCH_TYPE_INT
,
1175 .name
= "allow_vid_4095",
1176 .description
= "Allow VID 4095",
1177 .set
= b53_global_set_4095_enable
,
1178 .get
= b53_global_get_4095_enable
,
1183 static struct switch_attr b53_port_ops
[] = {
1185 .type
= SWITCH_TYPE_STRING
,
1187 .description
= "Get port's MIB counters",
1188 .get
= b53_port_get_mib
,
1192 static struct switch_attr b53_no_ops
[] = {
1195 static const struct switch_dev_ops b53_switch_ops_25
= {
1197 .attr
= b53_global_ops_25
,
1198 .n_attr
= ARRAY_SIZE(b53_global_ops_25
),
1202 .n_attr
= ARRAY_SIZE(b53_no_ops
),
1206 .n_attr
= ARRAY_SIZE(b53_no_ops
),
1209 .get_vlan_ports
= b53_vlan_get_ports
,
1210 .set_vlan_ports
= b53_vlan_set_ports
,
1211 .get_port_pvid
= b53_port_get_pvid
,
1212 .set_port_pvid
= b53_port_set_pvid
,
1213 .apply_config
= b53_global_apply_config
,
1214 .reset_switch
= b53_global_reset_switch
,
1215 .get_port_link
= b53_port_get_link
,
1216 .set_port_link
= b53_port_set_link
,
1217 .get_port_stats
= b53_port_get_stats
,
1218 .phy_read16
= b53_phy_read16
,
1219 .phy_write16
= b53_phy_write16
,
1222 static const struct switch_dev_ops b53_switch_ops_65
= {
1224 .attr
= b53_global_ops_65
,
1225 .n_attr
= ARRAY_SIZE(b53_global_ops_65
),
1228 .attr
= b53_port_ops
,
1229 .n_attr
= ARRAY_SIZE(b53_port_ops
),
1233 .n_attr
= ARRAY_SIZE(b53_no_ops
),
1236 .get_vlan_ports
= b53_vlan_get_ports
,
1237 .set_vlan_ports
= b53_vlan_set_ports
,
1238 .get_port_pvid
= b53_port_get_pvid
,
1239 .set_port_pvid
= b53_port_set_pvid
,
1240 .apply_config
= b53_global_apply_config
,
1241 .reset_switch
= b53_global_reset_switch
,
1242 .get_port_link
= b53_port_get_link
,
1243 .set_port_link
= b53_port_set_link
,
1244 .get_port_stats
= b53_port_get_stats
,
1245 .phy_read16
= b53_phy_read16
,
1246 .phy_write16
= b53_phy_write16
,
1249 static const struct switch_dev_ops b53_switch_ops
= {
1251 .attr
= b53_global_ops
,
1252 .n_attr
= ARRAY_SIZE(b53_global_ops
),
1255 .attr
= b53_port_ops
,
1256 .n_attr
= ARRAY_SIZE(b53_port_ops
),
1260 .n_attr
= ARRAY_SIZE(b53_no_ops
),
1263 .get_vlan_ports
= b53_vlan_get_ports
,
1264 .set_vlan_ports
= b53_vlan_set_ports
,
1265 .get_port_pvid
= b53_port_get_pvid
,
1266 .set_port_pvid
= b53_port_set_pvid
,
1267 .apply_config
= b53_global_apply_config
,
1268 .reset_switch
= b53_global_reset_switch
,
1269 .get_port_link
= b53_port_get_link
,
1270 .set_port_link
= b53_port_set_link
,
1271 .get_port_stats
= b53_port_get_stats
,
1272 .phy_read16
= b53_phy_read16
,
1273 .phy_write16
= b53_phy_write16
,
1276 struct b53_chip_data
{
1278 const char *dev_name
;
1287 const struct switch_dev_ops
*sw_ops
;
1290 #define B53_VTA_REGS \
1291 { B53_VT_ACCESS, B53_VT_INDEX, B53_VT_ENTRY }
1292 #define B53_VTA_REGS_9798 \
1293 { B53_VT_ACCESS_9798, B53_VT_INDEX_9798, B53_VT_ENTRY_9798 }
1294 #define B53_VTA_REGS_63XX \
1295 { B53_VT_ACCESS_63XX, B53_VT_INDEX_63XX, B53_VT_ENTRY_63XX }
1297 static const struct b53_chip_data b53_switch_chips
[] = {
1299 .chip_id
= BCM5325_DEVICE_ID
,
1300 .dev_name
= "BCM5325",
1303 .enabled_ports
= 0x1f,
1304 .cpu_port
= B53_CPU_PORT_25
,
1305 .duplex_reg
= B53_DUPLEX_STAT_FE
,
1306 .sw_ops
= &b53_switch_ops_25
,
1309 .chip_id
= BCM5365_DEVICE_ID
,
1310 .dev_name
= "BCM5365",
1313 .enabled_ports
= 0x1f,
1314 .cpu_port
= B53_CPU_PORT_25
,
1315 .duplex_reg
= B53_DUPLEX_STAT_FE
,
1316 .sw_ops
= &b53_switch_ops_65
,
1319 .chip_id
= BCM5395_DEVICE_ID
,
1320 .dev_name
= "BCM5395",
1323 .enabled_ports
= 0x1f,
1324 .cpu_port
= B53_CPU_PORT
,
1325 .vta_regs
= B53_VTA_REGS
,
1326 .duplex_reg
= B53_DUPLEX_STAT_GE
,
1327 .jumbo_pm_reg
= B53_JUMBO_PORT_MASK
,
1328 .jumbo_size_reg
= B53_JUMBO_MAX_SIZE
,
1329 .sw_ops
= &b53_switch_ops
,
1332 .chip_id
= BCM5397_DEVICE_ID
,
1333 .dev_name
= "BCM5397",
1336 .enabled_ports
= 0x1f,
1337 .cpu_port
= B53_CPU_PORT
,
1338 .vta_regs
= B53_VTA_REGS_9798
,
1339 .duplex_reg
= B53_DUPLEX_STAT_GE
,
1340 .jumbo_pm_reg
= B53_JUMBO_PORT_MASK
,
1341 .jumbo_size_reg
= B53_JUMBO_MAX_SIZE
,
1342 .sw_ops
= &b53_switch_ops
,
1345 .chip_id
= BCM5398_DEVICE_ID
,
1346 .dev_name
= "BCM5398",
1349 .enabled_ports
= 0x7f,
1350 .cpu_port
= B53_CPU_PORT
,
1351 .vta_regs
= B53_VTA_REGS_9798
,
1352 .duplex_reg
= B53_DUPLEX_STAT_GE
,
1353 .jumbo_pm_reg
= B53_JUMBO_PORT_MASK
,
1354 .jumbo_size_reg
= B53_JUMBO_MAX_SIZE
,
1355 .sw_ops
= &b53_switch_ops
,
1358 .chip_id
= BCM53115_DEVICE_ID
,
1359 .dev_name
= "BCM53115",
1360 .alias
= "bcm53115",
1362 .enabled_ports
= 0x1f,
1363 .vta_regs
= B53_VTA_REGS
,
1364 .cpu_port
= B53_CPU_PORT
,
1365 .duplex_reg
= B53_DUPLEX_STAT_GE
,
1366 .jumbo_pm_reg
= B53_JUMBO_PORT_MASK
,
1367 .jumbo_size_reg
= B53_JUMBO_MAX_SIZE
,
1368 .sw_ops
= &b53_switch_ops
,
1371 .chip_id
= BCM53125_DEVICE_ID
,
1372 .dev_name
= "BCM53125",
1373 .alias
= "bcm53125",
1375 .enabled_ports
= 0x1f,
1376 .cpu_port
= B53_CPU_PORT
,
1377 .vta_regs
= B53_VTA_REGS
,
1378 .duplex_reg
= B53_DUPLEX_STAT_GE
,
1379 .jumbo_pm_reg
= B53_JUMBO_PORT_MASK
,
1380 .jumbo_size_reg
= B53_JUMBO_MAX_SIZE
,
1381 .sw_ops
= &b53_switch_ops
,
1384 .chip_id
= BCM53128_DEVICE_ID
,
1385 .dev_name
= "BCM53128",
1386 .alias
= "bcm53128",
1388 .enabled_ports
= 0x1ff,
1389 .cpu_port
= B53_CPU_PORT
,
1390 .vta_regs
= B53_VTA_REGS
,
1391 .duplex_reg
= B53_DUPLEX_STAT_GE
,
1392 .jumbo_pm_reg
= B53_JUMBO_PORT_MASK
,
1393 .jumbo_size_reg
= B53_JUMBO_MAX_SIZE
,
1394 .sw_ops
= &b53_switch_ops
,
1397 .chip_id
= BCM63XX_DEVICE_ID
,
1398 .dev_name
= "BCM63xx",
1401 .enabled_ports
= 0, /* pdata must provide them */
1402 .cpu_port
= B53_CPU_PORT
,
1403 .vta_regs
= B53_VTA_REGS_63XX
,
1404 .duplex_reg
= B53_DUPLEX_STAT_63XX
,
1405 .jumbo_pm_reg
= B53_JUMBO_PORT_MASK_63XX
,
1406 .jumbo_size_reg
= B53_JUMBO_MAX_SIZE_63XX
,
1407 .sw_ops
= &b53_switch_ops
,
1410 .chip_id
= BCM53010_DEVICE_ID
,
1411 .dev_name
= "BCM53010",
1412 .alias
= "bcm53011",
1414 .enabled_ports
= 0x1f,
1415 .cpu_port
= B53_CPU_PORT_25
, /* TODO: auto detect */
1416 .vta_regs
= B53_VTA_REGS
,
1417 .duplex_reg
= B53_DUPLEX_STAT_GE
,
1418 .jumbo_pm_reg
= B53_JUMBO_PORT_MASK
,
1419 .jumbo_size_reg
= B53_JUMBO_MAX_SIZE
,
1420 .sw_ops
= &b53_switch_ops
,
1423 .chip_id
= BCM53011_DEVICE_ID
,
1424 .dev_name
= "BCM53011",
1425 .alias
= "bcm53011",
1427 .enabled_ports
= 0x1bf,
1428 .cpu_port
= B53_CPU_PORT_25
, /* TODO: auto detect */
1429 .vta_regs
= B53_VTA_REGS
,
1430 .duplex_reg
= B53_DUPLEX_STAT_GE
,
1431 .jumbo_pm_reg
= B53_JUMBO_PORT_MASK
,
1432 .jumbo_size_reg
= B53_JUMBO_MAX_SIZE
,
1433 .sw_ops
= &b53_switch_ops
,
1436 .chip_id
= BCM53012_DEVICE_ID
,
1437 .dev_name
= "BCM53012",
1438 .alias
= "bcm53011",
1440 .enabled_ports
= 0x1bf,
1441 .cpu_port
= B53_CPU_PORT_25
, /* TODO: auto detect */
1442 .vta_regs
= B53_VTA_REGS
,
1443 .duplex_reg
= B53_DUPLEX_STAT_GE
,
1444 .jumbo_pm_reg
= B53_JUMBO_PORT_MASK
,
1445 .jumbo_size_reg
= B53_JUMBO_MAX_SIZE
,
1446 .sw_ops
= &b53_switch_ops
,
1449 .chip_id
= BCM53018_DEVICE_ID
,
1450 .dev_name
= "BCM53018",
1451 .alias
= "bcm53018",
1453 .enabled_ports
= 0x1f,
1454 .cpu_port
= B53_CPU_PORT_25
, /* TODO: auto detect */
1455 .vta_regs
= B53_VTA_REGS
,
1456 .duplex_reg
= B53_DUPLEX_STAT_GE
,
1457 .jumbo_pm_reg
= B53_JUMBO_PORT_MASK
,
1458 .jumbo_size_reg
= B53_JUMBO_MAX_SIZE
,
1459 .sw_ops
= &b53_switch_ops
,
1462 .chip_id
= BCM53019_DEVICE_ID
,
1463 .dev_name
= "BCM53019",
1464 .alias
= "bcm53019",
1466 .enabled_ports
= 0x1f,
1467 .cpu_port
= B53_CPU_PORT_25
, /* TODO: auto detect */
1468 .vta_regs
= B53_VTA_REGS
,
1469 .duplex_reg
= B53_DUPLEX_STAT_GE
,
1470 .jumbo_pm_reg
= B53_JUMBO_PORT_MASK
,
1471 .jumbo_size_reg
= B53_JUMBO_MAX_SIZE
,
1472 .sw_ops
= &b53_switch_ops
,
1476 static int b53_switch_init_of(struct b53_device
*dev
)
1478 struct device_node
*dn
, *pn
;
1483 dn
= of_get_child_by_name(dev_of_node(dev
->dev
), "ports");
1487 for_each_available_child_of_node(dn
, pn
) {
1491 if (of_property_read_u32(pn
, "reg", &port_num
))
1494 if (port_num
> B53_CPU_PORT
)
1497 ports
|= BIT(port_num
);
1499 label
= of_get_property(pn
, "label", &len
);
1500 if (label
&& !strcmp(label
, "cpu"))
1501 dev
->sw_dev
.cpu_port
= port_num
;
1504 dev
->enabled_ports
= ports
;
1506 if (!of_property_read_string(dev_of_node(dev
->dev
), "lede,alias",
1508 dev
->sw_dev
.alias
= devm_kstrdup(dev
->dev
, alias
, GFP_KERNEL
);
1513 static int b53_switch_init(struct b53_device
*dev
)
1515 struct switch_dev
*sw_dev
= &dev
->sw_dev
;
1519 for (i
= 0; i
< ARRAY_SIZE(b53_switch_chips
); i
++) {
1520 const struct b53_chip_data
*chip
= &b53_switch_chips
[i
];
1522 if (chip
->chip_id
== dev
->chip_id
) {
1523 sw_dev
->name
= chip
->dev_name
;
1525 sw_dev
->alias
= chip
->alias
;
1526 if (!dev
->enabled_ports
)
1527 dev
->enabled_ports
= chip
->enabled_ports
;
1528 dev
->duplex_reg
= chip
->duplex_reg
;
1529 dev
->vta_regs
[0] = chip
->vta_regs
[0];
1530 dev
->vta_regs
[1] = chip
->vta_regs
[1];
1531 dev
->vta_regs
[2] = chip
->vta_regs
[2];
1532 dev
->jumbo_pm_reg
= chip
->jumbo_pm_reg
;
1533 sw_dev
->ops
= chip
->sw_ops
;
1534 sw_dev
->cpu_port
= chip
->cpu_port
;
1535 sw_dev
->vlans
= chip
->vlans
;
1543 /* check which BCM5325x version we have */
1547 b53_read8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL4_25
, &vc4
);
1549 /* check reserved bits */
1555 /* BCM5325F - do not use port 4 */
1556 dev
->enabled_ports
&= ~BIT(4);
1559 /* On the BCM47XX SoCs this is the supported internal switch.*/
1560 #ifndef CONFIG_BCM47XX
1567 } else if (dev
->chip_id
== BCM53115_DEVICE_ID
) {
1570 b53_read48(dev
, B53_STAT_PAGE
, B53_STRAP_VALUE
, &strap_value
);
1571 /* use second IMP port if GMII is enabled */
1572 if (strap_value
& SV_GMII_CTRL_115
)
1573 sw_dev
->cpu_port
= 5;
1576 if (dev_of_node(dev
->dev
)) {
1577 ret
= b53_switch_init_of(dev
);
1582 dev
->enabled_ports
|= BIT(sw_dev
->cpu_port
);
1583 sw_dev
->ports
= fls(dev
->enabled_ports
);
1585 dev
->ports
= devm_kzalloc(dev
->dev
,
1586 sizeof(struct b53_port
) * sw_dev
->ports
,
1591 dev
->vlans
= devm_kzalloc(dev
->dev
,
1592 sizeof(struct b53_vlan
) * sw_dev
->vlans
,
1597 dev
->buf
= devm_kzalloc(dev
->dev
, B53_BUF_SIZE
, GFP_KERNEL
);
1601 dev
->reset_gpio
= b53_switch_get_reset_gpio(dev
);
1602 if (dev
->reset_gpio
>= 0) {
1603 ret
= devm_gpio_request_one(dev
->dev
, dev
->reset_gpio
,
1604 GPIOF_OUT_INIT_HIGH
, "robo_reset");
1609 return b53_switch_reset(dev
);
1612 struct b53_device
*b53_switch_alloc(struct device
*base
, struct b53_io_ops
*ops
,
1615 struct b53_device
*dev
;
1617 dev
= devm_kzalloc(base
, sizeof(*dev
), GFP_KERNEL
);
1624 mutex_init(&dev
->reg_mutex
);
1628 EXPORT_SYMBOL(b53_switch_alloc
);
1630 int b53_switch_detect(struct b53_device
*dev
)
1637 ret
= b53_read8(dev
, B53_MGMT_PAGE
, B53_DEVICE_ID
, &id8
);
1644 * BCM5325 and BCM5365 do not have this register so reads
1645 * return 0. But the read operation did succeed, so assume
1646 * this is one of them.
1648 * Next check if we can write to the 5325's VTA register; for
1649 * 5365 it is read only.
1652 b53_write16(dev
, B53_VLAN_PAGE
, B53_VLAN_TABLE_ACCESS_25
, 0xf);
1653 b53_read16(dev
, B53_VLAN_PAGE
, B53_VLAN_TABLE_ACCESS_25
, &tmp
);
1656 dev
->chip_id
= BCM5325_DEVICE_ID
;
1658 dev
->chip_id
= BCM5365_DEVICE_ID
;
1660 case BCM5395_DEVICE_ID
:
1661 case BCM5397_DEVICE_ID
:
1662 case BCM5398_DEVICE_ID
:
1666 ret
= b53_read32(dev
, B53_MGMT_PAGE
, B53_DEVICE_ID
, &id32
);
1671 case BCM53115_DEVICE_ID
:
1672 case BCM53125_DEVICE_ID
:
1673 case BCM53128_DEVICE_ID
:
1674 case BCM53010_DEVICE_ID
:
1675 case BCM53011_DEVICE_ID
:
1676 case BCM53012_DEVICE_ID
:
1677 case BCM53018_DEVICE_ID
:
1678 case BCM53019_DEVICE_ID
:
1679 dev
->chip_id
= id32
;
1682 pr_err("unsupported switch detected (BCM53%02x/BCM%x)\n",
1688 if (dev
->chip_id
== BCM5325_DEVICE_ID
)
1689 return b53_read8(dev
, B53_STAT_PAGE
, B53_REV_ID_25
,
1692 return b53_read8(dev
, B53_MGMT_PAGE
, B53_REV_ID
,
1695 EXPORT_SYMBOL(b53_switch_detect
);
1697 int b53_switch_register(struct b53_device
*dev
)
1702 dev
->chip_id
= dev
->pdata
->chip_id
;
1703 dev
->enabled_ports
= dev
->pdata
->enabled_ports
;
1704 dev
->sw_dev
.alias
= dev
->pdata
->alias
;
1707 if (!dev
->chip_id
&& b53_switch_detect(dev
))
1710 ret
= b53_switch_init(dev
);
1714 pr_info("found switch: %s, rev %i\n", dev
->sw_dev
.name
, dev
->core_rev
);
1716 return register_switch(&dev
->sw_dev
, NULL
);
1718 EXPORT_SYMBOL(b53_switch_register
);
1720 MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>");
1721 MODULE_DESCRIPTION("B53 switch library");
1722 MODULE_LICENSE("Dual BSD/GPL");