2 * B53 switch driver main logic
4 * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
21 #include <linux/delay.h>
22 #include <linux/export.h>
23 #include <linux/gpio.h>
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/switch.h>
27 #include <linux/platform_data/b53.h>
32 /* buffer size needed for displaying all MIBs with max'd values */
33 #define B53_BUF_SIZE 1188
42 /* BCM5365 MIB counters */
43 static const struct b53_mib_desc b53_mibs_65
[] = {
44 { 8, 0x00, "TxOctets" },
45 { 4, 0x08, "TxDropPkts" },
46 { 4, 0x10, "TxBroadcastPkts" },
47 { 4, 0x14, "TxMulticastPkts" },
48 { 4, 0x18, "TxUnicastPkts" },
49 { 4, 0x1c, "TxCollisions" },
50 { 4, 0x20, "TxSingleCollision" },
51 { 4, 0x24, "TxMultipleCollision" },
52 { 4, 0x28, "TxDeferredTransmit" },
53 { 4, 0x2c, "TxLateCollision" },
54 { 4, 0x30, "TxExcessiveCollision" },
55 { 4, 0x38, "TxPausePkts" },
56 { 8, 0x44, "RxOctets" },
57 { 4, 0x4c, "RxUndersizePkts" },
58 { 4, 0x50, "RxPausePkts" },
59 { 4, 0x54, "Pkts64Octets" },
60 { 4, 0x58, "Pkts65to127Octets" },
61 { 4, 0x5c, "Pkts128to255Octets" },
62 { 4, 0x60, "Pkts256to511Octets" },
63 { 4, 0x64, "Pkts512to1023Octets" },
64 { 4, 0x68, "Pkts1024to1522Octets" },
65 { 4, 0x6c, "RxOversizePkts" },
66 { 4, 0x70, "RxJabbers" },
67 { 4, 0x74, "RxAlignmentErrors" },
68 { 4, 0x78, "RxFCSErrors" },
69 { 8, 0x7c, "RxGoodOctets" },
70 { 4, 0x84, "RxDropPkts" },
71 { 4, 0x88, "RxUnicastPkts" },
72 { 4, 0x8c, "RxMulticastPkts" },
73 { 4, 0x90, "RxBroadcastPkts" },
74 { 4, 0x94, "RxSAChanges" },
75 { 4, 0x98, "RxFragments" },
79 /* BCM63xx MIB counters */
80 static const struct b53_mib_desc b53_mibs_63xx
[] = {
81 { 8, 0x00, "TxOctets" },
82 { 4, 0x08, "TxDropPkts" },
83 { 4, 0x0c, "TxQoSPkts" },
84 { 4, 0x10, "TxBroadcastPkts" },
85 { 4, 0x14, "TxMulticastPkts" },
86 { 4, 0x18, "TxUnicastPkts" },
87 { 4, 0x1c, "TxCollisions" },
88 { 4, 0x20, "TxSingleCollision" },
89 { 4, 0x24, "TxMultipleCollision" },
90 { 4, 0x28, "TxDeferredTransmit" },
91 { 4, 0x2c, "TxLateCollision" },
92 { 4, 0x30, "TxExcessiveCollision" },
93 { 4, 0x38, "TxPausePkts" },
94 { 8, 0x3c, "TxQoSOctets" },
95 { 8, 0x44, "RxOctets" },
96 { 4, 0x4c, "RxUndersizePkts" },
97 { 4, 0x50, "RxPausePkts" },
98 { 4, 0x54, "Pkts64Octets" },
99 { 4, 0x58, "Pkts65to127Octets" },
100 { 4, 0x5c, "Pkts128to255Octets" },
101 { 4, 0x60, "Pkts256to511Octets" },
102 { 4, 0x64, "Pkts512to1023Octets" },
103 { 4, 0x68, "Pkts1024to1522Octets" },
104 { 4, 0x6c, "RxOversizePkts" },
105 { 4, 0x70, "RxJabbers" },
106 { 4, 0x74, "RxAlignmentErrors" },
107 { 4, 0x78, "RxFCSErrors" },
108 { 8, 0x7c, "RxGoodOctets" },
109 { 4, 0x84, "RxDropPkts" },
110 { 4, 0x88, "RxUnicastPkts" },
111 { 4, 0x8c, "RxMulticastPkts" },
112 { 4, 0x90, "RxBroadcastPkts" },
113 { 4, 0x94, "RxSAChanges" },
114 { 4, 0x98, "RxFragments" },
115 { 4, 0xa0, "RxSymbolErrors" },
116 { 4, 0xa4, "RxQoSPkts" },
117 { 8, 0xa8, "RxQoSOctets" },
118 { 4, 0xb0, "Pkts1523to2047Octets" },
119 { 4, 0xb4, "Pkts2048to4095Octets" },
120 { 4, 0xb8, "Pkts4096to8191Octets" },
121 { 4, 0xbc, "Pkts8192to9728Octets" },
122 { 4, 0xc0, "RxDiscarded" },
127 static const struct b53_mib_desc b53_mibs
[] = {
128 { 8, 0x00, "TxOctets" },
129 { 4, 0x08, "TxDropPkts" },
130 { 4, 0x10, "TxBroadcastPkts" },
131 { 4, 0x14, "TxMulticastPkts" },
132 { 4, 0x18, "TxUnicastPkts" },
133 { 4, 0x1c, "TxCollisions" },
134 { 4, 0x20, "TxSingleCollision" },
135 { 4, 0x24, "TxMultipleCollision" },
136 { 4, 0x28, "TxDeferredTransmit" },
137 { 4, 0x2c, "TxLateCollision" },
138 { 4, 0x30, "TxExcessiveCollision" },
139 { 4, 0x38, "TxPausePkts" },
140 { 8, 0x50, "RxOctets" },
141 { 4, 0x58, "RxUndersizePkts" },
142 { 4, 0x5c, "RxPausePkts" },
143 { 4, 0x60, "Pkts64Octets" },
144 { 4, 0x64, "Pkts65to127Octets" },
145 { 4, 0x68, "Pkts128to255Octets" },
146 { 4, 0x6c, "Pkts256to511Octets" },
147 { 4, 0x70, "Pkts512to1023Octets" },
148 { 4, 0x74, "Pkts1024to1522Octets" },
149 { 4, 0x78, "RxOversizePkts" },
150 { 4, 0x7c, "RxJabbers" },
151 { 4, 0x80, "RxAlignmentErrors" },
152 { 4, 0x84, "RxFCSErrors" },
153 { 8, 0x88, "RxGoodOctets" },
154 { 4, 0x90, "RxDropPkts" },
155 { 4, 0x94, "RxUnicastPkts" },
156 { 4, 0x98, "RxMulticastPkts" },
157 { 4, 0x9c, "RxBroadcastPkts" },
158 { 4, 0xa0, "RxSAChanges" },
159 { 4, 0xa4, "RxFragments" },
160 { 4, 0xa8, "RxJumboPkts" },
161 { 4, 0xac, "RxSymbolErrors" },
162 { 4, 0xc0, "RxDiscarded" },
166 static int b53_do_vlan_op(struct b53_device
*dev
, u8 op
)
170 b53_write8(dev
, B53_ARLIO_PAGE
, dev
->vta_regs
[0], VTA_START_CMD
| op
);
172 for (i
= 0; i
< 10; i
++) {
175 b53_read8(dev
, B53_ARLIO_PAGE
, dev
->vta_regs
[0], &vta
);
176 if (!(vta
& VTA_START_CMD
))
179 usleep_range(100, 200);
185 static void b53_set_vlan_entry(struct b53_device
*dev
, u16 vid
, u16 members
,
192 entry
= ((untag
& VA_UNTAG_MASK_25
) << VA_UNTAG_S_25
) |
194 if (dev
->core_rev
>= 3)
195 entry
|= VA_VALID_25_R4
| vid
<< VA_VID_HIGH_S
;
197 entry
|= VA_VALID_25
;
200 b53_write32(dev
, B53_VLAN_PAGE
, B53_VLAN_WRITE_25
, entry
);
201 b53_write16(dev
, B53_VLAN_PAGE
, B53_VLAN_TABLE_ACCESS_25
, vid
|
202 VTA_RW_STATE_WR
| VTA_RW_OP_EN
);
203 } else if (is5365(dev
)) {
207 entry
= ((untag
& VA_UNTAG_MASK_65
) << VA_UNTAG_S_65
) |
208 members
| VA_VALID_65
;
210 b53_write16(dev
, B53_VLAN_PAGE
, B53_VLAN_WRITE_65
, entry
);
211 b53_write16(dev
, B53_VLAN_PAGE
, B53_VLAN_TABLE_ACCESS_65
, vid
|
212 VTA_RW_STATE_WR
| VTA_RW_OP_EN
);
214 b53_write16(dev
, B53_ARLIO_PAGE
, dev
->vta_regs
[1], vid
);
215 b53_write32(dev
, B53_ARLIO_PAGE
, dev
->vta_regs
[2],
216 (untag
<< VTE_UNTAG_S
) | members
);
218 b53_do_vlan_op(dev
, VTA_CMD_WRITE
);
222 void b53_set_forwarding(struct b53_device
*dev
, int enable
)
226 b53_read8(dev
, B53_CTRL_PAGE
, B53_SWITCH_MODE
, &mgmt
);
229 mgmt
|= SM_SW_FWD_EN
;
231 mgmt
&= ~SM_SW_FWD_EN
;
233 b53_write8(dev
, B53_CTRL_PAGE
, B53_SWITCH_MODE
, mgmt
);
236 static void b53_enable_vlan(struct b53_device
*dev
, int enable
)
238 u8 mgmt
, vc0
, vc1
, vc4
= 0, vc5
;
240 b53_read8(dev
, B53_CTRL_PAGE
, B53_SWITCH_MODE
, &mgmt
);
241 b53_read8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL0
, &vc0
);
242 b53_read8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL1
, &vc1
);
244 if (is5325(dev
) || is5365(dev
)) {
245 b53_read8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL4_25
, &vc4
);
246 b53_read8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL5_25
, &vc5
);
247 } else if (is63xx(dev
)) {
248 b53_read8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL4_63XX
, &vc4
);
249 b53_read8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL5_63XX
, &vc5
);
251 b53_read8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL4
, &vc4
);
252 b53_read8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL5
, &vc5
);
255 mgmt
&= ~SM_SW_FWD_MODE
;
258 vc0
|= VC0_VLAN_EN
| VC0_VID_CHK_EN
| VC0_VID_HASH_VID
;
259 vc1
|= VC1_RX_MCST_UNTAG_EN
| VC1_RX_MCST_FWD_EN
;
260 vc4
&= ~VC4_ING_VID_CHECK_MASK
;
261 vc4
|= VC4_ING_VID_VIO_DROP
<< VC4_ING_VID_CHECK_S
;
262 vc5
|= VC5_DROP_VTABLE_MISS
;
265 vc0
&= ~VC0_RESERVED_1
;
267 if (is5325(dev
) || is5365(dev
))
268 vc1
|= VC1_RX_MCST_TAG_EN
;
270 if (!is5325(dev
) && !is5365(dev
)) {
271 if (dev
->allow_vid_4095
)
272 vc5
|= VC5_VID_FFF_EN
;
274 vc5
&= ~VC5_VID_FFF_EN
;
277 vc0
&= ~(VC0_VLAN_EN
| VC0_VID_CHK_EN
| VC0_VID_HASH_VID
);
278 vc1
&= ~(VC1_RX_MCST_UNTAG_EN
| VC1_RX_MCST_FWD_EN
);
279 vc4
&= ~VC4_ING_VID_CHECK_MASK
;
280 vc5
&= ~VC5_DROP_VTABLE_MISS
;
282 if (is5325(dev
) || is5365(dev
))
283 vc4
|= VC4_ING_VID_VIO_FWD
<< VC4_ING_VID_CHECK_S
;
285 vc4
|= VC4_ING_VID_VIO_TO_IMP
<< VC4_ING_VID_CHECK_S
;
287 if (is5325(dev
) || is5365(dev
))
288 vc1
&= ~VC1_RX_MCST_TAG_EN
;
290 if (!is5325(dev
) && !is5365(dev
))
291 vc5
&= ~VC5_VID_FFF_EN
;
294 b53_write8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL0
, vc0
);
295 b53_write8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL1
, vc1
);
297 if (is5325(dev
) || is5365(dev
)) {
298 /* enable the high 8 bit vid check on 5325 */
299 if (is5325(dev
) && enable
)
300 b53_write8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL3
,
303 b53_write8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL3
, 0);
305 b53_write8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL4_25
, vc4
);
306 b53_write8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL5_25
, vc5
);
307 } else if (is63xx(dev
)) {
308 b53_write16(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL3_63XX
, 0);
309 b53_write8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL4_63XX
, vc4
);
310 b53_write8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL5_63XX
, vc5
);
312 b53_write16(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL3
, 0);
313 b53_write8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL4
, vc4
);
314 b53_write8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL5
, vc5
);
317 b53_write8(dev
, B53_CTRL_PAGE
, B53_SWITCH_MODE
, mgmt
);
320 static int b53_set_jumbo(struct b53_device
*dev
, int enable
, int allow_10_100
)
323 u16 max_size
= JMS_MIN_SIZE
;
325 if (is5325(dev
) || is5365(dev
))
329 port_mask
= dev
->enabled_ports
;
330 max_size
= JMS_MAX_SIZE
;
332 port_mask
|= JPM_10_100_JUMBO_EN
;
335 b53_write32(dev
, B53_JUMBO_PAGE
, dev
->jumbo_pm_reg
, port_mask
);
336 return b53_write16(dev
, B53_JUMBO_PAGE
, dev
->jumbo_size_reg
, max_size
);
339 static int b53_flush_arl(struct b53_device
*dev
)
343 b53_write8(dev
, B53_CTRL_PAGE
, B53_FAST_AGE_CTRL
,
344 FAST_AGE_DONE
| FAST_AGE_DYNAMIC
| FAST_AGE_STATIC
);
346 for (i
= 0; i
< 10; i
++) {
349 b53_read8(dev
, B53_CTRL_PAGE
, B53_FAST_AGE_CTRL
,
352 if (!(fast_age_ctrl
& FAST_AGE_DONE
))
358 pr_warn("time out while flushing ARL\n");
363 static void b53_enable_ports(struct b53_device
*dev
)
367 b53_for_each_port(dev
, i
) {
372 * prevent leaking packets between wan and lan in unmanaged
373 * mode through port vlans.
375 if (dev
->enable_vlan
|| is_cpu_port(dev
, i
))
377 else if (is531x5(dev
) || is5301x(dev
))
378 /* BCM53115 may use a different port as cpu port */
379 pvlan_mask
= BIT(dev
->sw_dev
.cpu_port
);
381 pvlan_mask
= BIT(B53_CPU_PORT
);
383 /* BCM5325 CPU port is at 8 */
384 if ((is5325(dev
) || is5365(dev
)) && i
== B53_CPU_PORT_25
)
387 if (dev
->chip_id
== BCM5398_DEVICE_ID
&& (i
== 6 || i
== 7))
388 /* disable unused ports 6 & 7 */
389 port_ctrl
= PORT_CTRL_RX_DISABLE
| PORT_CTRL_TX_DISABLE
;
390 else if (i
== B53_CPU_PORT
)
391 port_ctrl
= PORT_CTRL_RX_BCST_EN
|
392 PORT_CTRL_RX_MCST_EN
|
393 PORT_CTRL_RX_UCST_EN
;
397 b53_write16(dev
, B53_PVLAN_PAGE
, B53_PVLAN_PORT_MASK(i
),
400 /* port state is handled by bcm63xx_enet driver */
401 if (!is63xx(dev
) && !(is5301x(dev
) && i
== 6))
402 b53_write8(dev
, B53_CTRL_PAGE
, B53_PORT_CTRL(i
),
407 static void b53_enable_mib(struct b53_device
*dev
)
411 b53_read8(dev
, B53_CTRL_PAGE
, B53_GLOBAL_CONFIG
, &gc
);
413 gc
&= ~(GC_RESET_MIB
| GC_MIB_AC_EN
);
415 b53_write8(dev
, B53_CTRL_PAGE
, B53_GLOBAL_CONFIG
, gc
);
418 static int b53_apply(struct b53_device
*dev
)
422 /* clear all vlan entries */
423 if (is5325(dev
) || is5365(dev
)) {
424 for (i
= 1; i
< dev
->sw_dev
.vlans
; i
++)
425 b53_set_vlan_entry(dev
, i
, 0, 0);
427 b53_do_vlan_op(dev
, VTA_CMD_CLEAR
);
430 b53_enable_vlan(dev
, dev
->enable_vlan
);
432 /* fill VLAN table */
433 if (dev
->enable_vlan
) {
434 for (i
= 0; i
< dev
->sw_dev
.vlans
; i
++) {
435 struct b53_vlan
*vlan
= &dev
->vlans
[i
];
440 b53_set_vlan_entry(dev
, i
, vlan
->members
, vlan
->untag
);
443 b53_for_each_port(dev
, i
)
444 b53_write16(dev
, B53_VLAN_PAGE
,
445 B53_VLAN_PORT_DEF_TAG(i
),
448 b53_for_each_port(dev
, i
)
449 b53_write16(dev
, B53_VLAN_PAGE
,
450 B53_VLAN_PORT_DEF_TAG(i
), 1);
454 b53_enable_ports(dev
);
456 if (!is5325(dev
) && !is5365(dev
))
457 b53_set_jumbo(dev
, dev
->enable_jumbo
, 1);
462 static void b53_switch_reset_gpio(struct b53_device
*dev
)
464 int gpio
= dev
->reset_gpio
;
470 * Reset sequence: RESET low(50ms)->high(20ms)
472 gpio_set_value(gpio
, 0);
475 gpio_set_value(gpio
, 1);
478 dev
->current_page
= 0xff;
481 static int b53_switch_reset(struct b53_device
*dev
)
485 b53_switch_reset_gpio(dev
);
488 b53_write8(dev
, B53_CTRL_PAGE
, B53_SOFTRESET
, 0x83);
489 b53_write8(dev
, B53_CTRL_PAGE
, B53_SOFTRESET
, 0x00);
492 b53_read8(dev
, B53_CTRL_PAGE
, B53_SWITCH_MODE
, &mgmt
);
494 if (!(mgmt
& SM_SW_FWD_EN
)) {
495 mgmt
&= ~SM_SW_FWD_MODE
;
496 mgmt
|= SM_SW_FWD_EN
;
498 b53_write8(dev
, B53_CTRL_PAGE
, B53_SWITCH_MODE
, mgmt
);
499 b53_read8(dev
, B53_CTRL_PAGE
, B53_SWITCH_MODE
, &mgmt
);
501 if (!(mgmt
& SM_SW_FWD_EN
)) {
502 pr_err("Failed to enable switch!\n");
507 /* enable all ports */
508 b53_enable_ports(dev
);
510 /* configure MII port if necessary */
512 u8 mii_port_override
;
514 b53_read8(dev
, B53_CTRL_PAGE
, B53_PORT_OVERRIDE_CTRL
,
516 /* reverse mii needs to be enabled */
517 if (!(mii_port_override
& PORT_OVERRIDE_RV_MII_25
)) {
518 b53_write8(dev
, B53_CTRL_PAGE
, B53_PORT_OVERRIDE_CTRL
,
519 mii_port_override
| PORT_OVERRIDE_RV_MII_25
);
520 b53_read8(dev
, B53_CTRL_PAGE
, B53_PORT_OVERRIDE_CTRL
,
523 if (!(mii_port_override
& PORT_OVERRIDE_RV_MII_25
)) {
524 pr_err("Failed to enable reverse MII mode\n");
528 } else if ((is531x5(dev
) || is5301x(dev
)) && dev
->sw_dev
.cpu_port
== B53_CPU_PORT
) {
529 u8 mii_port_override
;
531 b53_read8(dev
, B53_CTRL_PAGE
, B53_PORT_OVERRIDE_CTRL
,
533 b53_write8(dev
, B53_CTRL_PAGE
, B53_PORT_OVERRIDE_CTRL
,
534 mii_port_override
| PORT_OVERRIDE_EN
|
540 return b53_flush_arl(dev
);
544 * Swconfig glue functions
547 static int b53_global_get_vlan_enable(struct switch_dev
*dev
,
548 const struct switch_attr
*attr
,
549 struct switch_val
*val
)
551 struct b53_device
*priv
= sw_to_b53(dev
);
553 val
->value
.i
= priv
->enable_vlan
;
558 static int b53_global_set_vlan_enable(struct switch_dev
*dev
,
559 const struct switch_attr
*attr
,
560 struct switch_val
*val
)
562 struct b53_device
*priv
= sw_to_b53(dev
);
564 priv
->enable_vlan
= val
->value
.i
;
569 static int b53_global_get_jumbo_enable(struct switch_dev
*dev
,
570 const struct switch_attr
*attr
,
571 struct switch_val
*val
)
573 struct b53_device
*priv
= sw_to_b53(dev
);
575 val
->value
.i
= priv
->enable_jumbo
;
580 static int b53_global_set_jumbo_enable(struct switch_dev
*dev
,
581 const struct switch_attr
*attr
,
582 struct switch_val
*val
)
584 struct b53_device
*priv
= sw_to_b53(dev
);
586 priv
->enable_jumbo
= val
->value
.i
;
591 static int b53_global_get_4095_enable(struct switch_dev
*dev
,
592 const struct switch_attr
*attr
,
593 struct switch_val
*val
)
595 struct b53_device
*priv
= sw_to_b53(dev
);
597 val
->value
.i
= priv
->allow_vid_4095
;
602 static int b53_global_set_4095_enable(struct switch_dev
*dev
,
603 const struct switch_attr
*attr
,
604 struct switch_val
*val
)
606 struct b53_device
*priv
= sw_to_b53(dev
);
608 priv
->allow_vid_4095
= val
->value
.i
;
613 static int b53_global_get_ports(struct switch_dev
*dev
,
614 const struct switch_attr
*attr
,
615 struct switch_val
*val
)
617 struct b53_device
*priv
= sw_to_b53(dev
);
619 val
->len
= snprintf(priv
->buf
, B53_BUF_SIZE
, "0x%04x",
620 priv
->enabled_ports
);
621 val
->value
.s
= priv
->buf
;
626 static int b53_port_get_pvid(struct switch_dev
*dev
, int port
, int *val
)
628 struct b53_device
*priv
= sw_to_b53(dev
);
630 *val
= priv
->ports
[port
].pvid
;
635 static int b53_port_set_pvid(struct switch_dev
*dev
, int port
, int val
)
637 struct b53_device
*priv
= sw_to_b53(dev
);
639 if (val
> 15 && is5325(priv
))
641 if (val
== 4095 && !priv
->allow_vid_4095
)
644 priv
->ports
[port
].pvid
= val
;
649 static int b53_vlan_get_ports(struct switch_dev
*dev
, struct switch_val
*val
)
651 struct b53_device
*priv
= sw_to_b53(dev
);
652 struct switch_port
*port
= &val
->value
.ports
[0];
653 struct b53_vlan
*vlan
= &priv
->vlans
[val
->port_vlan
];
661 for (i
= 0; i
< dev
->ports
; i
++) {
662 if (!(vlan
->members
& BIT(i
)))
666 if (!(vlan
->untag
& BIT(i
)))
667 port
->flags
= BIT(SWITCH_PORT_FLAG_TAGGED
);
679 static int b53_vlan_set_ports(struct switch_dev
*dev
, struct switch_val
*val
)
681 struct b53_device
*priv
= sw_to_b53(dev
);
682 struct switch_port
*port
;
683 struct b53_vlan
*vlan
= &priv
->vlans
[val
->port_vlan
];
686 /* only BCM5325 and BCM5365 supports VID 0 */
687 if (val
->port_vlan
== 0 && !is5325(priv
) && !is5365(priv
))
690 /* VLAN 4095 needs special handling */
691 if (val
->port_vlan
== 4095 && !priv
->allow_vid_4095
)
694 port
= &val
->value
.ports
[0];
697 for (i
= 0; i
< val
->len
; i
++, port
++) {
698 vlan
->members
|= BIT(port
->id
);
700 if (!(port
->flags
& BIT(SWITCH_PORT_FLAG_TAGGED
))) {
701 vlan
->untag
|= BIT(port
->id
);
702 priv
->ports
[port
->id
].pvid
= val
->port_vlan
;
706 /* ignore disabled ports */
707 vlan
->members
&= priv
->enabled_ports
;
708 vlan
->untag
&= priv
->enabled_ports
;
713 static int b53_port_get_link(struct switch_dev
*dev
, int port
,
714 struct switch_port_link
*link
)
716 struct b53_device
*priv
= sw_to_b53(dev
);
718 if (is_cpu_port(priv
, port
)) {
721 link
->speed
= is5325(priv
) || is5365(priv
) ?
722 SWITCH_PORT_SPEED_100
: SWITCH_PORT_SPEED_1000
;
724 } else if (priv
->enabled_ports
& BIT(port
)) {
728 b53_read16(priv
, B53_STAT_PAGE
, B53_LINK_STAT
, &lnk
);
729 b53_read16(priv
, B53_STAT_PAGE
, priv
->duplex_reg
, &duplex
);
731 lnk
= (lnk
>> port
) & 1;
732 duplex
= (duplex
>> port
) & 1;
734 if (is5325(priv
) || is5365(priv
)) {
737 b53_read16(priv
, B53_STAT_PAGE
, B53_SPEED_STAT
, &tmp
);
738 speed
= SPEED_PORT_FE(tmp
, port
);
740 b53_read32(priv
, B53_STAT_PAGE
, B53_SPEED_STAT
, &speed
);
741 speed
= SPEED_PORT_GE(speed
, port
);
746 link
->duplex
= duplex
;
749 link
->speed
= SWITCH_PORT_SPEED_10
;
751 case SPEED_STAT_100M
:
752 link
->speed
= SWITCH_PORT_SPEED_100
;
754 case SPEED_STAT_1000M
:
755 link
->speed
= SWITCH_PORT_SPEED_1000
;
769 static int b53_global_reset_switch(struct switch_dev
*dev
)
771 struct b53_device
*priv
= sw_to_b53(dev
);
774 priv
->enable_vlan
= 0;
775 priv
->enable_jumbo
= 0;
776 priv
->allow_vid_4095
= 0;
778 memset(priv
->vlans
, 0, sizeof(priv
->vlans
) * dev
->vlans
);
779 memset(priv
->ports
, 0, sizeof(priv
->ports
) * dev
->ports
);
781 return b53_switch_reset(priv
);
784 static int b53_global_apply_config(struct switch_dev
*dev
)
786 struct b53_device
*priv
= sw_to_b53(dev
);
788 /* disable switching */
789 b53_set_forwarding(priv
, 0);
793 /* enable switching */
794 b53_set_forwarding(priv
, 1);
800 static int b53_global_reset_mib(struct switch_dev
*dev
,
801 const struct switch_attr
*attr
,
802 struct switch_val
*val
)
804 struct b53_device
*priv
= sw_to_b53(dev
);
807 b53_read8(priv
, B53_MGMT_PAGE
, B53_GLOBAL_CONFIG
, &gc
);
809 b53_write8(priv
, B53_MGMT_PAGE
, B53_GLOBAL_CONFIG
, gc
| GC_RESET_MIB
);
811 b53_write8(priv
, B53_MGMT_PAGE
, B53_GLOBAL_CONFIG
, gc
& ~GC_RESET_MIB
);
817 static int b53_port_get_mib(struct switch_dev
*sw_dev
,
818 const struct switch_attr
*attr
,
819 struct switch_val
*val
)
821 struct b53_device
*dev
= sw_to_b53(sw_dev
);
822 const struct b53_mib_desc
*mibs
;
823 int port
= val
->port_vlan
;
826 if (!(BIT(port
) & dev
->enabled_ports
))
834 } else if (is63xx(dev
)) {
835 mibs
= b53_mibs_63xx
;
842 for (; mibs
->size
> 0; mibs
++) {
845 if (mibs
->size
== 8) {
846 b53_read64(dev
, B53_MIB_PAGE(port
), mibs
->offset
, &val
);
850 b53_read32(dev
, B53_MIB_PAGE(port
), mibs
->offset
,
855 len
+= snprintf(dev
->buf
+ len
, B53_BUF_SIZE
- len
,
856 "%-20s: %llu\n", mibs
->name
, val
);
860 val
->value
.s
= dev
->buf
;
865 static struct switch_attr b53_global_ops_25
[] = {
867 .type
= SWITCH_TYPE_INT
,
868 .name
= "enable_vlan",
869 .description
= "Enable VLAN mode",
870 .set
= b53_global_set_vlan_enable
,
871 .get
= b53_global_get_vlan_enable
,
875 .type
= SWITCH_TYPE_STRING
,
877 .description
= "Available ports (as bitmask)",
878 .get
= b53_global_get_ports
,
882 static struct switch_attr b53_global_ops_65
[] = {
884 .type
= SWITCH_TYPE_INT
,
885 .name
= "enable_vlan",
886 .description
= "Enable VLAN mode",
887 .set
= b53_global_set_vlan_enable
,
888 .get
= b53_global_get_vlan_enable
,
892 .type
= SWITCH_TYPE_STRING
,
894 .description
= "Available ports (as bitmask)",
895 .get
= b53_global_get_ports
,
898 .type
= SWITCH_TYPE_INT
,
900 .description
= "Reset MIB counters",
901 .set
= b53_global_reset_mib
,
905 static struct switch_attr b53_global_ops
[] = {
907 .type
= SWITCH_TYPE_INT
,
908 .name
= "enable_vlan",
909 .description
= "Enable VLAN mode",
910 .set
= b53_global_set_vlan_enable
,
911 .get
= b53_global_get_vlan_enable
,
915 .type
= SWITCH_TYPE_STRING
,
917 .description
= "Available Ports (as bitmask)",
918 .get
= b53_global_get_ports
,
921 .type
= SWITCH_TYPE_INT
,
923 .description
= "Reset MIB counters",
924 .set
= b53_global_reset_mib
,
927 .type
= SWITCH_TYPE_INT
,
928 .name
= "enable_jumbo",
929 .description
= "Enable Jumbo Frames",
930 .set
= b53_global_set_jumbo_enable
,
931 .get
= b53_global_get_jumbo_enable
,
935 .type
= SWITCH_TYPE_INT
,
936 .name
= "allow_vid_4095",
937 .description
= "Allow VID 4095",
938 .set
= b53_global_set_4095_enable
,
939 .get
= b53_global_get_4095_enable
,
944 static struct switch_attr b53_port_ops
[] = {
946 .type
= SWITCH_TYPE_STRING
,
948 .description
= "Get port's MIB counters",
949 .get
= b53_port_get_mib
,
953 static struct switch_attr b53_no_ops
[] = {
956 static const struct switch_dev_ops b53_switch_ops_25
= {
958 .attr
= b53_global_ops_25
,
959 .n_attr
= ARRAY_SIZE(b53_global_ops_25
),
963 .n_attr
= ARRAY_SIZE(b53_no_ops
),
967 .n_attr
= ARRAY_SIZE(b53_no_ops
),
970 .get_vlan_ports
= b53_vlan_get_ports
,
971 .set_vlan_ports
= b53_vlan_set_ports
,
972 .get_port_pvid
= b53_port_get_pvid
,
973 .set_port_pvid
= b53_port_set_pvid
,
974 .apply_config
= b53_global_apply_config
,
975 .reset_switch
= b53_global_reset_switch
,
976 .get_port_link
= b53_port_get_link
,
979 static const struct switch_dev_ops b53_switch_ops_65
= {
981 .attr
= b53_global_ops_65
,
982 .n_attr
= ARRAY_SIZE(b53_global_ops_65
),
985 .attr
= b53_port_ops
,
986 .n_attr
= ARRAY_SIZE(b53_port_ops
),
990 .n_attr
= ARRAY_SIZE(b53_no_ops
),
993 .get_vlan_ports
= b53_vlan_get_ports
,
994 .set_vlan_ports
= b53_vlan_set_ports
,
995 .get_port_pvid
= b53_port_get_pvid
,
996 .set_port_pvid
= b53_port_set_pvid
,
997 .apply_config
= b53_global_apply_config
,
998 .reset_switch
= b53_global_reset_switch
,
999 .get_port_link
= b53_port_get_link
,
1002 static const struct switch_dev_ops b53_switch_ops
= {
1004 .attr
= b53_global_ops
,
1005 .n_attr
= ARRAY_SIZE(b53_global_ops
),
1008 .attr
= b53_port_ops
,
1009 .n_attr
= ARRAY_SIZE(b53_port_ops
),
1013 .n_attr
= ARRAY_SIZE(b53_no_ops
),
1016 .get_vlan_ports
= b53_vlan_get_ports
,
1017 .set_vlan_ports
= b53_vlan_set_ports
,
1018 .get_port_pvid
= b53_port_get_pvid
,
1019 .set_port_pvid
= b53_port_set_pvid
,
1020 .apply_config
= b53_global_apply_config
,
1021 .reset_switch
= b53_global_reset_switch
,
1022 .get_port_link
= b53_port_get_link
,
1025 struct b53_chip_data
{
1027 const char *dev_name
;
1036 const struct switch_dev_ops
*sw_ops
;
1039 #define B53_VTA_REGS \
1040 { B53_VT_ACCESS, B53_VT_INDEX, B53_VT_ENTRY }
1041 #define B53_VTA_REGS_9798 \
1042 { B53_VT_ACCESS_9798, B53_VT_INDEX_9798, B53_VT_ENTRY_9798 }
1043 #define B53_VTA_REGS_63XX \
1044 { B53_VT_ACCESS_63XX, B53_VT_INDEX_63XX, B53_VT_ENTRY_63XX }
1046 static const struct b53_chip_data b53_switch_chips
[] = {
1048 .chip_id
= BCM5325_DEVICE_ID
,
1049 .dev_name
= "BCM5325",
1052 .enabled_ports
= 0x1f,
1053 .cpu_port
= B53_CPU_PORT_25
,
1054 .duplex_reg
= B53_DUPLEX_STAT_FE
,
1055 .sw_ops
= &b53_switch_ops_25
,
1058 .chip_id
= BCM5365_DEVICE_ID
,
1059 .dev_name
= "BCM5365",
1062 .enabled_ports
= 0x1f,
1063 .cpu_port
= B53_CPU_PORT_25
,
1064 .duplex_reg
= B53_DUPLEX_STAT_FE
,
1065 .sw_ops
= &b53_switch_ops_65
,
1068 .chip_id
= BCM5395_DEVICE_ID
,
1069 .dev_name
= "BCM5395",
1072 .enabled_ports
= 0x1f,
1073 .cpu_port
= B53_CPU_PORT
,
1074 .vta_regs
= B53_VTA_REGS
,
1075 .duplex_reg
= B53_DUPLEX_STAT_GE
,
1076 .jumbo_pm_reg
= B53_JUMBO_PORT_MASK
,
1077 .jumbo_size_reg
= B53_JUMBO_MAX_SIZE
,
1078 .sw_ops
= &b53_switch_ops
,
1081 .chip_id
= BCM5397_DEVICE_ID
,
1082 .dev_name
= "BCM5397",
1085 .enabled_ports
= 0x1f,
1086 .cpu_port
= B53_CPU_PORT
,
1087 .vta_regs
= B53_VTA_REGS_9798
,
1088 .duplex_reg
= B53_DUPLEX_STAT_GE
,
1089 .jumbo_pm_reg
= B53_JUMBO_PORT_MASK
,
1090 .jumbo_size_reg
= B53_JUMBO_MAX_SIZE
,
1091 .sw_ops
= &b53_switch_ops
,
1094 .chip_id
= BCM5398_DEVICE_ID
,
1095 .dev_name
= "BCM5398",
1098 .enabled_ports
= 0x7f,
1099 .cpu_port
= B53_CPU_PORT
,
1100 .vta_regs
= B53_VTA_REGS_9798
,
1101 .duplex_reg
= B53_DUPLEX_STAT_GE
,
1102 .jumbo_pm_reg
= B53_JUMBO_PORT_MASK
,
1103 .jumbo_size_reg
= B53_JUMBO_MAX_SIZE
,
1104 .sw_ops
= &b53_switch_ops
,
1107 .chip_id
= BCM53115_DEVICE_ID
,
1108 .dev_name
= "BCM53115",
1109 .alias
= "bcm53115",
1111 .enabled_ports
= 0x1f,
1112 .vta_regs
= B53_VTA_REGS
,
1113 .cpu_port
= B53_CPU_PORT
,
1114 .duplex_reg
= B53_DUPLEX_STAT_GE
,
1115 .jumbo_pm_reg
= B53_JUMBO_PORT_MASK
,
1116 .jumbo_size_reg
= B53_JUMBO_MAX_SIZE
,
1117 .sw_ops
= &b53_switch_ops
,
1120 .chip_id
= BCM53125_DEVICE_ID
,
1121 .dev_name
= "BCM53125",
1122 .alias
= "bcm53125",
1124 .enabled_ports
= 0x1f,
1125 .cpu_port
= B53_CPU_PORT
,
1126 .vta_regs
= B53_VTA_REGS
,
1127 .duplex_reg
= B53_DUPLEX_STAT_GE
,
1128 .jumbo_pm_reg
= B53_JUMBO_PORT_MASK
,
1129 .jumbo_size_reg
= B53_JUMBO_MAX_SIZE
,
1130 .sw_ops
= &b53_switch_ops
,
1133 .chip_id
= BCM53128_DEVICE_ID
,
1134 .dev_name
= "BCM53128",
1135 .alias
= "bcm53128",
1137 .enabled_ports
= 0x1ff,
1138 .cpu_port
= B53_CPU_PORT
,
1139 .vta_regs
= B53_VTA_REGS
,
1140 .duplex_reg
= B53_DUPLEX_STAT_GE
,
1141 .jumbo_pm_reg
= B53_JUMBO_PORT_MASK
,
1142 .jumbo_size_reg
= B53_JUMBO_MAX_SIZE
,
1143 .sw_ops
= &b53_switch_ops
,
1146 .chip_id
= BCM63XX_DEVICE_ID
,
1147 .dev_name
= "BCM63xx",
1150 .enabled_ports
= 0, /* pdata must provide them */
1151 .cpu_port
= B53_CPU_PORT
,
1152 .vta_regs
= B53_VTA_REGS_63XX
,
1153 .duplex_reg
= B53_DUPLEX_STAT_63XX
,
1154 .jumbo_pm_reg
= B53_JUMBO_PORT_MASK_63XX
,
1155 .jumbo_size_reg
= B53_JUMBO_MAX_SIZE_63XX
,
1156 .sw_ops
= &b53_switch_ops
,
1159 .chip_id
= BCM53010_DEVICE_ID
,
1160 .dev_name
= "BCM53010",
1161 .alias
= "bcm53011",
1163 .enabled_ports
= 0x1f,
1164 .cpu_port
= B53_CPU_PORT_25
, // TODO: auto detect
1165 .vta_regs
= B53_VTA_REGS
,
1166 .duplex_reg
= B53_DUPLEX_STAT_GE
,
1167 .jumbo_pm_reg
= B53_JUMBO_PORT_MASK
,
1168 .jumbo_size_reg
= B53_JUMBO_MAX_SIZE
,
1169 .sw_ops
= &b53_switch_ops
,
1172 .chip_id
= BCM53011_DEVICE_ID
,
1173 .dev_name
= "BCM53011",
1174 .alias
= "bcm53011",
1176 .enabled_ports
= 0x1f,
1177 .cpu_port
= B53_CPU_PORT_25
, // TODO: auto detect
1178 .vta_regs
= B53_VTA_REGS
,
1179 .duplex_reg
= B53_DUPLEX_STAT_GE
,
1180 .jumbo_pm_reg
= B53_JUMBO_PORT_MASK
,
1181 .jumbo_size_reg
= B53_JUMBO_MAX_SIZE
,
1182 .sw_ops
= &b53_switch_ops
,
1185 .chip_id
= BCM53012_DEVICE_ID
,
1186 .dev_name
= "BCM53012",
1187 .alias
= "bcm53011",
1189 .enabled_ports
= 0x1f,
1190 .cpu_port
= B53_CPU_PORT_25
, // TODO: auto detect
1191 .vta_regs
= B53_VTA_REGS
,
1192 .duplex_reg
= B53_DUPLEX_STAT_GE
,
1193 .jumbo_pm_reg
= B53_JUMBO_PORT_MASK
,
1194 .jumbo_size_reg
= B53_JUMBO_MAX_SIZE
,
1195 .sw_ops
= &b53_switch_ops
,
1198 .chip_id
= BCM53018_DEVICE_ID
,
1199 .dev_name
= "BCM53018",
1200 .alias
= "bcm53018",
1202 .enabled_ports
= 0x1f,
1203 .cpu_port
= B53_CPU_PORT_25
, // TODO: auto detect
1204 .vta_regs
= B53_VTA_REGS
,
1205 .duplex_reg
= B53_DUPLEX_STAT_GE
,
1206 .jumbo_pm_reg
= B53_JUMBO_PORT_MASK
,
1207 .jumbo_size_reg
= B53_JUMBO_MAX_SIZE
,
1208 .sw_ops
= &b53_switch_ops
,
1211 .chip_id
= BCM53019_DEVICE_ID
,
1212 .dev_name
= "BCM53019",
1213 .alias
= "bcm53019",
1215 .enabled_ports
= 0x1f,
1216 .cpu_port
= B53_CPU_PORT_25
, // TODO: auto detect
1217 .vta_regs
= B53_VTA_REGS
,
1218 .duplex_reg
= B53_DUPLEX_STAT_GE
,
1219 .jumbo_pm_reg
= B53_JUMBO_PORT_MASK
,
1220 .jumbo_size_reg
= B53_JUMBO_MAX_SIZE
,
1221 .sw_ops
= &b53_switch_ops
,
1225 static int b53_switch_init(struct b53_device
*dev
)
1227 struct switch_dev
*sw_dev
= &dev
->sw_dev
;
1231 for (i
= 0; i
< ARRAY_SIZE(b53_switch_chips
); i
++) {
1232 const struct b53_chip_data
*chip
= &b53_switch_chips
[i
];
1234 if (chip
->chip_id
== dev
->chip_id
) {
1235 sw_dev
->name
= chip
->dev_name
;
1237 sw_dev
->alias
= chip
->alias
;
1238 if (!dev
->enabled_ports
)
1239 dev
->enabled_ports
= chip
->enabled_ports
;
1240 dev
->duplex_reg
= chip
->duplex_reg
;
1241 dev
->vta_regs
[0] = chip
->vta_regs
[0];
1242 dev
->vta_regs
[1] = chip
->vta_regs
[1];
1243 dev
->vta_regs
[2] = chip
->vta_regs
[2];
1244 dev
->jumbo_pm_reg
= chip
->jumbo_pm_reg
;
1245 sw_dev
->ops
= chip
->sw_ops
;
1246 sw_dev
->cpu_port
= chip
->cpu_port
;
1247 sw_dev
->vlans
= chip
->vlans
;
1255 /* check which BCM5325x version we have */
1259 b53_read8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL4_25
, &vc4
);
1261 /* check reserved bits */
1267 /* BCM5325F - do not use port 4 */
1268 dev
->enabled_ports
&= ~BIT(4);
1271 /* On the BCM47XX SoCs this is the supported internal switch.*/
1272 #ifndef CONFIG_BCM47XX
1279 } else if (dev
->chip_id
== BCM53115_DEVICE_ID
) {
1282 b53_read48(dev
, B53_STAT_PAGE
, B53_STRAP_VALUE
, &strap_value
);
1283 /* use second IMP port if GMII is enabled */
1284 if (strap_value
& SV_GMII_CTRL_115
)
1285 sw_dev
->cpu_port
= 5;
1288 /* cpu port is always last */
1289 sw_dev
->ports
= sw_dev
->cpu_port
+ 1;
1290 dev
->enabled_ports
|= BIT(sw_dev
->cpu_port
);
1292 dev
->ports
= devm_kzalloc(dev
->dev
,
1293 sizeof(struct b53_port
) * sw_dev
->ports
,
1298 dev
->vlans
= devm_kzalloc(dev
->dev
,
1299 sizeof(struct b53_vlan
) * sw_dev
->vlans
,
1304 dev
->buf
= devm_kzalloc(dev
->dev
, B53_BUF_SIZE
, GFP_KERNEL
);
1308 dev
->reset_gpio
= b53_switch_get_reset_gpio(dev
);
1309 if (dev
->reset_gpio
>= 0) {
1310 ret
= devm_gpio_request_one(dev
->dev
, dev
->reset_gpio
, GPIOF_OUT_INIT_HIGH
, "robo_reset");
1315 return b53_switch_reset(dev
);
1318 struct b53_device
*b53_switch_alloc(struct device
*base
, struct b53_io_ops
*ops
,
1321 struct b53_device
*dev
;
1323 dev
= devm_kzalloc(base
, sizeof(*dev
), GFP_KERNEL
);
1330 mutex_init(&dev
->reg_mutex
);
1334 EXPORT_SYMBOL(b53_switch_alloc
);
1336 int b53_switch_detect(struct b53_device
*dev
)
1343 ret
= b53_read8(dev
, B53_MGMT_PAGE
, B53_DEVICE_ID
, &id8
);
1350 * BCM5325 and BCM5365 do not have this register so reads
1351 * return 0. But the read operation did succeed, so assume
1352 * this is one of them.
1354 * Next check if we can write to the 5325's VTA register; for
1355 * 5365 it is read only.
1358 b53_write16(dev
, B53_VLAN_PAGE
, B53_VLAN_TABLE_ACCESS_25
, 0xf);
1359 b53_read16(dev
, B53_VLAN_PAGE
, B53_VLAN_TABLE_ACCESS_25
, &tmp
);
1362 dev
->chip_id
= BCM5325_DEVICE_ID
;
1364 dev
->chip_id
= BCM5365_DEVICE_ID
;
1366 case BCM5395_DEVICE_ID
:
1367 case BCM5397_DEVICE_ID
:
1368 case BCM5398_DEVICE_ID
:
1372 ret
= b53_read32(dev
, B53_MGMT_PAGE
, B53_DEVICE_ID
, &id32
);
1377 case BCM53115_DEVICE_ID
:
1378 case BCM53125_DEVICE_ID
:
1379 case BCM53128_DEVICE_ID
:
1380 case BCM53010_DEVICE_ID
:
1381 case BCM53011_DEVICE_ID
:
1382 case BCM53012_DEVICE_ID
:
1383 case BCM53018_DEVICE_ID
:
1384 case BCM53019_DEVICE_ID
:
1385 dev
->chip_id
= id32
;
1388 pr_err("unsupported switch detected (BCM53%02x/BCM%x)\n",
1394 if (dev
->chip_id
== BCM5325_DEVICE_ID
)
1395 return b53_read8(dev
, B53_STAT_PAGE
, B53_REV_ID_25
,
1398 return b53_read8(dev
, B53_MGMT_PAGE
, B53_REV_ID
,
1401 EXPORT_SYMBOL(b53_switch_detect
);
1403 int b53_switch_register(struct b53_device
*dev
)
1408 dev
->chip_id
= dev
->pdata
->chip_id
;
1409 dev
->enabled_ports
= dev
->pdata
->enabled_ports
;
1410 dev
->sw_dev
.alias
= dev
->pdata
->alias
;
1413 if (!dev
->chip_id
&& b53_switch_detect(dev
))
1416 ret
= b53_switch_init(dev
);
1420 pr_info("found switch: %s, rev %i\n", dev
->sw_dev
.name
, dev
->core_rev
);
1422 return register_switch(&dev
->sw_dev
, NULL
);
1424 EXPORT_SYMBOL(b53_switch_register
);
1426 MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>");
1427 MODULE_DESCRIPTION("B53 switch library");
1428 MODULE_LICENSE("Dual BSD/GPL");