2 * rtl8306.c: RTL8306S switch driver
4 * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
17 #include <linux/module.h>
18 #include <linux/init.h>
19 #include <linux/list.h>
20 #include <linux/if_ether.h>
21 #include <linux/skbuff.h>
22 #include <linux/netdevice.h>
23 #include <linux/netlink.h>
24 #include <net/genetlink.h>
25 #include <linux/switch.h>
26 #include <linux/delay.h>
27 #include <linux/phy.h>
32 #define RTL8306_REG_PAGE 16
33 #define RTL8306_REG_PAGE_LO (1 << 15)
34 #define RTL8306_REG_PAGE_HI (1 << 1) /* inverted */
36 #define RTL8306_NUM_VLANS 16
37 #define RTL8306_NUM_PORTS 6
38 #define RTL8306_PORT_CPU 5
39 #define RTL8306_NUM_PAGES 4
40 #define RTL8306_NUM_REGS 32
42 #define RTL_NAME_S "RTL8306S"
43 #define RTL_NAME_SD "RTL8306SD"
44 #define RTL_NAME_SDM "RTL8306SDM"
45 #define RTL_NAME_UNKNOWN "RTL8306(unknown)"
47 #define RTL8306_MAGIC 0x8306
49 static LIST_HEAD(phydevs
);
52 struct list_head list
;
53 struct switch_dev dev
;
58 char hwname
[sizeof(RTL_NAME_UNKNOWN
)];
68 #define to_rtl(_dev) container_of(_dev, struct rtl_priv, dev)
85 #define RTL_VLAN_REGOFS(name) \
86 (RTL_REG_VLAN1_##name - RTL_REG_VLAN0_##name)
88 #define RTL_PORT_REGOFS(name) \
89 (RTL_REG_PORT1_##name - RTL_REG_PORT0_##name)
91 #define RTL_PORT_REG(id, reg) \
92 (RTL_REG_PORT0_##reg + (id * RTL_PORT_REGOFS(reg)))
94 #define RTL_VLAN_REG(id, reg) \
95 (RTL_REG_VLAN0_##reg + (id * RTL_VLAN_REGOFS(reg)))
97 #define RTL_GLOBAL_REGATTR(reg) \
98 .id = RTL_REG_##reg, \
99 .type = SWITCH_TYPE_INT, \
101 .set = rtl_attr_set_int, \
102 .get = rtl_attr_get_int
104 #define RTL_PORT_REGATTR(reg) \
105 .id = RTL_REG_PORT0_##reg, \
106 .type = SWITCH_TYPE_INT, \
107 .ofs = RTL_PORT_REGOFS(reg), \
108 .set = rtl_attr_set_port_int, \
109 .get = rtl_attr_get_port_int
111 #define RTL_VLAN_REGATTR(reg) \
112 .id = RTL_REG_VLAN0_##reg, \
113 .type = SWITCH_TYPE_INT, \
114 .ofs = RTL_VLAN_REGOFS(reg), \
115 .set = rtl_attr_set_vlan_int, \
116 .get = rtl_attr_get_vlan_int
129 RTL_REG_TRUNK_PORTSEL
,
135 RTL_REG_VLAN_TAG_ONLY
,
136 RTL_REG_VLAN_TAG_AWARE
,
137 #define RTL_VLAN_ENUM(id) \
138 RTL_REG_VLAN##id##_VID, \
139 RTL_REG_VLAN##id##_PORTMASK
156 #define RTL_PORT_ENUM(id) \
157 RTL_REG_PORT##id##_PVID, \
158 RTL_REG_PORT##id##_NULL_VID_REPLACE, \
159 RTL_REG_PORT##id##_NON_PVID_DISCARD, \
160 RTL_REG_PORT##id##_VID_INSERT, \
161 RTL_REG_PORT##id##_TAG_INSERT, \
162 RTL_REG_PORT##id##_LINK, \
163 RTL_REG_PORT##id##_SPEED, \
164 RTL_REG_PORT##id##_NWAY, \
165 RTL_REG_PORT##id##_NRESTART, \
166 RTL_REG_PORT##id##_DUPLEX, \
167 RTL_REG_PORT##id##_RXEN, \
168 RTL_REG_PORT##id##_TXEN
177 static const struct rtl_reg rtl_regs
[] = {
178 [RTL_REG_CHIPID
] = { 0, 4, 30, 16, 0, 0 },
179 [RTL_REG_CHIPVER
] = { 0, 4, 31, 8, 0, 0 },
180 [RTL_REG_CHIPTYPE
] = { 0, 4, 31, 2, 8, 0 },
182 /* CPU port number */
183 [RTL_REG_CPUPORT
] = { 2, 4, 21, 3, 0, 0 },
184 /* Enable CPU port function */
185 [RTL_REG_EN_CPUPORT
] = { 3, 2, 21, 1, 15, 1 },
186 /* Enable CPU port tag insertion */
187 [RTL_REG_EN_TAG_OUT
] = { 3, 2, 21, 1, 12, 0 },
188 /* Enable CPU port tag removal */
189 [RTL_REG_EN_TAG_CLR
] = { 3, 2, 21, 1, 11, 0 },
190 /* Enable CPU port tag checking */
191 [RTL_REG_EN_TAG_IN
] = { 0, 4, 21, 1, 7, 0 },
192 [RTL_REG_EN_TRUNK
] = { 0, 0, 19, 1, 11, 1 },
193 [RTL_REG_TRUNK_PORTSEL
] = { 0, 0, 16, 1, 6, 1 },
194 [RTL_REG_RESET
] = { 0, 0, 16, 1, 12, 0 },
196 [RTL_REG_TRAP_CPU
] = { 3, 2, 22, 1, 6, 0 },
198 [RTL_REG_VLAN_TAG_ONLY
] = { 0, 0, 16, 1, 8, 1 },
199 [RTL_REG_VLAN_FILTER
] = { 0, 0, 16, 1, 9, 1 },
200 [RTL_REG_VLAN_TAG_AWARE
] = { 0, 0, 16, 1, 10, 1 },
201 [RTL_REG_VLAN_ENABLE
] = { 0, 0, 18, 1, 8, 1 },
203 #define RTL_VLAN_REGS(id, phy, page, regofs) \
204 [RTL_REG_VLAN##id##_VID] = { page, phy, 25 + regofs, 12, 0, 0 }, \
205 [RTL_REG_VLAN##id##_PORTMASK] = { page, phy, 24 + regofs, 6, 0, 0 }
206 RTL_VLAN_REGS( 0, 0, 0, 0),
207 RTL_VLAN_REGS( 1, 1, 0, 0),
208 RTL_VLAN_REGS( 2, 2, 0, 0),
209 RTL_VLAN_REGS( 3, 3, 0, 0),
210 RTL_VLAN_REGS( 4, 4, 0, 0),
211 RTL_VLAN_REGS( 5, 0, 1, 2),
212 RTL_VLAN_REGS( 6, 1, 1, 2),
213 RTL_VLAN_REGS( 7, 2, 1, 2),
214 RTL_VLAN_REGS( 8, 3, 1, 2),
215 RTL_VLAN_REGS( 9, 4, 1, 2),
216 RTL_VLAN_REGS(10, 0, 1, 4),
217 RTL_VLAN_REGS(11, 1, 1, 4),
218 RTL_VLAN_REGS(12, 2, 1, 4),
219 RTL_VLAN_REGS(13, 3, 1, 4),
220 RTL_VLAN_REGS(14, 4, 1, 4),
221 RTL_VLAN_REGS(15, 0, 1, 6),
223 #define REG_PORT_SETTING(port, phy) \
224 [RTL_REG_PORT##port##_SPEED] = { 0, phy, 0, 1, 13, 0 }, \
225 [RTL_REG_PORT##port##_NWAY] = { 0, phy, 0, 1, 12, 0 }, \
226 [RTL_REG_PORT##port##_NRESTART] = { 0, phy, 0, 1, 9, 0 }, \
227 [RTL_REG_PORT##port##_DUPLEX] = { 0, phy, 0, 1, 8, 0 }, \
228 [RTL_REG_PORT##port##_TXEN] = { 0, phy, 24, 1, 11, 0 }, \
229 [RTL_REG_PORT##port##_RXEN] = { 0, phy, 24, 1, 10, 0 }, \
230 [RTL_REG_PORT##port##_LINK] = { 0, phy, 1, 1, 2, 0 }, \
231 [RTL_REG_PORT##port##_NULL_VID_REPLACE] = { 0, phy, 22, 1, 12, 0 }, \
232 [RTL_REG_PORT##port##_NON_PVID_DISCARD] = { 0, phy, 22, 1, 11, 0 }, \
233 [RTL_REG_PORT##port##_VID_INSERT] = { 0, phy, 22, 2, 9, 0 }, \
234 [RTL_REG_PORT##port##_TAG_INSERT] = { 0, phy, 22, 2, 0, 0 }
236 REG_PORT_SETTING(0, 0),
237 REG_PORT_SETTING(1, 1),
238 REG_PORT_SETTING(2, 2),
239 REG_PORT_SETTING(3, 3),
240 REG_PORT_SETTING(4, 4),
241 REG_PORT_SETTING(5, 6),
243 #define REG_PORT_PVID(phy, page, regofs) \
244 { page, phy, 24 + regofs, 4, 12, 0 }
245 [RTL_REG_PORT0_PVID
] = REG_PORT_PVID(0, 0, 0),
246 [RTL_REG_PORT1_PVID
] = REG_PORT_PVID(1, 0, 0),
247 [RTL_REG_PORT2_PVID
] = REG_PORT_PVID(2, 0, 0),
248 [RTL_REG_PORT3_PVID
] = REG_PORT_PVID(3, 0, 0),
249 [RTL_REG_PORT4_PVID
] = REG_PORT_PVID(4, 0, 0),
250 [RTL_REG_PORT5_PVID
] = REG_PORT_PVID(0, 1, 2),
255 rtl_set_page(struct rtl_priv
*priv
, unsigned int page
)
257 struct mii_bus
*bus
= priv
->bus
;
263 if (priv
->page
== page
)
266 BUG_ON(page
> RTL8306_NUM_PAGES
);
267 pgsel
= bus
->read(bus
, 0, RTL8306_REG_PAGE
);
268 pgsel
&= ~(RTL8306_REG_PAGE_LO
| RTL8306_REG_PAGE_HI
);
270 pgsel
|= RTL8306_REG_PAGE_LO
;
271 if (!(page
& (1 << 1))) /* bit is inverted */
272 pgsel
|= RTL8306_REG_PAGE_HI
;
273 bus
->write(bus
, 0, RTL8306_REG_PAGE
, pgsel
);
277 rtl_w16(struct switch_dev
*dev
, unsigned int page
, unsigned int phy
, unsigned int reg
, u16 val
)
279 struct rtl_priv
*priv
= to_rtl(dev
);
280 struct mii_bus
*bus
= priv
->bus
;
282 rtl_set_page(priv
, page
);
283 bus
->write(bus
, phy
, reg
, val
);
284 bus
->read(bus
, phy
, reg
); /* flush */
289 rtl_r16(struct switch_dev
*dev
, unsigned int page
, unsigned int phy
, unsigned int reg
)
291 struct rtl_priv
*priv
= to_rtl(dev
);
292 struct mii_bus
*bus
= priv
->bus
;
294 rtl_set_page(priv
, page
);
295 return bus
->read(bus
, phy
, reg
);
299 rtl_rmw(struct switch_dev
*dev
, unsigned int page
, unsigned int phy
, unsigned int reg
, u16 mask
, u16 val
)
301 struct rtl_priv
*priv
= to_rtl(dev
);
302 struct mii_bus
*bus
= priv
->bus
;
305 rtl_set_page(priv
, page
);
306 r
= bus
->read(bus
, phy
, reg
);
309 bus
->write(bus
, phy
, reg
, r
);
310 return bus
->read(bus
, phy
, reg
); /* flush */
315 rtl_get(struct switch_dev
*dev
, enum rtl_regidx s
)
317 const struct rtl_reg
*r
= &rtl_regs
[s
];
320 BUG_ON(s
>= ARRAY_SIZE(rtl_regs
));
321 if (r
->bits
== 0) /* unimplemented */
324 val
= rtl_r16(dev
, r
->page
, r
->phy
, r
->reg
);
332 val
&= (1 << r
->bits
) - 1;
338 rtl_set(struct switch_dev
*dev
, enum rtl_regidx s
, unsigned int val
)
340 const struct rtl_reg
*r
= &rtl_regs
[s
];
343 BUG_ON(s
>= ARRAY_SIZE(rtl_regs
));
345 if (r
->bits
== 0) /* unimplemented */
355 mask
= (1 << r
->bits
) - 1;
359 return rtl_rmw(dev
, r
->page
, r
->phy
, r
->reg
, mask
, val
);
363 rtl_fix_pvids(struct switch_dev
*dev
)
365 unsigned int port
, vlan
, mask
;
367 for (port
= 0; port
< RTL8306_NUM_PORTS
; port
++)
369 /* skip tagged ports */
370 if (rtl_get(dev
, RTL_PORT_REG(port
, TAG_INSERT
)) != 1)
373 for (vlan
= 0; vlan
< RTL8306_NUM_VLANS
; vlan
++)
375 mask
= rtl_get(dev
, RTL_VLAN_REG(vlan
, PORTMASK
));
376 /* skip non-members */
377 if (!(mask
& (1 << port
)))
380 rtl_set(dev
, RTL_PORT_REG(port
, PVID
), vlan
);
388 rtl_phy_save(struct switch_dev
*dev
, int port
, struct rtl_phyregs
*regs
)
390 regs
->nway
= rtl_get(dev
, RTL_PORT_REG(port
, NWAY
));
391 regs
->speed
= rtl_get(dev
, RTL_PORT_REG(port
, SPEED
));
392 regs
->duplex
= rtl_get(dev
, RTL_PORT_REG(port
, DUPLEX
));
396 rtl_phy_restore(struct switch_dev
*dev
, int port
, struct rtl_phyregs
*regs
)
398 rtl_set(dev
, RTL_PORT_REG(port
, NWAY
), regs
->nway
);
399 rtl_set(dev
, RTL_PORT_REG(port
, SPEED
), regs
->speed
);
400 rtl_set(dev
, RTL_PORT_REG(port
, DUPLEX
), regs
->duplex
);
404 rtl_port_set_enable(struct switch_dev
*dev
, int port
, int enabled
)
406 rtl_set(dev
, RTL_PORT_REG(port
, RXEN
), enabled
);
407 rtl_set(dev
, RTL_PORT_REG(port
, TXEN
), enabled
);
409 if ((port
>= 5) || !enabled
)
412 /* restart autonegotiation if enabled */
413 rtl_set(dev
, RTL_PORT_REG(port
, NRESTART
), 1);
417 rtl_hw_apply(struct switch_dev
*dev
)
420 int trunk_en
, trunk_psel
;
421 struct rtl_phyregs port5
;
423 rtl_phy_save(dev
, 5, &port5
);
425 /* disable rx/tx from PHYs */
426 for (i
= 0; i
< RTL8306_NUM_PORTS
- 1; i
++) {
427 rtl_port_set_enable(dev
, i
, 0);
430 /* save trunking status */
431 trunk_en
= rtl_get(dev
, RTL_REG_EN_TRUNK
);
432 trunk_psel
= rtl_get(dev
, RTL_REG_TRUNK_PORTSEL
);
434 /* trunk port 3 and 4
435 * XXX: Big WTF, but RealTek seems to do it */
436 rtl_set(dev
, RTL_REG_EN_TRUNK
, 1);
437 rtl_set(dev
, RTL_REG_TRUNK_PORTSEL
, 1);
439 /* execute the software reset */
440 rtl_set(dev
, RTL_REG_RESET
, 1);
442 /* wait for the reset to complete,
443 * but don't wait for too long */
444 for (i
= 0; i
< 10; i
++) {
445 if (rtl_get(dev
, RTL_REG_RESET
) == 0)
451 /* enable rx/tx from PHYs */
452 for (i
= 0; i
< RTL8306_NUM_PORTS
- 1; i
++) {
453 rtl_port_set_enable(dev
, i
, 1);
456 /* restore trunking settings */
457 rtl_set(dev
, RTL_REG_EN_TRUNK
, trunk_en
);
458 rtl_set(dev
, RTL_REG_TRUNK_PORTSEL
, trunk_psel
);
459 rtl_phy_restore(dev
, 5, &port5
);
465 rtl_hw_init(struct switch_dev
*dev
)
467 struct rtl_priv
*priv
= to_rtl(dev
);
470 rtl_set(dev
, RTL_REG_VLAN_ENABLE
, 0);
471 rtl_set(dev
, RTL_REG_VLAN_FILTER
, 0);
472 rtl_set(dev
, RTL_REG_EN_TRUNK
, 0);
473 rtl_set(dev
, RTL_REG_TRUNK_PORTSEL
, 0);
475 /* initialize cpu port settings */
477 rtl_set(dev
, RTL_REG_CPUPORT
, dev
->cpu_port
);
478 rtl_set(dev
, RTL_REG_EN_CPUPORT
, 1);
480 rtl_set(dev
, RTL_REG_CPUPORT
, 7);
481 rtl_set(dev
, RTL_REG_EN_CPUPORT
, 0);
483 rtl_set(dev
, RTL_REG_EN_TAG_OUT
, 0);
484 rtl_set(dev
, RTL_REG_EN_TAG_IN
, 0);
485 rtl_set(dev
, RTL_REG_EN_TAG_CLR
, 0);
487 /* reset all vlans */
488 for (i
= 0; i
< RTL8306_NUM_VLANS
; i
++) {
489 rtl_set(dev
, RTL_VLAN_REG(i
, VID
), i
);
490 rtl_set(dev
, RTL_VLAN_REG(i
, PORTMASK
), 0);
494 /* default to port isolation */
495 for (i
= 0; i
< RTL8306_NUM_PORTS
; i
++) {
496 if (i
!= dev
->cpu_port
)
497 rtl_set(dev
, RTL_VLAN_REG(i
, PORTMASK
), (1 << dev
->cpu_port
) | (1 << i
));
498 rtl_set(dev
, RTL_PORT_REG(i
, PVID
), i
);
499 rtl_set(dev
, RTL_PORT_REG(i
, NULL_VID_REPLACE
), 1);
500 rtl_set(dev
, RTL_PORT_REG(i
, VID_INSERT
), 1);
501 rtl_set(dev
, RTL_PORT_REG(i
, TAG_INSERT
), 3);
511 rtl_set_use_cpuport(struct switch_dev
*dev
, const struct switch_attr
*attr
, struct switch_val
*val
)
513 struct rtl_priv
*priv
= to_rtl(dev
);
514 priv
->do_cpu
= val
->value
.i
;
520 rtl_get_use_cpuport(struct switch_dev
*dev
, const struct switch_attr
*attr
, struct switch_val
*val
)
522 struct rtl_priv
*priv
= to_rtl(dev
);
523 val
->value
.i
= priv
->do_cpu
;
528 rtl_set_cpuport(struct switch_dev
*dev
, const struct switch_attr
*attr
, struct switch_val
*val
)
530 dev
->cpu_port
= val
->value
.i
;
536 rtl_get_cpuport(struct switch_dev
*dev
, const struct switch_attr
*attr
, struct switch_val
*val
)
538 val
->value
.i
= dev
->cpu_port
;
544 rtl_reset(struct switch_dev
*dev
)
551 rtl_attr_set_int(struct switch_dev
*dev
, const struct switch_attr
*attr
, struct switch_val
*val
)
553 int idx
= attr
->id
+ (val
->port_vlan
* attr
->ofs
);
554 struct rtl_phyregs port
;
556 if (attr
->id
>= ARRAY_SIZE(rtl_regs
))
559 if ((attr
->max
> 0) && (val
->value
.i
> attr
->max
))
562 /* access to phy register 22 on port 4/5
563 * needs phy status save/restore */
564 if ((val
->port_vlan
> 3) &&
565 (rtl_regs
[idx
].reg
== 22) &&
566 (rtl_regs
[idx
].page
== 0)) {
568 rtl_phy_save(dev
, val
->port_vlan
, &port
);
569 rtl_set(dev
, idx
, val
->value
.i
);
570 rtl_phy_restore(dev
, val
->port_vlan
, &port
);
572 rtl_set(dev
, idx
, val
->value
.i
);
579 rtl_attr_get_int(struct switch_dev
*dev
, const struct switch_attr
*attr
, struct switch_val
*val
)
581 int idx
= attr
->id
+ (val
->port_vlan
* attr
->ofs
);
583 if (idx
>= ARRAY_SIZE(rtl_regs
))
586 val
->value
.i
= rtl_get(dev
, idx
);
592 rtl_attr_set_port_int(struct switch_dev
*dev
, const struct switch_attr
*attr
, struct switch_val
*val
)
594 if (val
->port_vlan
>= RTL8306_NUM_PORTS
)
597 return rtl_attr_set_int(dev
, attr
, val
);
601 rtl_attr_get_port_int(struct switch_dev
*dev
, const struct switch_attr
*attr
, struct switch_val
*val
)
603 if (val
->port_vlan
>= RTL8306_NUM_PORTS
)
605 return rtl_attr_get_int(dev
, attr
, val
);
610 rtl_attr_set_port_pvid(struct switch_dev
*dev
, const struct switch_attr
*attr
, struct switch_val
*val
)
614 if (val
->port_vlan
>= RTL8306_NUM_PORTS
)
617 for (vlan
= 0; vlan
< RTL8306_NUM_VLANS
; vlan
++) {
618 if (rtl_get(dev
, RTL_VLAN_REG(vlan
, VID
)) == val
->value
.i
) {
619 rtl_set(dev
, RTL_PORT_REG(val
->port_vlan
, PVID
), vlan
);
628 rtl_attr_get_port_pvid(struct switch_dev
*dev
, const struct switch_attr
*attr
, struct switch_val
*val
)
632 if (val
->port_vlan
>= RTL8306_NUM_PORTS
)
635 vlan
= rtl_get(dev
, RTL_PORT_REG(val
->port_vlan
, PVID
));
636 val
->value
.i
= rtl_get(dev
, RTL_VLAN_REG(vlan
, VID
));
642 rtl_get_port_link(struct switch_dev
*dev
, int port
, struct switch_port_link
*link
)
644 if (port
>= RTL8306_NUM_PORTS
)
647 link
->link
= rtl_get(dev
, RTL_PORT_REG(port
, LINK
));
651 link
->duplex
= rtl_get(dev
, RTL_PORT_REG(port
, DUPLEX
));
652 link
->aneg
= rtl_get(dev
, RTL_PORT_REG(port
, NWAY
));
654 if (rtl_get(dev
, RTL_PORT_REG(port
, SPEED
)))
655 link
->speed
= SWITCH_PORT_SPEED_100
;
657 link
->speed
= SWITCH_PORT_SPEED_10
;
663 rtl_attr_set_vlan_int(struct switch_dev
*dev
, const struct switch_attr
*attr
, struct switch_val
*val
)
665 if (val
->port_vlan
>= dev
->vlans
)
668 return rtl_attr_set_int(dev
, attr
, val
);
672 rtl_attr_get_vlan_int(struct switch_dev
*dev
, const struct switch_attr
*attr
, struct switch_val
*val
)
674 if (val
->port_vlan
>= dev
->vlans
)
677 return rtl_attr_get_int(dev
, attr
, val
);
681 rtl_get_ports(struct switch_dev
*dev
, struct switch_val
*val
)
683 unsigned int i
, mask
;
685 mask
= rtl_get(dev
, RTL_VLAN_REG(val
->port_vlan
, PORTMASK
));
686 for (i
= 0; i
< RTL8306_NUM_PORTS
; i
++) {
687 struct switch_port
*port
;
689 if (!(mask
& (1 << i
)))
692 port
= &val
->value
.ports
[val
->len
];
694 if (rtl_get(dev
, RTL_PORT_REG(i
, TAG_INSERT
)) == 2)
695 port
->flags
= (1 << SWITCH_PORT_FLAG_TAGGED
);
703 rtl_set_vlan(struct switch_dev
*dev
, const struct switch_attr
*attr
, struct switch_val
*val
)
705 struct rtl_priv
*priv
= to_rtl(dev
);
706 struct rtl_phyregs port
;
707 int en
= val
->value
.i
;
710 rtl_set(dev
, RTL_REG_EN_TAG_OUT
, en
&& priv
->do_cpu
);
711 rtl_set(dev
, RTL_REG_EN_TAG_IN
, en
&& priv
->do_cpu
);
712 rtl_set(dev
, RTL_REG_EN_TAG_CLR
, en
&& priv
->do_cpu
);
713 rtl_set(dev
, RTL_REG_VLAN_TAG_AWARE
, en
);
715 rtl_set(dev
, RTL_REG_VLAN_FILTER
, en
);
717 for (i
= 0; i
< RTL8306_NUM_PORTS
; i
++) {
719 rtl_phy_save(dev
, val
->port_vlan
, &port
);
720 rtl_set(dev
, RTL_PORT_REG(i
, NULL_VID_REPLACE
), 1);
721 rtl_set(dev
, RTL_PORT_REG(i
, VID_INSERT
), 1);
722 rtl_set(dev
, RTL_PORT_REG(i
, TAG_INSERT
), (en
? 1 : 3));
724 rtl_phy_restore(dev
, val
->port_vlan
, &port
);
726 rtl_set(dev
, RTL_REG_VLAN_ENABLE
, en
);
734 rtl_get_vlan(struct switch_dev
*dev
, const struct switch_attr
*attr
, struct switch_val
*val
)
736 val
->value
.i
= rtl_get(dev
, RTL_REG_VLAN_ENABLE
);
741 rtl_set_ports(struct switch_dev
*dev
, struct switch_val
*val
)
743 unsigned int mask
= 0;
746 for(i
= 0; i
< val
->len
; i
++)
748 struct switch_port
*port
= &val
->value
.ports
[i
];
751 mask
|= (1 << port
->id
);
753 if (port
->flags
& (1 << SWITCH_PORT_FLAG_TAGGED
))
756 rtl_set(dev
, RTL_PORT_REG(port
->id
, NON_PVID_DISCARD
), (tagged
? 0 : 1));
757 rtl_set(dev
, RTL_PORT_REG(port
->id
, VID_INSERT
), (tagged
? 0 : 1));
758 rtl_set(dev
, RTL_PORT_REG(port
->id
, TAG_INSERT
), (tagged
? 2 : 1));
761 rtl_set(dev
, RTL_VLAN_REG(val
->port_vlan
, PORTMASK
), mask
);
768 static struct switch_attr rtl_globals
[] = {
770 .type
= SWITCH_TYPE_INT
,
771 .name
= "enable_vlan",
772 .description
= "Enable VLAN mode",
778 RTL_GLOBAL_REGATTR(EN_TRUNK
),
780 .description
= "Enable port trunking",
784 RTL_GLOBAL_REGATTR(TRUNK_PORTSEL
),
786 .description
= "Select ports for trunking (0: 0,1 - 1: 3,4)",
791 RTL_GLOBAL_REGATTR(VLAN_FILTER
),
792 .name
= "vlan_filter",
793 .description
= "Filter incoming packets for allowed VLANS",
797 .type
= SWITCH_TYPE_INT
,
799 .description
= "CPU Port",
800 .set
= rtl_set_cpuport
,
801 .get
= rtl_get_cpuport
,
802 .max
= RTL8306_NUM_PORTS
,
805 .type
= SWITCH_TYPE_INT
,
806 .name
= "use_cpuport",
807 .description
= "CPU Port handling flag",
808 .set
= rtl_set_use_cpuport
,
809 .get
= rtl_get_use_cpuport
,
810 .max
= RTL8306_NUM_PORTS
,
813 RTL_GLOBAL_REGATTR(TRAP_CPU
),
815 .description
= "VLAN trap to CPU",
819 RTL_GLOBAL_REGATTR(VLAN_TAG_AWARE
),
820 .name
= "vlan_tag_aware",
821 .description
= "Enable VLAN tag awareness",
825 RTL_GLOBAL_REGATTR(VLAN_TAG_ONLY
),
827 .description
= "Only accept tagged packets",
832 static struct switch_attr rtl_port
[] = {
834 .type
= SWITCH_TYPE_INT
,
835 .set
= rtl_attr_set_port_pvid
,
836 .get
= rtl_attr_get_port_pvid
,
838 .description
= "Port VLAN ID",
843 RTL_PORT_REGATTR(NULL_VID_REPLACE
),
845 .description
= "NULL VID gets replaced by port default vid",
849 RTL_PORT_REGATTR(NON_PVID_DISCARD
),
850 .name
= "non_pvid_discard",
851 .description
= "discard packets with VID != PVID",
855 RTL_PORT_REGATTR(VID_INSERT
),
856 .name
= "vid_insert_remove",
857 .description
= "how should the switch insert and remove vids ?",
861 RTL_PORT_REGATTR(TAG_INSERT
),
862 .name
= "tag_insert",
863 .description
= "tag insertion handling",
869 static struct switch_attr rtl_vlan
[] = {
871 RTL_VLAN_REGATTR(VID
),
873 .description
= "VLAN ID (1-4095)",
878 static const struct switch_dev_ops rtl8306_ops
= {
881 .n_attr
= ARRAY_SIZE(rtl_globals
),
885 .n_attr
= ARRAY_SIZE(rtl_port
),
889 .n_attr
= ARRAY_SIZE(rtl_vlan
),
892 .get_vlan_ports
= rtl_get_ports
,
893 .set_vlan_ports
= rtl_set_ports
,
894 .apply_config
= rtl_hw_apply
,
895 .reset_switch
= rtl_reset
,
896 .get_port_link
= rtl_get_port_link
,
900 rtl8306_config_init(struct phy_device
*pdev
)
902 struct net_device
*netdev
= pdev
->attached_dev
;
903 struct rtl_priv
*priv
= pdev
->priv
;
904 struct switch_dev
*dev
= &priv
->dev
;
905 struct switch_val val
;
906 unsigned int chipid
, chipver
, chiptype
;
909 /* Only init the switch for the primary PHY */
914 priv
->dev
.cpu_port
= RTL8306_PORT_CPU
;
915 priv
->dev
.ports
= RTL8306_NUM_PORTS
;
916 priv
->dev
.vlans
= RTL8306_NUM_VLANS
;
917 priv
->dev
.ops
= &rtl8306_ops
;
920 priv
->bus
= pdev
->bus
;
922 chipid
= rtl_get(dev
, RTL_REG_CHIPID
);
923 chipver
= rtl_get(dev
, RTL_REG_CHIPVER
);
924 chiptype
= rtl_get(dev
, RTL_REG_CHIPTYPE
);
928 strncpy(priv
->hwname
, RTL_NAME_S
, sizeof(priv
->hwname
));
929 priv
->type
= RTL_TYPE_S
;
932 strncpy(priv
->hwname
, RTL_NAME_SD
, sizeof(priv
->hwname
));
933 priv
->type
= RTL_TYPE_SD
;
936 strncpy(priv
->hwname
, RTL_NAME_SDM
, sizeof(priv
->hwname
));
937 priv
->type
= RTL_TYPE_SDM
;
940 strncpy(priv
->hwname
, RTL_NAME_UNKNOWN
, sizeof(priv
->hwname
));
944 dev
->name
= priv
->hwname
;
947 printk(KERN_INFO
"Registering %s switch with Chip ID: 0x%04x, version: 0x%04x\n", priv
->hwname
, chipid
, chipver
);
949 err
= register_switch(dev
, netdev
);
960 rtl8306_fixup(struct phy_device
*pdev
)
962 struct rtl_priv priv
;
965 /* Attach to primary LAN port and WAN port */
966 if (pdev
->addr
!= 0 && pdev
->addr
!= 4)
969 memset(&priv
, 0, sizeof(priv
));
972 priv
.bus
= pdev
->bus
;
973 chipid
= rtl_get(&priv
.dev
, RTL_REG_CHIPID
);
974 if (chipid
== 0x5988)
975 pdev
->phy_id
= RTL8306_MAGIC
;
981 rtl8306_probe(struct phy_device
*pdev
)
983 struct rtl_priv
*priv
;
985 list_for_each_entry(priv
, &phydevs
, list
) {
987 * share one rtl_priv instance between virtual phy
988 * devices on the same bus
990 if (priv
->bus
== pdev
->bus
)
993 priv
= kzalloc(sizeof(struct rtl_priv
), GFP_KERNEL
);
997 priv
->bus
= pdev
->bus
;
1005 rtl8306_remove(struct phy_device
*pdev
)
1007 struct rtl_priv
*priv
= pdev
->priv
;
1008 unregister_switch(&priv
->dev
);
1013 rtl8306_config_aneg(struct phy_device
*pdev
)
1015 struct rtl_priv
*priv
= pdev
->priv
;
1018 if (pdev
->addr
== 0)
1021 /* Restart autonegotiation */
1022 rtl_set(&priv
->dev
, RTL_PORT_REG(4, NWAY
), 1);
1023 rtl_set(&priv
->dev
, RTL_PORT_REG(4, NRESTART
), 1);
1029 rtl8306_read_status(struct phy_device
*pdev
)
1031 struct rtl_priv
*priv
= pdev
->priv
;
1032 struct switch_dev
*dev
= &priv
->dev
;
1034 if (pdev
->addr
== 4) {
1036 pdev
->speed
= rtl_get(dev
, RTL_PORT_REG(4, SPEED
)) ? SPEED_100
: SPEED_10
;
1037 pdev
->duplex
= rtl_get(dev
, RTL_PORT_REG(4, DUPLEX
)) ? DUPLEX_FULL
: DUPLEX_HALF
;
1038 pdev
->link
= !!rtl_get(dev
, RTL_PORT_REG(4, LINK
));
1041 pdev
->speed
= SPEED_100
;
1042 pdev
->duplex
= DUPLEX_FULL
;
1047 * Bypass generic PHY status read,
1048 * it doesn't work with this switch
1051 pdev
->state
= PHY_RUNNING
;
1052 netif_carrier_on(pdev
->attached_dev
);
1053 pdev
->adjust_link(pdev
->attached_dev
);
1055 pdev
->state
= PHY_NOLINK
;
1056 netif_carrier_off(pdev
->attached_dev
);
1057 pdev
->adjust_link(pdev
->attached_dev
);
1064 static struct phy_driver rtl8306_driver
= {
1065 .name
= "Realtek RTL8306S",
1066 .flags
= PHY_HAS_MAGICANEG
,
1067 .phy_id
= RTL8306_MAGIC
,
1068 .phy_id_mask
= 0xffffffff,
1069 .features
= PHY_BASIC_FEATURES
,
1070 .probe
= &rtl8306_probe
,
1071 .remove
= &rtl8306_remove
,
1072 .config_init
= &rtl8306_config_init
,
1073 .config_aneg
= &rtl8306_config_aneg
,
1074 .read_status
= &rtl8306_read_status
,
1075 .driver
= { .owner
= THIS_MODULE
,},
1082 phy_register_fixup_for_id(PHY_ANY_ID
, rtl8306_fixup
);
1083 return phy_driver_register(&rtl8306_driver
);
1089 phy_driver_unregister(&rtl8306_driver
);
1092 module_init(rtl_init
);
1093 module_exit(rtl_exit
);
1094 MODULE_LICENSE("GPL");