2 * Platform driver for the Realtek RTL8366S ethernet switch
4 * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/platform_device.h>
16 #include <linux/delay.h>
17 #include <linux/skbuff.h>
18 #include <linux/switch.h>
19 #include <linux/rtl8366rb.h>
21 #include "rtl8366_smi.h"
23 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
24 #include <linux/debugfs.h>
27 #define RTL8366S_DRIVER_DESC "Realtek RTL8366RB ethernet switch driver"
28 #define RTL8366S_DRIVER_VER "0.2.2"
30 #define RTL8366S_PHY_NO_MAX 4
31 #define RTL8366S_PHY_PAGE_MAX 7
32 #define RTL8366S_PHY_ADDR_MAX 31
34 #define RTL8366_CHIP_GLOBAL_CTRL_REG 0x0000
35 #define RTL8366_CHIP_CTRL_VLAN (1 << 13)
36 #define RTL8366_CHIP_CTRL_VLAN_4KTB (1 << 14)
38 /* Switch Global Configuration register */
39 #define RTL8366_SGCR 0x0000
40 #define RTL8366_SGCR_EN_BC_STORM_CTRL BIT(0)
41 #define RTL8366_SGCR_MAX_LENGTH(_x) (_x << 4)
42 #define RTL8366_SGCR_MAX_LENGTH_MASK RTL8366_SGCR_MAX_LENGTH(0x3)
43 #define RTL8366_SGCR_MAX_LENGTH_1522 RTL8366_SGCR_MAX_LENGTH(0x0)
44 #define RTL8366_SGCR_MAX_LENGTH_1536 RTL8366_SGCR_MAX_LENGTH(0x1)
45 #define RTL8366_SGCR_MAX_LENGTH_1552 RTL8366_SGCR_MAX_LENGTH(0x2)
46 #define RTL8366_SGCR_MAX_LENGTH_9216 RTL8366_SGCR_MAX_LENGTH(0x3)
48 /* Port Enable Control register */
49 #define RTL8366_PECR 0x0001
51 /* Switch Security Control registers */
52 #define RTL8366_SSCR0 0x0002
53 #define RTL8366_SSCR1 0x0003
54 #define RTL8366_SSCR2 0x0004
55 #define RTL8366_SSCR2_DROP_UNKNOWN_DA BIT(0)
57 #define RTL8366_RESET_CTRL_REG 0x0100
58 #define RTL8366_CHIP_CTRL_RESET_HW 1
59 #define RTL8366_CHIP_CTRL_RESET_SW (1 << 1)
61 #define RTL8366S_CHIP_VERSION_CTRL_REG 0x050A
62 #define RTL8366S_CHIP_VERSION_MASK 0xf
63 #define RTL8366S_CHIP_ID_REG 0x0509
64 #define RTL8366S_CHIP_ID_8366 0x5937
66 /* PHY registers control */
67 #define RTL8366S_PHY_ACCESS_CTRL_REG 0x8000
68 #define RTL8366S_PHY_ACCESS_DATA_REG 0x8002
70 #define RTL8366S_PHY_CTRL_READ 1
71 #define RTL8366S_PHY_CTRL_WRITE 0
73 #define RTL8366S_PHY_REG_MASK 0x1f
74 #define RTL8366S_PHY_PAGE_OFFSET 5
75 #define RTL8366S_PHY_PAGE_MASK (0xf << 5)
76 #define RTL8366S_PHY_NO_OFFSET 9
77 #define RTL8366S_PHY_NO_MASK (0x1f << 9)
79 /* LED control registers */
80 #define RTL8366_LED_BLINKRATE_REG 0x0430
81 #define RTL8366_LED_BLINKRATE_BIT 0
82 #define RTL8366_LED_BLINKRATE_MASK 0x0007
84 #define RTL8366_LED_CTRL_REG 0x0431
85 #define RTL8366_LED_0_1_CTRL_REG 0x0432
86 #define RTL8366_LED_2_3_CTRL_REG 0x0433
88 #define RTL8366S_MIB_COUNT 33
89 #define RTL8366S_GLOBAL_MIB_COUNT 1
90 #define RTL8366S_MIB_COUNTER_PORT_OFFSET 0x0050
91 #define RTL8366S_MIB_COUNTER_BASE 0x1000
92 #define RTL8366S_MIB_CTRL_REG 0x13F0
93 #define RTL8366S_MIB_CTRL_USER_MASK 0x0FFC
94 #define RTL8366S_MIB_CTRL_BUSY_MASK 0x0001
95 #define RTL8366S_MIB_CTRL_RESET_MASK 0x0001
97 #define RTL8366S_MIB_CTRL_GLOBAL_RESET_MASK 0x0004
98 #define RTL8366S_MIB_CTRL_PORT_RESET_BIT 0x0003
99 #define RTL8366S_MIB_CTRL_PORT_RESET_MASK 0x01FC
102 #define RTL8366S_PORT_VLAN_CTRL_BASE 0x0063
103 #define RTL8366S_PORT_VLAN_CTRL_REG(_p) \
104 (RTL8366S_PORT_VLAN_CTRL_BASE + (_p) / 4)
105 #define RTL8366S_PORT_VLAN_CTRL_MASK 0xf
106 #define RTL8366S_PORT_VLAN_CTRL_SHIFT(_p) (4 * ((_p) % 4))
109 #define RTL8366S_VLAN_TABLE_READ_BASE 0x018C
110 #define RTL8366S_VLAN_TABLE_WRITE_BASE 0x0185
113 #define RTL8366S_TABLE_ACCESS_CTRL_REG 0x0180
114 #define RTL8366S_TABLE_VLAN_READ_CTRL 0x0E01
115 #define RTL8366S_TABLE_VLAN_WRITE_CTRL 0x0F01
117 #define RTL8366S_VLAN_MEMCONF_BASE 0x0020
120 #define RTL8366S_PORT_LINK_STATUS_BASE 0x0014
121 #define RTL8366S_PORT_STATUS_SPEED_MASK 0x0003
122 #define RTL8366S_PORT_STATUS_DUPLEX_MASK 0x0004
123 #define RTL8366S_PORT_STATUS_LINK_MASK 0x0010
124 #define RTL8366S_PORT_STATUS_TXPAUSE_MASK 0x0020
125 #define RTL8366S_PORT_STATUS_RXPAUSE_MASK 0x0040
126 #define RTL8366S_PORT_STATUS_AN_MASK 0x0080
129 #define RTL8366_PORT_NUM_CPU 5
130 #define RTL8366_NUM_PORTS 6
131 #define RTL8366_NUM_VLANS 16
132 #define RTL8366_NUM_LEDGROUPS 4
133 #define RTL8366_NUM_VIDS 4096
134 #define RTL8366S_PRIORITYMAX 7
135 #define RTL8366S_FIDMAX 7
138 #define RTL8366_PORT_1 (1 << 0) /* In userspace port 0 */
139 #define RTL8366_PORT_2 (1 << 1) /* In userspace port 1 */
140 #define RTL8366_PORT_3 (1 << 2) /* In userspace port 2 */
141 #define RTL8366_PORT_4 (1 << 3) /* In userspace port 3 */
142 #define RTL8366_PORT_5 (1 << 4) /* In userspace port 4 */
144 #define RTL8366_PORT_CPU (1 << 5) /* CPU port */
146 #define RTL8366_PORT_ALL (RTL8366_PORT_1 | \
153 #define RTL8366_PORT_ALL_BUT_CPU (RTL8366_PORT_1 | \
159 #define RTL8366_PORT_ALL_EXTERNAL (RTL8366_PORT_1 | \
164 #define RTL8366_PORT_ALL_INTERNAL RTL8366_PORT_CPU
167 struct device
*parent
;
168 struct rtl8366_smi smi
;
169 struct switch_dev dev
;
171 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
172 struct dentry
*debugfs_root
;
176 struct rtl8366rb_vlan_mc
{
188 struct rtl8366rb_vlan_4k
{
197 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
207 static struct mib_counter rtl8366rb_mib_counters
[RTL8366S_MIB_COUNT
] = {
208 { 0, 4, "IfInOctets" },
209 { 4, 4, "EtherStatsOctets" },
210 { 8, 2, "EtherStatsUnderSizePkts" },
211 { 10, 2, "EtherFragments" },
212 { 12, 2, "EtherStatsPkts64Octets" },
213 { 14, 2, "EtherStatsPkts65to127Octets" },
214 { 16, 2, "EtherStatsPkts128to255Octets" },
215 { 18, 2, "EtherStatsPkts256to511Octets" },
216 { 20, 2, "EtherStatsPkts512to1023Octets" },
217 { 22, 2, "EtherStatsPkts1024to1518Octets" },
218 { 24, 2, "EtherOversizeStats" },
219 { 26, 2, "EtherStatsJabbers" },
220 { 28, 2, "IfInUcastPkts" },
221 { 30, 2, "EtherStatsMulticastPkts" },
222 { 32, 2, "EtherStatsBroadcastPkts" },
223 { 34, 2, "EtherStatsDropEvents" },
224 { 36, 2, "Dot3StatsFCSErrors" },
225 { 38, 2, "Dot3StatsSymbolErrors" },
226 { 40, 2, "Dot3InPauseFrames" },
227 { 42, 2, "Dot3ControlInUnknownOpcodes" },
228 { 44, 4, "IfOutOctets" },
229 { 48, 2, "Dot3StatsSingleCollisionFrames" },
230 { 50, 2, "Dot3StatMultipleCollisionFrames" },
231 { 52, 2, "Dot3sDeferredTransmissions" },
232 { 54, 2, "Dot3StatsLateCollisions" },
233 { 56, 2, "EtherStatsCollisions" },
234 { 58, 2, "Dot3StatsExcessiveCollisions" },
235 { 60, 2, "Dot3OutPauseFrames" },
236 { 62, 2, "Dot1dBasePortDelayExceededDiscards" },
237 { 64, 2, "Dot1dTpPortInDiscards" },
238 { 66, 2, "IfOutUcastPkts" },
239 { 68, 2, "IfOutMulticastPkts" },
240 { 70, 2, "IfOutBroadcastPkts" },
243 #define REG_WR(_smi, _reg, _val) \
245 err = rtl8366_smi_write_reg(_smi, _reg, _val); \
250 #define REG_RMW(_smi, _reg, _mask, _val) \
252 err = rtl8366_smi_rmwr(_smi, _reg, _mask, _val); \
257 static inline struct rtl8366rb
*smi_to_rtl8366rb(struct rtl8366_smi
*smi
)
259 return container_of(smi
, struct rtl8366rb
, smi
);
262 static inline struct rtl8366rb
*sw_to_rtl8366rb(struct switch_dev
*sw
)
264 return container_of(sw
, struct rtl8366rb
, dev
);
267 static inline struct rtl8366_smi
*sw_to_rtl8366_smi(struct switch_dev
*sw
)
269 struct rtl8366rb
*rtl
= sw_to_rtl8366rb(sw
);
273 static int rtl8366rb_reset_chip(struct rtl8366_smi
*smi
)
278 rtl8366_smi_write_reg(smi
, RTL8366_RESET_CTRL_REG
,
279 RTL8366_CHIP_CTRL_RESET_HW
);
282 if (rtl8366_smi_read_reg(smi
, RTL8366_RESET_CTRL_REG
, &data
))
285 if (!(data
& RTL8366_CHIP_CTRL_RESET_HW
))
290 printk("Timeout waiting for the switch to reset\n");
297 static int rtl8366rb_hw_init(struct rtl8366_smi
*smi
)
301 /* set maximum packet length to 1536 bytes */
302 REG_RMW(smi
, RTL8366_SGCR
, RTL8366_SGCR_MAX_LENGTH_MASK
,
303 RTL8366_SGCR_MAX_LENGTH_1536
);
305 /* enable all ports */
306 REG_WR(smi
, RTL8366_PECR
, 0);
308 /* disable learning for all ports */
309 REG_WR(smi
, RTL8366_SSCR0
, RTL8366_PORT_ALL
);
311 /* disable auto ageing for all ports */
312 REG_WR(smi
, RTL8366_SSCR1
, RTL8366_PORT_ALL
);
314 /* don't drop packets whose DA has not been learned */
315 REG_RMW(smi
, RTL8366_SSCR2
, RTL8366_SSCR2_DROP_UNKNOWN_DA
, 0);
320 static int rtl8366rb_read_phy_reg(struct rtl8366_smi
*smi
,
321 u32 phy_no
, u32 page
, u32 addr
, u32
*data
)
326 if (phy_no
> RTL8366S_PHY_NO_MAX
)
329 if (page
> RTL8366S_PHY_PAGE_MAX
)
332 if (addr
> RTL8366S_PHY_ADDR_MAX
)
335 ret
= rtl8366_smi_write_reg(smi
, RTL8366S_PHY_ACCESS_CTRL_REG
,
336 RTL8366S_PHY_CTRL_READ
);
340 reg
= 0x8000 | (1 << (phy_no
+ RTL8366S_PHY_NO_OFFSET
)) |
341 ((page
<< RTL8366S_PHY_PAGE_OFFSET
) & RTL8366S_PHY_PAGE_MASK
) |
342 (addr
& RTL8366S_PHY_REG_MASK
);
344 ret
= rtl8366_smi_write_reg(smi
, reg
, 0);
348 ret
= rtl8366_smi_read_reg(smi
, RTL8366S_PHY_ACCESS_DATA_REG
, data
);
355 static int rtl8366rb_write_phy_reg(struct rtl8366_smi
*smi
,
356 u32 phy_no
, u32 page
, u32 addr
, u32 data
)
361 if (phy_no
> RTL8366S_PHY_NO_MAX
)
364 if (page
> RTL8366S_PHY_PAGE_MAX
)
367 if (addr
> RTL8366S_PHY_ADDR_MAX
)
370 ret
= rtl8366_smi_write_reg(smi
, RTL8366S_PHY_ACCESS_CTRL_REG
,
371 RTL8366S_PHY_CTRL_WRITE
);
375 reg
= 0x8000 | (1 << (phy_no
+ RTL8366S_PHY_NO_OFFSET
)) |
376 ((page
<< RTL8366S_PHY_PAGE_OFFSET
) & RTL8366S_PHY_PAGE_MASK
) |
377 (addr
& RTL8366S_PHY_REG_MASK
);
379 ret
= rtl8366_smi_write_reg(smi
, reg
, data
);
386 static int rtl8366_get_mib_counter(struct rtl8366_smi
*smi
, int counter
,
387 int port
, unsigned long long *val
)
394 if (port
> RTL8366_NUM_PORTS
|| counter
>= RTL8366S_MIB_COUNT
)
397 addr
= RTL8366S_MIB_COUNTER_BASE
+
398 RTL8366S_MIB_COUNTER_PORT_OFFSET
* (port
) +
399 rtl8366rb_mib_counters
[counter
].offset
;
402 * Writing access counter address first
403 * then ASIC will prepare 64bits counter wait for being retrived
405 data
= 0; /* writing data will be discard by ASIC */
406 err
= rtl8366_smi_write_reg(smi
, addr
, data
);
410 /* read MIB control register */
411 err
= rtl8366_smi_read_reg(smi
, RTL8366S_MIB_CTRL_REG
, &data
);
415 if (data
& RTL8366S_MIB_CTRL_BUSY_MASK
)
418 if (data
& RTL8366S_MIB_CTRL_RESET_MASK
)
422 for (i
= rtl8366rb_mib_counters
[counter
].length
; i
> 0; i
--) {
423 err
= rtl8366_smi_read_reg(smi
, addr
+ (i
- 1), &data
);
427 mibvalue
= (mibvalue
<< 16) | (data
& 0xFFFF);
434 static int rtl8366rb_get_vlan_4k(struct rtl8366_smi
*smi
, u32 vid
,
435 struct rtl8366_vlan_4k
*vlan4k
)
437 struct rtl8366rb_vlan_4k vlan4k_priv
;
442 memset(vlan4k
, '\0', sizeof(struct rtl8366_vlan_4k
));
443 vlan4k_priv
.vid
= vid
;
445 if (vid
>= RTL8366_NUM_VIDS
)
448 tableaddr
= (u16
*)&vlan4k_priv
;
452 err
= rtl8366_smi_write_reg(smi
, RTL8366S_VLAN_TABLE_WRITE_BASE
, data
);
456 /* write table access control word */
457 err
= rtl8366_smi_write_reg(smi
, RTL8366S_TABLE_ACCESS_CTRL_REG
,
458 RTL8366S_TABLE_VLAN_READ_CTRL
);
462 err
= rtl8366_smi_read_reg(smi
, RTL8366S_VLAN_TABLE_READ_BASE
, &data
);
469 err
= rtl8366_smi_read_reg(smi
, RTL8366S_VLAN_TABLE_READ_BASE
+ 1,
477 err
= rtl8366_smi_read_reg(smi
, RTL8366S_VLAN_TABLE_READ_BASE
+ 2,
484 vlan4k
->untag
= vlan4k_priv
.untag
;
485 vlan4k
->member
= vlan4k_priv
.member
;
486 vlan4k
->fid
= vlan4k_priv
.fid
;
491 static int rtl8366rb_set_vlan_4k(struct rtl8366_smi
*smi
,
492 const struct rtl8366_vlan_4k
*vlan4k
)
494 struct rtl8366rb_vlan_4k vlan4k_priv
;
499 if (vlan4k
->vid
>= RTL8366_NUM_VIDS
||
500 vlan4k
->member
> RTL8366_PORT_ALL
||
501 vlan4k
->untag
> RTL8366_PORT_ALL
||
502 vlan4k
->fid
> RTL8366S_FIDMAX
)
505 vlan4k_priv
.vid
= vlan4k
->vid
;
506 vlan4k_priv
.untag
= vlan4k
->untag
;
507 vlan4k_priv
.member
= vlan4k
->member
;
508 vlan4k_priv
.fid
= vlan4k
->fid
;
510 tableaddr
= (u16
*)&vlan4k_priv
;
514 err
= rtl8366_smi_write_reg(smi
, RTL8366S_VLAN_TABLE_WRITE_BASE
, data
);
522 err
= rtl8366_smi_write_reg(smi
, RTL8366S_VLAN_TABLE_WRITE_BASE
+ 1,
531 err
= rtl8366_smi_write_reg(smi
, RTL8366S_VLAN_TABLE_WRITE_BASE
+ 2,
536 /* write table access control word */
537 err
= rtl8366_smi_write_reg(smi
, RTL8366S_TABLE_ACCESS_CTRL_REG
,
538 RTL8366S_TABLE_VLAN_WRITE_CTRL
);
543 static int rtl8366rb_get_vlan_mc(struct rtl8366_smi
*smi
, u32 index
,
544 struct rtl8366_vlan_mc
*vlanmc
)
546 struct rtl8366rb_vlan_mc vlanmc_priv
;
552 memset(vlanmc
, '\0', sizeof(struct rtl8366_vlan_mc
));
554 if (index
>= RTL8366_NUM_VLANS
)
557 tableaddr
= (u16
*)&vlanmc_priv
;
559 addr
= RTL8366S_VLAN_MEMCONF_BASE
+ (index
* 3);
560 err
= rtl8366_smi_read_reg(smi
, addr
, &data
);
567 addr
= RTL8366S_VLAN_MEMCONF_BASE
+ 1 + (index
* 3);
568 err
= rtl8366_smi_read_reg(smi
, addr
, &data
);
575 addr
= RTL8366S_VLAN_MEMCONF_BASE
+ 2 + (index
* 3);
576 err
= rtl8366_smi_read_reg(smi
, addr
, &data
);
582 vlanmc
->vid
= vlanmc_priv
.vid
;
583 vlanmc
->priority
= vlanmc_priv
.priority
;
584 vlanmc
->untag
= vlanmc_priv
.untag
;
585 vlanmc
->member
= vlanmc_priv
.member
;
586 vlanmc
->fid
= vlanmc_priv
.fid
;
591 static int rtl8366rb_set_vlan_mc(struct rtl8366_smi
*smi
, u32 index
,
592 const struct rtl8366_vlan_mc
*vlanmc
)
594 struct rtl8366rb_vlan_mc vlanmc_priv
;
600 if (index
>= RTL8366_NUM_VLANS
||
601 vlanmc
->vid
>= RTL8366_NUM_VIDS
||
602 vlanmc
->priority
> RTL8366S_PRIORITYMAX
||
603 vlanmc
->member
> RTL8366_PORT_ALL
||
604 vlanmc
->untag
> RTL8366_PORT_ALL
||
605 vlanmc
->fid
> RTL8366S_FIDMAX
)
608 vlanmc_priv
.vid
= vlanmc
->vid
;
609 vlanmc_priv
.priority
= vlanmc
->priority
;
610 vlanmc_priv
.untag
= vlanmc
->untag
;
611 vlanmc_priv
.member
= vlanmc
->member
;
612 vlanmc_priv
.stag_mbr
= 0;
613 vlanmc_priv
.stag_idx
= 0;
614 vlanmc_priv
.fid
= vlanmc
->fid
;
616 addr
= RTL8366S_VLAN_MEMCONF_BASE
+ (index
* 3);
618 tableaddr
= (u16
*)&vlanmc_priv
;
621 err
= rtl8366_smi_write_reg(smi
, addr
, data
);
625 addr
= RTL8366S_VLAN_MEMCONF_BASE
+ 1 + (index
* 3);
630 err
= rtl8366_smi_write_reg(smi
, addr
, data
);
634 addr
= RTL8366S_VLAN_MEMCONF_BASE
+ 2 + (index
* 3);
639 err
= rtl8366_smi_write_reg(smi
, addr
, data
);
645 static int rtl8366rb_get_mc_index(struct rtl8366_smi
*smi
, int port
, int *val
)
650 if (port
>= RTL8366_NUM_PORTS
)
653 err
= rtl8366_smi_read_reg(smi
, RTL8366S_PORT_VLAN_CTRL_REG(port
),
658 *val
= (data
>> RTL8366S_PORT_VLAN_CTRL_SHIFT(port
)) &
659 RTL8366S_PORT_VLAN_CTRL_MASK
;
665 static int rtl8366rb_set_mc_index(struct rtl8366_smi
*smi
, int port
, int index
)
667 if (port
>= RTL8366_NUM_PORTS
|| index
>= RTL8366_NUM_VLANS
)
670 return rtl8366_smi_rmwr(smi
, RTL8366S_PORT_VLAN_CTRL_REG(port
),
671 RTL8366S_PORT_VLAN_CTRL_MASK
<<
672 RTL8366S_PORT_VLAN_CTRL_SHIFT(port
),
673 (index
& RTL8366S_PORT_VLAN_CTRL_MASK
) <<
674 RTL8366S_PORT_VLAN_CTRL_SHIFT(port
));
677 static int rtl8366rb_set_vlan(struct rtl8366_smi
*smi
, int vid
, u32 member
,
680 struct rtl8366_vlan_4k vlan4k
;
684 /* Update the 4K table */
685 err
= rtl8366rb_get_vlan_4k(smi
, vid
, &vlan4k
);
689 vlan4k
.member
= member
;
690 vlan4k
.untag
= untag
;
692 err
= rtl8366rb_set_vlan_4k(smi
, &vlan4k
);
696 /* Try to find an existing MC entry for this VID */
697 for (i
= 0; i
< RTL8366_NUM_VLANS
; i
++) {
698 struct rtl8366_vlan_mc vlanmc
;
700 err
= rtl8366rb_get_vlan_mc(smi
, i
, &vlanmc
);
704 if (vid
== vlanmc
.vid
) {
705 /* update the MC entry */
706 vlanmc
.member
= member
;
707 vlanmc
.untag
= untag
;
710 err
= rtl8366rb_set_vlan_mc(smi
, i
, &vlanmc
);
718 static int rtl8366rb_get_pvid(struct rtl8366_smi
*smi
, int port
, int *val
)
720 struct rtl8366_vlan_mc vlanmc
;
724 err
= rtl8366rb_get_mc_index(smi
, port
, &index
);
728 err
= rtl8366rb_get_vlan_mc(smi
, index
, &vlanmc
);
736 static int rtl8366rb_mc_is_used(struct rtl8366_smi
*smi
, int mc_index
,
743 for (i
= 0; i
< RTL8366_NUM_PORTS
; i
++) {
746 err
= rtl8366rb_get_mc_index(smi
, i
, &index
);
750 if (mc_index
== index
) {
759 static int rtl8366rb_set_pvid(struct rtl8366_smi
*smi
, unsigned port
,
762 struct rtl8366_vlan_mc vlanmc
;
763 struct rtl8366_vlan_4k vlan4k
;
767 /* Try to find an existing MC entry for this VID */
768 for (i
= 0; i
< RTL8366_NUM_VLANS
; i
++) {
769 err
= rtl8366rb_get_vlan_mc(smi
, i
, &vlanmc
);
773 if (vid
== vlanmc
.vid
) {
774 err
= rtl8366rb_set_vlan_mc(smi
, i
, &vlanmc
);
778 err
= rtl8366rb_set_mc_index(smi
, port
, i
);
783 /* We have no MC entry for this VID, try to find an empty one */
784 for (i
= 0; i
< RTL8366_NUM_VLANS
; i
++) {
785 err
= rtl8366rb_get_vlan_mc(smi
, i
, &vlanmc
);
789 if (vlanmc
.vid
== 0 && vlanmc
.member
== 0) {
790 /* Update the entry from the 4K table */
791 err
= rtl8366rb_get_vlan_4k(smi
, vid
, &vlan4k
);
796 vlanmc
.member
= vlan4k
.member
;
797 vlanmc
.untag
= vlan4k
.untag
;
798 vlanmc
.fid
= vlan4k
.fid
;
799 err
= rtl8366rb_set_vlan_mc(smi
, i
, &vlanmc
);
803 err
= rtl8366rb_set_mc_index(smi
, port
, i
);
808 /* MC table is full, try to find an unused entry and replace it */
809 for (i
= 0; i
< RTL8366_NUM_VLANS
; i
++) {
812 err
= rtl8366rb_mc_is_used(smi
, i
, &used
);
817 /* Update the entry from the 4K table */
818 err
= rtl8366rb_get_vlan_4k(smi
, vid
, &vlan4k
);
823 vlanmc
.member
= vlan4k
.member
;
824 vlanmc
.untag
= vlan4k
.untag
;
825 vlanmc
.fid
= vlan4k
.fid
;
826 err
= rtl8366rb_set_vlan_mc(smi
, i
, &vlanmc
);
830 err
= rtl8366rb_set_mc_index(smi
, port
, i
);
836 "all VLAN member configurations are in use\n");
841 static int rtl8366rb_vlan_set_vlan(struct rtl8366_smi
*smi
, int enable
)
843 return rtl8366_smi_rmwr(smi
, RTL8366_CHIP_GLOBAL_CTRL_REG
,
844 RTL8366_CHIP_CTRL_VLAN
,
845 (enable
) ? RTL8366_CHIP_CTRL_VLAN
: 0);
848 static int rtl8366rb_vlan_set_4ktable(struct rtl8366_smi
*smi
, int enable
)
850 return rtl8366_smi_rmwr(smi
, RTL8366_CHIP_GLOBAL_CTRL_REG
,
851 RTL8366_CHIP_CTRL_VLAN_4KTB
,
852 (enable
) ? RTL8366_CHIP_CTRL_VLAN_4KTB
: 0);
855 static int rtl8366rb_reset_vlan(struct rtl8366_smi
*smi
)
857 struct rtl8366_vlan_mc vlanmc
;
861 /* clear VLAN member configurations */
867 for (i
= 0; i
< RTL8366_NUM_VLANS
; i
++) {
868 err
= rtl8366rb_set_vlan_mc(smi
, i
, &vlanmc
);
873 for (i
= 0; i
< RTL8366_NUM_PORTS
; i
++) {
874 if (i
== RTL8366_PORT_CPU
)
877 err
= rtl8366rb_set_vlan(smi
, (i
+ 1),
878 (1 << i
) | RTL8366_PORT_CPU
,
879 (1 << i
) | RTL8366_PORT_CPU
,
884 err
= rtl8366rb_set_pvid(smi
, i
, (i
+ 1));
892 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
893 static int rtl8366rb_debugfs_open(struct inode
*inode
, struct file
*file
)
895 file
->private_data
= inode
->i_private
;
899 static ssize_t
rtl8366rb_read_debugfs_mibs(struct file
*file
,
900 char __user
*user_buf
,
901 size_t count
, loff_t
*ppos
)
903 struct rtl8366rb
*rtl
= (struct rtl8366rb
*)file
->private_data
;
904 struct rtl8366_smi
*smi
= &rtl
->smi
;
906 char *buf
= rtl
->buf
;
908 len
+= snprintf(buf
+ len
, sizeof(rtl
->buf
) - len
,
909 "%-36s %12s %12s %12s %12s %12s %12s\n",
911 "Port 0", "Port 1", "Port 2",
912 "Port 3", "Port 4", "Port 5");
914 for (i
= 0; i
< ARRAY_SIZE(rtl8366rb_mib_counters
); ++i
) {
915 len
+= snprintf(buf
+ len
, sizeof(rtl
->buf
) - len
, "%-36s ",
916 rtl8366rb_mib_counters
[i
].name
);
917 for (j
= 0; j
< RTL8366_NUM_PORTS
; ++j
) {
918 unsigned long long counter
= 0;
920 if (!rtl8366_get_mib_counter(smi
, i
, j
, &counter
))
921 len
+= snprintf(buf
+ len
,
922 sizeof(rtl
->buf
) - len
,
925 len
+= snprintf(buf
+ len
,
926 sizeof(rtl
->buf
) - len
,
929 len
+= snprintf(buf
+ len
, sizeof(rtl
->buf
) - len
, "\n");
932 return simple_read_from_buffer(user_buf
, count
, ppos
, buf
, len
);
935 static ssize_t
rtl8366rb_read_debugfs_vlan_mc(struct file
*file
,
936 char __user
*user_buf
,
937 size_t count
, loff_t
*ppos
)
939 struct rtl8366rb
*rtl
= (struct rtl8366rb
*)file
->private_data
;
940 struct rtl8366_smi
*smi
= &rtl
->smi
;
942 char *buf
= rtl
->buf
;
944 len
+= snprintf(buf
+ len
, sizeof(rtl
->buf
) - len
,
945 "%2s %6s %4s %6s %6s %3s\n",
946 "id", "vid","prio", "member", "untag", "fid");
948 for (i
= 0; i
< RTL8366_NUM_VLANS
; ++i
) {
949 struct rtl8366_vlan_mc vlanmc
;
951 rtl8366rb_get_vlan_mc(smi
, i
, &vlanmc
);
953 len
+= snprintf(buf
+ len
, sizeof(rtl
->buf
) - len
,
954 "%2d %6d %4d 0x%04x 0x%04x %3d\n",
955 i
, vlanmc
.vid
, vlanmc
.priority
,
956 vlanmc
.member
, vlanmc
.untag
, vlanmc
.fid
);
959 return simple_read_from_buffer(user_buf
, count
, ppos
, buf
, len
);
962 static ssize_t
rtl8366rb_read_debugfs_reg(struct file
*file
,
963 char __user
*user_buf
,
964 size_t count
, loff_t
*ppos
)
966 struct rtl8366rb
*rtl
= (struct rtl8366rb
*)file
->private_data
;
967 struct rtl8366_smi
*smi
= &rtl
->smi
;
968 u32 t
, reg
= gl_dbg_reg
;
970 char *buf
= rtl
->buf
;
972 memset(buf
, '\0', sizeof(rtl
->buf
));
974 err
= rtl8366_smi_read_reg(smi
, reg
, &t
);
976 len
+= snprintf(buf
, sizeof(rtl
->buf
),
977 "Read failed (reg: 0x%04x)\n", reg
);
978 return simple_read_from_buffer(user_buf
, count
, ppos
, buf
, len
);
981 len
+= snprintf(buf
, sizeof(rtl
->buf
), "reg = 0x%04x, val = 0x%04x\n",
984 return simple_read_from_buffer(user_buf
, count
, ppos
, buf
, len
);
987 static ssize_t
rtl8366rb_write_debugfs_reg(struct file
*file
,
988 const char __user
*user_buf
,
989 size_t count
, loff_t
*ppos
)
991 struct rtl8366rb
*rtl
= (struct rtl8366rb
*)file
->private_data
;
992 struct rtl8366_smi
*smi
= &rtl
->smi
;
994 u32 reg
= gl_dbg_reg
;
997 char *buf
= rtl
->buf
;
999 len
= min(count
, sizeof(rtl
->buf
) - 1);
1000 if (copy_from_user(buf
, user_buf
, len
)) {
1001 dev_err(rtl
->parent
, "copy from user failed\n");
1006 if (len
> 0 && buf
[len
- 1] == '\n')
1007 buf
[len
- 1] = '\0';
1010 if (strict_strtoul(buf
, 16, &data
)) {
1011 dev_err(rtl
->parent
, "Invalid reg value %s\n", buf
);
1013 err
= rtl8366_smi_write_reg(smi
, reg
, data
);
1015 dev_err(rtl
->parent
,
1016 "writing reg 0x%04x val 0x%04lx failed\n",
1024 static const struct file_operations fops_rtl8366rb_regs
= {
1025 .read
= rtl8366rb_read_debugfs_reg
,
1026 .write
= rtl8366rb_write_debugfs_reg
,
1027 .open
= rtl8366rb_debugfs_open
,
1028 .owner
= THIS_MODULE
1031 static const struct file_operations fops_rtl8366rb_vlan_mc
= {
1032 .read
= rtl8366rb_read_debugfs_vlan_mc
,
1033 .open
= rtl8366rb_debugfs_open
,
1034 .owner
= THIS_MODULE
1037 static const struct file_operations fops_rtl8366rb_mibs
= {
1038 .read
= rtl8366rb_read_debugfs_mibs
,
1039 .open
= rtl8366rb_debugfs_open
,
1040 .owner
= THIS_MODULE
1043 static void rtl8366rb_debugfs_init(struct rtl8366rb
*rtl
)
1045 struct dentry
*node
;
1046 struct dentry
*root
;
1048 if (!rtl
->debugfs_root
)
1049 rtl
->debugfs_root
= debugfs_create_dir("rtl8366rb", NULL
);
1051 if (!rtl
->debugfs_root
) {
1052 dev_err(rtl
->parent
, "Unable to create debugfs dir\n");
1055 root
= rtl
->debugfs_root
;
1057 node
= debugfs_create_x16("reg", S_IRUGO
| S_IWUSR
, root
, &gl_dbg_reg
);
1059 dev_err(rtl
->parent
, "Creating debugfs file '%s' failed\n",
1064 node
= debugfs_create_file("val", S_IRUGO
| S_IWUSR
, root
, rtl
,
1065 &fops_rtl8366rb_regs
);
1067 dev_err(rtl
->parent
, "Creating debugfs file '%s' failed\n",
1072 node
= debugfs_create_file("vlan_mc", S_IRUSR
, root
, rtl
,
1073 &fops_rtl8366rb_vlan_mc
);
1075 dev_err(rtl
->parent
, "Creating debugfs file '%s' failed\n",
1080 node
= debugfs_create_file("mibs", S_IRUSR
, root
, rtl
,
1081 &fops_rtl8366rb_mibs
);
1083 dev_err(rtl
->parent
, "Creating debugfs file '%s' failed\n",
1089 static void rtl8366rb_debugfs_remove(struct rtl8366rb
*rtl
)
1091 if (rtl
->debugfs_root
) {
1092 debugfs_remove_recursive(rtl
->debugfs_root
);
1093 rtl
->debugfs_root
= NULL
;
1098 static inline void rtl8366rb_debugfs_init(struct rtl8366rb
*rtl
) {}
1099 static inline void rtl8366rb_debugfs_remove(struct rtl8366rb
*rtl
) {}
1100 #endif /* CONFIG_RTL8366S_PHY_DEBUG_FS */
1102 static int rtl8366rb_sw_reset_mibs(struct switch_dev
*dev
,
1103 const struct switch_attr
*attr
,
1104 struct switch_val
*val
)
1106 struct rtl8366_smi
*smi
= sw_to_rtl8366_smi(dev
);
1109 if (val
->value
.i
== 1)
1110 err
= rtl8366_smi_rmwr(smi
, RTL8366S_MIB_CTRL_REG
, 0, (1 << 2));
1115 static int rtl8366rb_sw_get_vlan_enable(struct switch_dev
*dev
,
1116 const struct switch_attr
*attr
,
1117 struct switch_val
*val
)
1119 struct rtl8366_smi
*smi
= sw_to_rtl8366_smi(dev
);
1122 if (attr
->ofs
== 1) {
1123 rtl8366_smi_read_reg(smi
, RTL8366_CHIP_GLOBAL_CTRL_REG
, &data
);
1125 if (data
& RTL8366_CHIP_CTRL_VLAN
)
1129 } else if (attr
->ofs
== 2) {
1130 rtl8366_smi_read_reg(smi
, RTL8366_CHIP_GLOBAL_CTRL_REG
, &data
);
1132 if (data
& RTL8366_CHIP_CTRL_VLAN_4KTB
)
1141 static int rtl8366rb_sw_get_blinkrate(struct switch_dev
*dev
,
1142 const struct switch_attr
*attr
,
1143 struct switch_val
*val
)
1145 struct rtl8366_smi
*smi
= sw_to_rtl8366_smi(dev
);
1148 rtl8366_smi_read_reg(smi
, RTL8366_LED_BLINKRATE_REG
, &data
);
1150 val
->value
.i
= (data
& (RTL8366_LED_BLINKRATE_MASK
));
1155 static int rtl8366rb_sw_set_blinkrate(struct switch_dev
*dev
,
1156 const struct switch_attr
*attr
,
1157 struct switch_val
*val
)
1159 struct rtl8366_smi
*smi
= sw_to_rtl8366_smi(dev
);
1161 if (val
->value
.i
>= 6)
1164 return rtl8366_smi_rmwr(smi
, RTL8366_LED_BLINKRATE_REG
,
1165 RTL8366_LED_BLINKRATE_MASK
,
1169 static int rtl8366rb_sw_set_vlan_enable(struct switch_dev
*dev
,
1170 const struct switch_attr
*attr
,
1171 struct switch_val
*val
)
1173 struct rtl8366_smi
*smi
= sw_to_rtl8366_smi(dev
);
1176 return rtl8366rb_vlan_set_vlan(smi
, val
->value
.i
);
1178 return rtl8366rb_vlan_set_4ktable(smi
, val
->value
.i
);
1181 static const char *rtl8366rb_speed_str(unsigned speed
)
1195 static int rtl8366rb_sw_get_port_link(struct switch_dev
*dev
,
1196 const struct switch_attr
*attr
,
1197 struct switch_val
*val
)
1199 struct rtl8366rb
*rtl
= sw_to_rtl8366rb(dev
);
1200 struct rtl8366_smi
*smi
= &rtl
->smi
;
1201 u32 len
= 0, data
= 0;
1203 if (val
->port_vlan
>= RTL8366_NUM_PORTS
)
1206 memset(rtl
->buf
, '\0', sizeof(rtl
->buf
));
1207 rtl8366_smi_read_reg(smi
, RTL8366S_PORT_LINK_STATUS_BASE
+
1208 (val
->port_vlan
/ 2), &data
);
1210 if (val
->port_vlan
% 2)
1213 if (data
& RTL8366S_PORT_STATUS_LINK_MASK
) {
1214 len
= snprintf(rtl
->buf
, sizeof(rtl
->buf
),
1215 "port:%d link:up speed:%s %s-duplex %s%s%s",
1217 rtl8366rb_speed_str(data
&
1218 RTL8366S_PORT_STATUS_SPEED_MASK
),
1219 (data
& RTL8366S_PORT_STATUS_DUPLEX_MASK
) ?
1221 (data
& RTL8366S_PORT_STATUS_TXPAUSE_MASK
) ?
1223 (data
& RTL8366S_PORT_STATUS_RXPAUSE_MASK
) ?
1225 (data
& RTL8366S_PORT_STATUS_AN_MASK
) ?
1228 len
= snprintf(rtl
->buf
, sizeof(rtl
->buf
), "port:%d link: down",
1232 val
->value
.s
= rtl
->buf
;
1238 static int rtl8366rb_sw_get_vlan_info(struct switch_dev
*dev
,
1239 const struct switch_attr
*attr
,
1240 struct switch_val
*val
)
1244 struct rtl8366_vlan_4k vlan4k
;
1245 struct rtl8366rb
*rtl
= sw_to_rtl8366rb(dev
);
1246 struct rtl8366_smi
*smi
= &rtl
->smi
;
1247 char *buf
= rtl
->buf
;
1250 if (val
->port_vlan
== 0 || val
->port_vlan
>= RTL8366_NUM_VLANS
)
1253 memset(buf
, '\0', sizeof(rtl
->buf
));
1255 err
= rtl8366rb_get_vlan_4k(smi
, val
->port_vlan
, &vlan4k
);
1259 len
+= snprintf(buf
+ len
, sizeof(rtl
->buf
) - len
,
1260 "VLAN %d: Ports: '", vlan4k
.vid
);
1262 for (i
= 0; i
< RTL8366_NUM_PORTS
; i
++) {
1263 if (!(vlan4k
.member
& (1 << i
)))
1266 len
+= snprintf(buf
+ len
, sizeof(rtl
->buf
) - len
, "%d%s", i
,
1267 (vlan4k
.untag
& (1 << i
)) ? "" : "t");
1270 len
+= snprintf(buf
+ len
, sizeof(rtl
->buf
) - len
,
1271 "', members=%04x, untag=%04x, fid=%u",
1272 vlan4k
.member
, vlan4k
.untag
, vlan4k
.fid
);
1280 static int rtl8366rb_sw_set_port_led(struct switch_dev
*dev
,
1281 const struct switch_attr
*attr
,
1282 struct switch_val
*val
)
1284 struct rtl8366_smi
*smi
= sw_to_rtl8366_smi(dev
);
1289 if (val
->port_vlan
>= RTL8366_NUM_PORTS
)
1292 if (val
->port_vlan
== RTL8366_PORT_NUM_CPU
) {
1293 reg
= RTL8366_LED_BLINKRATE_REG
;
1295 data
= val
->value
.i
<< 4;
1297 reg
= RTL8366_LED_CTRL_REG
;
1298 mask
= 0xF << (val
->port_vlan
* 4),
1299 data
= val
->value
.i
<< (val
->port_vlan
* 4);
1302 return rtl8366_smi_rmwr(smi
, RTL8366_LED_BLINKRATE_REG
, mask
, data
);
1305 static int rtl8366rb_sw_get_port_led(struct switch_dev
*dev
,
1306 const struct switch_attr
*attr
,
1307 struct switch_val
*val
)
1309 struct rtl8366_smi
*smi
= sw_to_rtl8366_smi(dev
);
1312 if (val
->port_vlan
>= RTL8366_NUM_LEDGROUPS
)
1315 rtl8366_smi_read_reg(smi
, RTL8366_LED_CTRL_REG
, &data
);
1316 val
->value
.i
= (data
>> (val
->port_vlan
* 4)) & 0x000F;
1321 static int rtl8366rb_sw_reset_port_mibs(struct switch_dev
*dev
,
1322 const struct switch_attr
*attr
,
1323 struct switch_val
*val
)
1325 struct rtl8366_smi
*smi
= sw_to_rtl8366_smi(dev
);
1327 if (val
->port_vlan
>= RTL8366_NUM_PORTS
)
1330 return rtl8366_smi_rmwr(smi
, RTL8366S_MIB_CTRL_REG
,
1331 0, (1 << (val
->port_vlan
+ 3)));
1334 static int rtl8366rb_sw_get_port_mib(struct switch_dev
*dev
,
1335 const struct switch_attr
*attr
,
1336 struct switch_val
*val
)
1338 struct rtl8366rb
*rtl
= sw_to_rtl8366rb(dev
);
1339 struct rtl8366_smi
*smi
= &rtl
->smi
;
1341 unsigned long long counter
= 0;
1342 char *buf
= rtl
->buf
;
1344 if (val
->port_vlan
>= RTL8366_NUM_PORTS
)
1347 len
+= snprintf(buf
+ len
, sizeof(rtl
->buf
) - len
,
1348 "Port %d MIB counters\n",
1351 for (i
= 0; i
< ARRAY_SIZE(rtl8366rb_mib_counters
); ++i
) {
1352 len
+= snprintf(buf
+ len
, sizeof(rtl
->buf
) - len
,
1353 "%-36s: ", rtl8366rb_mib_counters
[i
].name
);
1354 if (!rtl8366_get_mib_counter(smi
, i
, val
->port_vlan
, &counter
))
1355 len
+= snprintf(buf
+ len
, sizeof(rtl
->buf
) - len
,
1358 len
+= snprintf(buf
+ len
, sizeof(rtl
->buf
) - len
,
1367 static int rtl8366rb_sw_get_vlan_ports(struct switch_dev
*dev
,
1368 struct switch_val
*val
)
1370 struct rtl8366_smi
*smi
= sw_to_rtl8366_smi(dev
);
1371 struct switch_port
*port
;
1372 struct rtl8366_vlan_4k vlan4k
;
1375 if (val
->port_vlan
== 0 || val
->port_vlan
>= RTL8366_NUM_VLANS
)
1378 rtl8366rb_get_vlan_4k(smi
, val
->port_vlan
, &vlan4k
);
1380 port
= &val
->value
.ports
[0];
1382 for (i
= 0; i
< RTL8366_NUM_PORTS
; i
++) {
1383 if (!(vlan4k
.member
& BIT(i
)))
1387 port
->flags
= (vlan4k
.untag
& BIT(i
)) ?
1388 0 : BIT(SWITCH_PORT_FLAG_TAGGED
);
1395 static int rtl8366rb_sw_set_vlan_ports(struct switch_dev
*dev
,
1396 struct switch_val
*val
)
1398 struct rtl8366_smi
*smi
= sw_to_rtl8366_smi(dev
);
1399 struct switch_port
*port
;
1404 if (val
->port_vlan
== 0 || val
->port_vlan
>= RTL8366_NUM_VLANS
)
1407 port
= &val
->value
.ports
[0];
1408 for (i
= 0; i
< val
->len
; i
++, port
++) {
1409 member
|= BIT(port
->id
);
1411 if (!(port
->flags
& BIT(SWITCH_PORT_FLAG_TAGGED
)))
1412 untag
|= BIT(port
->id
);
1415 return rtl8366rb_set_vlan(smi
, val
->port_vlan
, member
, untag
, 0);
1418 static int rtl8366rb_sw_get_port_pvid(struct switch_dev
*dev
, int port
, int *val
)
1420 struct rtl8366_smi
*smi
= sw_to_rtl8366_smi(dev
);
1421 return rtl8366rb_get_pvid(smi
, port
, val
);
1424 static int rtl8366rb_sw_set_port_pvid(struct switch_dev
*dev
, int port
, int val
)
1426 struct rtl8366_smi
*smi
= sw_to_rtl8366_smi(dev
);
1427 return rtl8366rb_set_pvid(smi
, port
, val
);
1430 static int rtl8366rb_sw_reset_switch(struct switch_dev
*dev
)
1432 struct rtl8366_smi
*smi
= sw_to_rtl8366_smi(dev
);
1435 err
= rtl8366rb_reset_chip(smi
);
1439 err
= rtl8366rb_hw_init(smi
);
1443 return rtl8366rb_reset_vlan(smi
);
1446 static struct switch_attr rtl8366rb_globals
[] = {
1448 .type
= SWITCH_TYPE_INT
,
1449 .name
= "enable_vlan",
1450 .description
= "Enable VLAN mode",
1451 .set
= rtl8366rb_sw_set_vlan_enable
,
1452 .get
= rtl8366rb_sw_get_vlan_enable
,
1456 .type
= SWITCH_TYPE_INT
,
1457 .name
= "enable_vlan4k",
1458 .description
= "Enable VLAN 4K mode",
1459 .set
= rtl8366rb_sw_set_vlan_enable
,
1460 .get
= rtl8366rb_sw_get_vlan_enable
,
1464 .type
= SWITCH_TYPE_INT
,
1465 .name
= "reset_mibs",
1466 .description
= "Reset all MIB counters",
1467 .set
= rtl8366rb_sw_reset_mibs
,
1471 .type
= SWITCH_TYPE_INT
,
1472 .name
= "blinkrate",
1473 .description
= "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms,"
1474 " 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)",
1475 .set
= rtl8366rb_sw_set_blinkrate
,
1476 .get
= rtl8366rb_sw_get_blinkrate
,
1481 static struct switch_attr rtl8366rb_port
[] = {
1483 .type
= SWITCH_TYPE_STRING
,
1485 .description
= "Get port link information",
1488 .get
= rtl8366rb_sw_get_port_link
,
1490 .type
= SWITCH_TYPE_INT
,
1491 .name
= "reset_mib",
1492 .description
= "Reset single port MIB counters",
1494 .set
= rtl8366rb_sw_reset_port_mibs
,
1497 .type
= SWITCH_TYPE_STRING
,
1499 .description
= "Get MIB counters for port",
1502 .get
= rtl8366rb_sw_get_port_mib
,
1504 .type
= SWITCH_TYPE_INT
,
1506 .description
= "Get/Set port group (0 - 3) led mode (0 - 15)",
1508 .set
= rtl8366rb_sw_set_port_led
,
1509 .get
= rtl8366rb_sw_get_port_led
,
1513 static struct switch_attr rtl8366rb_vlan
[] = {
1515 .type
= SWITCH_TYPE_STRING
,
1517 .description
= "Get vlan information",
1520 .get
= rtl8366rb_sw_get_vlan_info
,
1525 static struct switch_dev rtl8366_switch_dev
= {
1527 .cpu_port
= RTL8366_PORT_NUM_CPU
,
1528 .ports
= RTL8366_NUM_PORTS
,
1529 .vlans
= RTL8366_NUM_VLANS
,
1531 .attr
= rtl8366rb_globals
,
1532 .n_attr
= ARRAY_SIZE(rtl8366rb_globals
),
1535 .attr
= rtl8366rb_port
,
1536 .n_attr
= ARRAY_SIZE(rtl8366rb_port
),
1539 .attr
= rtl8366rb_vlan
,
1540 .n_attr
= ARRAY_SIZE(rtl8366rb_vlan
),
1543 .get_vlan_ports
= rtl8366rb_sw_get_vlan_ports
,
1544 .set_vlan_ports
= rtl8366rb_sw_set_vlan_ports
,
1545 .get_port_pvid
= rtl8366rb_sw_get_port_pvid
,
1546 .set_port_pvid
= rtl8366rb_sw_set_port_pvid
,
1547 .reset_switch
= rtl8366rb_sw_reset_switch
,
1550 static int rtl8366rb_switch_init(struct rtl8366rb
*rtl
)
1552 struct switch_dev
*dev
= &rtl
->dev
;
1555 memcpy(dev
, &rtl8366_switch_dev
, sizeof(struct switch_dev
));
1557 dev
->devname
= dev_name(rtl
->parent
);
1559 err
= register_switch(dev
, NULL
);
1561 dev_err(rtl
->parent
, "switch registration failed\n");
1566 static void rtl8366rb_switch_cleanup(struct rtl8366rb
*rtl
)
1568 unregister_switch(&rtl
->dev
);
1571 static int rtl8366rb_mii_read(struct mii_bus
*bus
, int addr
, int reg
)
1573 struct rtl8366_smi
*smi
= bus
->priv
;
1577 err
= rtl8366rb_read_phy_reg(smi
, addr
, 0, reg
, &val
);
1584 static int rtl8366rb_mii_write(struct mii_bus
*bus
, int addr
, int reg
, u16 val
)
1586 struct rtl8366_smi
*smi
= bus
->priv
;
1590 err
= rtl8366rb_write_phy_reg(smi
, addr
, 0, reg
, val
);
1592 (void) rtl8366rb_read_phy_reg(smi
, addr
, 0, reg
, &t
);
1597 static int rtl8366rb_mii_bus_match(struct mii_bus
*bus
)
1599 return (bus
->read
== rtl8366rb_mii_read
&&
1600 bus
->write
== rtl8366rb_mii_write
);
1603 static int rtl8366rb_setup(struct rtl8366rb
*rtl
)
1605 struct rtl8366_smi
*smi
= &rtl
->smi
;
1608 rtl8366rb_debugfs_init(rtl
);
1610 ret
= rtl8366rb_reset_chip(smi
);
1614 ret
= rtl8366rb_hw_init(smi
);
1618 static int rtl8366rb_detect(struct rtl8366_smi
*smi
)
1624 ret
= rtl8366_smi_read_reg(smi
, RTL8366S_CHIP_ID_REG
, &chip_id
);
1626 dev_err(smi
->parent
, "unable to read chip id\n");
1631 case RTL8366S_CHIP_ID_8366
:
1634 dev_err(smi
->parent
, "unknown chip id (%04x)\n", chip_id
);
1638 ret
= rtl8366_smi_read_reg(smi
, RTL8366S_CHIP_VERSION_CTRL_REG
,
1641 dev_err(smi
->parent
, "unable to read chip version\n");
1645 dev_info(smi
->parent
, "RTL%04x ver. %u chip found\n",
1646 chip_id
, chip_ver
& RTL8366S_CHIP_VERSION_MASK
);
1651 static struct rtl8366_smi_ops rtl8366rb_smi_ops
= {
1652 .detect
= rtl8366rb_detect
,
1653 .mii_read
= rtl8366rb_mii_read
,
1654 .mii_write
= rtl8366rb_mii_write
,
1657 static int __init
rtl8366rb_probe(struct platform_device
*pdev
)
1659 static int rtl8366_smi_version_printed
;
1660 struct rtl8366rb_platform_data
*pdata
;
1661 struct rtl8366rb
*rtl
;
1662 struct rtl8366_smi
*smi
;
1665 if (!rtl8366_smi_version_printed
++)
1666 printk(KERN_NOTICE RTL8366S_DRIVER_DESC
1667 " version " RTL8366S_DRIVER_VER
"\n");
1669 pdata
= pdev
->dev
.platform_data
;
1671 dev_err(&pdev
->dev
, "no platform data specified\n");
1676 rtl
= kzalloc(sizeof(*rtl
), GFP_KERNEL
);
1678 dev_err(&pdev
->dev
, "no memory for private data\n");
1683 rtl
->parent
= &pdev
->dev
;
1686 smi
->parent
= &pdev
->dev
;
1687 smi
->gpio_sda
= pdata
->gpio_sda
;
1688 smi
->gpio_sck
= pdata
->gpio_sck
;
1689 smi
->ops
= &rtl8366rb_smi_ops
;
1691 err
= rtl8366_smi_init(smi
);
1695 platform_set_drvdata(pdev
, rtl
);
1697 err
= rtl8366rb_setup(rtl
);
1699 goto err_clear_drvdata
;
1701 err
= rtl8366rb_switch_init(rtl
);
1703 goto err_clear_drvdata
;
1708 platform_set_drvdata(pdev
, NULL
);
1709 rtl8366_smi_cleanup(smi
);
1716 static int rtl8366rb_phy_config_init(struct phy_device
*phydev
)
1718 if (!rtl8366rb_mii_bus_match(phydev
->bus
))
1724 static int rtl8366rb_phy_config_aneg(struct phy_device
*phydev
)
1729 static struct phy_driver rtl8366rb_phy_driver
= {
1730 .phy_id
= 0x001cc960,
1731 .name
= "Realtek RTL8366RB",
1732 .phy_id_mask
= 0x1ffffff0,
1733 .features
= PHY_GBIT_FEATURES
,
1734 .config_aneg
= rtl8366rb_phy_config_aneg
,
1735 .config_init
= rtl8366rb_phy_config_init
,
1736 .read_status
= genphy_read_status
,
1738 .owner
= THIS_MODULE
,
1742 static int __devexit
rtl8366rb_remove(struct platform_device
*pdev
)
1744 struct rtl8366rb
*rtl
= platform_get_drvdata(pdev
);
1747 rtl8366rb_switch_cleanup(rtl
);
1748 rtl8366rb_debugfs_remove(rtl
);
1749 platform_set_drvdata(pdev
, NULL
);
1750 rtl8366_smi_cleanup(&rtl
->smi
);
1757 static struct platform_driver rtl8366rb_driver
= {
1759 .name
= RTL8366RB_DRIVER_NAME
,
1760 .owner
= THIS_MODULE
,
1762 .probe
= rtl8366rb_probe
,
1763 .remove
= __devexit_p(rtl8366rb_remove
),
1766 static int __init
rtl8366rb_module_init(void)
1769 ret
= platform_driver_register(&rtl8366rb_driver
);
1773 ret
= phy_driver_register(&rtl8366rb_phy_driver
);
1775 goto err_platform_unregister
;
1779 err_platform_unregister
:
1780 platform_driver_unregister(&rtl8366rb_driver
);
1783 module_init(rtl8366rb_module_init
);
1785 static void __exit
rtl8366rb_module_exit(void)
1787 phy_driver_unregister(&rtl8366rb_phy_driver
);
1788 platform_driver_unregister(&rtl8366rb_driver
);
1790 module_exit(rtl8366rb_module_exit
);
1792 MODULE_DESCRIPTION(RTL8366S_DRIVER_DESC
);
1793 MODULE_VERSION(RTL8366S_DRIVER_VER
);
1794 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1795 MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>");
1796 MODULE_LICENSE("GPL v2");
1797 MODULE_ALIAS("platform:" RTL8366RB_DRIVER_NAME
);