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generic: rtl8366: add common read_debugfs_mibs function
[openwrt/svn-archive/archive.git] / target / linux / generic / files / drivers / net / phy / rtl8366rb.c
1 /*
2 * Platform driver for the Realtek RTL8366S ethernet switch
3 *
4 * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
10 */
11
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/platform_device.h>
16 #include <linux/delay.h>
17 #include <linux/skbuff.h>
18 #include <linux/switch.h>
19 #include <linux/rtl8366rb.h>
20
21 #include "rtl8366_smi.h"
22
23 #define RTL8366RB_DRIVER_DESC "Realtek RTL8366RB ethernet switch driver"
24 #define RTL8366RB_DRIVER_VER "0.2.2"
25
26 #define RTL8366RB_PHY_NO_MAX 4
27 #define RTL8366RB_PHY_PAGE_MAX 7
28 #define RTL8366RB_PHY_ADDR_MAX 31
29
30 #define RTL8366RB_CHIP_GLOBAL_CTRL_REG 0x0000
31 #define RTL8366RB_CHIP_CTRL_VLAN (1 << 13)
32 #define RTL8366RB_CHIP_CTRL_VLAN_4KTB (1 << 14)
33
34 /* Switch Global Configuration register */
35 #define RTL8366RB_SGCR 0x0000
36 #define RTL8366RB_SGCR_EN_BC_STORM_CTRL BIT(0)
37 #define RTL8366RB_SGCR_MAX_LENGTH(_x) (_x << 4)
38 #define RTL8366RB_SGCR_MAX_LENGTH_MASK RTL8366RB_SGCR_MAX_LENGTH(0x3)
39 #define RTL8366RB_SGCR_MAX_LENGTH_1522 RTL8366RB_SGCR_MAX_LENGTH(0x0)
40 #define RTL8366RB_SGCR_MAX_LENGTH_1536 RTL8366RB_SGCR_MAX_LENGTH(0x1)
41 #define RTL8366RB_SGCR_MAX_LENGTH_1552 RTL8366RB_SGCR_MAX_LENGTH(0x2)
42 #define RTL8366RB_SGCR_MAX_LENGTH_9216 RTL8366RB_SGCR_MAX_LENGTH(0x3)
43
44 /* Port Enable Control register */
45 #define RTL8366RB_PECR 0x0001
46
47 /* Switch Security Control registers */
48 #define RTL8366RB_SSCR0 0x0002
49 #define RTL8366RB_SSCR1 0x0003
50 #define RTL8366RB_SSCR2 0x0004
51 #define RTL8366RB_SSCR2_DROP_UNKNOWN_DA BIT(0)
52
53 #define RTL8366RB_RESET_CTRL_REG 0x0100
54 #define RTL8366RB_CHIP_CTRL_RESET_HW 1
55 #define RTL8366RB_CHIP_CTRL_RESET_SW (1 << 1)
56
57 #define RTL8366RB_CHIP_VERSION_CTRL_REG 0x050A
58 #define RTL8366RB_CHIP_VERSION_MASK 0xf
59 #define RTL8366RB_CHIP_ID_REG 0x0509
60 #define RTL8366RB_CHIP_ID_8366 0x5937
61
62 /* PHY registers control */
63 #define RTL8366RB_PHY_ACCESS_CTRL_REG 0x8000
64 #define RTL8366RB_PHY_ACCESS_DATA_REG 0x8002
65
66 #define RTL8366RB_PHY_CTRL_READ 1
67 #define RTL8366RB_PHY_CTRL_WRITE 0
68
69 #define RTL8366RB_PHY_REG_MASK 0x1f
70 #define RTL8366RB_PHY_PAGE_OFFSET 5
71 #define RTL8366RB_PHY_PAGE_MASK (0xf << 5)
72 #define RTL8366RB_PHY_NO_OFFSET 9
73 #define RTL8366RB_PHY_NO_MASK (0x1f << 9)
74
75 /* LED control registers */
76 #define RTL8366RB_LED_BLINKRATE_REG 0x0430
77 #define RTL8366RB_LED_BLINKRATE_BIT 0
78 #define RTL8366RB_LED_BLINKRATE_MASK 0x0007
79
80 #define RTL8366RB_LED_CTRL_REG 0x0431
81 #define RTL8366RB_LED_0_1_CTRL_REG 0x0432
82 #define RTL8366RB_LED_2_3_CTRL_REG 0x0433
83
84 #define RTL8366RB_MIB_COUNT 33
85 #define RTL8366RB_GLOBAL_MIB_COUNT 1
86 #define RTL8366RB_MIB_COUNTER_PORT_OFFSET 0x0050
87 #define RTL8366RB_MIB_COUNTER_BASE 0x1000
88 #define RTL8366RB_MIB_CTRL_REG 0x13F0
89 #define RTL8366RB_MIB_CTRL_USER_MASK 0x0FFC
90 #define RTL8366RB_MIB_CTRL_BUSY_MASK BIT(0)
91 #define RTL8366RB_MIB_CTRL_RESET_MASK BIT(1)
92 #define RTL8366RB_MIB_CTRL_PORT_RESET(_p) BIT(2 + (_p))
93 #define RTL8366RB_MIB_CTRL_GLOBAL_RESET BIT(11)
94
95 #define RTL8366RB_PORT_VLAN_CTRL_BASE 0x0063
96 #define RTL8366RB_PORT_VLAN_CTRL_REG(_p) \
97 (RTL8366RB_PORT_VLAN_CTRL_BASE + (_p) / 4)
98 #define RTL8366RB_PORT_VLAN_CTRL_MASK 0xf
99 #define RTL8366RB_PORT_VLAN_CTRL_SHIFT(_p) (4 * ((_p) % 4))
100
101
102 #define RTL8366RB_VLAN_TABLE_READ_BASE 0x018C
103 #define RTL8366RB_VLAN_TABLE_WRITE_BASE 0x0185
104
105
106 #define RTL8366RB_TABLE_ACCESS_CTRL_REG 0x0180
107 #define RTL8366RB_TABLE_VLAN_READ_CTRL 0x0E01
108 #define RTL8366RB_TABLE_VLAN_WRITE_CTRL 0x0F01
109
110 #define RTL8366RB_VLAN_MEMCONF_BASE 0x0020
111
112
113 #define RTL8366RB_PORT_LINK_STATUS_BASE 0x0014
114 #define RTL8366RB_PORT_STATUS_SPEED_MASK 0x0003
115 #define RTL8366RB_PORT_STATUS_DUPLEX_MASK 0x0004
116 #define RTL8366RB_PORT_STATUS_LINK_MASK 0x0010
117 #define RTL8366RB_PORT_STATUS_TXPAUSE_MASK 0x0020
118 #define RTL8366RB_PORT_STATUS_RXPAUSE_MASK 0x0040
119 #define RTL8366RB_PORT_STATUS_AN_MASK 0x0080
120
121
122 #define RTL8366RB_PORT_NUM_CPU 5
123 #define RTL8366RB_NUM_PORTS 6
124 #define RTL8366RB_NUM_VLANS 16
125 #define RTL8366RB_NUM_LEDGROUPS 4
126 #define RTL8366RB_NUM_VIDS 4096
127 #define RTL8366RB_PRIORITYMAX 7
128 #define RTL8366RB_FIDMAX 7
129
130
131 #define RTL8366RB_PORT_1 (1 << 0) /* In userspace port 0 */
132 #define RTL8366RB_PORT_2 (1 << 1) /* In userspace port 1 */
133 #define RTL8366RB_PORT_3 (1 << 2) /* In userspace port 2 */
134 #define RTL8366RB_PORT_4 (1 << 3) /* In userspace port 3 */
135 #define RTL8366RB_PORT_5 (1 << 4) /* In userspace port 4 */
136
137 #define RTL8366RB_PORT_CPU (1 << 5) /* CPU port */
138
139 #define RTL8366RB_PORT_ALL (RTL8366RB_PORT_1 | \
140 RTL8366RB_PORT_2 | \
141 RTL8366RB_PORT_3 | \
142 RTL8366RB_PORT_4 | \
143 RTL8366RB_PORT_5 | \
144 RTL8366RB_PORT_CPU)
145
146 #define RTL8366RB_PORT_ALL_BUT_CPU (RTL8366RB_PORT_1 | \
147 RTL8366RB_PORT_2 | \
148 RTL8366RB_PORT_3 | \
149 RTL8366RB_PORT_4 | \
150 RTL8366RB_PORT_5)
151
152 #define RTL8366RB_PORT_ALL_EXTERNAL (RTL8366RB_PORT_1 | \
153 RTL8366RB_PORT_2 | \
154 RTL8366RB_PORT_3 | \
155 RTL8366RB_PORT_4)
156
157 #define RTL8366RB_PORT_ALL_INTERNAL RTL8366RB_PORT_CPU
158
159 struct rtl8366rb {
160 struct device *parent;
161 struct rtl8366_smi smi;
162 struct switch_dev dev;
163 };
164
165 struct rtl8366rb_vlan_mc {
166 u16 reserved2:1;
167 u16 priority:3;
168 u16 vid:12;
169 u16 untag:8;
170 u16 member:8;
171 u16 stag_mbr:8;
172 u16 stag_idx:3;
173 u16 reserved1:2;
174 u16 fid:3;
175 };
176
177 struct rtl8366rb_vlan_4k {
178 u16 reserved1:4;
179 u16 vid:12;
180 u16 untag:8;
181 u16 member:8;
182 u16 reserved2:13;
183 u16 fid:3;
184 };
185
186 static struct rtl8366_mib_counter rtl8366rb_mib_counters[] = {
187 { 0, 0, 4, "IfInOctets" },
188 { 0, 4, 4, "EtherStatsOctets" },
189 { 0, 8, 2, "EtherStatsUnderSizePkts" },
190 { 0, 10, 2, "EtherFragments" },
191 { 0, 12, 2, "EtherStatsPkts64Octets" },
192 { 0, 14, 2, "EtherStatsPkts65to127Octets" },
193 { 0, 16, 2, "EtherStatsPkts128to255Octets" },
194 { 0, 18, 2, "EtherStatsPkts256to511Octets" },
195 { 0, 20, 2, "EtherStatsPkts512to1023Octets" },
196 { 0, 22, 2, "EtherStatsPkts1024to1518Octets" },
197 { 0, 24, 2, "EtherOversizeStats" },
198 { 0, 26, 2, "EtherStatsJabbers" },
199 { 0, 28, 2, "IfInUcastPkts" },
200 { 0, 30, 2, "EtherStatsMulticastPkts" },
201 { 0, 32, 2, "EtherStatsBroadcastPkts" },
202 { 0, 34, 2, "EtherStatsDropEvents" },
203 { 0, 36, 2, "Dot3StatsFCSErrors" },
204 { 0, 38, 2, "Dot3StatsSymbolErrors" },
205 { 0, 40, 2, "Dot3InPauseFrames" },
206 { 0, 42, 2, "Dot3ControlInUnknownOpcodes" },
207 { 0, 44, 4, "IfOutOctets" },
208 { 0, 48, 2, "Dot3StatsSingleCollisionFrames" },
209 { 0, 50, 2, "Dot3StatMultipleCollisionFrames" },
210 { 0, 52, 2, "Dot3sDeferredTransmissions" },
211 { 0, 54, 2, "Dot3StatsLateCollisions" },
212 { 0, 56, 2, "EtherStatsCollisions" },
213 { 0, 58, 2, "Dot3StatsExcessiveCollisions" },
214 { 0, 60, 2, "Dot3OutPauseFrames" },
215 { 0, 62, 2, "Dot1dBasePortDelayExceededDiscards" },
216 { 0, 64, 2, "Dot1dTpPortInDiscards" },
217 { 0, 66, 2, "IfOutUcastPkts" },
218 { 0, 68, 2, "IfOutMulticastPkts" },
219 { 0, 70, 2, "IfOutBroadcastPkts" },
220 };
221
222 #define REG_WR(_smi, _reg, _val) \
223 do { \
224 err = rtl8366_smi_write_reg(_smi, _reg, _val); \
225 if (err) \
226 return err; \
227 } while (0)
228
229 #define REG_RMW(_smi, _reg, _mask, _val) \
230 do { \
231 err = rtl8366_smi_rmwr(_smi, _reg, _mask, _val); \
232 if (err) \
233 return err; \
234 } while (0)
235
236 static inline struct rtl8366rb *smi_to_rtl8366rb(struct rtl8366_smi *smi)
237 {
238 return container_of(smi, struct rtl8366rb, smi);
239 }
240
241 static inline struct rtl8366rb *sw_to_rtl8366rb(struct switch_dev *sw)
242 {
243 return container_of(sw, struct rtl8366rb, dev);
244 }
245
246 static inline struct rtl8366_smi *sw_to_rtl8366_smi(struct switch_dev *sw)
247 {
248 struct rtl8366rb *rtl = sw_to_rtl8366rb(sw);
249 return &rtl->smi;
250 }
251
252 static int rtl8366rb_reset_chip(struct rtl8366_smi *smi)
253 {
254 int timeout = 10;
255 u32 data;
256
257 rtl8366_smi_write_reg(smi, RTL8366RB_RESET_CTRL_REG,
258 RTL8366RB_CHIP_CTRL_RESET_HW);
259 do {
260 msleep(1);
261 if (rtl8366_smi_read_reg(smi, RTL8366RB_RESET_CTRL_REG, &data))
262 return -EIO;
263
264 if (!(data & RTL8366RB_CHIP_CTRL_RESET_HW))
265 break;
266 } while (--timeout);
267
268 if (!timeout) {
269 printk("Timeout waiting for the switch to reset\n");
270 return -EIO;
271 }
272
273 return 0;
274 }
275
276 static int rtl8366rb_hw_init(struct rtl8366_smi *smi)
277 {
278 int err;
279
280 /* set maximum packet length to 1536 bytes */
281 REG_RMW(smi, RTL8366RB_SGCR, RTL8366RB_SGCR_MAX_LENGTH_MASK,
282 RTL8366RB_SGCR_MAX_LENGTH_1536);
283
284 /* enable all ports */
285 REG_WR(smi, RTL8366RB_PECR, 0);
286
287 /* disable learning for all ports */
288 REG_WR(smi, RTL8366RB_SSCR0, RTL8366RB_PORT_ALL);
289
290 /* disable auto ageing for all ports */
291 REG_WR(smi, RTL8366RB_SSCR1, RTL8366RB_PORT_ALL);
292
293 /* don't drop packets whose DA has not been learned */
294 REG_RMW(smi, RTL8366RB_SSCR2, RTL8366RB_SSCR2_DROP_UNKNOWN_DA, 0);
295
296 return 0;
297 }
298
299 static int rtl8366rb_read_phy_reg(struct rtl8366_smi *smi,
300 u32 phy_no, u32 page, u32 addr, u32 *data)
301 {
302 u32 reg;
303 int ret;
304
305 if (phy_no > RTL8366RB_PHY_NO_MAX)
306 return -EINVAL;
307
308 if (page > RTL8366RB_PHY_PAGE_MAX)
309 return -EINVAL;
310
311 if (addr > RTL8366RB_PHY_ADDR_MAX)
312 return -EINVAL;
313
314 ret = rtl8366_smi_write_reg(smi, RTL8366RB_PHY_ACCESS_CTRL_REG,
315 RTL8366RB_PHY_CTRL_READ);
316 if (ret)
317 return ret;
318
319 reg = 0x8000 | (1 << (phy_no + RTL8366RB_PHY_NO_OFFSET)) |
320 ((page << RTL8366RB_PHY_PAGE_OFFSET) & RTL8366RB_PHY_PAGE_MASK) |
321 (addr & RTL8366RB_PHY_REG_MASK);
322
323 ret = rtl8366_smi_write_reg(smi, reg, 0);
324 if (ret)
325 return ret;
326
327 ret = rtl8366_smi_read_reg(smi, RTL8366RB_PHY_ACCESS_DATA_REG, data);
328 if (ret)
329 return ret;
330
331 return 0;
332 }
333
334 static int rtl8366rb_write_phy_reg(struct rtl8366_smi *smi,
335 u32 phy_no, u32 page, u32 addr, u32 data)
336 {
337 u32 reg;
338 int ret;
339
340 if (phy_no > RTL8366RB_PHY_NO_MAX)
341 return -EINVAL;
342
343 if (page > RTL8366RB_PHY_PAGE_MAX)
344 return -EINVAL;
345
346 if (addr > RTL8366RB_PHY_ADDR_MAX)
347 return -EINVAL;
348
349 ret = rtl8366_smi_write_reg(smi, RTL8366RB_PHY_ACCESS_CTRL_REG,
350 RTL8366RB_PHY_CTRL_WRITE);
351 if (ret)
352 return ret;
353
354 reg = 0x8000 | (1 << (phy_no + RTL8366RB_PHY_NO_OFFSET)) |
355 ((page << RTL8366RB_PHY_PAGE_OFFSET) & RTL8366RB_PHY_PAGE_MASK) |
356 (addr & RTL8366RB_PHY_REG_MASK);
357
358 ret = rtl8366_smi_write_reg(smi, reg, data);
359 if (ret)
360 return ret;
361
362 return 0;
363 }
364
365 static int rtl8366rb_get_mib_counter(struct rtl8366_smi *smi, int counter,
366 int port, unsigned long long *val)
367 {
368 int i;
369 int err;
370 u32 addr, data;
371 u64 mibvalue;
372
373 if (port > RTL8366RB_NUM_PORTS || counter >= RTL8366RB_MIB_COUNT)
374 return -EINVAL;
375
376 addr = RTL8366RB_MIB_COUNTER_BASE +
377 RTL8366RB_MIB_COUNTER_PORT_OFFSET * (port) +
378 rtl8366rb_mib_counters[counter].offset;
379
380 /*
381 * Writing access counter address first
382 * then ASIC will prepare 64bits counter wait for being retrived
383 */
384 data = 0; /* writing data will be discard by ASIC */
385 err = rtl8366_smi_write_reg(smi, addr, data);
386 if (err)
387 return err;
388
389 /* read MIB control register */
390 err = rtl8366_smi_read_reg(smi, RTL8366RB_MIB_CTRL_REG, &data);
391 if (err)
392 return err;
393
394 if (data & RTL8366RB_MIB_CTRL_BUSY_MASK)
395 return -EBUSY;
396
397 if (data & RTL8366RB_MIB_CTRL_RESET_MASK)
398 return -EIO;
399
400 mibvalue = 0;
401 for (i = rtl8366rb_mib_counters[counter].length; i > 0; i--) {
402 err = rtl8366_smi_read_reg(smi, addr + (i - 1), &data);
403 if (err)
404 return err;
405
406 mibvalue = (mibvalue << 16) | (data & 0xFFFF);
407 }
408
409 *val = mibvalue;
410 return 0;
411 }
412
413 static int rtl8366rb_get_vlan_4k(struct rtl8366_smi *smi, u32 vid,
414 struct rtl8366_vlan_4k *vlan4k)
415 {
416 struct rtl8366rb_vlan_4k vlan4k_priv;
417 int err;
418 u32 data;
419 u16 *tableaddr;
420
421 memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k));
422 vlan4k_priv.vid = vid;
423
424 if (vid >= RTL8366RB_NUM_VIDS)
425 return -EINVAL;
426
427 tableaddr = (u16 *)&vlan4k_priv;
428
429 /* write VID */
430 data = *tableaddr;
431 err = rtl8366_smi_write_reg(smi, RTL8366RB_VLAN_TABLE_WRITE_BASE, data);
432 if (err)
433 return err;
434
435 /* write table access control word */
436 err = rtl8366_smi_write_reg(smi, RTL8366RB_TABLE_ACCESS_CTRL_REG,
437 RTL8366RB_TABLE_VLAN_READ_CTRL);
438 if (err)
439 return err;
440
441 err = rtl8366_smi_read_reg(smi, RTL8366RB_VLAN_TABLE_READ_BASE, &data);
442 if (err)
443 return err;
444
445 *tableaddr = data;
446 tableaddr++;
447
448 err = rtl8366_smi_read_reg(smi, RTL8366RB_VLAN_TABLE_READ_BASE + 1,
449 &data);
450 if (err)
451 return err;
452
453 *tableaddr = data;
454 tableaddr++;
455
456 err = rtl8366_smi_read_reg(smi, RTL8366RB_VLAN_TABLE_READ_BASE + 2,
457 &data);
458 if (err)
459 return err;
460 *tableaddr = data;
461
462 vlan4k->vid = vid;
463 vlan4k->untag = vlan4k_priv.untag;
464 vlan4k->member = vlan4k_priv.member;
465 vlan4k->fid = vlan4k_priv.fid;
466
467 return 0;
468 }
469
470 static int rtl8366rb_set_vlan_4k(struct rtl8366_smi *smi,
471 const struct rtl8366_vlan_4k *vlan4k)
472 {
473 struct rtl8366rb_vlan_4k vlan4k_priv;
474 int err;
475 u32 data;
476 u16 *tableaddr;
477
478 if (vlan4k->vid >= RTL8366RB_NUM_VIDS ||
479 vlan4k->member > RTL8366RB_PORT_ALL ||
480 vlan4k->untag > RTL8366RB_PORT_ALL ||
481 vlan4k->fid > RTL8366RB_FIDMAX)
482 return -EINVAL;
483
484 vlan4k_priv.vid = vlan4k->vid;
485 vlan4k_priv.untag = vlan4k->untag;
486 vlan4k_priv.member = vlan4k->member;
487 vlan4k_priv.fid = vlan4k->fid;
488
489 tableaddr = (u16 *)&vlan4k_priv;
490
491 data = *tableaddr;
492
493 err = rtl8366_smi_write_reg(smi, RTL8366RB_VLAN_TABLE_WRITE_BASE, data);
494 if (err)
495 return err;
496
497 tableaddr++;
498
499 data = *tableaddr;
500
501 err = rtl8366_smi_write_reg(smi, RTL8366RB_VLAN_TABLE_WRITE_BASE + 1,
502 data);
503 if (err)
504 return err;
505
506 tableaddr++;
507
508 data = *tableaddr;
509
510 err = rtl8366_smi_write_reg(smi, RTL8366RB_VLAN_TABLE_WRITE_BASE + 2,
511 data);
512 if (err)
513 return err;
514
515 /* write table access control word */
516 err = rtl8366_smi_write_reg(smi, RTL8366RB_TABLE_ACCESS_CTRL_REG,
517 RTL8366RB_TABLE_VLAN_WRITE_CTRL);
518
519 return err;
520 }
521
522 static int rtl8366rb_get_vlan_mc(struct rtl8366_smi *smi, u32 index,
523 struct rtl8366_vlan_mc *vlanmc)
524 {
525 struct rtl8366rb_vlan_mc vlanmc_priv;
526 int err;
527 u32 addr;
528 u32 data;
529 u16 *tableaddr;
530
531 memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc));
532
533 if (index >= RTL8366RB_NUM_VLANS)
534 return -EINVAL;
535
536 tableaddr = (u16 *)&vlanmc_priv;
537
538 addr = RTL8366RB_VLAN_MEMCONF_BASE + (index * 3);
539 err = rtl8366_smi_read_reg(smi, addr, &data);
540 if (err)
541 return err;
542
543 *tableaddr = data;
544 tableaddr++;
545
546 addr = RTL8366RB_VLAN_MEMCONF_BASE + 1 + (index * 3);
547 err = rtl8366_smi_read_reg(smi, addr, &data);
548 if (err)
549 return err;
550
551 *tableaddr = data;
552 tableaddr++;
553
554 addr = RTL8366RB_VLAN_MEMCONF_BASE + 2 + (index * 3);
555 err = rtl8366_smi_read_reg(smi, addr, &data);
556 if (err)
557 return err;
558
559 *tableaddr = data;
560
561 vlanmc->vid = vlanmc_priv.vid;
562 vlanmc->priority = vlanmc_priv.priority;
563 vlanmc->untag = vlanmc_priv.untag;
564 vlanmc->member = vlanmc_priv.member;
565 vlanmc->fid = vlanmc_priv.fid;
566
567 return 0;
568 }
569
570 static int rtl8366rb_set_vlan_mc(struct rtl8366_smi *smi, u32 index,
571 const struct rtl8366_vlan_mc *vlanmc)
572 {
573 struct rtl8366rb_vlan_mc vlanmc_priv;
574 int err;
575 u32 addr;
576 u32 data;
577 u16 *tableaddr;
578
579 if (index >= RTL8366RB_NUM_VLANS ||
580 vlanmc->vid >= RTL8366RB_NUM_VIDS ||
581 vlanmc->priority > RTL8366RB_PRIORITYMAX ||
582 vlanmc->member > RTL8366RB_PORT_ALL ||
583 vlanmc->untag > RTL8366RB_PORT_ALL ||
584 vlanmc->fid > RTL8366RB_FIDMAX)
585 return -EINVAL;
586
587 vlanmc_priv.vid = vlanmc->vid;
588 vlanmc_priv.priority = vlanmc->priority;
589 vlanmc_priv.untag = vlanmc->untag;
590 vlanmc_priv.member = vlanmc->member;
591 vlanmc_priv.stag_mbr = 0;
592 vlanmc_priv.stag_idx = 0;
593 vlanmc_priv.fid = vlanmc->fid;
594
595 addr = RTL8366RB_VLAN_MEMCONF_BASE + (index * 3);
596
597 tableaddr = (u16 *)&vlanmc_priv;
598 data = *tableaddr;
599
600 err = rtl8366_smi_write_reg(smi, addr, data);
601 if (err)
602 return err;
603
604 addr = RTL8366RB_VLAN_MEMCONF_BASE + 1 + (index * 3);
605
606 tableaddr++;
607 data = *tableaddr;
608
609 err = rtl8366_smi_write_reg(smi, addr, data);
610 if (err)
611 return err;
612
613 addr = RTL8366RB_VLAN_MEMCONF_BASE + 2 + (index * 3);
614
615 tableaddr++;
616 data = *tableaddr;
617
618 err = rtl8366_smi_write_reg(smi, addr, data);
619 if (err)
620 return err;
621 return 0;
622 }
623
624 static int rtl8366rb_get_mc_index(struct rtl8366_smi *smi, int port, int *val)
625 {
626 u32 data;
627 int err;
628
629 if (port >= RTL8366RB_NUM_PORTS)
630 return -EINVAL;
631
632 err = rtl8366_smi_read_reg(smi, RTL8366RB_PORT_VLAN_CTRL_REG(port),
633 &data);
634 if (err)
635 return err;
636
637 *val = (data >> RTL8366RB_PORT_VLAN_CTRL_SHIFT(port)) &
638 RTL8366RB_PORT_VLAN_CTRL_MASK;
639
640 return 0;
641
642 }
643
644 static int rtl8366rb_set_mc_index(struct rtl8366_smi *smi, int port, int index)
645 {
646 if (port >= RTL8366RB_NUM_PORTS || index >= RTL8366RB_NUM_VLANS)
647 return -EINVAL;
648
649 return rtl8366_smi_rmwr(smi, RTL8366RB_PORT_VLAN_CTRL_REG(port),
650 RTL8366RB_PORT_VLAN_CTRL_MASK <<
651 RTL8366RB_PORT_VLAN_CTRL_SHIFT(port),
652 (index & RTL8366RB_PORT_VLAN_CTRL_MASK) <<
653 RTL8366RB_PORT_VLAN_CTRL_SHIFT(port));
654 }
655
656 static int rtl8366rb_vlan_set_vlan(struct rtl8366_smi *smi, int enable)
657 {
658 return rtl8366_smi_rmwr(smi, RTL8366RB_CHIP_GLOBAL_CTRL_REG,
659 RTL8366RB_CHIP_CTRL_VLAN,
660 (enable) ? RTL8366RB_CHIP_CTRL_VLAN : 0);
661 }
662
663 static int rtl8366rb_vlan_set_4ktable(struct rtl8366_smi *smi, int enable)
664 {
665 return rtl8366_smi_rmwr(smi, RTL8366RB_CHIP_GLOBAL_CTRL_REG,
666 RTL8366RB_CHIP_CTRL_VLAN_4KTB,
667 (enable) ? RTL8366RB_CHIP_CTRL_VLAN_4KTB : 0);
668 }
669
670 static int rtl8366rb_sw_reset_mibs(struct switch_dev *dev,
671 const struct switch_attr *attr,
672 struct switch_val *val)
673 {
674 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
675 int err = 0;
676
677 if (val->value.i == 1)
678 err = rtl8366_smi_rmwr(smi, RTL8366RB_MIB_CTRL_REG, 0,
679 RTL8366RB_MIB_CTRL_GLOBAL_RESET);
680
681 return err;
682 }
683
684 static int rtl8366rb_sw_get_vlan_enable(struct switch_dev *dev,
685 const struct switch_attr *attr,
686 struct switch_val *val)
687 {
688 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
689 u32 data;
690
691 if (attr->ofs == 1) {
692 rtl8366_smi_read_reg(smi, RTL8366RB_CHIP_GLOBAL_CTRL_REG, &data);
693
694 if (data & RTL8366RB_CHIP_CTRL_VLAN)
695 val->value.i = 1;
696 else
697 val->value.i = 0;
698 } else if (attr->ofs == 2) {
699 rtl8366_smi_read_reg(smi, RTL8366RB_CHIP_GLOBAL_CTRL_REG, &data);
700
701 if (data & RTL8366RB_CHIP_CTRL_VLAN_4KTB)
702 val->value.i = 1;
703 else
704 val->value.i = 0;
705 }
706
707 return 0;
708 }
709
710 static int rtl8366rb_sw_get_blinkrate(struct switch_dev *dev,
711 const struct switch_attr *attr,
712 struct switch_val *val)
713 {
714 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
715 u32 data;
716
717 rtl8366_smi_read_reg(smi, RTL8366RB_LED_BLINKRATE_REG, &data);
718
719 val->value.i = (data & (RTL8366RB_LED_BLINKRATE_MASK));
720
721 return 0;
722 }
723
724 static int rtl8366rb_sw_set_blinkrate(struct switch_dev *dev,
725 const struct switch_attr *attr,
726 struct switch_val *val)
727 {
728 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
729
730 if (val->value.i >= 6)
731 return -EINVAL;
732
733 return rtl8366_smi_rmwr(smi, RTL8366RB_LED_BLINKRATE_REG,
734 RTL8366RB_LED_BLINKRATE_MASK,
735 val->value.i);
736 }
737
738 static int rtl8366rb_sw_set_vlan_enable(struct switch_dev *dev,
739 const struct switch_attr *attr,
740 struct switch_val *val)
741 {
742 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
743
744 if (attr->ofs == 1)
745 return rtl8366rb_vlan_set_vlan(smi, val->value.i);
746 else
747 return rtl8366rb_vlan_set_4ktable(smi, val->value.i);
748 }
749
750 static const char *rtl8366rb_speed_str(unsigned speed)
751 {
752 switch (speed) {
753 case 0:
754 return "10baseT";
755 case 1:
756 return "100baseT";
757 case 2:
758 return "1000baseT";
759 }
760
761 return "unknown";
762 }
763
764 static int rtl8366rb_sw_get_port_link(struct switch_dev *dev,
765 const struct switch_attr *attr,
766 struct switch_val *val)
767 {
768 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
769 u32 len = 0, data = 0;
770
771 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
772 return -EINVAL;
773
774 memset(smi->buf, '\0', sizeof(smi->buf));
775 rtl8366_smi_read_reg(smi, RTL8366RB_PORT_LINK_STATUS_BASE +
776 (val->port_vlan / 2), &data);
777
778 if (val->port_vlan % 2)
779 data = data >> 8;
780
781 if (data & RTL8366RB_PORT_STATUS_LINK_MASK) {
782 len = snprintf(smi->buf, sizeof(smi->buf),
783 "port:%d link:up speed:%s %s-duplex %s%s%s",
784 val->port_vlan,
785 rtl8366rb_speed_str(data &
786 RTL8366RB_PORT_STATUS_SPEED_MASK),
787 (data & RTL8366RB_PORT_STATUS_DUPLEX_MASK) ?
788 "full" : "half",
789 (data & RTL8366RB_PORT_STATUS_TXPAUSE_MASK) ?
790 "tx-pause ": "",
791 (data & RTL8366RB_PORT_STATUS_RXPAUSE_MASK) ?
792 "rx-pause " : "",
793 (data & RTL8366RB_PORT_STATUS_AN_MASK) ?
794 "nway ": "");
795 } else {
796 len = snprintf(smi->buf, sizeof(smi->buf), "port:%d link: down",
797 val->port_vlan);
798 }
799
800 val->value.s = smi->buf;
801 val->len = len;
802
803 return 0;
804 }
805
806 static int rtl8366rb_sw_get_vlan_info(struct switch_dev *dev,
807 const struct switch_attr *attr,
808 struct switch_val *val)
809 {
810 int i;
811 u32 len = 0;
812 struct rtl8366_vlan_4k vlan4k;
813 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
814 char *buf = smi->buf;
815 int err;
816
817 if (val->port_vlan == 0 || val->port_vlan >= RTL8366RB_NUM_VLANS)
818 return -EINVAL;
819
820 memset(buf, '\0', sizeof(smi->buf));
821
822 err = rtl8366rb_get_vlan_4k(smi, val->port_vlan, &vlan4k);
823 if (err)
824 return err;
825
826 len += snprintf(buf + len, sizeof(smi->buf) - len,
827 "VLAN %d: Ports: '", vlan4k.vid);
828
829 for (i = 0; i < RTL8366RB_NUM_PORTS; i++) {
830 if (!(vlan4k.member & (1 << i)))
831 continue;
832
833 len += snprintf(buf + len, sizeof(smi->buf) - len, "%d%s", i,
834 (vlan4k.untag & (1 << i)) ? "" : "t");
835 }
836
837 len += snprintf(buf + len, sizeof(smi->buf) - len,
838 "', members=%04x, untag=%04x, fid=%u",
839 vlan4k.member, vlan4k.untag, vlan4k.fid);
840
841 val->value.s = buf;
842 val->len = len;
843
844 return 0;
845 }
846
847 static int rtl8366rb_sw_set_port_led(struct switch_dev *dev,
848 const struct switch_attr *attr,
849 struct switch_val *val)
850 {
851 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
852 u32 data;
853 u32 mask;
854 u32 reg;
855
856 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
857 return -EINVAL;
858
859 if (val->port_vlan == RTL8366RB_PORT_NUM_CPU) {
860 reg = RTL8366RB_LED_BLINKRATE_REG;
861 mask = 0xF << 4;
862 data = val->value.i << 4;
863 } else {
864 reg = RTL8366RB_LED_CTRL_REG;
865 mask = 0xF << (val->port_vlan * 4),
866 data = val->value.i << (val->port_vlan * 4);
867 }
868
869 return rtl8366_smi_rmwr(smi, RTL8366RB_LED_BLINKRATE_REG, mask, data);
870 }
871
872 static int rtl8366rb_sw_get_port_led(struct switch_dev *dev,
873 const struct switch_attr *attr,
874 struct switch_val *val)
875 {
876 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
877 u32 data = 0;
878
879 if (val->port_vlan >= RTL8366RB_NUM_LEDGROUPS)
880 return -EINVAL;
881
882 rtl8366_smi_read_reg(smi, RTL8366RB_LED_CTRL_REG, &data);
883 val->value.i = (data >> (val->port_vlan * 4)) & 0x000F;
884
885 return 0;
886 }
887
888 static int rtl8366rb_sw_reset_port_mibs(struct switch_dev *dev,
889 const struct switch_attr *attr,
890 struct switch_val *val)
891 {
892 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
893
894 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
895 return -EINVAL;
896
897 return rtl8366_smi_rmwr(smi, RTL8366RB_MIB_CTRL_REG, 0,
898 RTL8366RB_MIB_CTRL_PORT_RESET(val->port_vlan));
899 }
900
901 static int rtl8366rb_sw_get_port_mib(struct switch_dev *dev,
902 const struct switch_attr *attr,
903 struct switch_val *val)
904 {
905 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
906 int i, len = 0;
907 unsigned long long counter = 0;
908 char *buf = smi->buf;
909
910 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
911 return -EINVAL;
912
913 len += snprintf(buf + len, sizeof(smi->buf) - len,
914 "Port %d MIB counters\n",
915 val->port_vlan);
916
917 for (i = 0; i < ARRAY_SIZE(rtl8366rb_mib_counters); ++i) {
918 len += snprintf(buf + len, sizeof(smi->buf) - len,
919 "%-36s: ", rtl8366rb_mib_counters[i].name);
920 if (!rtl8366rb_get_mib_counter(smi, i, val->port_vlan, &counter))
921 len += snprintf(buf + len, sizeof(smi->buf) - len,
922 "%llu\n", counter);
923 else
924 len += snprintf(buf + len, sizeof(smi->buf) - len,
925 "%s\n", "error");
926 }
927
928 val->value.s = buf;
929 val->len = len;
930 return 0;
931 }
932
933 static int rtl8366rb_sw_get_vlan_ports(struct switch_dev *dev,
934 struct switch_val *val)
935 {
936 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
937 struct switch_port *port;
938 struct rtl8366_vlan_4k vlan4k;
939 int i;
940
941 if (val->port_vlan == 0 || val->port_vlan >= RTL8366RB_NUM_VLANS)
942 return -EINVAL;
943
944 rtl8366rb_get_vlan_4k(smi, val->port_vlan, &vlan4k);
945
946 port = &val->value.ports[0];
947 val->len = 0;
948 for (i = 0; i < RTL8366RB_NUM_PORTS; i++) {
949 if (!(vlan4k.member & BIT(i)))
950 continue;
951
952 port->id = i;
953 port->flags = (vlan4k.untag & BIT(i)) ?
954 0 : BIT(SWITCH_PORT_FLAG_TAGGED);
955 val->len++;
956 port++;
957 }
958 return 0;
959 }
960
961 static int rtl8366rb_sw_set_vlan_ports(struct switch_dev *dev,
962 struct switch_val *val)
963 {
964 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
965 struct switch_port *port;
966 u32 member = 0;
967 u32 untag = 0;
968 int i;
969
970 if (val->port_vlan == 0 || val->port_vlan >= RTL8366RB_NUM_VLANS)
971 return -EINVAL;
972
973 port = &val->value.ports[0];
974 for (i = 0; i < val->len; i++, port++) {
975 member |= BIT(port->id);
976
977 if (!(port->flags & BIT(SWITCH_PORT_FLAG_TAGGED)))
978 untag |= BIT(port->id);
979 }
980
981 return rtl8366_set_vlan(smi, val->port_vlan, member, untag, 0);
982 }
983
984 static int rtl8366rb_sw_get_port_pvid(struct switch_dev *dev, int port, int *val)
985 {
986 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
987 return rtl8366_get_pvid(smi, port, val);
988 }
989
990 static int rtl8366rb_sw_set_port_pvid(struct switch_dev *dev, int port, int val)
991 {
992 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
993 return rtl8366_set_pvid(smi, port, val);
994 }
995
996 static int rtl8366rb_sw_reset_switch(struct switch_dev *dev)
997 {
998 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
999 int err;
1000
1001 err = rtl8366rb_reset_chip(smi);
1002 if (err)
1003 return err;
1004
1005 err = rtl8366rb_hw_init(smi);
1006 if (err)
1007 return err;
1008
1009 return rtl8366_reset_vlan(smi);
1010 }
1011
1012 static struct switch_attr rtl8366rb_globals[] = {
1013 {
1014 .type = SWITCH_TYPE_INT,
1015 .name = "enable_vlan",
1016 .description = "Enable VLAN mode",
1017 .set = rtl8366rb_sw_set_vlan_enable,
1018 .get = rtl8366rb_sw_get_vlan_enable,
1019 .max = 1,
1020 .ofs = 1
1021 }, {
1022 .type = SWITCH_TYPE_INT,
1023 .name = "enable_vlan4k",
1024 .description = "Enable VLAN 4K mode",
1025 .set = rtl8366rb_sw_set_vlan_enable,
1026 .get = rtl8366rb_sw_get_vlan_enable,
1027 .max = 1,
1028 .ofs = 2
1029 }, {
1030 .type = SWITCH_TYPE_INT,
1031 .name = "reset_mibs",
1032 .description = "Reset all MIB counters",
1033 .set = rtl8366rb_sw_reset_mibs,
1034 .get = NULL,
1035 .max = 1
1036 }, {
1037 .type = SWITCH_TYPE_INT,
1038 .name = "blinkrate",
1039 .description = "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms,"
1040 " 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)",
1041 .set = rtl8366rb_sw_set_blinkrate,
1042 .get = rtl8366rb_sw_get_blinkrate,
1043 .max = 5
1044 },
1045 };
1046
1047 static struct switch_attr rtl8366rb_port[] = {
1048 {
1049 .type = SWITCH_TYPE_STRING,
1050 .name = "link",
1051 .description = "Get port link information",
1052 .max = 1,
1053 .set = NULL,
1054 .get = rtl8366rb_sw_get_port_link,
1055 }, {
1056 .type = SWITCH_TYPE_INT,
1057 .name = "reset_mib",
1058 .description = "Reset single port MIB counters",
1059 .max = 1,
1060 .set = rtl8366rb_sw_reset_port_mibs,
1061 .get = NULL,
1062 }, {
1063 .type = SWITCH_TYPE_STRING,
1064 .name = "mib",
1065 .description = "Get MIB counters for port",
1066 .max = 33,
1067 .set = NULL,
1068 .get = rtl8366rb_sw_get_port_mib,
1069 }, {
1070 .type = SWITCH_TYPE_INT,
1071 .name = "led",
1072 .description = "Get/Set port group (0 - 3) led mode (0 - 15)",
1073 .max = 15,
1074 .set = rtl8366rb_sw_set_port_led,
1075 .get = rtl8366rb_sw_get_port_led,
1076 },
1077 };
1078
1079 static struct switch_attr rtl8366rb_vlan[] = {
1080 {
1081 .type = SWITCH_TYPE_STRING,
1082 .name = "info",
1083 .description = "Get vlan information",
1084 .max = 1,
1085 .set = NULL,
1086 .get = rtl8366rb_sw_get_vlan_info,
1087 },
1088 };
1089
1090 /* template */
1091 static struct switch_dev rtl8366_switch_dev = {
1092 .name = "RTL8366S",
1093 .cpu_port = RTL8366RB_PORT_NUM_CPU,
1094 .ports = RTL8366RB_NUM_PORTS,
1095 .vlans = RTL8366RB_NUM_VLANS,
1096 .attr_global = {
1097 .attr = rtl8366rb_globals,
1098 .n_attr = ARRAY_SIZE(rtl8366rb_globals),
1099 },
1100 .attr_port = {
1101 .attr = rtl8366rb_port,
1102 .n_attr = ARRAY_SIZE(rtl8366rb_port),
1103 },
1104 .attr_vlan = {
1105 .attr = rtl8366rb_vlan,
1106 .n_attr = ARRAY_SIZE(rtl8366rb_vlan),
1107 },
1108
1109 .get_vlan_ports = rtl8366rb_sw_get_vlan_ports,
1110 .set_vlan_ports = rtl8366rb_sw_set_vlan_ports,
1111 .get_port_pvid = rtl8366rb_sw_get_port_pvid,
1112 .set_port_pvid = rtl8366rb_sw_set_port_pvid,
1113 .reset_switch = rtl8366rb_sw_reset_switch,
1114 };
1115
1116 static int rtl8366rb_switch_init(struct rtl8366rb *rtl)
1117 {
1118 struct switch_dev *dev = &rtl->dev;
1119 int err;
1120
1121 memcpy(dev, &rtl8366_switch_dev, sizeof(struct switch_dev));
1122 dev->priv = rtl;
1123 dev->devname = dev_name(rtl->parent);
1124
1125 err = register_switch(dev, NULL);
1126 if (err)
1127 dev_err(rtl->parent, "switch registration failed\n");
1128
1129 return err;
1130 }
1131
1132 static void rtl8366rb_switch_cleanup(struct rtl8366rb *rtl)
1133 {
1134 unregister_switch(&rtl->dev);
1135 }
1136
1137 static int rtl8366rb_mii_read(struct mii_bus *bus, int addr, int reg)
1138 {
1139 struct rtl8366_smi *smi = bus->priv;
1140 u32 val = 0;
1141 int err;
1142
1143 err = rtl8366rb_read_phy_reg(smi, addr, 0, reg, &val);
1144 if (err)
1145 return 0xffff;
1146
1147 return val;
1148 }
1149
1150 static int rtl8366rb_mii_write(struct mii_bus *bus, int addr, int reg, u16 val)
1151 {
1152 struct rtl8366_smi *smi = bus->priv;
1153 u32 t;
1154 int err;
1155
1156 err = rtl8366rb_write_phy_reg(smi, addr, 0, reg, val);
1157 /* flush write */
1158 (void) rtl8366rb_read_phy_reg(smi, addr, 0, reg, &t);
1159
1160 return err;
1161 }
1162
1163 static int rtl8366rb_mii_bus_match(struct mii_bus *bus)
1164 {
1165 return (bus->read == rtl8366rb_mii_read &&
1166 bus->write == rtl8366rb_mii_write);
1167 }
1168
1169 static int rtl8366rb_setup(struct rtl8366rb *rtl)
1170 {
1171 struct rtl8366_smi *smi = &rtl->smi;
1172 int ret;
1173
1174 ret = rtl8366rb_reset_chip(smi);
1175 if (ret)
1176 return ret;
1177
1178 ret = rtl8366rb_hw_init(smi);
1179 return ret;
1180 }
1181
1182 static int rtl8366rb_detect(struct rtl8366_smi *smi)
1183 {
1184 u32 chip_id = 0;
1185 u32 chip_ver = 0;
1186 int ret;
1187
1188 ret = rtl8366_smi_read_reg(smi, RTL8366RB_CHIP_ID_REG, &chip_id);
1189 if (ret) {
1190 dev_err(smi->parent, "unable to read chip id\n");
1191 return ret;
1192 }
1193
1194 switch (chip_id) {
1195 case RTL8366RB_CHIP_ID_8366:
1196 break;
1197 default:
1198 dev_err(smi->parent, "unknown chip id (%04x)\n", chip_id);
1199 return -ENODEV;
1200 }
1201
1202 ret = rtl8366_smi_read_reg(smi, RTL8366RB_CHIP_VERSION_CTRL_REG,
1203 &chip_ver);
1204 if (ret) {
1205 dev_err(smi->parent, "unable to read chip version\n");
1206 return ret;
1207 }
1208
1209 dev_info(smi->parent, "RTL%04x ver. %u chip found\n",
1210 chip_id, chip_ver & RTL8366RB_CHIP_VERSION_MASK);
1211
1212 return 0;
1213 }
1214
1215 static struct rtl8366_smi_ops rtl8366rb_smi_ops = {
1216 .detect = rtl8366rb_detect,
1217 .mii_read = rtl8366rb_mii_read,
1218 .mii_write = rtl8366rb_mii_write,
1219
1220 .get_vlan_mc = rtl8366rb_get_vlan_mc,
1221 .set_vlan_mc = rtl8366rb_set_vlan_mc,
1222 .get_vlan_4k = rtl8366rb_get_vlan_4k,
1223 .set_vlan_4k = rtl8366rb_set_vlan_4k,
1224 .get_mc_index = rtl8366rb_get_mc_index,
1225 .set_mc_index = rtl8366rb_set_mc_index,
1226 .get_mib_counter = rtl8366rb_get_mib_counter,
1227 };
1228
1229 static int __init rtl8366rb_probe(struct platform_device *pdev)
1230 {
1231 static int rtl8366_smi_version_printed;
1232 struct rtl8366rb_platform_data *pdata;
1233 struct rtl8366rb *rtl;
1234 struct rtl8366_smi *smi;
1235 int err;
1236
1237 if (!rtl8366_smi_version_printed++)
1238 printk(KERN_NOTICE RTL8366RB_DRIVER_DESC
1239 " version " RTL8366RB_DRIVER_VER"\n");
1240
1241 pdata = pdev->dev.platform_data;
1242 if (!pdata) {
1243 dev_err(&pdev->dev, "no platform data specified\n");
1244 err = -EINVAL;
1245 goto err_out;
1246 }
1247
1248 rtl = kzalloc(sizeof(*rtl), GFP_KERNEL);
1249 if (!rtl) {
1250 dev_err(&pdev->dev, "no memory for private data\n");
1251 err = -ENOMEM;
1252 goto err_out;
1253 }
1254
1255 rtl->parent = &pdev->dev;
1256
1257 smi = &rtl->smi;
1258 smi->parent = &pdev->dev;
1259 smi->gpio_sda = pdata->gpio_sda;
1260 smi->gpio_sck = pdata->gpio_sck;
1261 smi->ops = &rtl8366rb_smi_ops;
1262 smi->cpu_port = RTL8366RB_PORT_NUM_CPU;
1263 smi->num_ports = RTL8366RB_NUM_PORTS;
1264 smi->num_vlan_mc = RTL8366RB_NUM_VLANS;
1265 smi->mib_counters = rtl8366rb_mib_counters;
1266 smi->num_mib_counters = ARRAY_SIZE(rtl8366rb_mib_counters);
1267
1268 err = rtl8366_smi_init(smi);
1269 if (err)
1270 goto err_free_rtl;
1271
1272 platform_set_drvdata(pdev, rtl);
1273
1274 err = rtl8366rb_setup(rtl);
1275 if (err)
1276 goto err_clear_drvdata;
1277
1278 err = rtl8366rb_switch_init(rtl);
1279 if (err)
1280 goto err_clear_drvdata;
1281
1282 return 0;
1283
1284 err_clear_drvdata:
1285 platform_set_drvdata(pdev, NULL);
1286 rtl8366_smi_cleanup(smi);
1287 err_free_rtl:
1288 kfree(rtl);
1289 err_out:
1290 return err;
1291 }
1292
1293 static int rtl8366rb_phy_config_init(struct phy_device *phydev)
1294 {
1295 if (!rtl8366rb_mii_bus_match(phydev->bus))
1296 return -EINVAL;
1297
1298 return 0;
1299 }
1300
1301 static int rtl8366rb_phy_config_aneg(struct phy_device *phydev)
1302 {
1303 return 0;
1304 }
1305
1306 static struct phy_driver rtl8366rb_phy_driver = {
1307 .phy_id = 0x001cc960,
1308 .name = "Realtek RTL8366RB",
1309 .phy_id_mask = 0x1ffffff0,
1310 .features = PHY_GBIT_FEATURES,
1311 .config_aneg = rtl8366rb_phy_config_aneg,
1312 .config_init = rtl8366rb_phy_config_init,
1313 .read_status = genphy_read_status,
1314 .driver = {
1315 .owner = THIS_MODULE,
1316 },
1317 };
1318
1319 static int __devexit rtl8366rb_remove(struct platform_device *pdev)
1320 {
1321 struct rtl8366rb *rtl = platform_get_drvdata(pdev);
1322
1323 if (rtl) {
1324 rtl8366rb_switch_cleanup(rtl);
1325 platform_set_drvdata(pdev, NULL);
1326 rtl8366_smi_cleanup(&rtl->smi);
1327 kfree(rtl);
1328 }
1329
1330 return 0;
1331 }
1332
1333 static struct platform_driver rtl8366rb_driver = {
1334 .driver = {
1335 .name = RTL8366RB_DRIVER_NAME,
1336 .owner = THIS_MODULE,
1337 },
1338 .probe = rtl8366rb_probe,
1339 .remove = __devexit_p(rtl8366rb_remove),
1340 };
1341
1342 static int __init rtl8366rb_module_init(void)
1343 {
1344 int ret;
1345 ret = platform_driver_register(&rtl8366rb_driver);
1346 if (ret)
1347 return ret;
1348
1349 ret = phy_driver_register(&rtl8366rb_phy_driver);
1350 if (ret)
1351 goto err_platform_unregister;
1352
1353 return 0;
1354
1355 err_platform_unregister:
1356 platform_driver_unregister(&rtl8366rb_driver);
1357 return ret;
1358 }
1359 module_init(rtl8366rb_module_init);
1360
1361 static void __exit rtl8366rb_module_exit(void)
1362 {
1363 phy_driver_unregister(&rtl8366rb_phy_driver);
1364 platform_driver_unregister(&rtl8366rb_driver);
1365 }
1366 module_exit(rtl8366rb_module_exit);
1367
1368 MODULE_DESCRIPTION(RTL8366RB_DRIVER_DESC);
1369 MODULE_VERSION(RTL8366RB_DRIVER_VER);
1370 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1371 MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>");
1372 MODULE_LICENSE("GPL v2");
1373 MODULE_ALIAS("platform:" RTL8366RB_DRIVER_NAME);
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