2 * Platform driver for the Realtek RTL8366S ethernet switch
4 * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/platform_device.h>
16 #include <linux/delay.h>
17 #include <linux/skbuff.h>
18 #include <linux/rtl8366s.h>
20 #include "rtl8366_smi.h"
22 #define RTL8366S_DRIVER_DESC "Realtek RTL8366S ethernet switch driver"
23 #define RTL8366S_DRIVER_VER "0.2.2"
25 #define RTL8366S_PHY_NO_MAX 4
26 #define RTL8366S_PHY_PAGE_MAX 7
27 #define RTL8366S_PHY_ADDR_MAX 31
28 #define RTL8366S_PHY_WAN 4
30 /* Switch Global Configuration register */
31 #define RTL8366S_SGCR 0x0000
32 #define RTL8366S_SGCR_EN_BC_STORM_CTRL BIT(0)
33 #define RTL8366S_SGCR_MAX_LENGTH(_x) (_x << 4)
34 #define RTL8366S_SGCR_MAX_LENGTH_MASK RTL8366S_SGCR_MAX_LENGTH(0x3)
35 #define RTL8366S_SGCR_MAX_LENGTH_1522 RTL8366S_SGCR_MAX_LENGTH(0x0)
36 #define RTL8366S_SGCR_MAX_LENGTH_1536 RTL8366S_SGCR_MAX_LENGTH(0x1)
37 #define RTL8366S_SGCR_MAX_LENGTH_1552 RTL8366S_SGCR_MAX_LENGTH(0x2)
38 #define RTL8366S_SGCR_MAX_LENGTH_16000 RTL8366S_SGCR_MAX_LENGTH(0x3)
39 #define RTL8366S_SGCR_EN_VLAN BIT(13)
41 /* Port Enable Control register */
42 #define RTL8366S_PECR 0x0001
44 /* Switch Security Control registers */
45 #define RTL8366S_SSCR0 0x0002
46 #define RTL8366S_SSCR1 0x0003
47 #define RTL8366S_SSCR2 0x0004
48 #define RTL8366S_SSCR2_DROP_UNKNOWN_DA BIT(0)
50 #define RTL8366S_RESET_CTRL_REG 0x0100
51 #define RTL8366S_CHIP_CTRL_RESET_HW 1
52 #define RTL8366S_CHIP_CTRL_RESET_SW (1 << 1)
54 #define RTL8366S_CHIP_VERSION_CTRL_REG 0x0104
55 #define RTL8366S_CHIP_VERSION_MASK 0xf
56 #define RTL8366S_CHIP_ID_REG 0x0105
57 #define RTL8366S_CHIP_ID_8366 0x8366
59 /* PHY registers control */
60 #define RTL8366S_PHY_ACCESS_CTRL_REG 0x8028
61 #define RTL8366S_PHY_ACCESS_DATA_REG 0x8029
63 #define RTL8366S_PHY_CTRL_READ 1
64 #define RTL8366S_PHY_CTRL_WRITE 0
66 #define RTL8366S_PHY_REG_MASK 0x1f
67 #define RTL8366S_PHY_PAGE_OFFSET 5
68 #define RTL8366S_PHY_PAGE_MASK (0x7 << 5)
69 #define RTL8366S_PHY_NO_OFFSET 9
70 #define RTL8366S_PHY_NO_MASK (0x1f << 9)
72 /* LED control registers */
73 #define RTL8366S_LED_BLINKRATE_REG 0x0420
74 #define RTL8366S_LED_BLINKRATE_BIT 0
75 #define RTL8366S_LED_BLINKRATE_MASK 0x0007
77 #define RTL8366S_LED_CTRL_REG 0x0421
78 #define RTL8366S_LED_0_1_CTRL_REG 0x0422
79 #define RTL8366S_LED_2_3_CTRL_REG 0x0423
81 #define RTL8366S_MIB_COUNT 33
82 #define RTL8366S_GLOBAL_MIB_COUNT 1
83 #define RTL8366S_MIB_COUNTER_PORT_OFFSET 0x0040
84 #define RTL8366S_MIB_COUNTER_BASE 0x1000
85 #define RTL8366S_MIB_COUNTER_PORT_OFFSET2 0x0008
86 #define RTL8366S_MIB_COUNTER_BASE2 0x1180
87 #define RTL8366S_MIB_CTRL_REG 0x11F0
88 #define RTL8366S_MIB_CTRL_USER_MASK 0x01FF
89 #define RTL8366S_MIB_CTRL_BUSY_MASK 0x0001
90 #define RTL8366S_MIB_CTRL_RESET_MASK 0x0002
92 #define RTL8366S_MIB_CTRL_GLOBAL_RESET_MASK 0x0004
93 #define RTL8366S_MIB_CTRL_PORT_RESET_BIT 0x0003
94 #define RTL8366S_MIB_CTRL_PORT_RESET_MASK 0x01FC
97 #define RTL8366S_PORT_VLAN_CTRL_BASE 0x0058
98 #define RTL8366S_PORT_VLAN_CTRL_REG(_p) \
99 (RTL8366S_PORT_VLAN_CTRL_BASE + (_p) / 4)
100 #define RTL8366S_PORT_VLAN_CTRL_MASK 0xf
101 #define RTL8366S_PORT_VLAN_CTRL_SHIFT(_p) (4 * ((_p) % 4))
104 #define RTL8366S_VLAN_TABLE_READ_BASE 0x018B
105 #define RTL8366S_VLAN_TABLE_WRITE_BASE 0x0185
107 #define RTL8366S_VLAN_TB_CTRL_REG 0x010F
109 #define RTL8366S_TABLE_ACCESS_CTRL_REG 0x0180
110 #define RTL8366S_TABLE_VLAN_READ_CTRL 0x0E01
111 #define RTL8366S_TABLE_VLAN_WRITE_CTRL 0x0F01
113 #define RTL8366S_VLAN_MC_BASE(_x) (0x0016 + (_x) * 2)
115 #define RTL8366S_VLAN_MEMBERINGRESS_REG 0x0379
117 #define RTL8366S_PORT_LINK_STATUS_BASE 0x0060
118 #define RTL8366S_PORT_STATUS_SPEED_MASK 0x0003
119 #define RTL8366S_PORT_STATUS_DUPLEX_MASK 0x0004
120 #define RTL8366S_PORT_STATUS_LINK_MASK 0x0010
121 #define RTL8366S_PORT_STATUS_TXPAUSE_MASK 0x0020
122 #define RTL8366S_PORT_STATUS_RXPAUSE_MASK 0x0040
123 #define RTL8366S_PORT_STATUS_AN_MASK 0x0080
126 #define RTL8366S_PORT_NUM_CPU 5
127 #define RTL8366S_NUM_PORTS 6
128 #define RTL8366S_NUM_VLANS 16
129 #define RTL8366S_NUM_LEDGROUPS 4
130 #define RTL8366S_NUM_VIDS 4096
131 #define RTL8366S_PRIORITYMAX 7
132 #define RTL8366S_FIDMAX 7
135 #define RTL8366S_PORT_1 (1 << 0) /* In userspace port 0 */
136 #define RTL8366S_PORT_2 (1 << 1) /* In userspace port 1 */
137 #define RTL8366S_PORT_3 (1 << 2) /* In userspace port 2 */
138 #define RTL8366S_PORT_4 (1 << 3) /* In userspace port 3 */
140 #define RTL8366S_PORT_UNKNOWN (1 << 4) /* No known connection */
141 #define RTL8366S_PORT_CPU (1 << 5) /* CPU port */
143 #define RTL8366S_PORT_ALL (RTL8366S_PORT_1 | \
147 RTL8366S_PORT_UNKNOWN | \
150 #define RTL8366S_PORT_ALL_BUT_CPU (RTL8366S_PORT_1 | \
154 RTL8366S_PORT_UNKNOWN)
156 #define RTL8366S_PORT_ALL_EXTERNAL (RTL8366S_PORT_1 | \
161 #define RTL8366S_PORT_ALL_INTERNAL (RTL8366S_PORT_UNKNOWN | \
164 #define RTL8366S_VLAN_VID_MASK 0xfff
165 #define RTL8366S_VLAN_PRIORITY_SHIFT 12
166 #define RTL8366S_VLAN_PRIORITY_MASK 0x7
167 #define RTL8366S_VLAN_MEMBER_MASK 0x3f
168 #define RTL8366S_VLAN_UNTAG_SHIFT 6
169 #define RTL8366S_VLAN_UNTAG_MASK 0x3f
170 #define RTL8366S_VLAN_FID_SHIFT 12
171 #define RTL8366S_VLAN_FID_MASK 0x7
173 static struct rtl8366_mib_counter rtl8366s_mib_counters
[] = {
174 { 0, 0, 4, "IfInOctets" },
175 { 0, 4, 4, "EtherStatsOctets" },
176 { 0, 8, 2, "EtherStatsUnderSizePkts" },
177 { 0, 10, 2, "EtherFragments" },
178 { 0, 12, 2, "EtherStatsPkts64Octets" },
179 { 0, 14, 2, "EtherStatsPkts65to127Octets" },
180 { 0, 16, 2, "EtherStatsPkts128to255Octets" },
181 { 0, 18, 2, "EtherStatsPkts256to511Octets" },
182 { 0, 20, 2, "EtherStatsPkts512to1023Octets" },
183 { 0, 22, 2, "EtherStatsPkts1024to1518Octets" },
184 { 0, 24, 2, "EtherOversizeStats" },
185 { 0, 26, 2, "EtherStatsJabbers" },
186 { 0, 28, 2, "IfInUcastPkts" },
187 { 0, 30, 2, "EtherStatsMulticastPkts" },
188 { 0, 32, 2, "EtherStatsBroadcastPkts" },
189 { 0, 34, 2, "EtherStatsDropEvents" },
190 { 0, 36, 2, "Dot3StatsFCSErrors" },
191 { 0, 38, 2, "Dot3StatsSymbolErrors" },
192 { 0, 40, 2, "Dot3InPauseFrames" },
193 { 0, 42, 2, "Dot3ControlInUnknownOpcodes" },
194 { 0, 44, 4, "IfOutOctets" },
195 { 0, 48, 2, "Dot3StatsSingleCollisionFrames" },
196 { 0, 50, 2, "Dot3StatMultipleCollisionFrames" },
197 { 0, 52, 2, "Dot3sDeferredTransmissions" },
198 { 0, 54, 2, "Dot3StatsLateCollisions" },
199 { 0, 56, 2, "EtherStatsCollisions" },
200 { 0, 58, 2, "Dot3StatsExcessiveCollisions" },
201 { 0, 60, 2, "Dot3OutPauseFrames" },
202 { 0, 62, 2, "Dot1dBasePortDelayExceededDiscards" },
205 * The following counters are accessible at a different
208 { 1, 0, 2, "Dot1dTpPortInDiscards" },
209 { 1, 2, 2, "IfOutUcastPkts" },
210 { 1, 4, 2, "IfOutMulticastPkts" },
211 { 1, 6, 2, "IfOutBroadcastPkts" },
214 #define REG_WR(_smi, _reg, _val) \
216 err = rtl8366_smi_write_reg(_smi, _reg, _val); \
221 #define REG_RMW(_smi, _reg, _mask, _val) \
223 err = rtl8366_smi_rmwr(_smi, _reg, _mask, _val); \
228 static int rtl8366s_reset_chip(struct rtl8366_smi
*smi
)
233 rtl8366_smi_write_reg(smi
, RTL8366S_RESET_CTRL_REG
,
234 RTL8366S_CHIP_CTRL_RESET_HW
);
237 if (rtl8366_smi_read_reg(smi
, RTL8366S_RESET_CTRL_REG
, &data
))
240 if (!(data
& RTL8366S_CHIP_CTRL_RESET_HW
))
245 printk("Timeout waiting for the switch to reset\n");
252 static int rtl8366s_hw_init(struct rtl8366_smi
*smi
)
256 /* set maximum packet length to 1536 bytes */
257 REG_RMW(smi
, RTL8366S_SGCR
, RTL8366S_SGCR_MAX_LENGTH_MASK
,
258 RTL8366S_SGCR_MAX_LENGTH_1536
);
260 /* enable all ports */
261 REG_WR(smi
, RTL8366S_PECR
, 0);
263 /* enable learning for all ports */
264 REG_WR(smi
, RTL8366S_SSCR0
, 0);
266 /* enable auto ageing for all ports */
267 REG_WR(smi
, RTL8366S_SSCR1
, 0);
270 * discard VLAN tagged packets if the port is not a member of
271 * the VLAN with which the packets is associated.
273 REG_WR(smi
, RTL8366S_VLAN_MEMBERINGRESS_REG
, RTL8366S_PORT_ALL
);
275 /* don't drop packets whose DA has not been learned */
276 REG_RMW(smi
, RTL8366S_SSCR2
, RTL8366S_SSCR2_DROP_UNKNOWN_DA
, 0);
281 static int rtl8366s_read_phy_reg(struct rtl8366_smi
*smi
,
282 u32 phy_no
, u32 page
, u32 addr
, u32
*data
)
287 if (phy_no
> RTL8366S_PHY_NO_MAX
)
290 if (page
> RTL8366S_PHY_PAGE_MAX
)
293 if (addr
> RTL8366S_PHY_ADDR_MAX
)
296 ret
= rtl8366_smi_write_reg(smi
, RTL8366S_PHY_ACCESS_CTRL_REG
,
297 RTL8366S_PHY_CTRL_READ
);
301 reg
= 0x8000 | (1 << (phy_no
+ RTL8366S_PHY_NO_OFFSET
)) |
302 ((page
<< RTL8366S_PHY_PAGE_OFFSET
) & RTL8366S_PHY_PAGE_MASK
) |
303 (addr
& RTL8366S_PHY_REG_MASK
);
305 ret
= rtl8366_smi_write_reg(smi
, reg
, 0);
309 ret
= rtl8366_smi_read_reg(smi
, RTL8366S_PHY_ACCESS_DATA_REG
, data
);
316 static int rtl8366s_write_phy_reg(struct rtl8366_smi
*smi
,
317 u32 phy_no
, u32 page
, u32 addr
, u32 data
)
322 if (phy_no
> RTL8366S_PHY_NO_MAX
)
325 if (page
> RTL8366S_PHY_PAGE_MAX
)
328 if (addr
> RTL8366S_PHY_ADDR_MAX
)
331 ret
= rtl8366_smi_write_reg(smi
, RTL8366S_PHY_ACCESS_CTRL_REG
,
332 RTL8366S_PHY_CTRL_WRITE
);
336 reg
= 0x8000 | (1 << (phy_no
+ RTL8366S_PHY_NO_OFFSET
)) |
337 ((page
<< RTL8366S_PHY_PAGE_OFFSET
) & RTL8366S_PHY_PAGE_MASK
) |
338 (addr
& RTL8366S_PHY_REG_MASK
);
340 ret
= rtl8366_smi_write_reg(smi
, reg
, data
);
347 static int rtl8366_get_mib_counter(struct rtl8366_smi
*smi
, int counter
,
348 int port
, unsigned long long *val
)
355 if (port
> RTL8366S_NUM_PORTS
|| counter
>= RTL8366S_MIB_COUNT
)
358 switch (rtl8366s_mib_counters
[counter
].base
) {
360 addr
= RTL8366S_MIB_COUNTER_BASE
+
361 RTL8366S_MIB_COUNTER_PORT_OFFSET
* port
;
365 addr
= RTL8366S_MIB_COUNTER_BASE2
+
366 RTL8366S_MIB_COUNTER_PORT_OFFSET2
* port
;
373 addr
+= rtl8366s_mib_counters
[counter
].offset
;
376 * Writing access counter address first
377 * then ASIC will prepare 64bits counter wait for being retrived
379 data
= 0; /* writing data will be discard by ASIC */
380 err
= rtl8366_smi_write_reg(smi
, addr
, data
);
384 /* read MIB control register */
385 err
= rtl8366_smi_read_reg(smi
, RTL8366S_MIB_CTRL_REG
, &data
);
389 if (data
& RTL8366S_MIB_CTRL_BUSY_MASK
)
392 if (data
& RTL8366S_MIB_CTRL_RESET_MASK
)
396 for (i
= rtl8366s_mib_counters
[counter
].length
; i
> 0; i
--) {
397 err
= rtl8366_smi_read_reg(smi
, addr
+ (i
- 1), &data
);
401 mibvalue
= (mibvalue
<< 16) | (data
& 0xFFFF);
408 static int rtl8366s_get_vlan_4k(struct rtl8366_smi
*smi
, u32 vid
,
409 struct rtl8366_vlan_4k
*vlan4k
)
415 memset(vlan4k
, '\0', sizeof(struct rtl8366_vlan_4k
));
417 if (vid
>= RTL8366S_NUM_VIDS
)
421 err
= rtl8366_smi_write_reg(smi
, RTL8366S_VLAN_TABLE_WRITE_BASE
,
422 vid
& RTL8366S_VLAN_VID_MASK
);
426 /* write table access control word */
427 err
= rtl8366_smi_write_reg(smi
, RTL8366S_TABLE_ACCESS_CTRL_REG
,
428 RTL8366S_TABLE_VLAN_READ_CTRL
);
432 for (i
= 0; i
< 2; i
++) {
433 err
= rtl8366_smi_read_reg(smi
,
434 RTL8366S_VLAN_TABLE_READ_BASE
+ i
,
441 vlan4k
->untag
= (data
[1] >> RTL8366S_VLAN_UNTAG_SHIFT
) &
442 RTL8366S_VLAN_UNTAG_MASK
;
443 vlan4k
->member
= data
[1] & RTL8366S_VLAN_MEMBER_MASK
;
444 vlan4k
->fid
= (data
[1] >> RTL8366S_VLAN_FID_SHIFT
) &
445 RTL8366S_VLAN_FID_MASK
;
450 static int rtl8366s_set_vlan_4k(struct rtl8366_smi
*smi
,
451 const struct rtl8366_vlan_4k
*vlan4k
)
457 if (vlan4k
->vid
>= RTL8366S_NUM_VIDS
||
458 vlan4k
->member
> RTL8366S_VLAN_MEMBER_MASK
||
459 vlan4k
->untag
> RTL8366S_VLAN_UNTAG_MASK
||
460 vlan4k
->fid
> RTL8366S_FIDMAX
)
463 data
[0] = vlan4k
->vid
& RTL8366S_VLAN_VID_MASK
;
464 data
[1] = (vlan4k
->member
& RTL8366S_VLAN_MEMBER_MASK
) |
465 ((vlan4k
->untag
& RTL8366S_VLAN_UNTAG_MASK
) <<
466 RTL8366S_VLAN_UNTAG_SHIFT
) |
467 ((vlan4k
->fid
& RTL8366S_VLAN_FID_MASK
) <<
468 RTL8366S_VLAN_FID_SHIFT
);
470 for (i
= 0; i
< 2; i
++) {
471 err
= rtl8366_smi_write_reg(smi
,
472 RTL8366S_VLAN_TABLE_WRITE_BASE
+ i
,
478 /* write table access control word */
479 err
= rtl8366_smi_write_reg(smi
, RTL8366S_TABLE_ACCESS_CTRL_REG
,
480 RTL8366S_TABLE_VLAN_WRITE_CTRL
);
485 static int rtl8366s_get_vlan_mc(struct rtl8366_smi
*smi
, u32 index
,
486 struct rtl8366_vlan_mc
*vlanmc
)
492 memset(vlanmc
, '\0', sizeof(struct rtl8366_vlan_mc
));
494 if (index
>= RTL8366S_NUM_VLANS
)
497 for (i
= 0; i
< 2; i
++) {
498 err
= rtl8366_smi_read_reg(smi
,
499 RTL8366S_VLAN_MC_BASE(index
) + i
,
505 vlanmc
->vid
= data
[0] & RTL8366S_VLAN_VID_MASK
;
506 vlanmc
->priority
= (data
[0] >> RTL8366S_VLAN_PRIORITY_SHIFT
) &
507 RTL8366S_VLAN_PRIORITY_MASK
;
508 vlanmc
->untag
= (data
[1] >> RTL8366S_VLAN_UNTAG_SHIFT
) &
509 RTL8366S_VLAN_UNTAG_MASK
;
510 vlanmc
->member
= data
[1] & RTL8366S_VLAN_MEMBER_MASK
;
511 vlanmc
->fid
= (data
[1] >> RTL8366S_VLAN_FID_SHIFT
) &
512 RTL8366S_VLAN_FID_MASK
;
517 static int rtl8366s_set_vlan_mc(struct rtl8366_smi
*smi
, u32 index
,
518 const struct rtl8366_vlan_mc
*vlanmc
)
524 if (index
>= RTL8366S_NUM_VLANS
||
525 vlanmc
->vid
>= RTL8366S_NUM_VIDS
||
526 vlanmc
->priority
> RTL8366S_PRIORITYMAX
||
527 vlanmc
->member
> RTL8366S_VLAN_MEMBER_MASK
||
528 vlanmc
->untag
> RTL8366S_VLAN_UNTAG_MASK
||
529 vlanmc
->fid
> RTL8366S_FIDMAX
)
532 data
[0] = (vlanmc
->vid
& RTL8366S_VLAN_VID_MASK
) |
533 ((vlanmc
->priority
& RTL8366S_VLAN_PRIORITY_MASK
) <<
534 RTL8366S_VLAN_PRIORITY_SHIFT
);
535 data
[1] = (vlanmc
->member
& RTL8366S_VLAN_MEMBER_MASK
) |
536 ((vlanmc
->untag
& RTL8366S_VLAN_UNTAG_MASK
) <<
537 RTL8366S_VLAN_UNTAG_SHIFT
) |
538 ((vlanmc
->fid
& RTL8366S_VLAN_FID_MASK
) <<
539 RTL8366S_VLAN_FID_SHIFT
);
541 for (i
= 0; i
< 2; i
++) {
542 err
= rtl8366_smi_write_reg(smi
,
543 RTL8366S_VLAN_MC_BASE(index
) + i
,
552 static int rtl8366s_get_mc_index(struct rtl8366_smi
*smi
, int port
, int *val
)
557 if (port
>= RTL8366S_NUM_PORTS
)
560 err
= rtl8366_smi_read_reg(smi
, RTL8366S_PORT_VLAN_CTRL_REG(port
),
565 *val
= (data
>> RTL8366S_PORT_VLAN_CTRL_SHIFT(port
)) &
566 RTL8366S_PORT_VLAN_CTRL_MASK
;
571 static int rtl8366s_set_mc_index(struct rtl8366_smi
*smi
, int port
, int index
)
573 if (port
>= RTL8366S_NUM_PORTS
|| index
>= RTL8366S_NUM_VLANS
)
576 return rtl8366_smi_rmwr(smi
, RTL8366S_PORT_VLAN_CTRL_REG(port
),
577 RTL8366S_PORT_VLAN_CTRL_MASK
<<
578 RTL8366S_PORT_VLAN_CTRL_SHIFT(port
),
579 (index
& RTL8366S_PORT_VLAN_CTRL_MASK
) <<
580 RTL8366S_PORT_VLAN_CTRL_SHIFT(port
));
583 static int rtl8366s_enable_vlan(struct rtl8366_smi
*smi
, int enable
)
585 return rtl8366_smi_rmwr(smi
, RTL8366S_SGCR
, RTL8366S_SGCR_EN_VLAN
,
586 (enable
) ? RTL8366S_SGCR_EN_VLAN
: 0);
589 static int rtl8366s_enable_vlan4k(struct rtl8366_smi
*smi
, int enable
)
591 return rtl8366_smi_rmwr(smi
, RTL8366S_VLAN_TB_CTRL_REG
,
592 1, (enable
) ? 1 : 0);
595 static int rtl8366s_is_vlan_valid(struct rtl8366_smi
*smi
, unsigned vlan
)
597 unsigned max
= RTL8366S_NUM_VLANS
;
599 if (smi
->vlan4k_enabled
)
600 max
= RTL8366S_NUM_VIDS
- 1;
602 if (vlan
== 0 || vlan
>= max
)
608 static int rtl8366s_enable_port(struct rtl8366_smi
*smi
, int port
, int enable
)
610 return rtl8366_smi_rmwr(smi
, RTL8366S_PECR
, (1 << port
),
611 (enable
) ? 0 : (1 << port
));
614 static int rtl8366s_sw_reset_mibs(struct switch_dev
*dev
,
615 const struct switch_attr
*attr
,
616 struct switch_val
*val
)
618 struct rtl8366_smi
*smi
= sw_to_rtl8366_smi(dev
);
620 return rtl8366_smi_rmwr(smi
, RTL8366S_MIB_CTRL_REG
, 0, (1 << 2));
623 static int rtl8366s_sw_get_blinkrate(struct switch_dev
*dev
,
624 const struct switch_attr
*attr
,
625 struct switch_val
*val
)
627 struct rtl8366_smi
*smi
= sw_to_rtl8366_smi(dev
);
630 rtl8366_smi_read_reg(smi
, RTL8366S_LED_BLINKRATE_REG
, &data
);
632 val
->value
.i
= (data
& (RTL8366S_LED_BLINKRATE_MASK
));
637 static int rtl8366s_sw_set_blinkrate(struct switch_dev
*dev
,
638 const struct switch_attr
*attr
,
639 struct switch_val
*val
)
641 struct rtl8366_smi
*smi
= sw_to_rtl8366_smi(dev
);
643 if (val
->value
.i
>= 6)
646 return rtl8366_smi_rmwr(smi
, RTL8366S_LED_BLINKRATE_REG
,
647 RTL8366S_LED_BLINKRATE_MASK
,
651 static int rtl8366s_sw_get_learning_enable(struct switch_dev
*dev
,
652 const struct switch_attr
*attr
,
653 struct switch_val
*val
)
655 struct rtl8366_smi
*smi
= sw_to_rtl8366_smi(dev
);
658 rtl8366_smi_read_reg(smi
,RTL8366S_SSCR0
, &data
);
659 val
->value
.i
= !data
;
665 static int rtl8366s_sw_set_learning_enable(struct switch_dev
*dev
,
666 const struct switch_attr
*attr
,
667 struct switch_val
*val
)
669 struct rtl8366_smi
*smi
= sw_to_rtl8366_smi(dev
);
674 portmask
= RTL8366S_PORT_ALL
;
676 /* set learning for all ports */
677 REG_WR(smi
, RTL8366S_SSCR0
, portmask
);
679 /* set auto ageing for all ports */
680 REG_WR(smi
, RTL8366S_SSCR1
, portmask
);
686 static const char *rtl8366s_speed_str(unsigned speed
)
700 static int rtl8366s_sw_get_port_link(struct switch_dev
*dev
,
701 const struct switch_attr
*attr
,
702 struct switch_val
*val
)
704 struct rtl8366_smi
*smi
= sw_to_rtl8366_smi(dev
);
705 u32 len
= 0, data
= 0;
707 if (val
->port_vlan
>= RTL8366S_NUM_PORTS
)
710 memset(smi
->buf
, '\0', sizeof(smi
->buf
));
711 rtl8366_smi_read_reg(smi
, RTL8366S_PORT_LINK_STATUS_BASE
+
712 (val
->port_vlan
/ 2), &data
);
714 if (val
->port_vlan
% 2)
717 if (data
& RTL8366S_PORT_STATUS_LINK_MASK
) {
718 len
= snprintf(smi
->buf
, sizeof(smi
->buf
),
719 "port:%d link:up speed:%s %s-duplex %s%s%s",
721 rtl8366s_speed_str(data
&
722 RTL8366S_PORT_STATUS_SPEED_MASK
),
723 (data
& RTL8366S_PORT_STATUS_DUPLEX_MASK
) ?
725 (data
& RTL8366S_PORT_STATUS_TXPAUSE_MASK
) ?
727 (data
& RTL8366S_PORT_STATUS_RXPAUSE_MASK
) ?
729 (data
& RTL8366S_PORT_STATUS_AN_MASK
) ?
732 len
= snprintf(smi
->buf
, sizeof(smi
->buf
), "port:%d link: down",
736 val
->value
.s
= smi
->buf
;
742 static int rtl8366s_sw_set_port_led(struct switch_dev
*dev
,
743 const struct switch_attr
*attr
,
744 struct switch_val
*val
)
746 struct rtl8366_smi
*smi
= sw_to_rtl8366_smi(dev
);
751 if (val
->port_vlan
>= RTL8366S_NUM_PORTS
||
752 (1 << val
->port_vlan
) == RTL8366S_PORT_UNKNOWN
)
755 if (val
->port_vlan
== RTL8366S_PORT_NUM_CPU
) {
756 reg
= RTL8366S_LED_BLINKRATE_REG
;
758 data
= val
->value
.i
<< 4;
760 reg
= RTL8366S_LED_CTRL_REG
;
761 mask
= 0xF << (val
->port_vlan
* 4),
762 data
= val
->value
.i
<< (val
->port_vlan
* 4);
765 return rtl8366_smi_rmwr(smi
, reg
, mask
, data
);
768 static int rtl8366s_sw_get_port_led(struct switch_dev
*dev
,
769 const struct switch_attr
*attr
,
770 struct switch_val
*val
)
772 struct rtl8366_smi
*smi
= sw_to_rtl8366_smi(dev
);
775 if (val
->port_vlan
>= RTL8366S_NUM_LEDGROUPS
)
778 rtl8366_smi_read_reg(smi
, RTL8366S_LED_CTRL_REG
, &data
);
779 val
->value
.i
= (data
>> (val
->port_vlan
* 4)) & 0x000F;
784 static int rtl8366s_sw_reset_port_mibs(struct switch_dev
*dev
,
785 const struct switch_attr
*attr
,
786 struct switch_val
*val
)
788 struct rtl8366_smi
*smi
= sw_to_rtl8366_smi(dev
);
790 if (val
->port_vlan
>= RTL8366S_NUM_PORTS
)
794 return rtl8366_smi_rmwr(smi
, RTL8366S_MIB_CTRL_REG
,
795 0, (1 << (val
->port_vlan
+ 3)));
798 static int rtl8366s_sw_reset_switch(struct switch_dev
*dev
)
800 struct rtl8366_smi
*smi
= sw_to_rtl8366_smi(dev
);
803 err
= rtl8366s_reset_chip(smi
);
807 err
= rtl8366s_hw_init(smi
);
811 return rtl8366_reset_vlan(smi
);
814 static struct switch_attr rtl8366s_globals
[] = {
816 .type
= SWITCH_TYPE_INT
,
817 .name
= "enable_learning",
818 .description
= "Enable learning, enable aging",
819 .set
= rtl8366s_sw_set_learning_enable
,
820 .get
= rtl8366s_sw_get_learning_enable
,
823 .type
= SWITCH_TYPE_INT
,
824 .name
= "enable_vlan",
825 .description
= "Enable VLAN mode",
826 .set
= rtl8366_sw_set_vlan_enable
,
827 .get
= rtl8366_sw_get_vlan_enable
,
831 .type
= SWITCH_TYPE_INT
,
832 .name
= "enable_vlan4k",
833 .description
= "Enable VLAN 4K mode",
834 .set
= rtl8366_sw_set_vlan_enable
,
835 .get
= rtl8366_sw_get_vlan_enable
,
839 .type
= SWITCH_TYPE_NOVAL
,
840 .name
= "reset_mibs",
841 .description
= "Reset all MIB counters",
842 .set
= rtl8366s_sw_reset_mibs
,
844 .type
= SWITCH_TYPE_INT
,
846 .description
= "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms,"
847 " 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)",
848 .set
= rtl8366s_sw_set_blinkrate
,
849 .get
= rtl8366s_sw_get_blinkrate
,
854 static struct switch_attr rtl8366s_port
[] = {
856 .type
= SWITCH_TYPE_STRING
,
858 .description
= "Get port link information",
861 .get
= rtl8366s_sw_get_port_link
,
863 .type
= SWITCH_TYPE_NOVAL
,
865 .description
= "Reset single port MIB counters",
866 .set
= rtl8366s_sw_reset_port_mibs
,
868 .type
= SWITCH_TYPE_STRING
,
870 .description
= "Get MIB counters for port",
873 .get
= rtl8366_sw_get_port_mib
,
875 .type
= SWITCH_TYPE_INT
,
877 .description
= "Get/Set port group (0 - 3) led mode (0 - 15)",
879 .set
= rtl8366s_sw_set_port_led
,
880 .get
= rtl8366s_sw_get_port_led
,
884 static struct switch_attr rtl8366s_vlan
[] = {
886 .type
= SWITCH_TYPE_STRING
,
888 .description
= "Get vlan information",
891 .get
= rtl8366_sw_get_vlan_info
,
893 .type
= SWITCH_TYPE_INT
,
895 .description
= "Get/Set vlan FID",
896 .max
= RTL8366S_FIDMAX
,
897 .set
= rtl8366_sw_set_vlan_fid
,
898 .get
= rtl8366_sw_get_vlan_fid
,
902 static const struct switch_dev_ops rtl8366_ops
= {
904 .attr
= rtl8366s_globals
,
905 .n_attr
= ARRAY_SIZE(rtl8366s_globals
),
908 .attr
= rtl8366s_port
,
909 .n_attr
= ARRAY_SIZE(rtl8366s_port
),
912 .attr
= rtl8366s_vlan
,
913 .n_attr
= ARRAY_SIZE(rtl8366s_vlan
),
916 .get_vlan_ports
= rtl8366_sw_get_vlan_ports
,
917 .set_vlan_ports
= rtl8366_sw_set_vlan_ports
,
918 .get_port_pvid
= rtl8366_sw_get_port_pvid
,
919 .set_port_pvid
= rtl8366_sw_set_port_pvid
,
920 .reset_switch
= rtl8366s_sw_reset_switch
,
923 static int rtl8366s_switch_init(struct rtl8366_smi
*smi
)
925 struct switch_dev
*dev
= &smi
->sw_dev
;
928 dev
->name
= "RTL8366S";
929 dev
->cpu_port
= RTL8366S_PORT_NUM_CPU
;
930 dev
->ports
= RTL8366S_NUM_PORTS
;
931 dev
->vlans
= RTL8366S_NUM_VIDS
;
932 dev
->ops
= &rtl8366_ops
;
933 dev
->devname
= dev_name(smi
->parent
);
935 err
= register_switch(dev
, NULL
);
937 dev_err(smi
->parent
, "switch registration failed\n");
942 static void rtl8366s_switch_cleanup(struct rtl8366_smi
*smi
)
944 unregister_switch(&smi
->sw_dev
);
947 static int rtl8366s_mii_read(struct mii_bus
*bus
, int addr
, int reg
)
949 struct rtl8366_smi
*smi
= bus
->priv
;
953 err
= rtl8366s_read_phy_reg(smi
, addr
, 0, reg
, &val
);
960 static int rtl8366s_mii_write(struct mii_bus
*bus
, int addr
, int reg
, u16 val
)
962 struct rtl8366_smi
*smi
= bus
->priv
;
966 err
= rtl8366s_write_phy_reg(smi
, addr
, 0, reg
, val
);
968 (void) rtl8366s_read_phy_reg(smi
, addr
, 0, reg
, &t
);
973 static int rtl8366s_mii_bus_match(struct mii_bus
*bus
)
975 return (bus
->read
== rtl8366s_mii_read
&&
976 bus
->write
== rtl8366s_mii_write
);
979 static int rtl8366s_setup(struct rtl8366_smi
*smi
)
983 ret
= rtl8366s_reset_chip(smi
);
987 ret
= rtl8366s_hw_init(smi
);
991 static int rtl8366s_detect(struct rtl8366_smi
*smi
)
997 ret
= rtl8366_smi_read_reg(smi
, RTL8366S_CHIP_ID_REG
, &chip_id
);
999 dev_err(smi
->parent
, "unable to read chip id\n");
1004 case RTL8366S_CHIP_ID_8366
:
1007 dev_err(smi
->parent
, "unknown chip id (%04x)\n", chip_id
);
1011 ret
= rtl8366_smi_read_reg(smi
, RTL8366S_CHIP_VERSION_CTRL_REG
,
1014 dev_err(smi
->parent
, "unable to read chip version\n");
1018 dev_info(smi
->parent
, "RTL%04x ver. %u chip found\n",
1019 chip_id
, chip_ver
& RTL8366S_CHIP_VERSION_MASK
);
1024 static struct rtl8366_smi_ops rtl8366s_smi_ops
= {
1025 .detect
= rtl8366s_detect
,
1026 .setup
= rtl8366s_setup
,
1028 .mii_read
= rtl8366s_mii_read
,
1029 .mii_write
= rtl8366s_mii_write
,
1031 .get_vlan_mc
= rtl8366s_get_vlan_mc
,
1032 .set_vlan_mc
= rtl8366s_set_vlan_mc
,
1033 .get_vlan_4k
= rtl8366s_get_vlan_4k
,
1034 .set_vlan_4k
= rtl8366s_set_vlan_4k
,
1035 .get_mc_index
= rtl8366s_get_mc_index
,
1036 .set_mc_index
= rtl8366s_set_mc_index
,
1037 .get_mib_counter
= rtl8366_get_mib_counter
,
1038 .is_vlan_valid
= rtl8366s_is_vlan_valid
,
1039 .enable_vlan
= rtl8366s_enable_vlan
,
1040 .enable_vlan4k
= rtl8366s_enable_vlan4k
,
1041 .enable_port
= rtl8366s_enable_port
,
1044 static int __devinit
rtl8366s_probe(struct platform_device
*pdev
)
1046 static int rtl8366_smi_version_printed
;
1047 struct rtl8366s_platform_data
*pdata
;
1048 struct rtl8366_smi
*smi
;
1051 if (!rtl8366_smi_version_printed
++)
1052 printk(KERN_NOTICE RTL8366S_DRIVER_DESC
1053 " version " RTL8366S_DRIVER_VER
"\n");
1055 pdata
= pdev
->dev
.platform_data
;
1057 dev_err(&pdev
->dev
, "no platform data specified\n");
1062 smi
= rtl8366_smi_alloc(&pdev
->dev
);
1068 smi
->gpio_sda
= pdata
->gpio_sda
;
1069 smi
->gpio_sck
= pdata
->gpio_sck
;
1070 smi
->ops
= &rtl8366s_smi_ops
;
1071 smi
->cpu_port
= RTL8366S_PORT_NUM_CPU
;
1072 smi
->num_ports
= RTL8366S_NUM_PORTS
;
1073 smi
->num_vlan_mc
= RTL8366S_NUM_VLANS
;
1074 smi
->mib_counters
= rtl8366s_mib_counters
;
1075 smi
->num_mib_counters
= ARRAY_SIZE(rtl8366s_mib_counters
);
1077 err
= rtl8366_smi_init(smi
);
1081 platform_set_drvdata(pdev
, smi
);
1083 err
= rtl8366s_switch_init(smi
);
1085 goto err_clear_drvdata
;
1090 platform_set_drvdata(pdev
, NULL
);
1091 rtl8366_smi_cleanup(smi
);
1098 static int rtl8366s_phy_config_init(struct phy_device
*phydev
)
1100 if (!rtl8366s_mii_bus_match(phydev
->bus
))
1106 static int rtl8366s_phy_config_aneg(struct phy_device
*phydev
)
1108 /* phy 4 might be connected to a second mac, allow aneg config */
1109 if (phydev
->addr
== RTL8366S_PHY_WAN
)
1110 return genphy_config_aneg(phydev
);
1115 static struct phy_driver rtl8366s_phy_driver
= {
1116 .phy_id
= 0x001cc960,
1117 .name
= "Realtek RTL8366S",
1118 .phy_id_mask
= 0x1ffffff0,
1119 .features
= PHY_GBIT_FEATURES
,
1120 .config_aneg
= rtl8366s_phy_config_aneg
,
1121 .config_init
= rtl8366s_phy_config_init
,
1122 .read_status
= genphy_read_status
,
1124 .owner
= THIS_MODULE
,
1128 static int __devexit
rtl8366s_remove(struct platform_device
*pdev
)
1130 struct rtl8366_smi
*smi
= platform_get_drvdata(pdev
);
1133 rtl8366s_switch_cleanup(smi
);
1134 platform_set_drvdata(pdev
, NULL
);
1135 rtl8366_smi_cleanup(smi
);
1142 static struct platform_driver rtl8366s_driver
= {
1144 .name
= RTL8366S_DRIVER_NAME
,
1145 .owner
= THIS_MODULE
,
1147 .probe
= rtl8366s_probe
,
1148 .remove
= __devexit_p(rtl8366s_remove
),
1151 static int __init
rtl8366s_module_init(void)
1154 ret
= platform_driver_register(&rtl8366s_driver
);
1158 ret
= phy_driver_register(&rtl8366s_phy_driver
);
1160 goto err_platform_unregister
;
1164 err_platform_unregister
:
1165 platform_driver_unregister(&rtl8366s_driver
);
1168 module_init(rtl8366s_module_init
);
1170 static void __exit
rtl8366s_module_exit(void)
1172 phy_driver_unregister(&rtl8366s_phy_driver
);
1173 platform_driver_unregister(&rtl8366s_driver
);
1175 module_exit(rtl8366s_module_exit
);
1177 MODULE_DESCRIPTION(RTL8366S_DRIVER_DESC
);
1178 MODULE_VERSION(RTL8366S_DRIVER_VER
);
1179 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1180 MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>");
1181 MODULE_LICENSE("GPL v2");
1182 MODULE_ALIAS("platform:" RTL8366S_DRIVER_NAME
);