2 * Platform driver for the Realtek RTL8366S ethernet switch
4 * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/platform_device.h>
16 #include <linux/delay.h>
17 #include <linux/skbuff.h>
18 #include <linux/rtl8366s.h>
20 #include "rtl8366_smi.h"
22 #define RTL8366S_DRIVER_DESC "Realtek RTL8366S ethernet switch driver"
23 #define RTL8366S_DRIVER_VER "0.2.2"
25 #define RTL8366S_PHY_NO_MAX 4
26 #define RTL8366S_PHY_PAGE_MAX 7
27 #define RTL8366S_PHY_ADDR_MAX 31
29 /* Switch Global Configuration register */
30 #define RTL8366S_SGCR 0x0000
31 #define RTL8366S_SGCR_EN_BC_STORM_CTRL BIT(0)
32 #define RTL8366S_SGCR_MAX_LENGTH(_x) (_x << 4)
33 #define RTL8366S_SGCR_MAX_LENGTH_MASK RTL8366S_SGCR_MAX_LENGTH(0x3)
34 #define RTL8366S_SGCR_MAX_LENGTH_1522 RTL8366S_SGCR_MAX_LENGTH(0x0)
35 #define RTL8366S_SGCR_MAX_LENGTH_1536 RTL8366S_SGCR_MAX_LENGTH(0x1)
36 #define RTL8366S_SGCR_MAX_LENGTH_1552 RTL8366S_SGCR_MAX_LENGTH(0x2)
37 #define RTL8366S_SGCR_MAX_LENGTH_16000 RTL8366S_SGCR_MAX_LENGTH(0x3)
38 #define RTL8366S_SGCR_EN_VLAN BIT(13)
40 /* Port Enable Control register */
41 #define RTL8366S_PECR 0x0001
43 /* Switch Security Control registers */
44 #define RTL8366S_SSCR0 0x0002
45 #define RTL8366S_SSCR1 0x0003
46 #define RTL8366S_SSCR2 0x0004
47 #define RTL8366S_SSCR2_DROP_UNKNOWN_DA BIT(0)
49 #define RTL8366S_RESET_CTRL_REG 0x0100
50 #define RTL8366S_CHIP_CTRL_RESET_HW 1
51 #define RTL8366S_CHIP_CTRL_RESET_SW (1 << 1)
53 #define RTL8366S_CHIP_VERSION_CTRL_REG 0x0104
54 #define RTL8366S_CHIP_VERSION_MASK 0xf
55 #define RTL8366S_CHIP_ID_REG 0x0105
56 #define RTL8366S_CHIP_ID_8366 0x8366
58 /* PHY registers control */
59 #define RTL8366S_PHY_ACCESS_CTRL_REG 0x8028
60 #define RTL8366S_PHY_ACCESS_DATA_REG 0x8029
62 #define RTL8366S_PHY_CTRL_READ 1
63 #define RTL8366S_PHY_CTRL_WRITE 0
65 #define RTL8366S_PHY_REG_MASK 0x1f
66 #define RTL8366S_PHY_PAGE_OFFSET 5
67 #define RTL8366S_PHY_PAGE_MASK (0x7 << 5)
68 #define RTL8366S_PHY_NO_OFFSET 9
69 #define RTL8366S_PHY_NO_MASK (0x1f << 9)
71 /* LED control registers */
72 #define RTL8366S_LED_BLINKRATE_REG 0x0420
73 #define RTL8366S_LED_BLINKRATE_BIT 0
74 #define RTL8366S_LED_BLINKRATE_MASK 0x0007
76 #define RTL8366S_LED_CTRL_REG 0x0421
77 #define RTL8366S_LED_0_1_CTRL_REG 0x0422
78 #define RTL8366S_LED_2_3_CTRL_REG 0x0423
80 #define RTL8366S_MIB_COUNT 33
81 #define RTL8366S_GLOBAL_MIB_COUNT 1
82 #define RTL8366S_MIB_COUNTER_PORT_OFFSET 0x0040
83 #define RTL8366S_MIB_COUNTER_BASE 0x1000
84 #define RTL8366S_MIB_COUNTER_PORT_OFFSET2 0x0008
85 #define RTL8366S_MIB_COUNTER_BASE2 0x1180
86 #define RTL8366S_MIB_CTRL_REG 0x11F0
87 #define RTL8366S_MIB_CTRL_USER_MASK 0x01FF
88 #define RTL8366S_MIB_CTRL_BUSY_MASK 0x0001
89 #define RTL8366S_MIB_CTRL_RESET_MASK 0x0002
91 #define RTL8366S_MIB_CTRL_GLOBAL_RESET_MASK 0x0004
92 #define RTL8366S_MIB_CTRL_PORT_RESET_BIT 0x0003
93 #define RTL8366S_MIB_CTRL_PORT_RESET_MASK 0x01FC
96 #define RTL8366S_PORT_VLAN_CTRL_BASE 0x0058
97 #define RTL8366S_PORT_VLAN_CTRL_REG(_p) \
98 (RTL8366S_PORT_VLAN_CTRL_BASE + (_p) / 4)
99 #define RTL8366S_PORT_VLAN_CTRL_MASK 0xf
100 #define RTL8366S_PORT_VLAN_CTRL_SHIFT(_p) (4 * ((_p) % 4))
103 #define RTL8366S_VLAN_TABLE_READ_BASE 0x018B
104 #define RTL8366S_VLAN_TABLE_WRITE_BASE 0x0185
106 #define RTL8366S_VLAN_TB_CTRL_REG 0x010F
108 #define RTL8366S_TABLE_ACCESS_CTRL_REG 0x0180
109 #define RTL8366S_TABLE_VLAN_READ_CTRL 0x0E01
110 #define RTL8366S_TABLE_VLAN_WRITE_CTRL 0x0F01
112 #define RTL8366S_VLAN_MC_BASE(_x) (0x0016 + (_x) * 2)
114 #define RTL8366S_VLAN_MEMBERINGRESS_REG 0x0379
116 #define RTL8366S_PORT_LINK_STATUS_BASE 0x0060
117 #define RTL8366S_PORT_STATUS_SPEED_MASK 0x0003
118 #define RTL8366S_PORT_STATUS_DUPLEX_MASK 0x0004
119 #define RTL8366S_PORT_STATUS_LINK_MASK 0x0010
120 #define RTL8366S_PORT_STATUS_TXPAUSE_MASK 0x0020
121 #define RTL8366S_PORT_STATUS_RXPAUSE_MASK 0x0040
122 #define RTL8366S_PORT_STATUS_AN_MASK 0x0080
125 #define RTL8366S_PORT_NUM_CPU 5
126 #define RTL8366S_NUM_PORTS 6
127 #define RTL8366S_NUM_VLANS 16
128 #define RTL8366S_NUM_LEDGROUPS 4
129 #define RTL8366S_NUM_VIDS 4096
130 #define RTL8366S_PRIORITYMAX 7
131 #define RTL8366S_FIDMAX 7
134 #define RTL8366S_PORT_1 (1 << 0) /* In userspace port 0 */
135 #define RTL8366S_PORT_2 (1 << 1) /* In userspace port 1 */
136 #define RTL8366S_PORT_3 (1 << 2) /* In userspace port 2 */
137 #define RTL8366S_PORT_4 (1 << 3) /* In userspace port 3 */
139 #define RTL8366S_PORT_UNKNOWN (1 << 4) /* No known connection */
140 #define RTL8366S_PORT_CPU (1 << 5) /* CPU port */
142 #define RTL8366S_PORT_ALL (RTL8366S_PORT_1 | \
146 RTL8366S_PORT_UNKNOWN | \
149 #define RTL8366S_PORT_ALL_BUT_CPU (RTL8366S_PORT_1 | \
153 RTL8366S_PORT_UNKNOWN)
155 #define RTL8366S_PORT_ALL_EXTERNAL (RTL8366S_PORT_1 | \
160 #define RTL8366S_PORT_ALL_INTERNAL (RTL8366S_PORT_UNKNOWN | \
163 #define RTL8366S_VLAN_VID_MASK 0xfff
164 #define RTL8366S_VLAN_PRIORITY_SHIFT 12
165 #define RTL8366S_VLAN_PRIORITY_MASK 0x7
166 #define RTL8366S_VLAN_MEMBER_MASK 0x3f
167 #define RTL8366S_VLAN_UNTAG_SHIFT 6
168 #define RTL8366S_VLAN_UNTAG_MASK 0x3f
169 #define RTL8366S_VLAN_FID_SHIFT 12
170 #define RTL8366S_VLAN_FID_MASK 0x7
172 static struct rtl8366_mib_counter rtl8366s_mib_counters
[] = {
173 { 0, 0, 4, "IfInOctets" },
174 { 0, 4, 4, "EtherStatsOctets" },
175 { 0, 8, 2, "EtherStatsUnderSizePkts" },
176 { 0, 10, 2, "EtherFragments" },
177 { 0, 12, 2, "EtherStatsPkts64Octets" },
178 { 0, 14, 2, "EtherStatsPkts65to127Octets" },
179 { 0, 16, 2, "EtherStatsPkts128to255Octets" },
180 { 0, 18, 2, "EtherStatsPkts256to511Octets" },
181 { 0, 20, 2, "EtherStatsPkts512to1023Octets" },
182 { 0, 22, 2, "EtherStatsPkts1024to1518Octets" },
183 { 0, 24, 2, "EtherOversizeStats" },
184 { 0, 26, 2, "EtherStatsJabbers" },
185 { 0, 28, 2, "IfInUcastPkts" },
186 { 0, 30, 2, "EtherStatsMulticastPkts" },
187 { 0, 32, 2, "EtherStatsBroadcastPkts" },
188 { 0, 34, 2, "EtherStatsDropEvents" },
189 { 0, 36, 2, "Dot3StatsFCSErrors" },
190 { 0, 38, 2, "Dot3StatsSymbolErrors" },
191 { 0, 40, 2, "Dot3InPauseFrames" },
192 { 0, 42, 2, "Dot3ControlInUnknownOpcodes" },
193 { 0, 44, 4, "IfOutOctets" },
194 { 0, 48, 2, "Dot3StatsSingleCollisionFrames" },
195 { 0, 50, 2, "Dot3StatMultipleCollisionFrames" },
196 { 0, 52, 2, "Dot3sDeferredTransmissions" },
197 { 0, 54, 2, "Dot3StatsLateCollisions" },
198 { 0, 56, 2, "EtherStatsCollisions" },
199 { 0, 58, 2, "Dot3StatsExcessiveCollisions" },
200 { 0, 60, 2, "Dot3OutPauseFrames" },
201 { 0, 62, 2, "Dot1dBasePortDelayExceededDiscards" },
204 * The following counters are accessible at a different
207 { 1, 0, 2, "Dot1dTpPortInDiscards" },
208 { 1, 2, 2, "IfOutUcastPkts" },
209 { 1, 4, 2, "IfOutMulticastPkts" },
210 { 1, 6, 2, "IfOutBroadcastPkts" },
213 #define REG_WR(_smi, _reg, _val) \
215 err = rtl8366_smi_write_reg(_smi, _reg, _val); \
220 #define REG_RMW(_smi, _reg, _mask, _val) \
222 err = rtl8366_smi_rmwr(_smi, _reg, _mask, _val); \
227 static int rtl8366s_reset_chip(struct rtl8366_smi
*smi
)
232 rtl8366_smi_write_reg(smi
, RTL8366S_RESET_CTRL_REG
,
233 RTL8366S_CHIP_CTRL_RESET_HW
);
236 if (rtl8366_smi_read_reg(smi
, RTL8366S_RESET_CTRL_REG
, &data
))
239 if (!(data
& RTL8366S_CHIP_CTRL_RESET_HW
))
244 printk("Timeout waiting for the switch to reset\n");
251 static int rtl8366s_hw_init(struct rtl8366_smi
*smi
)
255 /* set maximum packet length to 1536 bytes */
256 REG_RMW(smi
, RTL8366S_SGCR
, RTL8366S_SGCR_MAX_LENGTH_MASK
,
257 RTL8366S_SGCR_MAX_LENGTH_1536
);
259 /* enable all ports */
260 REG_WR(smi
, RTL8366S_PECR
, 0);
262 /* disable learning for all ports */
263 REG_WR(smi
, RTL8366S_SSCR0
, RTL8366S_PORT_ALL
);
265 /* disable auto ageing for all ports */
266 REG_WR(smi
, RTL8366S_SSCR1
, RTL8366S_PORT_ALL
);
269 * discard VLAN tagged packets if the port is not a member of
270 * the VLAN with which the packets is associated.
272 REG_WR(smi
, RTL8366S_VLAN_MEMBERINGRESS_REG
, RTL8366S_PORT_ALL
);
274 /* don't drop packets whose DA has not been learned */
275 REG_RMW(smi
, RTL8366S_SSCR2
, RTL8366S_SSCR2_DROP_UNKNOWN_DA
, 0);
280 static int rtl8366s_read_phy_reg(struct rtl8366_smi
*smi
,
281 u32 phy_no
, u32 page
, u32 addr
, u32
*data
)
286 if (phy_no
> RTL8366S_PHY_NO_MAX
)
289 if (page
> RTL8366S_PHY_PAGE_MAX
)
292 if (addr
> RTL8366S_PHY_ADDR_MAX
)
295 ret
= rtl8366_smi_write_reg(smi
, RTL8366S_PHY_ACCESS_CTRL_REG
,
296 RTL8366S_PHY_CTRL_READ
);
300 reg
= 0x8000 | (1 << (phy_no
+ RTL8366S_PHY_NO_OFFSET
)) |
301 ((page
<< RTL8366S_PHY_PAGE_OFFSET
) & RTL8366S_PHY_PAGE_MASK
) |
302 (addr
& RTL8366S_PHY_REG_MASK
);
304 ret
= rtl8366_smi_write_reg(smi
, reg
, 0);
308 ret
= rtl8366_smi_read_reg(smi
, RTL8366S_PHY_ACCESS_DATA_REG
, data
);
315 static int rtl8366s_write_phy_reg(struct rtl8366_smi
*smi
,
316 u32 phy_no
, u32 page
, u32 addr
, u32 data
)
321 if (phy_no
> RTL8366S_PHY_NO_MAX
)
324 if (page
> RTL8366S_PHY_PAGE_MAX
)
327 if (addr
> RTL8366S_PHY_ADDR_MAX
)
330 ret
= rtl8366_smi_write_reg(smi
, RTL8366S_PHY_ACCESS_CTRL_REG
,
331 RTL8366S_PHY_CTRL_WRITE
);
335 reg
= 0x8000 | (1 << (phy_no
+ RTL8366S_PHY_NO_OFFSET
)) |
336 ((page
<< RTL8366S_PHY_PAGE_OFFSET
) & RTL8366S_PHY_PAGE_MASK
) |
337 (addr
& RTL8366S_PHY_REG_MASK
);
339 ret
= rtl8366_smi_write_reg(smi
, reg
, data
);
346 static int rtl8366_get_mib_counter(struct rtl8366_smi
*smi
, int counter
,
347 int port
, unsigned long long *val
)
354 if (port
> RTL8366S_NUM_PORTS
|| counter
>= RTL8366S_MIB_COUNT
)
357 switch (rtl8366s_mib_counters
[counter
].base
) {
359 addr
= RTL8366S_MIB_COUNTER_BASE
+
360 RTL8366S_MIB_COUNTER_PORT_OFFSET
* port
;
364 addr
= RTL8366S_MIB_COUNTER_BASE2
+
365 RTL8366S_MIB_COUNTER_PORT_OFFSET2
* port
;
372 addr
+= rtl8366s_mib_counters
[counter
].offset
;
375 * Writing access counter address first
376 * then ASIC will prepare 64bits counter wait for being retrived
378 data
= 0; /* writing data will be discard by ASIC */
379 err
= rtl8366_smi_write_reg(smi
, addr
, data
);
383 /* read MIB control register */
384 err
= rtl8366_smi_read_reg(smi
, RTL8366S_MIB_CTRL_REG
, &data
);
388 if (data
& RTL8366S_MIB_CTRL_BUSY_MASK
)
391 if (data
& RTL8366S_MIB_CTRL_RESET_MASK
)
395 for (i
= rtl8366s_mib_counters
[counter
].length
; i
> 0; i
--) {
396 err
= rtl8366_smi_read_reg(smi
, addr
+ (i
- 1), &data
);
400 mibvalue
= (mibvalue
<< 16) | (data
& 0xFFFF);
407 static int rtl8366s_get_vlan_4k(struct rtl8366_smi
*smi
, u32 vid
,
408 struct rtl8366_vlan_4k
*vlan4k
)
414 memset(vlan4k
, '\0', sizeof(struct rtl8366_vlan_4k
));
416 if (vid
>= RTL8366S_NUM_VIDS
)
420 err
= rtl8366_smi_write_reg(smi
, RTL8366S_VLAN_TABLE_WRITE_BASE
,
421 vid
& RTL8366S_VLAN_VID_MASK
);
425 /* write table access control word */
426 err
= rtl8366_smi_write_reg(smi
, RTL8366S_TABLE_ACCESS_CTRL_REG
,
427 RTL8366S_TABLE_VLAN_READ_CTRL
);
431 for (i
= 0; i
< 2; i
++) {
432 err
= rtl8366_smi_read_reg(smi
,
433 RTL8366S_VLAN_TABLE_READ_BASE
+ i
,
440 vlan4k
->untag
= (data
[1] >> RTL8366S_VLAN_UNTAG_SHIFT
) &
441 RTL8366S_VLAN_UNTAG_MASK
;
442 vlan4k
->member
= data
[1] & RTL8366S_VLAN_MEMBER_MASK
;
443 vlan4k
->fid
= (data
[1] >> RTL8366S_VLAN_FID_SHIFT
) &
444 RTL8366S_VLAN_FID_MASK
;
449 static int rtl8366s_set_vlan_4k(struct rtl8366_smi
*smi
,
450 const struct rtl8366_vlan_4k
*vlan4k
)
456 if (vlan4k
->vid
>= RTL8366S_NUM_VIDS
||
457 vlan4k
->member
> RTL8366S_PORT_ALL
||
458 vlan4k
->untag
> RTL8366S_PORT_ALL
||
459 vlan4k
->fid
> RTL8366S_FIDMAX
)
462 data
[0] = vlan4k
->vid
& RTL8366S_VLAN_VID_MASK
;
463 data
[1] = (vlan4k
->member
& RTL8366S_VLAN_MEMBER_MASK
) |
464 ((vlan4k
->untag
& RTL8366S_VLAN_UNTAG_MASK
) <<
465 RTL8366S_VLAN_UNTAG_SHIFT
) |
466 ((vlan4k
->fid
& RTL8366S_VLAN_FID_MASK
) <<
467 RTL8366S_VLAN_FID_SHIFT
);
469 for (i
= 0; i
< 2; i
++) {
470 err
= rtl8366_smi_write_reg(smi
,
471 RTL8366S_VLAN_TABLE_WRITE_BASE
+ i
,
477 /* write table access control word */
478 err
= rtl8366_smi_write_reg(smi
, RTL8366S_TABLE_ACCESS_CTRL_REG
,
479 RTL8366S_TABLE_VLAN_WRITE_CTRL
);
484 static int rtl8366s_get_vlan_mc(struct rtl8366_smi
*smi
, u32 index
,
485 struct rtl8366_vlan_mc
*vlanmc
)
491 memset(vlanmc
, '\0', sizeof(struct rtl8366_vlan_mc
));
493 if (index
>= RTL8366S_NUM_VLANS
)
496 for (i
= 0; i
< 2; i
++) {
497 err
= rtl8366_smi_read_reg(smi
,
498 RTL8366S_VLAN_MC_BASE(index
) + i
,
504 vlanmc
->vid
= data
[0] & RTL8366S_VLAN_VID_MASK
;
505 vlanmc
->priority
= (data
[0] >> RTL8366S_VLAN_PRIORITY_SHIFT
) &
506 RTL8366S_VLAN_PRIORITY_MASK
;
507 vlanmc
->untag
= (data
[1] >> RTL8366S_VLAN_UNTAG_SHIFT
) &
508 RTL8366S_VLAN_UNTAG_MASK
;
509 vlanmc
->member
= data
[1] & RTL8366S_VLAN_MEMBER_MASK
;
510 vlanmc
->fid
= (data
[1] >> RTL8366S_VLAN_FID_SHIFT
) &
511 RTL8366S_VLAN_FID_MASK
;
516 static int rtl8366s_set_vlan_mc(struct rtl8366_smi
*smi
, u32 index
,
517 const struct rtl8366_vlan_mc
*vlanmc
)
523 if (index
>= RTL8366S_NUM_VLANS
||
524 vlanmc
->vid
>= RTL8366S_NUM_VIDS
||
525 vlanmc
->priority
> RTL8366S_PRIORITYMAX
||
526 vlanmc
->member
> RTL8366S_PORT_ALL
||
527 vlanmc
->untag
> RTL8366S_PORT_ALL
||
528 vlanmc
->fid
> RTL8366S_FIDMAX
)
531 data
[0] = (vlanmc
->vid
& RTL8366S_VLAN_VID_MASK
) |
532 ((vlanmc
->priority
& RTL8366S_VLAN_PRIORITY_MASK
) <<
533 RTL8366S_VLAN_PRIORITY_SHIFT
);
534 data
[1] = (vlanmc
->member
& RTL8366S_VLAN_MEMBER_MASK
) |
535 ((vlanmc
->untag
& RTL8366S_VLAN_UNTAG_MASK
) <<
536 RTL8366S_VLAN_UNTAG_SHIFT
) |
537 ((vlanmc
->fid
& RTL8366S_VLAN_FID_MASK
) <<
538 RTL8366S_VLAN_FID_SHIFT
);
540 for (i
= 0; i
< 2; i
++) {
541 err
= rtl8366_smi_write_reg(smi
,
542 RTL8366S_VLAN_MC_BASE(index
) + i
,
551 static int rtl8366s_get_mc_index(struct rtl8366_smi
*smi
, int port
, int *val
)
556 if (port
>= RTL8366S_NUM_PORTS
)
559 err
= rtl8366_smi_read_reg(smi
, RTL8366S_PORT_VLAN_CTRL_REG(port
),
564 *val
= (data
>> RTL8366S_PORT_VLAN_CTRL_SHIFT(port
)) &
565 RTL8366S_PORT_VLAN_CTRL_MASK
;
570 static int rtl8366s_set_mc_index(struct rtl8366_smi
*smi
, int port
, int index
)
572 if (port
>= RTL8366S_NUM_PORTS
|| index
>= RTL8366S_NUM_VLANS
)
575 return rtl8366_smi_rmwr(smi
, RTL8366S_PORT_VLAN_CTRL_REG(port
),
576 RTL8366S_PORT_VLAN_CTRL_MASK
<<
577 RTL8366S_PORT_VLAN_CTRL_SHIFT(port
),
578 (index
& RTL8366S_PORT_VLAN_CTRL_MASK
) <<
579 RTL8366S_PORT_VLAN_CTRL_SHIFT(port
));
582 static int rtl8366s_vlan_set_vlan(struct rtl8366_smi
*smi
, int enable
)
584 return rtl8366_smi_rmwr(smi
, RTL8366S_SGCR
, RTL8366S_SGCR_EN_VLAN
,
585 (enable
) ? RTL8366S_SGCR_EN_VLAN
: 0);
588 static int rtl8366s_vlan_set_4ktable(struct rtl8366_smi
*smi
, int enable
)
590 return rtl8366_smi_rmwr(smi
, RTL8366S_VLAN_TB_CTRL_REG
,
591 1, (enable
) ? 1 : 0);
594 static int rtl8366s_is_vlan_valid(struct rtl8366_smi
*smi
, unsigned vlan
)
596 if (vlan
== 0 || vlan
>= RTL8366S_NUM_VLANS
)
602 static int rtl8366s_sw_reset_mibs(struct switch_dev
*dev
,
603 const struct switch_attr
*attr
,
604 struct switch_val
*val
)
606 struct rtl8366_smi
*smi
= sw_to_rtl8366_smi(dev
);
608 return rtl8366_smi_rmwr(smi
, RTL8366S_MIB_CTRL_REG
, 0, (1 << 2));
611 static int rtl8366s_sw_get_vlan_enable(struct switch_dev
*dev
,
612 const struct switch_attr
*attr
,
613 struct switch_val
*val
)
615 struct rtl8366_smi
*smi
= sw_to_rtl8366_smi(dev
);
618 if (attr
->ofs
== 1) {
619 rtl8366_smi_read_reg(smi
, RTL8366S_SGCR
, &data
);
621 if (data
& RTL8366S_SGCR_EN_VLAN
)
625 } else if (attr
->ofs
== 2) {
626 rtl8366_smi_read_reg(smi
, RTL8366S_VLAN_TB_CTRL_REG
, &data
);
637 static int rtl8366s_sw_get_blinkrate(struct switch_dev
*dev
,
638 const struct switch_attr
*attr
,
639 struct switch_val
*val
)
641 struct rtl8366_smi
*smi
= sw_to_rtl8366_smi(dev
);
644 rtl8366_smi_read_reg(smi
, RTL8366S_LED_BLINKRATE_REG
, &data
);
646 val
->value
.i
= (data
& (RTL8366S_LED_BLINKRATE_MASK
));
651 static int rtl8366s_sw_set_blinkrate(struct switch_dev
*dev
,
652 const struct switch_attr
*attr
,
653 struct switch_val
*val
)
655 struct rtl8366_smi
*smi
= sw_to_rtl8366_smi(dev
);
657 if (val
->value
.i
>= 6)
660 return rtl8366_smi_rmwr(smi
, RTL8366S_LED_BLINKRATE_REG
,
661 RTL8366S_LED_BLINKRATE_MASK
,
665 static int rtl8366s_sw_set_vlan_enable(struct switch_dev
*dev
,
666 const struct switch_attr
*attr
,
667 struct switch_val
*val
)
669 struct rtl8366_smi
*smi
= sw_to_rtl8366_smi(dev
);
672 return rtl8366s_vlan_set_vlan(smi
, val
->value
.i
);
674 return rtl8366s_vlan_set_4ktable(smi
, val
->value
.i
);
677 static const char *rtl8366s_speed_str(unsigned speed
)
691 static int rtl8366s_sw_get_port_link(struct switch_dev
*dev
,
692 const struct switch_attr
*attr
,
693 struct switch_val
*val
)
695 struct rtl8366_smi
*smi
= sw_to_rtl8366_smi(dev
);
696 u32 len
= 0, data
= 0;
698 if (val
->port_vlan
>= RTL8366S_NUM_PORTS
)
701 memset(smi
->buf
, '\0', sizeof(smi
->buf
));
702 rtl8366_smi_read_reg(smi
, RTL8366S_PORT_LINK_STATUS_BASE
+
703 (val
->port_vlan
/ 2), &data
);
705 if (val
->port_vlan
% 2)
708 if (data
& RTL8366S_PORT_STATUS_LINK_MASK
) {
709 len
= snprintf(smi
->buf
, sizeof(smi
->buf
),
710 "port:%d link:up speed:%s %s-duplex %s%s%s",
712 rtl8366s_speed_str(data
&
713 RTL8366S_PORT_STATUS_SPEED_MASK
),
714 (data
& RTL8366S_PORT_STATUS_DUPLEX_MASK
) ?
716 (data
& RTL8366S_PORT_STATUS_TXPAUSE_MASK
) ?
718 (data
& RTL8366S_PORT_STATUS_RXPAUSE_MASK
) ?
720 (data
& RTL8366S_PORT_STATUS_AN_MASK
) ?
723 len
= snprintf(smi
->buf
, sizeof(smi
->buf
), "port:%d link: down",
727 val
->value
.s
= smi
->buf
;
733 static int rtl8366s_sw_get_vlan_info(struct switch_dev
*dev
,
734 const struct switch_attr
*attr
,
735 struct switch_val
*val
)
739 struct rtl8366_vlan_4k vlan4k
;
740 struct rtl8366_smi
*smi
= sw_to_rtl8366_smi(dev
);
741 char *buf
= smi
->buf
;
744 if (!smi
->ops
->is_vlan_valid(smi
, val
->port_vlan
))
747 memset(buf
, '\0', sizeof(smi
->buf
));
749 err
= rtl8366s_get_vlan_4k(smi
, val
->port_vlan
, &vlan4k
);
753 len
+= snprintf(buf
+ len
, sizeof(smi
->buf
) - len
,
754 "VLAN %d: Ports: '", vlan4k
.vid
);
756 for (i
= 0; i
< RTL8366S_NUM_PORTS
; i
++) {
757 if (!(vlan4k
.member
& (1 << i
)))
760 len
+= snprintf(buf
+ len
, sizeof(smi
->buf
) - len
, "%d%s", i
,
761 (vlan4k
.untag
& (1 << i
)) ? "" : "t");
764 len
+= snprintf(buf
+ len
, sizeof(smi
->buf
) - len
,
765 "', members=%04x, untag=%04x, fid=%u",
766 vlan4k
.member
, vlan4k
.untag
, vlan4k
.fid
);
774 static int rtl8366s_sw_set_port_led(struct switch_dev
*dev
,
775 const struct switch_attr
*attr
,
776 struct switch_val
*val
)
778 struct rtl8366_smi
*smi
= sw_to_rtl8366_smi(dev
);
783 if (val
->port_vlan
>= RTL8366S_NUM_PORTS
||
784 (1 << val
->port_vlan
) == RTL8366S_PORT_UNKNOWN
)
787 if (val
->port_vlan
== RTL8366S_PORT_NUM_CPU
) {
788 reg
= RTL8366S_LED_BLINKRATE_REG
;
790 data
= val
->value
.i
<< 4;
792 reg
= RTL8366S_LED_CTRL_REG
;
793 mask
= 0xF << (val
->port_vlan
* 4),
794 data
= val
->value
.i
<< (val
->port_vlan
* 4);
797 return rtl8366_smi_rmwr(smi
, RTL8366S_LED_BLINKRATE_REG
, mask
, data
);
800 static int rtl8366s_sw_get_port_led(struct switch_dev
*dev
,
801 const struct switch_attr
*attr
,
802 struct switch_val
*val
)
804 struct rtl8366_smi
*smi
= sw_to_rtl8366_smi(dev
);
807 if (val
->port_vlan
>= RTL8366S_NUM_LEDGROUPS
)
810 rtl8366_smi_read_reg(smi
, RTL8366S_LED_CTRL_REG
, &data
);
811 val
->value
.i
= (data
>> (val
->port_vlan
* 4)) & 0x000F;
816 static int rtl8366s_sw_reset_port_mibs(struct switch_dev
*dev
,
817 const struct switch_attr
*attr
,
818 struct switch_val
*val
)
820 struct rtl8366_smi
*smi
= sw_to_rtl8366_smi(dev
);
822 if (val
->port_vlan
>= RTL8366S_NUM_PORTS
)
826 return rtl8366_smi_rmwr(smi
, RTL8366S_MIB_CTRL_REG
,
827 0, (1 << (val
->port_vlan
+ 3)));
830 static int rtl8366s_sw_get_vlan_ports(struct switch_dev
*dev
,
831 struct switch_val
*val
)
833 struct rtl8366_smi
*smi
= sw_to_rtl8366_smi(dev
);
834 struct switch_port
*port
;
835 struct rtl8366_vlan_4k vlan4k
;
838 if (!smi
->ops
->is_vlan_valid(smi
, val
->port_vlan
))
841 rtl8366s_get_vlan_4k(smi
, val
->port_vlan
, &vlan4k
);
843 port
= &val
->value
.ports
[0];
845 for (i
= 0; i
< RTL8366S_NUM_PORTS
; i
++) {
846 if (!(vlan4k
.member
& BIT(i
)))
850 port
->flags
= (vlan4k
.untag
& BIT(i
)) ?
851 0 : BIT(SWITCH_PORT_FLAG_TAGGED
);
858 static int rtl8366s_sw_set_vlan_ports(struct switch_dev
*dev
,
859 struct switch_val
*val
)
861 struct rtl8366_smi
*smi
= sw_to_rtl8366_smi(dev
);
862 struct switch_port
*port
;
867 if (!smi
->ops
->is_vlan_valid(smi
, val
->port_vlan
))
870 port
= &val
->value
.ports
[0];
871 for (i
= 0; i
< val
->len
; i
++, port
++) {
872 member
|= BIT(port
->id
);
874 if (!(port
->flags
& BIT(SWITCH_PORT_FLAG_TAGGED
)))
875 untag
|= BIT(port
->id
);
878 return rtl8366_set_vlan(smi
, val
->port_vlan
, member
, untag
, 0);
881 static int rtl8366s_sw_reset_switch(struct switch_dev
*dev
)
883 struct rtl8366_smi
*smi
= sw_to_rtl8366_smi(dev
);
886 err
= rtl8366s_reset_chip(smi
);
890 err
= rtl8366s_hw_init(smi
);
894 return rtl8366_reset_vlan(smi
);
897 static struct switch_attr rtl8366s_globals
[] = {
899 .type
= SWITCH_TYPE_INT
,
900 .name
= "enable_vlan",
901 .description
= "Enable VLAN mode",
902 .set
= rtl8366s_sw_set_vlan_enable
,
903 .get
= rtl8366s_sw_get_vlan_enable
,
907 .type
= SWITCH_TYPE_INT
,
908 .name
= "enable_vlan4k",
909 .description
= "Enable VLAN 4K mode",
910 .set
= rtl8366s_sw_set_vlan_enable
,
911 .get
= rtl8366s_sw_get_vlan_enable
,
915 .type
= SWITCH_TYPE_NOVAL
,
916 .name
= "reset_mibs",
917 .description
= "Reset all MIB counters",
918 .set
= rtl8366s_sw_reset_mibs
,
920 .type
= SWITCH_TYPE_INT
,
922 .description
= "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms,"
923 " 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)",
924 .set
= rtl8366s_sw_set_blinkrate
,
925 .get
= rtl8366s_sw_get_blinkrate
,
930 static struct switch_attr rtl8366s_port
[] = {
932 .type
= SWITCH_TYPE_STRING
,
934 .description
= "Get port link information",
937 .get
= rtl8366s_sw_get_port_link
,
939 .type
= SWITCH_TYPE_NOVAL
,
941 .description
= "Reset single port MIB counters",
942 .set
= rtl8366s_sw_reset_port_mibs
,
944 .type
= SWITCH_TYPE_STRING
,
946 .description
= "Get MIB counters for port",
949 .get
= rtl8366_sw_get_port_mib
,
951 .type
= SWITCH_TYPE_INT
,
953 .description
= "Get/Set port group (0 - 3) led mode (0 - 15)",
955 .set
= rtl8366s_sw_set_port_led
,
956 .get
= rtl8366s_sw_get_port_led
,
960 static struct switch_attr rtl8366s_vlan
[] = {
962 .type
= SWITCH_TYPE_STRING
,
964 .description
= "Get vlan information",
967 .get
= rtl8366s_sw_get_vlan_info
,
972 static struct switch_dev rtl8366_switch_dev
= {
974 .cpu_port
= RTL8366S_PORT_NUM_CPU
,
975 .ports
= RTL8366S_NUM_PORTS
,
976 .vlans
= RTL8366S_NUM_VLANS
,
978 .attr
= rtl8366s_globals
,
979 .n_attr
= ARRAY_SIZE(rtl8366s_globals
),
982 .attr
= rtl8366s_port
,
983 .n_attr
= ARRAY_SIZE(rtl8366s_port
),
986 .attr
= rtl8366s_vlan
,
987 .n_attr
= ARRAY_SIZE(rtl8366s_vlan
),
990 .get_vlan_ports
= rtl8366s_sw_get_vlan_ports
,
991 .set_vlan_ports
= rtl8366s_sw_set_vlan_ports
,
992 .get_port_pvid
= rtl8366_sw_get_port_pvid
,
993 .set_port_pvid
= rtl8366_sw_set_port_pvid
,
994 .reset_switch
= rtl8366s_sw_reset_switch
,
997 static int rtl8366s_switch_init(struct rtl8366_smi
*smi
)
999 struct switch_dev
*dev
= &smi
->sw_dev
;
1002 memcpy(dev
, &rtl8366_switch_dev
, sizeof(struct switch_dev
));
1004 dev
->devname
= dev_name(smi
->parent
);
1006 err
= register_switch(dev
, NULL
);
1008 dev_err(smi
->parent
, "switch registration failed\n");
1013 static void rtl8366s_switch_cleanup(struct rtl8366_smi
*smi
)
1015 unregister_switch(&smi
->sw_dev
);
1018 static int rtl8366s_mii_read(struct mii_bus
*bus
, int addr
, int reg
)
1020 struct rtl8366_smi
*smi
= bus
->priv
;
1024 err
= rtl8366s_read_phy_reg(smi
, addr
, 0, reg
, &val
);
1031 static int rtl8366s_mii_write(struct mii_bus
*bus
, int addr
, int reg
, u16 val
)
1033 struct rtl8366_smi
*smi
= bus
->priv
;
1037 err
= rtl8366s_write_phy_reg(smi
, addr
, 0, reg
, val
);
1039 (void) rtl8366s_read_phy_reg(smi
, addr
, 0, reg
, &t
);
1044 static int rtl8366s_mii_bus_match(struct mii_bus
*bus
)
1046 return (bus
->read
== rtl8366s_mii_read
&&
1047 bus
->write
== rtl8366s_mii_write
);
1050 static int rtl8366s_setup(struct rtl8366_smi
*smi
)
1054 ret
= rtl8366s_reset_chip(smi
);
1058 ret
= rtl8366s_hw_init(smi
);
1062 static int rtl8366s_detect(struct rtl8366_smi
*smi
)
1068 ret
= rtl8366_smi_read_reg(smi
, RTL8366S_CHIP_ID_REG
, &chip_id
);
1070 dev_err(smi
->parent
, "unable to read chip id\n");
1075 case RTL8366S_CHIP_ID_8366
:
1078 dev_err(smi
->parent
, "unknown chip id (%04x)\n", chip_id
);
1082 ret
= rtl8366_smi_read_reg(smi
, RTL8366S_CHIP_VERSION_CTRL_REG
,
1085 dev_err(smi
->parent
, "unable to read chip version\n");
1089 dev_info(smi
->parent
, "RTL%04x ver. %u chip found\n",
1090 chip_id
, chip_ver
& RTL8366S_CHIP_VERSION_MASK
);
1095 static struct rtl8366_smi_ops rtl8366s_smi_ops
= {
1096 .detect
= rtl8366s_detect
,
1097 .setup
= rtl8366s_setup
,
1099 .mii_read
= rtl8366s_mii_read
,
1100 .mii_write
= rtl8366s_mii_write
,
1102 .get_vlan_mc
= rtl8366s_get_vlan_mc
,
1103 .set_vlan_mc
= rtl8366s_set_vlan_mc
,
1104 .get_vlan_4k
= rtl8366s_get_vlan_4k
,
1105 .set_vlan_4k
= rtl8366s_set_vlan_4k
,
1106 .get_mc_index
= rtl8366s_get_mc_index
,
1107 .set_mc_index
= rtl8366s_set_mc_index
,
1108 .get_mib_counter
= rtl8366_get_mib_counter
,
1109 .is_vlan_valid
= rtl8366s_is_vlan_valid
,
1112 static int __init
rtl8366s_probe(struct platform_device
*pdev
)
1114 static int rtl8366_smi_version_printed
;
1115 struct rtl8366s_platform_data
*pdata
;
1116 struct rtl8366_smi
*smi
;
1119 if (!rtl8366_smi_version_printed
++)
1120 printk(KERN_NOTICE RTL8366S_DRIVER_DESC
1121 " version " RTL8366S_DRIVER_VER
"\n");
1123 pdata
= pdev
->dev
.platform_data
;
1125 dev_err(&pdev
->dev
, "no platform data specified\n");
1130 smi
= rtl8366_smi_alloc(&pdev
->dev
);
1136 smi
->gpio_sda
= pdata
->gpio_sda
;
1137 smi
->gpio_sck
= pdata
->gpio_sck
;
1138 smi
->ops
= &rtl8366s_smi_ops
;
1139 smi
->cpu_port
= RTL8366S_PORT_NUM_CPU
;
1140 smi
->num_ports
= RTL8366S_NUM_PORTS
;
1141 smi
->num_vlan_mc
= RTL8366S_NUM_VLANS
;
1142 smi
->mib_counters
= rtl8366s_mib_counters
;
1143 smi
->num_mib_counters
= ARRAY_SIZE(rtl8366s_mib_counters
);
1145 err
= rtl8366_smi_init(smi
);
1149 platform_set_drvdata(pdev
, smi
);
1151 err
= rtl8366s_switch_init(smi
);
1153 goto err_clear_drvdata
;
1158 platform_set_drvdata(pdev
, NULL
);
1159 rtl8366_smi_cleanup(smi
);
1166 static int rtl8366s_phy_config_init(struct phy_device
*phydev
)
1168 if (!rtl8366s_mii_bus_match(phydev
->bus
))
1174 static int rtl8366s_phy_config_aneg(struct phy_device
*phydev
)
1179 static struct phy_driver rtl8366s_phy_driver
= {
1180 .phy_id
= 0x001cc960,
1181 .name
= "Realtek RTL8366S",
1182 .phy_id_mask
= 0x1ffffff0,
1183 .features
= PHY_GBIT_FEATURES
,
1184 .config_aneg
= rtl8366s_phy_config_aneg
,
1185 .config_init
= rtl8366s_phy_config_init
,
1186 .read_status
= genphy_read_status
,
1188 .owner
= THIS_MODULE
,
1192 static int __devexit
rtl8366s_remove(struct platform_device
*pdev
)
1194 struct rtl8366_smi
*smi
= platform_get_drvdata(pdev
);
1197 rtl8366s_switch_cleanup(smi
);
1198 platform_set_drvdata(pdev
, NULL
);
1199 rtl8366_smi_cleanup(smi
);
1206 static struct platform_driver rtl8366s_driver
= {
1208 .name
= RTL8366S_DRIVER_NAME
,
1209 .owner
= THIS_MODULE
,
1211 .probe
= rtl8366s_probe
,
1212 .remove
= __devexit_p(rtl8366s_remove
),
1215 static int __init
rtl8366s_module_init(void)
1218 ret
= platform_driver_register(&rtl8366s_driver
);
1222 ret
= phy_driver_register(&rtl8366s_phy_driver
);
1224 goto err_platform_unregister
;
1228 err_platform_unregister
:
1229 platform_driver_unregister(&rtl8366s_driver
);
1232 module_init(rtl8366s_module_init
);
1234 static void __exit
rtl8366s_module_exit(void)
1236 phy_driver_unregister(&rtl8366s_phy_driver
);
1237 platform_driver_unregister(&rtl8366s_driver
);
1239 module_exit(rtl8366s_module_exit
);
1241 MODULE_DESCRIPTION(RTL8366S_DRIVER_DESC
);
1242 MODULE_VERSION(RTL8366S_DRIVER_VER
);
1243 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1244 MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>");
1245 MODULE_LICENSE("GPL v2");
1246 MODULE_ALIAS("platform:" RTL8366S_DRIVER_NAME
);