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generic: rtl8366: minor cleanup
[openwrt/staging/yousong.git] / target / linux / generic / files / drivers / net / phy / rtl8366s.c
1 /*
2 * Platform driver for the Realtek RTL8366S ethernet switch
3 *
4 * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
10 */
11
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/platform_device.h>
16 #include <linux/delay.h>
17 #include <linux/skbuff.h>
18 #include <linux/switch.h>
19 #include <linux/rtl8366s.h>
20
21 #include "rtl8366_smi.h"
22
23 #define RTL8366S_DRIVER_DESC "Realtek RTL8366S ethernet switch driver"
24 #define RTL8366S_DRIVER_VER "0.2.2"
25
26 #define RTL8366S_PHY_NO_MAX 4
27 #define RTL8366S_PHY_PAGE_MAX 7
28 #define RTL8366S_PHY_ADDR_MAX 31
29
30 /* Switch Global Configuration register */
31 #define RTL8366S_SGCR 0x0000
32 #define RTL8366S_SGCR_EN_BC_STORM_CTRL BIT(0)
33 #define RTL8366S_SGCR_MAX_LENGTH(_x) (_x << 4)
34 #define RTL8366S_SGCR_MAX_LENGTH_MASK RTL8366S_SGCR_MAX_LENGTH(0x3)
35 #define RTL8366S_SGCR_MAX_LENGTH_1522 RTL8366S_SGCR_MAX_LENGTH(0x0)
36 #define RTL8366S_SGCR_MAX_LENGTH_1536 RTL8366S_SGCR_MAX_LENGTH(0x1)
37 #define RTL8366S_SGCR_MAX_LENGTH_1552 RTL8366S_SGCR_MAX_LENGTH(0x2)
38 #define RTL8366S_SGCR_MAX_LENGTH_16000 RTL8366S_SGCR_MAX_LENGTH(0x3)
39 #define RTL8366S_SGCR_EN_VLAN BIT(13)
40
41 /* Port Enable Control register */
42 #define RTL8366S_PECR 0x0001
43
44 /* Switch Security Control registers */
45 #define RTL8366S_SSCR0 0x0002
46 #define RTL8366S_SSCR1 0x0003
47 #define RTL8366S_SSCR2 0x0004
48 #define RTL8366S_SSCR2_DROP_UNKNOWN_DA BIT(0)
49
50 #define RTL8366S_RESET_CTRL_REG 0x0100
51 #define RTL8366S_CHIP_CTRL_RESET_HW 1
52 #define RTL8366S_CHIP_CTRL_RESET_SW (1 << 1)
53
54 #define RTL8366S_CHIP_VERSION_CTRL_REG 0x0104
55 #define RTL8366S_CHIP_VERSION_MASK 0xf
56 #define RTL8366S_CHIP_ID_REG 0x0105
57 #define RTL8366S_CHIP_ID_8366 0x8366
58
59 /* PHY registers control */
60 #define RTL8366S_PHY_ACCESS_CTRL_REG 0x8028
61 #define RTL8366S_PHY_ACCESS_DATA_REG 0x8029
62
63 #define RTL8366S_PHY_CTRL_READ 1
64 #define RTL8366S_PHY_CTRL_WRITE 0
65
66 #define RTL8366S_PHY_REG_MASK 0x1f
67 #define RTL8366S_PHY_PAGE_OFFSET 5
68 #define RTL8366S_PHY_PAGE_MASK (0x7 << 5)
69 #define RTL8366S_PHY_NO_OFFSET 9
70 #define RTL8366S_PHY_NO_MASK (0x1f << 9)
71
72 /* LED control registers */
73 #define RTL8366S_LED_BLINKRATE_REG 0x0420
74 #define RTL8366S_LED_BLINKRATE_BIT 0
75 #define RTL8366S_LED_BLINKRATE_MASK 0x0007
76
77 #define RTL8366S_LED_CTRL_REG 0x0421
78 #define RTL8366S_LED_0_1_CTRL_REG 0x0422
79 #define RTL8366S_LED_2_3_CTRL_REG 0x0423
80
81 #define RTL8366S_MIB_COUNT 33
82 #define RTL8366S_GLOBAL_MIB_COUNT 1
83 #define RTL8366S_MIB_COUNTER_PORT_OFFSET 0x0040
84 #define RTL8366S_MIB_COUNTER_BASE 0x1000
85 #define RTL8366S_MIB_COUNTER_PORT_OFFSET2 0x0008
86 #define RTL8366S_MIB_COUNTER_BASE2 0x1180
87 #define RTL8366S_MIB_CTRL_REG 0x11F0
88 #define RTL8366S_MIB_CTRL_USER_MASK 0x01FF
89 #define RTL8366S_MIB_CTRL_BUSY_MASK 0x0001
90 #define RTL8366S_MIB_CTRL_RESET_MASK 0x0002
91
92 #define RTL8366S_MIB_CTRL_GLOBAL_RESET_MASK 0x0004
93 #define RTL8366S_MIB_CTRL_PORT_RESET_BIT 0x0003
94 #define RTL8366S_MIB_CTRL_PORT_RESET_MASK 0x01FC
95
96
97 #define RTL8366S_PORT_VLAN_CTRL_BASE 0x0058
98 #define RTL8366S_PORT_VLAN_CTRL_REG(_p) \
99 (RTL8366S_PORT_VLAN_CTRL_BASE + (_p) / 4)
100 #define RTL8366S_PORT_VLAN_CTRL_MASK 0xf
101 #define RTL8366S_PORT_VLAN_CTRL_SHIFT(_p) (4 * ((_p) % 4))
102
103
104 #define RTL8366S_VLAN_TABLE_READ_BASE 0x018B
105 #define RTL8366S_VLAN_TABLE_WRITE_BASE 0x0185
106
107 #define RTL8366S_VLAN_TB_CTRL_REG 0x010F
108
109 #define RTL8366S_TABLE_ACCESS_CTRL_REG 0x0180
110 #define RTL8366S_TABLE_VLAN_READ_CTRL 0x0E01
111 #define RTL8366S_TABLE_VLAN_WRITE_CTRL 0x0F01
112
113 #define RTL8366S_VLAN_MEMCONF_BASE 0x0016
114
115
116 #define RTL8366S_PORT_LINK_STATUS_BASE 0x0060
117 #define RTL8366S_PORT_STATUS_SPEED_MASK 0x0003
118 #define RTL8366S_PORT_STATUS_DUPLEX_MASK 0x0004
119 #define RTL8366S_PORT_STATUS_LINK_MASK 0x0010
120 #define RTL8366S_PORT_STATUS_TXPAUSE_MASK 0x0020
121 #define RTL8366S_PORT_STATUS_RXPAUSE_MASK 0x0040
122 #define RTL8366S_PORT_STATUS_AN_MASK 0x0080
123
124
125 #define RTL8366S_PORT_NUM_CPU 5
126 #define RTL8366S_NUM_PORTS 6
127 #define RTL8366S_NUM_VLANS 16
128 #define RTL8366S_NUM_LEDGROUPS 4
129 #define RTL8366S_NUM_VIDS 4096
130 #define RTL8366S_PRIORITYMAX 7
131 #define RTL8366S_FIDMAX 7
132
133
134 #define RTL8366S_PORT_1 (1 << 0) /* In userspace port 0 */
135 #define RTL8366S_PORT_2 (1 << 1) /* In userspace port 1 */
136 #define RTL8366S_PORT_3 (1 << 2) /* In userspace port 2 */
137 #define RTL8366S_PORT_4 (1 << 3) /* In userspace port 3 */
138
139 #define RTL8366S_PORT_UNKNOWN (1 << 4) /* No known connection */
140 #define RTL8366S_PORT_CPU (1 << 5) /* CPU port */
141
142 #define RTL8366S_PORT_ALL (RTL8366S_PORT_1 | \
143 RTL8366S_PORT_2 | \
144 RTL8366S_PORT_3 | \
145 RTL8366S_PORT_4 | \
146 RTL8366S_PORT_UNKNOWN | \
147 RTL8366S_PORT_CPU)
148
149 #define RTL8366S_PORT_ALL_BUT_CPU (RTL8366S_PORT_1 | \
150 RTL8366S_PORT_2 | \
151 RTL8366S_PORT_3 | \
152 RTL8366S_PORT_4 | \
153 RTL8366S_PORT_UNKNOWN)
154
155 #define RTL8366S_PORT_ALL_EXTERNAL (RTL8366S_PORT_1 | \
156 RTL8366S_PORT_2 | \
157 RTL8366S_PORT_3 | \
158 RTL8366S_PORT_4)
159
160 #define RTL8366S_PORT_ALL_INTERNAL (RTL8366S_PORT_UNKNOWN | \
161 RTL8366S_PORT_CPU)
162
163 struct rtl8366s {
164 struct device *parent;
165 struct rtl8366_smi smi;
166 struct switch_dev dev;
167 };
168
169 struct rtl8366s_vlan_mc {
170 u16 reserved2:1;
171 u16 priority:3;
172 u16 vid:12;
173
174 u16 reserved1:1;
175 u16 fid:3;
176 u16 untag:6;
177 u16 member:6;
178 };
179
180 struct rtl8366s_vlan_4k {
181 u16 reserved1:4;
182 u16 vid:12;
183
184 u16 reserved2:1;
185 u16 fid:3;
186 u16 untag:6;
187 u16 member:6;
188 };
189
190 static struct rtl8366_mib_counter rtl8366s_mib_counters[] = {
191 { 0, 0, 4, "IfInOctets" },
192 { 0, 4, 4, "EtherStatsOctets" },
193 { 0, 8, 2, "EtherStatsUnderSizePkts" },
194 { 0, 10, 2, "EtherFragments" },
195 { 0, 12, 2, "EtherStatsPkts64Octets" },
196 { 0, 14, 2, "EtherStatsPkts65to127Octets" },
197 { 0, 16, 2, "EtherStatsPkts128to255Octets" },
198 { 0, 18, 2, "EtherStatsPkts256to511Octets" },
199 { 0, 20, 2, "EtherStatsPkts512to1023Octets" },
200 { 0, 22, 2, "EtherStatsPkts1024to1518Octets" },
201 { 0, 24, 2, "EtherOversizeStats" },
202 { 0, 26, 2, "EtherStatsJabbers" },
203 { 0, 28, 2, "IfInUcastPkts" },
204 { 0, 30, 2, "EtherStatsMulticastPkts" },
205 { 0, 32, 2, "EtherStatsBroadcastPkts" },
206 { 0, 34, 2, "EtherStatsDropEvents" },
207 { 0, 36, 2, "Dot3StatsFCSErrors" },
208 { 0, 38, 2, "Dot3StatsSymbolErrors" },
209 { 0, 40, 2, "Dot3InPauseFrames" },
210 { 0, 42, 2, "Dot3ControlInUnknownOpcodes" },
211 { 0, 44, 4, "IfOutOctets" },
212 { 0, 48, 2, "Dot3StatsSingleCollisionFrames" },
213 { 0, 50, 2, "Dot3StatMultipleCollisionFrames" },
214 { 0, 52, 2, "Dot3sDeferredTransmissions" },
215 { 0, 54, 2, "Dot3StatsLateCollisions" },
216 { 0, 56, 2, "EtherStatsCollisions" },
217 { 0, 58, 2, "Dot3StatsExcessiveCollisions" },
218 { 0, 60, 2, "Dot3OutPauseFrames" },
219 { 0, 62, 2, "Dot1dBasePortDelayExceededDiscards" },
220
221 /*
222 * The following counters are accessible at a different
223 * base address.
224 */
225 { 1, 0, 2, "Dot1dTpPortInDiscards" },
226 { 1, 2, 2, "IfOutUcastPkts" },
227 { 1, 4, 2, "IfOutMulticastPkts" },
228 { 1, 6, 2, "IfOutBroadcastPkts" },
229 };
230
231 #define REG_WR(_smi, _reg, _val) \
232 do { \
233 err = rtl8366_smi_write_reg(_smi, _reg, _val); \
234 if (err) \
235 return err; \
236 } while (0)
237
238 #define REG_RMW(_smi, _reg, _mask, _val) \
239 do { \
240 err = rtl8366_smi_rmwr(_smi, _reg, _mask, _val); \
241 if (err) \
242 return err; \
243 } while (0)
244
245 static inline struct rtl8366s *smi_to_rtl8366s(struct rtl8366_smi *smi)
246 {
247 return container_of(smi, struct rtl8366s, smi);
248 }
249
250 static inline struct rtl8366s *sw_to_rtl8366s(struct switch_dev *sw)
251 {
252 return container_of(sw, struct rtl8366s, dev);
253 }
254
255 static inline struct rtl8366_smi *sw_to_rtl8366_smi(struct switch_dev *sw)
256 {
257 struct rtl8366s *rtl = sw_to_rtl8366s(sw);
258 return &rtl->smi;
259 }
260
261 static int rtl8366s_reset_chip(struct rtl8366_smi *smi)
262 {
263 int timeout = 10;
264 u32 data;
265
266 rtl8366_smi_write_reg(smi, RTL8366S_RESET_CTRL_REG,
267 RTL8366S_CHIP_CTRL_RESET_HW);
268 do {
269 msleep(1);
270 if (rtl8366_smi_read_reg(smi, RTL8366S_RESET_CTRL_REG, &data))
271 return -EIO;
272
273 if (!(data & RTL8366S_CHIP_CTRL_RESET_HW))
274 break;
275 } while (--timeout);
276
277 if (!timeout) {
278 printk("Timeout waiting for the switch to reset\n");
279 return -EIO;
280 }
281
282 return 0;
283 }
284
285 static int rtl8366s_hw_init(struct rtl8366_smi *smi)
286 {
287 int err;
288
289 /* set maximum packet length to 1536 bytes */
290 REG_RMW(smi, RTL8366S_SGCR, RTL8366S_SGCR_MAX_LENGTH_MASK,
291 RTL8366S_SGCR_MAX_LENGTH_1536);
292
293 /* enable all ports */
294 REG_WR(smi, RTL8366S_PECR, 0);
295
296 /* disable learning for all ports */
297 REG_WR(smi, RTL8366S_SSCR0, RTL8366S_PORT_ALL);
298
299 /* disable auto ageing for all ports */
300 REG_WR(smi, RTL8366S_SSCR1, RTL8366S_PORT_ALL);
301
302 /* don't drop packets whose DA has not been learned */
303 REG_RMW(smi, RTL8366S_SSCR2, RTL8366S_SSCR2_DROP_UNKNOWN_DA, 0);
304
305 return 0;
306 }
307
308 static int rtl8366s_read_phy_reg(struct rtl8366_smi *smi,
309 u32 phy_no, u32 page, u32 addr, u32 *data)
310 {
311 u32 reg;
312 int ret;
313
314 if (phy_no > RTL8366S_PHY_NO_MAX)
315 return -EINVAL;
316
317 if (page > RTL8366S_PHY_PAGE_MAX)
318 return -EINVAL;
319
320 if (addr > RTL8366S_PHY_ADDR_MAX)
321 return -EINVAL;
322
323 ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
324 RTL8366S_PHY_CTRL_READ);
325 if (ret)
326 return ret;
327
328 reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
329 ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
330 (addr & RTL8366S_PHY_REG_MASK);
331
332 ret = rtl8366_smi_write_reg(smi, reg, 0);
333 if (ret)
334 return ret;
335
336 ret = rtl8366_smi_read_reg(smi, RTL8366S_PHY_ACCESS_DATA_REG, data);
337 if (ret)
338 return ret;
339
340 return 0;
341 }
342
343 static int rtl8366s_write_phy_reg(struct rtl8366_smi *smi,
344 u32 phy_no, u32 page, u32 addr, u32 data)
345 {
346 u32 reg;
347 int ret;
348
349 if (phy_no > RTL8366S_PHY_NO_MAX)
350 return -EINVAL;
351
352 if (page > RTL8366S_PHY_PAGE_MAX)
353 return -EINVAL;
354
355 if (addr > RTL8366S_PHY_ADDR_MAX)
356 return -EINVAL;
357
358 ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
359 RTL8366S_PHY_CTRL_WRITE);
360 if (ret)
361 return ret;
362
363 reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
364 ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
365 (addr & RTL8366S_PHY_REG_MASK);
366
367 ret = rtl8366_smi_write_reg(smi, reg, data);
368 if (ret)
369 return ret;
370
371 return 0;
372 }
373
374 static int rtl8366_get_mib_counter(struct rtl8366_smi *smi, int counter,
375 int port, unsigned long long *val)
376 {
377 int i;
378 int err;
379 u32 addr, data;
380 u64 mibvalue;
381
382 if (port > RTL8366S_NUM_PORTS || counter >= RTL8366S_MIB_COUNT)
383 return -EINVAL;
384
385 switch (rtl8366s_mib_counters[counter].base) {
386 case 0:
387 addr = RTL8366S_MIB_COUNTER_BASE +
388 RTL8366S_MIB_COUNTER_PORT_OFFSET * port;
389 break;
390
391 case 1:
392 addr = RTL8366S_MIB_COUNTER_BASE2 +
393 RTL8366S_MIB_COUNTER_PORT_OFFSET2 * port;
394 break;
395
396 default:
397 return -EINVAL;
398 }
399
400 addr += rtl8366s_mib_counters[counter].offset;
401
402 /*
403 * Writing access counter address first
404 * then ASIC will prepare 64bits counter wait for being retrived
405 */
406 data = 0; /* writing data will be discard by ASIC */
407 err = rtl8366_smi_write_reg(smi, addr, data);
408 if (err)
409 return err;
410
411 /* read MIB control register */
412 err = rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
413 if (err)
414 return err;
415
416 if (data & RTL8366S_MIB_CTRL_BUSY_MASK)
417 return -EBUSY;
418
419 if (data & RTL8366S_MIB_CTRL_RESET_MASK)
420 return -EIO;
421
422 mibvalue = 0;
423 for (i = rtl8366s_mib_counters[counter].length; i > 0; i--) {
424 err = rtl8366_smi_read_reg(smi, addr + (i - 1), &data);
425 if (err)
426 return err;
427
428 mibvalue = (mibvalue << 16) | (data & 0xFFFF);
429 }
430
431 *val = mibvalue;
432 return 0;
433 }
434
435 static int rtl8366s_get_vlan_4k(struct rtl8366_smi *smi, u32 vid,
436 struct rtl8366_vlan_4k *vlan4k)
437 {
438 struct rtl8366s_vlan_4k vlan4k_priv;
439 int err;
440 u32 data;
441 u16 *tableaddr;
442
443 memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k));
444 vlan4k_priv.vid = vid;
445
446 if (vid >= RTL8366S_NUM_VIDS)
447 return -EINVAL;
448
449 tableaddr = (u16 *)&vlan4k_priv;
450
451 /* write VID */
452 data = *tableaddr;
453 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE, data);
454 if (err)
455 return err;
456
457 /* write table access control word */
458 err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
459 RTL8366S_TABLE_VLAN_READ_CTRL);
460 if (err)
461 return err;
462
463 err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE, &data);
464 if (err)
465 return err;
466
467 *tableaddr = data;
468 tableaddr++;
469
470 err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE + 1,
471 &data);
472 if (err)
473 return err;
474
475 *tableaddr = data;
476
477 vlan4k->vid = vid;
478 vlan4k->untag = vlan4k_priv.untag;
479 vlan4k->member = vlan4k_priv.member;
480 vlan4k->fid = vlan4k_priv.fid;
481
482 return 0;
483 }
484
485 static int rtl8366s_set_vlan_4k(struct rtl8366_smi *smi,
486 const struct rtl8366_vlan_4k *vlan4k)
487 {
488 struct rtl8366s_vlan_4k vlan4k_priv;
489 int err;
490 u32 data;
491 u16 *tableaddr;
492
493 if (vlan4k->vid >= RTL8366S_NUM_VIDS ||
494 vlan4k->member > RTL8366S_PORT_ALL ||
495 vlan4k->untag > RTL8366S_PORT_ALL ||
496 vlan4k->fid > RTL8366S_FIDMAX)
497 return -EINVAL;
498
499 vlan4k_priv.vid = vlan4k->vid;
500 vlan4k_priv.untag = vlan4k->untag;
501 vlan4k_priv.member = vlan4k->member;
502 vlan4k_priv.fid = vlan4k->fid;
503
504 tableaddr = (u16 *)&vlan4k_priv;
505
506 data = *tableaddr;
507
508 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE, data);
509 if (err)
510 return err;
511
512 tableaddr++;
513
514 data = *tableaddr;
515
516 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE + 1,
517 data);
518 if (err)
519 return err;
520
521 /* write table access control word */
522 err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
523 RTL8366S_TABLE_VLAN_WRITE_CTRL);
524
525 return err;
526 }
527
528 static int rtl8366s_get_vlan_mc(struct rtl8366_smi *smi, u32 index,
529 struct rtl8366_vlan_mc *vlanmc)
530 {
531 struct rtl8366s_vlan_mc vlanmc_priv;
532 int err;
533 u32 addr;
534 u32 data;
535 u16 *tableaddr;
536
537 memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc));
538
539 if (index >= RTL8366S_NUM_VLANS)
540 return -EINVAL;
541
542 tableaddr = (u16 *)&vlanmc_priv;
543
544 addr = RTL8366S_VLAN_MEMCONF_BASE + (index << 1);
545 err = rtl8366_smi_read_reg(smi, addr, &data);
546 if (err)
547 return err;
548
549 *tableaddr = data;
550 tableaddr++;
551
552 addr = RTL8366S_VLAN_MEMCONF_BASE + 1 + (index << 1);
553 err = rtl8366_smi_read_reg(smi, addr, &data);
554 if (err)
555 return err;
556
557 *tableaddr = data;
558
559 vlanmc->vid = vlanmc_priv.vid;
560 vlanmc->priority = vlanmc_priv.priority;
561 vlanmc->untag = vlanmc_priv.untag;
562 vlanmc->member = vlanmc_priv.member;
563 vlanmc->fid = vlanmc_priv.fid;
564
565 return 0;
566 }
567
568 static int rtl8366s_set_vlan_mc(struct rtl8366_smi *smi, u32 index,
569 const struct rtl8366_vlan_mc *vlanmc)
570 {
571 struct rtl8366s_vlan_mc vlanmc_priv;
572 int err;
573 u32 addr;
574 u32 data;
575 u16 *tableaddr;
576
577 if (index >= RTL8366S_NUM_VLANS ||
578 vlanmc->vid >= RTL8366S_NUM_VIDS ||
579 vlanmc->priority > RTL8366S_PRIORITYMAX ||
580 vlanmc->member > RTL8366S_PORT_ALL ||
581 vlanmc->untag > RTL8366S_PORT_ALL ||
582 vlanmc->fid > RTL8366S_FIDMAX)
583 return -EINVAL;
584
585 vlanmc_priv.vid = vlanmc->vid;
586 vlanmc_priv.priority = vlanmc->priority;
587 vlanmc_priv.untag = vlanmc->untag;
588 vlanmc_priv.member = vlanmc->member;
589 vlanmc_priv.fid = vlanmc->fid;
590
591 addr = RTL8366S_VLAN_MEMCONF_BASE + (index << 1);
592
593 tableaddr = (u16 *)&vlanmc_priv;
594 data = *tableaddr;
595
596 err = rtl8366_smi_write_reg(smi, addr, data);
597 if (err)
598 return err;
599
600 addr = RTL8366S_VLAN_MEMCONF_BASE + 1 + (index << 1);
601
602 tableaddr++;
603 data = *tableaddr;
604
605 err = rtl8366_smi_write_reg(smi, addr, data);
606 if (err)
607 return err;
608
609 return 0;
610 }
611
612 static int rtl8366s_get_mc_index(struct rtl8366_smi *smi, int port, int *val)
613 {
614 u32 data;
615 int err;
616
617 if (port >= RTL8366S_NUM_PORTS)
618 return -EINVAL;
619
620 err = rtl8366_smi_read_reg(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
621 &data);
622 if (err)
623 return err;
624
625 *val = (data >> RTL8366S_PORT_VLAN_CTRL_SHIFT(port)) &
626 RTL8366S_PORT_VLAN_CTRL_MASK;
627
628 return 0;
629 }
630
631 static int rtl8366s_set_mc_index(struct rtl8366_smi *smi, int port, int index)
632 {
633 if (port >= RTL8366S_NUM_PORTS || index >= RTL8366S_NUM_VLANS)
634 return -EINVAL;
635
636 return rtl8366_smi_rmwr(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
637 RTL8366S_PORT_VLAN_CTRL_MASK <<
638 RTL8366S_PORT_VLAN_CTRL_SHIFT(port),
639 (index & RTL8366S_PORT_VLAN_CTRL_MASK) <<
640 RTL8366S_PORT_VLAN_CTRL_SHIFT(port));
641 }
642
643 static int rtl8366s_vlan_set_vlan(struct rtl8366_smi *smi, int enable)
644 {
645 return rtl8366_smi_rmwr(smi, RTL8366S_SGCR, RTL8366S_SGCR_EN_VLAN,
646 (enable) ? RTL8366S_SGCR_EN_VLAN : 0);
647 }
648
649 static int rtl8366s_vlan_set_4ktable(struct rtl8366_smi *smi, int enable)
650 {
651 return rtl8366_smi_rmwr(smi, RTL8366S_VLAN_TB_CTRL_REG,
652 1, (enable) ? 1 : 0);
653 }
654
655 static int rtl8366s_sw_reset_mibs(struct switch_dev *dev,
656 const struct switch_attr *attr,
657 struct switch_val *val)
658 {
659 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
660 int err = 0;
661
662 if (val->value.i == 1)
663 err = rtl8366_smi_rmwr(smi, RTL8366S_MIB_CTRL_REG, 0, (1 << 2));
664
665 return err;
666 }
667
668 static int rtl8366s_sw_get_vlan_enable(struct switch_dev *dev,
669 const struct switch_attr *attr,
670 struct switch_val *val)
671 {
672 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
673 u32 data;
674
675 if (attr->ofs == 1) {
676 rtl8366_smi_read_reg(smi, RTL8366S_SGCR, &data);
677
678 if (data & RTL8366S_SGCR_EN_VLAN)
679 val->value.i = 1;
680 else
681 val->value.i = 0;
682 } else if (attr->ofs == 2) {
683 rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TB_CTRL_REG, &data);
684
685 if (data & 0x0001)
686 val->value.i = 1;
687 else
688 val->value.i = 0;
689 }
690
691 return 0;
692 }
693
694 static int rtl8366s_sw_get_blinkrate(struct switch_dev *dev,
695 const struct switch_attr *attr,
696 struct switch_val *val)
697 {
698 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
699 u32 data;
700
701 rtl8366_smi_read_reg(smi, RTL8366S_LED_BLINKRATE_REG, &data);
702
703 val->value.i = (data & (RTL8366S_LED_BLINKRATE_MASK));
704
705 return 0;
706 }
707
708 static int rtl8366s_sw_set_blinkrate(struct switch_dev *dev,
709 const struct switch_attr *attr,
710 struct switch_val *val)
711 {
712 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
713
714 if (val->value.i >= 6)
715 return -EINVAL;
716
717 return rtl8366_smi_rmwr(smi, RTL8366S_LED_BLINKRATE_REG,
718 RTL8366S_LED_BLINKRATE_MASK,
719 val->value.i);
720 }
721
722 static int rtl8366s_sw_set_vlan_enable(struct switch_dev *dev,
723 const struct switch_attr *attr,
724 struct switch_val *val)
725 {
726 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
727
728 if (attr->ofs == 1)
729 return rtl8366s_vlan_set_vlan(smi, val->value.i);
730 else
731 return rtl8366s_vlan_set_4ktable(smi, val->value.i);
732 }
733
734 static const char *rtl8366s_speed_str(unsigned speed)
735 {
736 switch (speed) {
737 case 0:
738 return "10baseT";
739 case 1:
740 return "100baseT";
741 case 2:
742 return "1000baseT";
743 }
744
745 return "unknown";
746 }
747
748 static int rtl8366s_sw_get_port_link(struct switch_dev *dev,
749 const struct switch_attr *attr,
750 struct switch_val *val)
751 {
752 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
753 u32 len = 0, data = 0;
754
755 if (val->port_vlan >= RTL8366S_NUM_PORTS)
756 return -EINVAL;
757
758 memset(smi->buf, '\0', sizeof(smi->buf));
759 rtl8366_smi_read_reg(smi, RTL8366S_PORT_LINK_STATUS_BASE +
760 (val->port_vlan / 2), &data);
761
762 if (val->port_vlan % 2)
763 data = data >> 8;
764
765 if (data & RTL8366S_PORT_STATUS_LINK_MASK) {
766 len = snprintf(smi->buf, sizeof(smi->buf),
767 "port:%d link:up speed:%s %s-duplex %s%s%s",
768 val->port_vlan,
769 rtl8366s_speed_str(data &
770 RTL8366S_PORT_STATUS_SPEED_MASK),
771 (data & RTL8366S_PORT_STATUS_DUPLEX_MASK) ?
772 "full" : "half",
773 (data & RTL8366S_PORT_STATUS_TXPAUSE_MASK) ?
774 "tx-pause ": "",
775 (data & RTL8366S_PORT_STATUS_RXPAUSE_MASK) ?
776 "rx-pause " : "",
777 (data & RTL8366S_PORT_STATUS_AN_MASK) ?
778 "nway ": "");
779 } else {
780 len = snprintf(smi->buf, sizeof(smi->buf), "port:%d link: down",
781 val->port_vlan);
782 }
783
784 val->value.s = smi->buf;
785 val->len = len;
786
787 return 0;
788 }
789
790 static int rtl8366s_sw_get_vlan_info(struct switch_dev *dev,
791 const struct switch_attr *attr,
792 struct switch_val *val)
793 {
794 int i;
795 u32 len = 0;
796 struct rtl8366_vlan_4k vlan4k;
797 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
798 char *buf = smi->buf;
799 int err;
800
801 if (val->port_vlan == 0 || val->port_vlan >= RTL8366S_NUM_VLANS)
802 return -EINVAL;
803
804 memset(buf, '\0', sizeof(smi->buf));
805
806 err = rtl8366s_get_vlan_4k(smi, val->port_vlan, &vlan4k);
807 if (err)
808 return err;
809
810 len += snprintf(buf + len, sizeof(smi->buf) - len,
811 "VLAN %d: Ports: '", vlan4k.vid);
812
813 for (i = 0; i < RTL8366S_NUM_PORTS; i++) {
814 if (!(vlan4k.member & (1 << i)))
815 continue;
816
817 len += snprintf(buf + len, sizeof(smi->buf) - len, "%d%s", i,
818 (vlan4k.untag & (1 << i)) ? "" : "t");
819 }
820
821 len += snprintf(buf + len, sizeof(smi->buf) - len,
822 "', members=%04x, untag=%04x, fid=%u",
823 vlan4k.member, vlan4k.untag, vlan4k.fid);
824
825 val->value.s = buf;
826 val->len = len;
827
828 return 0;
829 }
830
831 static int rtl8366s_sw_set_port_led(struct switch_dev *dev,
832 const struct switch_attr *attr,
833 struct switch_val *val)
834 {
835 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
836 u32 data;
837 u32 mask;
838 u32 reg;
839
840 if (val->port_vlan >= RTL8366S_NUM_PORTS ||
841 (1 << val->port_vlan) == RTL8366S_PORT_UNKNOWN)
842 return -EINVAL;
843
844 if (val->port_vlan == RTL8366S_PORT_NUM_CPU) {
845 reg = RTL8366S_LED_BLINKRATE_REG;
846 mask = 0xF << 4;
847 data = val->value.i << 4;
848 } else {
849 reg = RTL8366S_LED_CTRL_REG;
850 mask = 0xF << (val->port_vlan * 4),
851 data = val->value.i << (val->port_vlan * 4);
852 }
853
854 return rtl8366_smi_rmwr(smi, RTL8366S_LED_BLINKRATE_REG, mask, data);
855 }
856
857 static int rtl8366s_sw_get_port_led(struct switch_dev *dev,
858 const struct switch_attr *attr,
859 struct switch_val *val)
860 {
861 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
862 u32 data = 0;
863
864 if (val->port_vlan >= RTL8366S_NUM_LEDGROUPS)
865 return -EINVAL;
866
867 rtl8366_smi_read_reg(smi, RTL8366S_LED_CTRL_REG, &data);
868 val->value.i = (data >> (val->port_vlan * 4)) & 0x000F;
869
870 return 0;
871 }
872
873 static int rtl8366s_sw_reset_port_mibs(struct switch_dev *dev,
874 const struct switch_attr *attr,
875 struct switch_val *val)
876 {
877 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
878
879 if (val->port_vlan >= RTL8366S_NUM_PORTS)
880 return -EINVAL;
881
882
883 return rtl8366_smi_rmwr(smi, RTL8366S_MIB_CTRL_REG,
884 0, (1 << (val->port_vlan + 3)));
885 }
886
887 static int rtl8366s_sw_get_port_mib(struct switch_dev *dev,
888 const struct switch_attr *attr,
889 struct switch_val *val)
890 {
891 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
892 int i, len = 0;
893 unsigned long long counter = 0;
894 char *buf = smi->buf;
895
896 if (val->port_vlan >= RTL8366S_NUM_PORTS)
897 return -EINVAL;
898
899 len += snprintf(buf + len, sizeof(smi->buf) - len,
900 "Port %d MIB counters\n",
901 val->port_vlan);
902
903 for (i = 0; i < ARRAY_SIZE(rtl8366s_mib_counters); ++i) {
904 len += snprintf(buf + len, sizeof(smi->buf) - len,
905 "%-36s: ", rtl8366s_mib_counters[i].name);
906 if (!rtl8366_get_mib_counter(smi, i, val->port_vlan, &counter))
907 len += snprintf(buf + len, sizeof(smi->buf) - len,
908 "%llu\n", counter);
909 else
910 len += snprintf(buf + len, sizeof(smi->buf) - len,
911 "%s\n", "error");
912 }
913
914 val->value.s = buf;
915 val->len = len;
916 return 0;
917 }
918
919 static int rtl8366s_sw_get_vlan_ports(struct switch_dev *dev,
920 struct switch_val *val)
921 {
922 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
923 struct switch_port *port;
924 struct rtl8366_vlan_4k vlan4k;
925 int i;
926
927 if (val->port_vlan == 0 || val->port_vlan >= RTL8366S_NUM_VLANS)
928 return -EINVAL;
929
930 rtl8366s_get_vlan_4k(smi, val->port_vlan, &vlan4k);
931
932 port = &val->value.ports[0];
933 val->len = 0;
934 for (i = 0; i < RTL8366S_NUM_PORTS; i++) {
935 if (!(vlan4k.member & BIT(i)))
936 continue;
937
938 port->id = i;
939 port->flags = (vlan4k.untag & BIT(i)) ?
940 0 : BIT(SWITCH_PORT_FLAG_TAGGED);
941 val->len++;
942 port++;
943 }
944 return 0;
945 }
946
947 static int rtl8366s_sw_set_vlan_ports(struct switch_dev *dev,
948 struct switch_val *val)
949 {
950 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
951 struct switch_port *port;
952 u32 member = 0;
953 u32 untag = 0;
954 int i;
955
956 if (val->port_vlan == 0 || val->port_vlan >= RTL8366S_NUM_VLANS)
957 return -EINVAL;
958
959 port = &val->value.ports[0];
960 for (i = 0; i < val->len; i++, port++) {
961 member |= BIT(port->id);
962
963 if (!(port->flags & BIT(SWITCH_PORT_FLAG_TAGGED)))
964 untag |= BIT(port->id);
965 }
966
967 return rtl8366_set_vlan(smi, val->port_vlan, member, untag, 0);
968 }
969
970 static int rtl8366s_sw_get_port_pvid(struct switch_dev *dev, int port, int *val)
971 {
972 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
973 return rtl8366_get_pvid(smi, port, val);
974 }
975
976 static int rtl8366s_sw_set_port_pvid(struct switch_dev *dev, int port, int val)
977 {
978 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
979 return rtl8366_set_pvid(smi, port, val);
980 }
981
982 static int rtl8366s_sw_reset_switch(struct switch_dev *dev)
983 {
984 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
985 int err;
986
987 err = rtl8366s_reset_chip(smi);
988 if (err)
989 return err;
990
991 err = rtl8366s_hw_init(smi);
992 if (err)
993 return err;
994
995 return rtl8366_reset_vlan(smi);
996 }
997
998 static struct switch_attr rtl8366s_globals[] = {
999 {
1000 .type = SWITCH_TYPE_INT,
1001 .name = "enable_vlan",
1002 .description = "Enable VLAN mode",
1003 .set = rtl8366s_sw_set_vlan_enable,
1004 .get = rtl8366s_sw_get_vlan_enable,
1005 .max = 1,
1006 .ofs = 1
1007 }, {
1008 .type = SWITCH_TYPE_INT,
1009 .name = "enable_vlan4k",
1010 .description = "Enable VLAN 4K mode",
1011 .set = rtl8366s_sw_set_vlan_enable,
1012 .get = rtl8366s_sw_get_vlan_enable,
1013 .max = 1,
1014 .ofs = 2
1015 }, {
1016 .type = SWITCH_TYPE_INT,
1017 .name = "reset_mibs",
1018 .description = "Reset all MIB counters",
1019 .set = rtl8366s_sw_reset_mibs,
1020 .get = NULL,
1021 .max = 1
1022 }, {
1023 .type = SWITCH_TYPE_INT,
1024 .name = "blinkrate",
1025 .description = "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms,"
1026 " 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)",
1027 .set = rtl8366s_sw_set_blinkrate,
1028 .get = rtl8366s_sw_get_blinkrate,
1029 .max = 5
1030 },
1031 };
1032
1033 static struct switch_attr rtl8366s_port[] = {
1034 {
1035 .type = SWITCH_TYPE_STRING,
1036 .name = "link",
1037 .description = "Get port link information",
1038 .max = 1,
1039 .set = NULL,
1040 .get = rtl8366s_sw_get_port_link,
1041 }, {
1042 .type = SWITCH_TYPE_INT,
1043 .name = "reset_mib",
1044 .description = "Reset single port MIB counters",
1045 .max = 1,
1046 .set = rtl8366s_sw_reset_port_mibs,
1047 .get = NULL,
1048 }, {
1049 .type = SWITCH_TYPE_STRING,
1050 .name = "mib",
1051 .description = "Get MIB counters for port",
1052 .max = 33,
1053 .set = NULL,
1054 .get = rtl8366s_sw_get_port_mib,
1055 }, {
1056 .type = SWITCH_TYPE_INT,
1057 .name = "led",
1058 .description = "Get/Set port group (0 - 3) led mode (0 - 15)",
1059 .max = 15,
1060 .set = rtl8366s_sw_set_port_led,
1061 .get = rtl8366s_sw_get_port_led,
1062 },
1063 };
1064
1065 static struct switch_attr rtl8366s_vlan[] = {
1066 {
1067 .type = SWITCH_TYPE_STRING,
1068 .name = "info",
1069 .description = "Get vlan information",
1070 .max = 1,
1071 .set = NULL,
1072 .get = rtl8366s_sw_get_vlan_info,
1073 },
1074 };
1075
1076 /* template */
1077 static struct switch_dev rtl8366_switch_dev = {
1078 .name = "RTL8366S",
1079 .cpu_port = RTL8366S_PORT_NUM_CPU,
1080 .ports = RTL8366S_NUM_PORTS,
1081 .vlans = RTL8366S_NUM_VLANS,
1082 .attr_global = {
1083 .attr = rtl8366s_globals,
1084 .n_attr = ARRAY_SIZE(rtl8366s_globals),
1085 },
1086 .attr_port = {
1087 .attr = rtl8366s_port,
1088 .n_attr = ARRAY_SIZE(rtl8366s_port),
1089 },
1090 .attr_vlan = {
1091 .attr = rtl8366s_vlan,
1092 .n_attr = ARRAY_SIZE(rtl8366s_vlan),
1093 },
1094
1095 .get_vlan_ports = rtl8366s_sw_get_vlan_ports,
1096 .set_vlan_ports = rtl8366s_sw_set_vlan_ports,
1097 .get_port_pvid = rtl8366s_sw_get_port_pvid,
1098 .set_port_pvid = rtl8366s_sw_set_port_pvid,
1099 .reset_switch = rtl8366s_sw_reset_switch,
1100 };
1101
1102 static int rtl8366s_switch_init(struct rtl8366s *rtl)
1103 {
1104 struct switch_dev *dev = &rtl->dev;
1105 int err;
1106
1107 memcpy(dev, &rtl8366_switch_dev, sizeof(struct switch_dev));
1108 dev->priv = rtl;
1109 dev->devname = dev_name(rtl->parent);
1110
1111 err = register_switch(dev, NULL);
1112 if (err)
1113 dev_err(rtl->parent, "switch registration failed\n");
1114
1115 return err;
1116 }
1117
1118 static void rtl8366s_switch_cleanup(struct rtl8366s *rtl)
1119 {
1120 unregister_switch(&rtl->dev);
1121 }
1122
1123 static int rtl8366s_mii_read(struct mii_bus *bus, int addr, int reg)
1124 {
1125 struct rtl8366_smi *smi = bus->priv;
1126 u32 val = 0;
1127 int err;
1128
1129 err = rtl8366s_read_phy_reg(smi, addr, 0, reg, &val);
1130 if (err)
1131 return 0xffff;
1132
1133 return val;
1134 }
1135
1136 static int rtl8366s_mii_write(struct mii_bus *bus, int addr, int reg, u16 val)
1137 {
1138 struct rtl8366_smi *smi = bus->priv;
1139 u32 t;
1140 int err;
1141
1142 err = rtl8366s_write_phy_reg(smi, addr, 0, reg, val);
1143 /* flush write */
1144 (void) rtl8366s_read_phy_reg(smi, addr, 0, reg, &t);
1145
1146 return err;
1147 }
1148
1149 static int rtl8366s_mii_bus_match(struct mii_bus *bus)
1150 {
1151 return (bus->read == rtl8366s_mii_read &&
1152 bus->write == rtl8366s_mii_write);
1153 }
1154
1155 static int rtl8366s_setup(struct rtl8366s *rtl)
1156 {
1157 struct rtl8366_smi *smi = &rtl->smi;
1158 int ret;
1159
1160 ret = rtl8366s_reset_chip(smi);
1161 if (ret)
1162 return ret;
1163
1164 ret = rtl8366s_hw_init(smi);
1165 return ret;
1166 }
1167
1168 static int rtl8366s_detect(struct rtl8366_smi *smi)
1169 {
1170 u32 chip_id = 0;
1171 u32 chip_ver = 0;
1172 int ret;
1173
1174 ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_ID_REG, &chip_id);
1175 if (ret) {
1176 dev_err(smi->parent, "unable to read chip id\n");
1177 return ret;
1178 }
1179
1180 switch (chip_id) {
1181 case RTL8366S_CHIP_ID_8366:
1182 break;
1183 default:
1184 dev_err(smi->parent, "unknown chip id (%04x)\n", chip_id);
1185 return -ENODEV;
1186 }
1187
1188 ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_VERSION_CTRL_REG,
1189 &chip_ver);
1190 if (ret) {
1191 dev_err(smi->parent, "unable to read chip version\n");
1192 return ret;
1193 }
1194
1195 dev_info(smi->parent, "RTL%04x ver. %u chip found\n",
1196 chip_id, chip_ver & RTL8366S_CHIP_VERSION_MASK);
1197
1198 return 0;
1199 }
1200
1201 static struct rtl8366_smi_ops rtl8366s_smi_ops = {
1202 .detect = rtl8366s_detect,
1203 .mii_read = rtl8366s_mii_read,
1204 .mii_write = rtl8366s_mii_write,
1205
1206 .get_vlan_mc = rtl8366s_get_vlan_mc,
1207 .set_vlan_mc = rtl8366s_set_vlan_mc,
1208 .get_vlan_4k = rtl8366s_get_vlan_4k,
1209 .set_vlan_4k = rtl8366s_set_vlan_4k,
1210 .get_mc_index = rtl8366s_get_mc_index,
1211 .set_mc_index = rtl8366s_set_mc_index,
1212 .get_mib_counter = rtl8366_get_mib_counter,
1213 };
1214
1215 static int __init rtl8366s_probe(struct platform_device *pdev)
1216 {
1217 static int rtl8366_smi_version_printed;
1218 struct rtl8366s_platform_data *pdata;
1219 struct rtl8366s *rtl;
1220 struct rtl8366_smi *smi;
1221 int err;
1222
1223 if (!rtl8366_smi_version_printed++)
1224 printk(KERN_NOTICE RTL8366S_DRIVER_DESC
1225 " version " RTL8366S_DRIVER_VER"\n");
1226
1227 pdata = pdev->dev.platform_data;
1228 if (!pdata) {
1229 dev_err(&pdev->dev, "no platform data specified\n");
1230 err = -EINVAL;
1231 goto err_out;
1232 }
1233
1234 rtl = kzalloc(sizeof(*rtl), GFP_KERNEL);
1235 if (!rtl) {
1236 dev_err(&pdev->dev, "no memory for private data\n");
1237 err = -ENOMEM;
1238 goto err_out;
1239 }
1240
1241 rtl->parent = &pdev->dev;
1242
1243 smi = &rtl->smi;
1244 smi->parent = &pdev->dev;
1245 smi->gpio_sda = pdata->gpio_sda;
1246 smi->gpio_sck = pdata->gpio_sck;
1247 smi->ops = &rtl8366s_smi_ops;
1248 smi->cpu_port = RTL8366S_PORT_NUM_CPU;
1249 smi->num_ports = RTL8366S_NUM_PORTS;
1250 smi->num_vlan_mc = RTL8366S_NUM_VLANS;
1251 smi->mib_counters = rtl8366s_mib_counters;
1252 smi->num_mib_counters = ARRAY_SIZE(rtl8366s_mib_counters);
1253
1254 err = rtl8366_smi_init(smi);
1255 if (err)
1256 goto err_free_rtl;
1257
1258 platform_set_drvdata(pdev, rtl);
1259
1260 err = rtl8366s_setup(rtl);
1261 if (err)
1262 goto err_clear_drvdata;
1263
1264 err = rtl8366s_switch_init(rtl);
1265 if (err)
1266 goto err_clear_drvdata;
1267
1268 return 0;
1269
1270 err_clear_drvdata:
1271 platform_set_drvdata(pdev, NULL);
1272 rtl8366_smi_cleanup(smi);
1273 err_free_rtl:
1274 kfree(rtl);
1275 err_out:
1276 return err;
1277 }
1278
1279 static int rtl8366s_phy_config_init(struct phy_device *phydev)
1280 {
1281 if (!rtl8366s_mii_bus_match(phydev->bus))
1282 return -EINVAL;
1283
1284 return 0;
1285 }
1286
1287 static int rtl8366s_phy_config_aneg(struct phy_device *phydev)
1288 {
1289 return 0;
1290 }
1291
1292 static struct phy_driver rtl8366s_phy_driver = {
1293 .phy_id = 0x001cc960,
1294 .name = "Realtek RTL8366S",
1295 .phy_id_mask = 0x1ffffff0,
1296 .features = PHY_GBIT_FEATURES,
1297 .config_aneg = rtl8366s_phy_config_aneg,
1298 .config_init = rtl8366s_phy_config_init,
1299 .read_status = genphy_read_status,
1300 .driver = {
1301 .owner = THIS_MODULE,
1302 },
1303 };
1304
1305 static int __devexit rtl8366s_remove(struct platform_device *pdev)
1306 {
1307 struct rtl8366s *rtl = platform_get_drvdata(pdev);
1308
1309 if (rtl) {
1310 rtl8366s_switch_cleanup(rtl);
1311 platform_set_drvdata(pdev, NULL);
1312 rtl8366_smi_cleanup(&rtl->smi);
1313 kfree(rtl);
1314 }
1315
1316 return 0;
1317 }
1318
1319 static struct platform_driver rtl8366s_driver = {
1320 .driver = {
1321 .name = RTL8366S_DRIVER_NAME,
1322 .owner = THIS_MODULE,
1323 },
1324 .probe = rtl8366s_probe,
1325 .remove = __devexit_p(rtl8366s_remove),
1326 };
1327
1328 static int __init rtl8366s_module_init(void)
1329 {
1330 int ret;
1331 ret = platform_driver_register(&rtl8366s_driver);
1332 if (ret)
1333 return ret;
1334
1335 ret = phy_driver_register(&rtl8366s_phy_driver);
1336 if (ret)
1337 goto err_platform_unregister;
1338
1339 return 0;
1340
1341 err_platform_unregister:
1342 platform_driver_unregister(&rtl8366s_driver);
1343 return ret;
1344 }
1345 module_init(rtl8366s_module_init);
1346
1347 static void __exit rtl8366s_module_exit(void)
1348 {
1349 phy_driver_unregister(&rtl8366s_phy_driver);
1350 platform_driver_unregister(&rtl8366s_driver);
1351 }
1352 module_exit(rtl8366s_module_exit);
1353
1354 MODULE_DESCRIPTION(RTL8366S_DRIVER_DESC);
1355 MODULE_VERSION(RTL8366S_DRIVER_VER);
1356 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1357 MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>");
1358 MODULE_LICENSE("GPL v2");
1359 MODULE_ALIAS("platform:" RTL8366S_DRIVER_NAME);
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