2 * Platform driver for the Realtek RTL8367R/M ethernet switches
4 * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/init.h>
15 #include <linux/of_platform.h>
16 #include <linux/delay.h>
17 #include <linux/skbuff.h>
18 #include <linux/rtl8367.h>
20 #include "rtl8366_smi.h"
22 #define RTL8367_RESET_DELAY 1000 /* msecs*/
24 #define RTL8367_PHY_ADDR_MAX 8
25 #define RTL8367_PHY_REG_MAX 31
27 #define RTL8367_VID_MASK 0xffff
28 #define RTL8367_FID_MASK 0xfff
29 #define RTL8367_UNTAG_MASK 0xffff
30 #define RTL8367_MEMBER_MASK 0xffff
32 #define RTL8367_PORT_CFG_REG(_p) (0x000e + 0x20 * (_p))
33 #define RTL8367_PORT_CFG_EGRESS_MODE_SHIFT 4
34 #define RTL8367_PORT_CFG_EGRESS_MODE_MASK 0x3
35 #define RTL8367_PORT_CFG_EGRESS_MODE_ORIGINAL 0
36 #define RTL8367_PORT_CFG_EGRESS_MODE_KEEP 1
37 #define RTL8367_PORT_CFG_EGRESS_MODE_PRI 2
38 #define RTL8367_PORT_CFG_EGRESS_MODE_REAL 3
40 #define RTL8367_BYPASS_LINE_RATE_REG 0x03f7
42 #define RTL8367_TA_CTRL_REG 0x0500
43 #define RTL8367_TA_CTRL_STATUS BIT(12)
44 #define RTL8367_TA_CTRL_METHOD BIT(5)
45 #define RTL8367_TA_CTRL_CMD_SHIFT 4
46 #define RTL8367_TA_CTRL_CMD_READ 0
47 #define RTL8367_TA_CTRL_CMD_WRITE 1
48 #define RTL8367_TA_CTRL_TABLE_SHIFT 0
49 #define RTL8367_TA_CTRL_TABLE_ACLRULE 1
50 #define RTL8367_TA_CTRL_TABLE_ACLACT 2
51 #define RTL8367_TA_CTRL_TABLE_CVLAN 3
52 #define RTL8367_TA_CTRL_TABLE_L2 4
53 #define RTL8367_TA_CTRL_CVLAN_READ \
54 ((RTL8367_TA_CTRL_CMD_READ << RTL8367_TA_CTRL_CMD_SHIFT) | \
55 RTL8367_TA_CTRL_TABLE_CVLAN)
56 #define RTL8367_TA_CTRL_CVLAN_WRITE \
57 ((RTL8367_TA_CTRL_CMD_WRITE << RTL8367_TA_CTRL_CMD_SHIFT) | \
58 RTL8367_TA_CTRL_TABLE_CVLAN)
60 #define RTL8367_TA_ADDR_REG 0x0501
61 #define RTL8367_TA_ADDR_MASK 0x3fff
63 #define RTL8367_TA_DATA_REG(_x) (0x0503 + (_x))
64 #define RTL8367_TA_VLAN_DATA_SIZE 4
65 #define RTL8367_TA_VLAN_VID_MASK RTL8367_VID_MASK
66 #define RTL8367_TA_VLAN_MEMBER_SHIFT 0
67 #define RTL8367_TA_VLAN_MEMBER_MASK RTL8367_MEMBER_MASK
68 #define RTL8367_TA_VLAN_FID_SHIFT 0
69 #define RTL8367_TA_VLAN_FID_MASK RTL8367_FID_MASK
70 #define RTL8367_TA_VLAN_UNTAG1_SHIFT 14
71 #define RTL8367_TA_VLAN_UNTAG1_MASK 0x3
72 #define RTL8367_TA_VLAN_UNTAG2_SHIFT 0
73 #define RTL8367_TA_VLAN_UNTAG2_MASK 0x3fff
75 #define RTL8367_VLAN_PVID_CTRL_REG(_p) (0x0700 + (_p) / 2)
76 #define RTL8367_VLAN_PVID_CTRL_MASK 0x1f
77 #define RTL8367_VLAN_PVID_CTRL_SHIFT(_p) (8 * ((_p) % 2))
79 #define RTL8367_VLAN_MC_BASE(_x) (0x0728 + (_x) * 4)
80 #define RTL8367_VLAN_MC_DATA_SIZE 4
81 #define RTL8367_VLAN_MC_MEMBER_SHIFT 0
82 #define RTL8367_VLAN_MC_MEMBER_MASK RTL8367_MEMBER_MASK
83 #define RTL8367_VLAN_MC_FID_SHIFT 0
84 #define RTL8367_VLAN_MC_FID_MASK RTL8367_FID_MASK
85 #define RTL8367_VLAN_MC_EVID_SHIFT 0
86 #define RTL8367_VLAN_MC_EVID_MASK RTL8367_VID_MASK
88 #define RTL8367_VLAN_CTRL_REG 0x07a8
89 #define RTL8367_VLAN_CTRL_ENABLE BIT(0)
91 #define RTL8367_VLAN_INGRESS_REG 0x07a9
93 #define RTL8367_PORT_ISOLATION_REG(_p) (0x08a2 + (_p))
95 #define RTL8367_MIB_COUNTER_REG(_x) (0x1000 + (_x))
97 #define RTL8367_MIB_ADDRESS_REG 0x1004
99 #define RTL8367_MIB_CTRL_REG(_x) (0x1005 + (_x))
100 #define RTL8367_MIB_CTRL_GLOBAL_RESET_MASK BIT(11)
101 #define RTL8367_MIB_CTRL_QM_RESET_MASK BIT(10)
102 #define RTL8367_MIB_CTRL_PORT_RESET_MASK(_p) BIT(2 + (_p))
103 #define RTL8367_MIB_CTRL_RESET_MASK BIT(1)
104 #define RTL8367_MIB_CTRL_BUSY_MASK BIT(0)
106 #define RTL8367_MIB_COUNT 36
107 #define RTL8367_MIB_COUNTER_PORT_OFFSET 0x0050
109 #define RTL8367_SWC0_REG 0x1200
110 #define RTL8367_SWC0_MAX_LENGTH_SHIFT 13
111 #define RTL8367_SWC0_MAX_LENGTH(_x) ((_x) << 13)
112 #define RTL8367_SWC0_MAX_LENGTH_MASK RTL8367_SWC0_MAX_LENGTH(0x3)
113 #define RTL8367_SWC0_MAX_LENGTH_1522 RTL8367_SWC0_MAX_LENGTH(0)
114 #define RTL8367_SWC0_MAX_LENGTH_1536 RTL8367_SWC0_MAX_LENGTH(1)
115 #define RTL8367_SWC0_MAX_LENGTH_1552 RTL8367_SWC0_MAX_LENGTH(2)
116 #define RTL8367_SWC0_MAX_LENGTH_16000 RTL8367_SWC0_MAX_LENGTH(3)
118 #define RTL8367_CHIP_NUMBER_REG 0x1300
120 #define RTL8367_CHIP_VER_REG 0x1301
121 #define RTL8367_CHIP_VER_RLVID_SHIFT 12
122 #define RTL8367_CHIP_VER_RLVID_MASK 0xf
123 #define RTL8367_CHIP_VER_MCID_SHIFT 8
124 #define RTL8367_CHIP_VER_MCID_MASK 0xf
125 #define RTL8367_CHIP_VER_BOID_SHIFT 4
126 #define RTL8367_CHIP_VER_BOID_MASK 0xf
128 #define RTL8367_CHIP_MODE_REG 0x1302
129 #define RTL8367_CHIP_MODE_MASK 0x7
131 #define RTL8367_CHIP_DEBUG0_REG 0x1303
132 #define RTL8367_CHIP_DEBUG0_DUMMY0(_x) BIT(8 + (_x))
134 #define RTL8367_CHIP_DEBUG1_REG 0x1304
136 #define RTL8367_DIS_REG 0x1305
137 #define RTL8367_DIS_SKIP_MII_RXER(_x) BIT(12 + (_x))
138 #define RTL8367_DIS_RGMII_SHIFT(_x) (4 * (_x))
139 #define RTL8367_DIS_RGMII_MASK 0x7
141 #define RTL8367_EXT_RGMXF_REG(_x) (0x1306 + (_x))
142 #define RTL8367_EXT_RGMXF_DUMMY0_SHIFT 5
143 #define RTL8367_EXT_RGMXF_DUMMY0_MASK 0x7ff
144 #define RTL8367_EXT_RGMXF_TXDELAY_SHIFT 3
145 #define RTL8367_EXT_RGMXF_TXDELAY_MASK 1
146 #define RTL8367_EXT_RGMXF_RXDELAY_MASK 0x7
148 #define RTL8367_DI_FORCE_REG(_x) (0x1310 + (_x))
149 #define RTL8367_DI_FORCE_MODE BIT(12)
150 #define RTL8367_DI_FORCE_NWAY BIT(7)
151 #define RTL8367_DI_FORCE_TXPAUSE BIT(6)
152 #define RTL8367_DI_FORCE_RXPAUSE BIT(5)
153 #define RTL8367_DI_FORCE_LINK BIT(4)
154 #define RTL8367_DI_FORCE_DUPLEX BIT(2)
155 #define RTL8367_DI_FORCE_SPEED_MASK 3
156 #define RTL8367_DI_FORCE_SPEED_10 0
157 #define RTL8367_DI_FORCE_SPEED_100 1
158 #define RTL8367_DI_FORCE_SPEED_1000 2
160 #define RTL8367_MAC_FORCE_REG(_x) (0x1312 + (_x))
162 #define RTL8367_CHIP_RESET_REG 0x1322
163 #define RTL8367_CHIP_RESET_SW BIT(1)
164 #define RTL8367_CHIP_RESET_HW BIT(0)
166 #define RTL8367_PORT_STATUS_REG(_p) (0x1352 + (_p))
167 #define RTL8367_PORT_STATUS_NWAY BIT(7)
168 #define RTL8367_PORT_STATUS_TXPAUSE BIT(6)
169 #define RTL8367_PORT_STATUS_RXPAUSE BIT(5)
170 #define RTL8367_PORT_STATUS_LINK BIT(4)
171 #define RTL8367_PORT_STATUS_DUPLEX BIT(2)
172 #define RTL8367_PORT_STATUS_SPEED_MASK 0x0003
173 #define RTL8367_PORT_STATUS_SPEED_10 0
174 #define RTL8367_PORT_STATUS_SPEED_100 1
175 #define RTL8367_PORT_STATUS_SPEED_1000 2
177 #define RTL8367_RTL_NO_REG 0x13c0
178 #define RTL8367_RTL_NO_8367R 0x3670
179 #define RTL8367_RTL_NO_8367M 0x3671
181 #define RTL8367_RTL_VER_REG 0x13c1
182 #define RTL8367_RTL_VER_MASK 0xf
184 #define RTL8367_RTL_MAGIC_ID_REG 0x13c2
185 #define RTL8367_RTL_MAGIC_ID_VAL 0x0249
187 #define RTL8367_LED_SYS_CONFIG_REG 0x1b00
188 #define RTL8367_LED_MODE_REG 0x1b02
189 #define RTL8367_LED_MODE_RATE_M 0x7
190 #define RTL8367_LED_MODE_RATE_S 1
192 #define RTL8367_LED_CONFIG_REG 0x1b03
193 #define RTL8367_LED_CONFIG_DATA_S 12
194 #define RTL8367_LED_CONFIG_DATA_M 0x3
195 #define RTL8367_LED_CONFIG_SEL BIT(14)
196 #define RTL8367_LED_CONFIG_LED_CFG_M 0xf
198 #define RTL8367_PARA_LED_IO_EN1_REG 0x1b24
199 #define RTL8367_PARA_LED_IO_EN2_REG 0x1b25
200 #define RTL8367_PARA_LED_IO_EN_PMASK 0xff
202 #define RTL8367_IA_CTRL_REG 0x1f00
203 #define RTL8367_IA_CTRL_RW(_x) ((_x) << 1)
204 #define RTL8367_IA_CTRL_RW_READ RTL8367_IA_CTRL_RW(0)
205 #define RTL8367_IA_CTRL_RW_WRITE RTL8367_IA_CTRL_RW(1)
206 #define RTL8367_IA_CTRL_CMD_MASK BIT(0)
208 #define RTL8367_IA_STATUS_REG 0x1f01
209 #define RTL8367_IA_STATUS_PHY_BUSY BIT(2)
210 #define RTL8367_IA_STATUS_SDS_BUSY BIT(1)
211 #define RTL8367_IA_STATUS_MDX_BUSY BIT(0)
213 #define RTL8367_IA_ADDRESS_REG 0x1f02
215 #define RTL8367_IA_WRITE_DATA_REG 0x1f03
216 #define RTL8367_IA_READ_DATA_REG 0x1f04
218 #define RTL8367_INTERNAL_PHY_REG(_a, _r) (0x2000 + 32 * (_a) + (_r))
220 #define RTL8367_CPU_PORT_NUM 9
221 #define RTL8367_NUM_PORTS 10
222 #define RTL8367_NUM_VLANS 32
223 #define RTL8367_NUM_LEDGROUPS 4
224 #define RTL8367_NUM_VIDS 4096
225 #define RTL8367_PRIORITYMAX 7
226 #define RTL8367_FIDMAX 7
228 #define RTL8367_PORT_0 BIT(0)
229 #define RTL8367_PORT_1 BIT(1)
230 #define RTL8367_PORT_2 BIT(2)
231 #define RTL8367_PORT_3 BIT(3)
232 #define RTL8367_PORT_4 BIT(4)
233 #define RTL8367_PORT_5 BIT(5)
234 #define RTL8367_PORT_6 BIT(6)
235 #define RTL8367_PORT_7 BIT(7)
236 #define RTL8367_PORT_E1 BIT(8) /* external port 1 */
237 #define RTL8367_PORT_E0 BIT(9) /* external port 0 */
239 #define RTL8367_PORTS_ALL \
240 (RTL8367_PORT_0 | RTL8367_PORT_1 | RTL8367_PORT_2 | \
241 RTL8367_PORT_3 | RTL8367_PORT_4 | RTL8367_PORT_5 | \
242 RTL8367_PORT_6 | RTL8367_PORT_7 | RTL8367_PORT_E1 | \
245 #define RTL8367_PORTS_ALL_BUT_CPU \
246 (RTL8367_PORT_0 | RTL8367_PORT_1 | RTL8367_PORT_2 | \
247 RTL8367_PORT_3 | RTL8367_PORT_4 | RTL8367_PORT_5 | \
248 RTL8367_PORT_6 | RTL8367_PORT_7 | RTL8367_PORT_E1)
250 struct rtl8367_initval
{
255 static struct rtl8366_mib_counter rtl8367_mib_counters
[] = {
256 { 0, 0, 4, "IfInOctets" },
257 { 0, 4, 2, "Dot3StatsFCSErrors" },
258 { 0, 6, 2, "Dot3StatsSymbolErrors" },
259 { 0, 8, 2, "Dot3InPauseFrames" },
260 { 0, 10, 2, "Dot3ControlInUnknownOpcodes" },
261 { 0, 12, 2, "EtherStatsFragments" },
262 { 0, 14, 2, "EtherStatsJabbers" },
263 { 0, 16, 2, "IfInUcastPkts" },
264 { 0, 18, 2, "EtherStatsDropEvents" },
265 { 0, 20, 4, "EtherStatsOctets" },
267 { 0, 24, 2, "EtherStatsUnderSizePkts" },
268 { 0, 26, 2, "EtherOversizeStats" },
269 { 0, 28, 2, "EtherStatsPkts64Octets" },
270 { 0, 30, 2, "EtherStatsPkts65to127Octets" },
271 { 0, 32, 2, "EtherStatsPkts128to255Octets" },
272 { 0, 34, 2, "EtherStatsPkts256to511Octets" },
273 { 0, 36, 2, "EtherStatsPkts512to1023Octets" },
274 { 0, 38, 2, "EtherStatsPkts1024to1518Octets" },
275 { 0, 40, 2, "EtherStatsMulticastPkts" },
276 { 0, 42, 2, "EtherStatsBroadcastPkts" },
278 { 0, 44, 4, "IfOutOctets" },
280 { 0, 48, 2, "Dot3StatsSingleCollisionFrames" },
281 { 0, 50, 2, "Dot3StatMultipleCollisionFrames" },
282 { 0, 52, 2, "Dot3sDeferredTransmissions" },
283 { 0, 54, 2, "Dot3StatsLateCollisions" },
284 { 0, 56, 2, "EtherStatsCollisions" },
285 { 0, 58, 2, "Dot3StatsExcessiveCollisions" },
286 { 0, 60, 2, "Dot3OutPauseFrames" },
287 { 0, 62, 2, "Dot1dBasePortDelayExceededDiscards" },
288 { 0, 64, 2, "Dot1dTpPortInDiscards" },
289 { 0, 66, 2, "IfOutUcastPkts" },
290 { 0, 68, 2, "IfOutMulticastPkts" },
291 { 0, 70, 2, "IfOutBroadcastPkts" },
292 { 0, 72, 2, "OutOampduPkts" },
293 { 0, 74, 2, "InOampduPkts" },
294 { 0, 76, 2, "PktgenPkts" },
297 #define REG_RD(_smi, _reg, _val) \
299 err = rtl8366_smi_read_reg(_smi, _reg, _val); \
304 #define REG_WR(_smi, _reg, _val) \
306 err = rtl8366_smi_write_reg(_smi, _reg, _val); \
311 #define REG_RMW(_smi, _reg, _mask, _val) \
313 err = rtl8366_smi_rmwr(_smi, _reg, _mask, _val); \
318 static const struct rtl8367_initval rtl8367_initvals_0_0
[] = {
319 {0x133f, 0x0030}, {0x133e, 0x000e}, {0x221f, 0x0000}, {0x2215, 0x1006},
320 {0x221f, 0x0005}, {0x2200, 0x00c6}, {0x221f, 0x0007}, {0x221e, 0x0048},
321 {0x2215, 0x6412}, {0x2216, 0x6412}, {0x2217, 0x6412}, {0x2218, 0x6412},
322 {0x2219, 0x6412}, {0x221A, 0x6412}, {0x221f, 0x0001}, {0x220c, 0xdbf0},
323 {0x2209, 0x2576}, {0x2207, 0x287E}, {0x220A, 0x68E5}, {0x221D, 0x3DA4},
324 {0x221C, 0xE7F7}, {0x2214, 0x7F52}, {0x2218, 0x7FCE}, {0x2208, 0x04B7},
325 {0x2206, 0x4072}, {0x2210, 0xF05E}, {0x221B, 0xB414}, {0x221F, 0x0003},
326 {0x221A, 0x06A6}, {0x2210, 0xF05E}, {0x2213, 0x06EB}, {0x2212, 0xF4D2},
327 {0x220E, 0xE120}, {0x2200, 0x7C00}, {0x2202, 0x5FD0}, {0x220D, 0x0207},
328 {0x221f, 0x0002}, {0x2205, 0x0978}, {0x2202, 0x8C01}, {0x2207, 0x3620},
329 {0x221C, 0x0001}, {0x2203, 0x0420}, {0x2204, 0x80C8}, {0x133e, 0x0ede},
330 {0x221f, 0x0002}, {0x220c, 0x0073}, {0x220d, 0xEB65}, {0x220e, 0x51d1},
331 {0x220f, 0x5dcb}, {0x2210, 0x3044}, {0x2211, 0x1800}, {0x2212, 0x7E00},
332 {0x2213, 0x0000}, {0x133f, 0x0010}, {0x133e, 0x0ffe}, {0x207f, 0x0002},
333 {0x2074, 0x3D22}, {0x2075, 0x2000}, {0x2076, 0x6040}, {0x2077, 0x0000},
334 {0x2078, 0x0f0a}, {0x2079, 0x50AB}, {0x207a, 0x0000}, {0x207b, 0x0f0f},
335 {0x205f, 0x0002}, {0x2054, 0xFF00}, {0x2055, 0x000A}, {0x2056, 0x000A},
336 {0x2057, 0x0005}, {0x2058, 0x0005}, {0x2059, 0x0000}, {0x205A, 0x0005},
337 {0x205B, 0x0005}, {0x205C, 0x0005}, {0x209f, 0x0002}, {0x2094, 0x00AA},
338 {0x2095, 0x00AA}, {0x2096, 0x00AA}, {0x2097, 0x00AA}, {0x2098, 0x0055},
339 {0x2099, 0x00AA}, {0x209A, 0x00AA}, {0x209B, 0x00AA}, {0x1363, 0x8354},
340 {0x1270, 0x3333}, {0x1271, 0x3333}, {0x1272, 0x3333}, {0x1330, 0x00DB},
341 {0x1203, 0xff00}, {0x1200, 0x7fc4}, {0x121d, 0x1006}, {0x121e, 0x03e8},
342 {0x121f, 0x02b3}, {0x1220, 0x028f}, {0x1221, 0x029b}, {0x1222, 0x0277},
343 {0x1223, 0x02b3}, {0x1224, 0x028f}, {0x1225, 0x029b}, {0x1226, 0x0277},
344 {0x1227, 0x00c0}, {0x1228, 0x00b4}, {0x122f, 0x00c0}, {0x1230, 0x00b4},
345 {0x1229, 0x0020}, {0x122a, 0x000c}, {0x1231, 0x0030}, {0x1232, 0x0024},
346 {0x0219, 0x0032}, {0x0200, 0x03e8}, {0x0201, 0x03e8}, {0x0202, 0x03e8},
347 {0x0203, 0x03e8}, {0x0204, 0x03e8}, {0x0205, 0x03e8}, {0x0206, 0x03e8},
348 {0x0207, 0x03e8}, {0x0218, 0x0032}, {0x0208, 0x029b}, {0x0209, 0x029b},
349 {0x020a, 0x029b}, {0x020b, 0x029b}, {0x020c, 0x029b}, {0x020d, 0x029b},
350 {0x020e, 0x029b}, {0x020f, 0x029b}, {0x0210, 0x029b}, {0x0211, 0x029b},
351 {0x0212, 0x029b}, {0x0213, 0x029b}, {0x0214, 0x029b}, {0x0215, 0x029b},
352 {0x0216, 0x029b}, {0x0217, 0x029b}, {0x0900, 0x0000}, {0x0901, 0x0000},
353 {0x0902, 0x0000}, {0x0903, 0x0000}, {0x0865, 0x3210}, {0x087b, 0x0000},
354 {0x087c, 0xff00}, {0x087d, 0x0000}, {0x087e, 0x0000}, {0x0801, 0x0100},
355 {0x0802, 0x0100}, {0x1700, 0x014C}, {0x0301, 0x00FF}, {0x12AA, 0x0096},
356 {0x133f, 0x0030}, {0x133e, 0x000e}, {0x221f, 0x0005}, {0x2200, 0x00C4},
357 {0x221f, 0x0000}, {0x2210, 0x05EF}, {0x2204, 0x05E1}, {0x2200, 0x1340},
358 {0x133f, 0x0010}, {0x20A0, 0x1940}, {0x20C0, 0x1940}, {0x20E0, 0x1940},
361 static const struct rtl8367_initval rtl8367_initvals_0_1
[] = {
362 {0x133f, 0x0030}, {0x133e, 0x000e}, {0x221f, 0x0000}, {0x2215, 0x1006},
363 {0x221f, 0x0005}, {0x2200, 0x00c6}, {0x221f, 0x0007}, {0x221e, 0x0048},
364 {0x2215, 0x6412}, {0x2216, 0x6412}, {0x2217, 0x6412}, {0x2218, 0x6412},
365 {0x2219, 0x6412}, {0x221A, 0x6412}, {0x221f, 0x0001}, {0x220c, 0xdbf0},
366 {0x2209, 0x2576}, {0x2207, 0x287E}, {0x220A, 0x68E5}, {0x221D, 0x3DA4},
367 {0x221C, 0xE7F7}, {0x2214, 0x7F52}, {0x2218, 0x7FCE}, {0x2208, 0x04B7},
368 {0x2206, 0x4072}, {0x2210, 0xF05E}, {0x221B, 0xB414}, {0x221F, 0x0003},
369 {0x221A, 0x06A6}, {0x2210, 0xF05E}, {0x2213, 0x06EB}, {0x2212, 0xF4D2},
370 {0x220E, 0xE120}, {0x2200, 0x7C00}, {0x2202, 0x5FD0}, {0x220D, 0x0207},
371 {0x221f, 0x0002}, {0x2205, 0x0978}, {0x2202, 0x8C01}, {0x2207, 0x3620},
372 {0x221C, 0x0001}, {0x2203, 0x0420}, {0x2204, 0x80C8}, {0x133e, 0x0ede},
373 {0x221f, 0x0002}, {0x220c, 0x0073}, {0x220d, 0xEB65}, {0x220e, 0x51d1},
374 {0x220f, 0x5dcb}, {0x2210, 0x3044}, {0x2211, 0x1800}, {0x2212, 0x7E00},
375 {0x2213, 0x0000}, {0x133f, 0x0010}, {0x133e, 0x0ffe}, {0x207f, 0x0002},
376 {0x2074, 0x3D22}, {0x2075, 0x2000}, {0x2076, 0x6040}, {0x2077, 0x0000},
377 {0x2078, 0x0f0a}, {0x2079, 0x50AB}, {0x207a, 0x0000}, {0x207b, 0x0f0f},
378 {0x205f, 0x0002}, {0x2054, 0xFF00}, {0x2055, 0x000A}, {0x2056, 0x000A},
379 {0x2057, 0x0005}, {0x2058, 0x0005}, {0x2059, 0x0000}, {0x205A, 0x0005},
380 {0x205B, 0x0005}, {0x205C, 0x0005}, {0x209f, 0x0002}, {0x2094, 0x00AA},
381 {0x2095, 0x00AA}, {0x2096, 0x00AA}, {0x2097, 0x00AA}, {0x2098, 0x0055},
382 {0x2099, 0x00AA}, {0x209A, 0x00AA}, {0x209B, 0x00AA}, {0x1363, 0x8354},
383 {0x1270, 0x3333}, {0x1271, 0x3333}, {0x1272, 0x3333}, {0x1330, 0x00DB},
384 {0x1203, 0xff00}, {0x1200, 0x7fc4}, {0x121d, 0x1b06}, {0x121e, 0x07f0},
385 {0x121f, 0x0438}, {0x1220, 0x040f}, {0x1221, 0x040f}, {0x1222, 0x03eb},
386 {0x1223, 0x0438}, {0x1224, 0x040f}, {0x1225, 0x040f}, {0x1226, 0x03eb},
387 {0x1227, 0x0144}, {0x1228, 0x0138}, {0x122f, 0x0144}, {0x1230, 0x0138},
388 {0x1229, 0x0020}, {0x122a, 0x000c}, {0x1231, 0x0030}, {0x1232, 0x0024},
389 {0x0219, 0x0032}, {0x0200, 0x07d0}, {0x0201, 0x07d0}, {0x0202, 0x07d0},
390 {0x0203, 0x07d0}, {0x0204, 0x07d0}, {0x0205, 0x07d0}, {0x0206, 0x07d0},
391 {0x0207, 0x07d0}, {0x0218, 0x0032}, {0x0208, 0x0190}, {0x0209, 0x0190},
392 {0x020a, 0x0190}, {0x020b, 0x0190}, {0x020c, 0x0190}, {0x020d, 0x0190},
393 {0x020e, 0x0190}, {0x020f, 0x0190}, {0x0210, 0x0190}, {0x0211, 0x0190},
394 {0x0212, 0x0190}, {0x0213, 0x0190}, {0x0214, 0x0190}, {0x0215, 0x0190},
395 {0x0216, 0x0190}, {0x0217, 0x0190}, {0x0900, 0x0000}, {0x0901, 0x0000},
396 {0x0902, 0x0000}, {0x0903, 0x0000}, {0x0865, 0x3210}, {0x087b, 0x0000},
397 {0x087c, 0xff00}, {0x087d, 0x0000}, {0x087e, 0x0000}, {0x0801, 0x0100},
398 {0x0802, 0x0100}, {0x1700, 0x0125}, {0x0301, 0x00FF}, {0x12AA, 0x0096},
399 {0x133f, 0x0030}, {0x133e, 0x000e}, {0x221f, 0x0005}, {0x2200, 0x00C4},
400 {0x221f, 0x0000}, {0x2210, 0x05EF}, {0x2204, 0x05E1}, {0x2200, 0x1340},
404 static const struct rtl8367_initval rtl8367_initvals_1_0
[] = {
405 {0x1B24, 0x0000}, {0x1B25, 0x0000}, {0x1B26, 0x0000}, {0x1B27, 0x0000},
406 {0x207F, 0x0002}, {0x2079, 0x0200}, {0x207F, 0x0000}, {0x133F, 0x0030},
407 {0x133E, 0x000E}, {0x221F, 0x0005}, {0x2201, 0x0700}, {0x2205, 0x8B82},
408 {0x2206, 0x05CB}, {0x221F, 0x0002}, {0x2204, 0x80C2}, {0x2205, 0x0938},
409 {0x221F, 0x0003}, {0x2212, 0xC4D2}, {0x220D, 0x0207}, {0x221F, 0x0001},
410 {0x2207, 0x267E}, {0x221C, 0xE5F7}, {0x221B, 0x0424}, {0x221F, 0x0007},
411 {0x221E, 0x0040}, {0x2218, 0x0000}, {0x221F, 0x0007}, {0x221E, 0x002C},
412 {0x2218, 0x008B}, {0x221F, 0x0005}, {0x2205, 0xFFF6}, {0x2206, 0x0080},
413 {0x2205, 0x8000}, {0x2206, 0xF8E0}, {0x2206, 0xE000}, {0x2206, 0xE1E0},
414 {0x2206, 0x01AC}, {0x2206, 0x2408}, {0x2206, 0xE08B}, {0x2206, 0x84F7},
415 {0x2206, 0x20E4}, {0x2206, 0x8B84}, {0x2206, 0xFC05}, {0x2206, 0xF8FA},
416 {0x2206, 0xEF69}, {0x2206, 0xE08B}, {0x2206, 0x86AC}, {0x2206, 0x201A},
417 {0x2206, 0xBF80}, {0x2206, 0x59D0}, {0x2206, 0x2402}, {0x2206, 0x803D},
418 {0x2206, 0xE0E0}, {0x2206, 0xE4E1}, {0x2206, 0xE0E5}, {0x2206, 0x5806},
419 {0x2206, 0x68C0}, {0x2206, 0xD1D2}, {0x2206, 0xE4E0}, {0x2206, 0xE4E5},
420 {0x2206, 0xE0E5}, {0x2206, 0xEF96}, {0x2206, 0xFEFC}, {0x2206, 0x05FB},
421 {0x2206, 0x0BFB}, {0x2206, 0x58FF}, {0x2206, 0x9E11}, {0x2206, 0x06F0},
422 {0x2206, 0x0C81}, {0x2206, 0x8AE0}, {0x2206, 0x0019}, {0x2206, 0x1B89},
423 {0x2206, 0xCFEB}, {0x2206, 0x19EB}, {0x2206, 0x19B0}, {0x2206, 0xEFFF},
424 {0x2206, 0x0BFF}, {0x2206, 0x0425}, {0x2206, 0x0807}, {0x2206, 0x2640},
425 {0x2206, 0x7227}, {0x2206, 0x267E}, {0x2206, 0x2804}, {0x2206, 0xB729},
426 {0x2206, 0x2576}, {0x2206, 0x2A68}, {0x2206, 0xE52B}, {0x2206, 0xAD00},
427 {0x2206, 0x2CDB}, {0x2206, 0xF02D}, {0x2206, 0x67BB}, {0x2206, 0x2E7B},
428 {0x2206, 0x0F2F}, {0x2206, 0x7365}, {0x2206, 0x31AC}, {0x2206, 0xCC32},
429 {0x2206, 0x2300}, {0x2206, 0x332D}, {0x2206, 0x1734}, {0x2206, 0x7F52},
430 {0x2206, 0x3510}, {0x2206, 0x0036}, {0x2206, 0x0600}, {0x2206, 0x370C},
431 {0x2206, 0xC038}, {0x2206, 0x7FCE}, {0x2206, 0x3CE5}, {0x2206, 0xF73D},
432 {0x2206, 0x3DA4}, {0x2206, 0x6530}, {0x2206, 0x3E67}, {0x2206, 0x0053},
433 {0x2206, 0x69D2}, {0x2206, 0x0F6A}, {0x2206, 0x012C}, {0x2206, 0x6C2B},
434 {0x2206, 0x136E}, {0x2206, 0xE100}, {0x2206, 0x6F12}, {0x2206, 0xF771},
435 {0x2206, 0x006B}, {0x2206, 0x7306}, {0x2206, 0xEB74}, {0x2206, 0x94C7},
436 {0x2206, 0x7698}, {0x2206, 0x0A77}, {0x2206, 0x5000}, {0x2206, 0x788A},
437 {0x2206, 0x1579}, {0x2206, 0x7F6F}, {0x2206, 0x7A06}, {0x2206, 0xA600},
438 {0x2205, 0x8B90}, {0x2206, 0x8000}, {0x2205, 0x8B92}, {0x2206, 0x8000},
439 {0x2205, 0x8B94}, {0x2206, 0x8014}, {0x2208, 0xFFFA}, {0x2202, 0x3C65},
440 {0x2205, 0xFFF6}, {0x2206, 0x00F7}, {0x221F, 0x0000}, {0x221F, 0x0007},
441 {0x221E, 0x0042}, {0x2218, 0x0000}, {0x221E, 0x002D}, {0x2218, 0xF010},
442 {0x221E, 0x0020}, {0x2215, 0x0000}, {0x221E, 0x0023}, {0x2216, 0x8000},
443 {0x221F, 0x0000}, {0x133F, 0x0010}, {0x133E, 0x0FFE}, {0x1362, 0x0115},
444 {0x1363, 0x0002}, {0x1363, 0x0000}, {0x1306, 0x000C}, {0x1307, 0x000C},
445 {0x1303, 0x0067}, {0x1304, 0x4444}, {0x1203, 0xFF00}, {0x1200, 0x7FC4},
446 {0x121D, 0x7D16}, {0x121E, 0x03E8}, {0x121F, 0x024E}, {0x1220, 0x0230},
447 {0x1221, 0x0244}, {0x1222, 0x0226}, {0x1223, 0x024E}, {0x1224, 0x0230},
448 {0x1225, 0x0244}, {0x1226, 0x0226}, {0x1227, 0x00C0}, {0x1228, 0x00B4},
449 {0x122F, 0x00C0}, {0x1230, 0x00B4}, {0x0208, 0x03E8}, {0x0209, 0x03E8},
450 {0x020A, 0x03E8}, {0x020B, 0x03E8}, {0x020C, 0x03E8}, {0x020D, 0x03E8},
451 {0x020E, 0x03E8}, {0x020F, 0x03E8}, {0x0210, 0x03E8}, {0x0211, 0x03E8},
452 {0x0212, 0x03E8}, {0x0213, 0x03E8}, {0x0214, 0x03E8}, {0x0215, 0x03E8},
453 {0x0216, 0x03E8}, {0x0217, 0x03E8}, {0x0900, 0x0000}, {0x0901, 0x0000},
454 {0x0902, 0x0000}, {0x0903, 0x0000}, {0x0865, 0x3210}, {0x087B, 0x0000},
455 {0x087C, 0xFF00}, {0x087D, 0x0000}, {0x087E, 0x0000}, {0x0801, 0x0100},
456 {0x0802, 0x0100}, {0x0A20, 0x2040}, {0x0A21, 0x2040}, {0x0A22, 0x2040},
457 {0x0A23, 0x2040}, {0x0A24, 0x2040}, {0x0A28, 0x2040}, {0x0A29, 0x2040},
458 {0x133F, 0x0030}, {0x133E, 0x000E}, {0x221F, 0x0000}, {0x2200, 0x1340},
459 {0x221F, 0x0000}, {0x133F, 0x0010}, {0x133E, 0x0FFE}, {0x20A0, 0x1940},
460 {0x20C0, 0x1940}, {0x20E0, 0x1940}, {0x130c, 0x0050},
463 static const struct rtl8367_initval rtl8367_initvals_1_1
[] = {
464 {0x1B24, 0x0000}, {0x1B25, 0x0000}, {0x1B26, 0x0000}, {0x1B27, 0x0000},
465 {0x207F, 0x0002}, {0x2079, 0x0200}, {0x207F, 0x0000}, {0x133F, 0x0030},
466 {0x133E, 0x000E}, {0x221F, 0x0005}, {0x2201, 0x0700}, {0x2205, 0x8B82},
467 {0x2206, 0x05CB}, {0x221F, 0x0002}, {0x2204, 0x80C2}, {0x2205, 0x0938},
468 {0x221F, 0x0003}, {0x2212, 0xC4D2}, {0x220D, 0x0207}, {0x221F, 0x0001},
469 {0x2207, 0x267E}, {0x221C, 0xE5F7}, {0x221B, 0x0424}, {0x221F, 0x0007},
470 {0x221E, 0x0040}, {0x2218, 0x0000}, {0x221F, 0x0007}, {0x221E, 0x002C},
471 {0x2218, 0x008B}, {0x221F, 0x0005}, {0x2205, 0xFFF6}, {0x2206, 0x0080},
472 {0x2205, 0x8000}, {0x2206, 0xF8E0}, {0x2206, 0xE000}, {0x2206, 0xE1E0},
473 {0x2206, 0x01AC}, {0x2206, 0x2408}, {0x2206, 0xE08B}, {0x2206, 0x84F7},
474 {0x2206, 0x20E4}, {0x2206, 0x8B84}, {0x2206, 0xFC05}, {0x2206, 0xF8FA},
475 {0x2206, 0xEF69}, {0x2206, 0xE08B}, {0x2206, 0x86AC}, {0x2206, 0x201A},
476 {0x2206, 0xBF80}, {0x2206, 0x59D0}, {0x2206, 0x2402}, {0x2206, 0x803D},
477 {0x2206, 0xE0E0}, {0x2206, 0xE4E1}, {0x2206, 0xE0E5}, {0x2206, 0x5806},
478 {0x2206, 0x68C0}, {0x2206, 0xD1D2}, {0x2206, 0xE4E0}, {0x2206, 0xE4E5},
479 {0x2206, 0xE0E5}, {0x2206, 0xEF96}, {0x2206, 0xFEFC}, {0x2206, 0x05FB},
480 {0x2206, 0x0BFB}, {0x2206, 0x58FF}, {0x2206, 0x9E11}, {0x2206, 0x06F0},
481 {0x2206, 0x0C81}, {0x2206, 0x8AE0}, {0x2206, 0x0019}, {0x2206, 0x1B89},
482 {0x2206, 0xCFEB}, {0x2206, 0x19EB}, {0x2206, 0x19B0}, {0x2206, 0xEFFF},
483 {0x2206, 0x0BFF}, {0x2206, 0x0425}, {0x2206, 0x0807}, {0x2206, 0x2640},
484 {0x2206, 0x7227}, {0x2206, 0x267E}, {0x2206, 0x2804}, {0x2206, 0xB729},
485 {0x2206, 0x2576}, {0x2206, 0x2A68}, {0x2206, 0xE52B}, {0x2206, 0xAD00},
486 {0x2206, 0x2CDB}, {0x2206, 0xF02D}, {0x2206, 0x67BB}, {0x2206, 0x2E7B},
487 {0x2206, 0x0F2F}, {0x2206, 0x7365}, {0x2206, 0x31AC}, {0x2206, 0xCC32},
488 {0x2206, 0x2300}, {0x2206, 0x332D}, {0x2206, 0x1734}, {0x2206, 0x7F52},
489 {0x2206, 0x3510}, {0x2206, 0x0036}, {0x2206, 0x0600}, {0x2206, 0x370C},
490 {0x2206, 0xC038}, {0x2206, 0x7FCE}, {0x2206, 0x3CE5}, {0x2206, 0xF73D},
491 {0x2206, 0x3DA4}, {0x2206, 0x6530}, {0x2206, 0x3E67}, {0x2206, 0x0053},
492 {0x2206, 0x69D2}, {0x2206, 0x0F6A}, {0x2206, 0x012C}, {0x2206, 0x6C2B},
493 {0x2206, 0x136E}, {0x2206, 0xE100}, {0x2206, 0x6F12}, {0x2206, 0xF771},
494 {0x2206, 0x006B}, {0x2206, 0x7306}, {0x2206, 0xEB74}, {0x2206, 0x94C7},
495 {0x2206, 0x7698}, {0x2206, 0x0A77}, {0x2206, 0x5000}, {0x2206, 0x788A},
496 {0x2206, 0x1579}, {0x2206, 0x7F6F}, {0x2206, 0x7A06}, {0x2206, 0xA600},
497 {0x2205, 0x8B90}, {0x2206, 0x8000}, {0x2205, 0x8B92}, {0x2206, 0x8000},
498 {0x2205, 0x8B94}, {0x2206, 0x8014}, {0x2208, 0xFFFA}, {0x2202, 0x3C65},
499 {0x2205, 0xFFF6}, {0x2206, 0x00F7}, {0x221F, 0x0000}, {0x221F, 0x0007},
500 {0x221E, 0x0042}, {0x2218, 0x0000}, {0x221E, 0x002D}, {0x2218, 0xF010},
501 {0x221E, 0x0020}, {0x2215, 0x0000}, {0x221E, 0x0023}, {0x2216, 0x8000},
502 {0x221F, 0x0000}, {0x133F, 0x0010}, {0x133E, 0x0FFE}, {0x1362, 0x0115},
503 {0x1363, 0x0002}, {0x1363, 0x0000}, {0x1306, 0x000C}, {0x1307, 0x000C},
504 {0x1303, 0x0067}, {0x1304, 0x4444}, {0x1203, 0xFF00}, {0x1200, 0x7FC4},
505 {0x0900, 0x0000}, {0x0901, 0x0000}, {0x0902, 0x0000}, {0x0903, 0x0000},
506 {0x0865, 0x3210}, {0x087B, 0x0000}, {0x087C, 0xFF00}, {0x087D, 0x0000},
507 {0x087E, 0x0000}, {0x0801, 0x0100}, {0x0802, 0x0100}, {0x0A20, 0x2040},
508 {0x0A21, 0x2040}, {0x0A22, 0x2040}, {0x0A23, 0x2040}, {0x0A24, 0x2040},
509 {0x0A25, 0x2040}, {0x0A26, 0x2040}, {0x0A27, 0x2040}, {0x0A28, 0x2040},
510 {0x0A29, 0x2040}, {0x133F, 0x0030}, {0x133E, 0x000E}, {0x221F, 0x0000},
511 {0x2200, 0x1340}, {0x221F, 0x0000}, {0x133F, 0x0010}, {0x133E, 0x0FFE},
515 static const struct rtl8367_initval rtl8367_initvals_2_0
[] = {
516 {0x1b24, 0x0000}, {0x1b25, 0x0000}, {0x1b26, 0x0000}, {0x1b27, 0x0000},
517 {0x133f, 0x0030}, {0x133e, 0x000e}, {0x221f, 0x0007}, {0x221e, 0x0048},
518 {0x2219, 0x4012}, {0x221f, 0x0003}, {0x2201, 0x3554}, {0x2202, 0x63e8},
519 {0x2203, 0x99c2}, {0x2204, 0x0113}, {0x2205, 0x303e}, {0x220d, 0x0207},
520 {0x220e, 0xe100}, {0x221f, 0x0007}, {0x221e, 0x0040}, {0x2218, 0x0000},
521 {0x221f, 0x0007}, {0x221e, 0x002c}, {0x2218, 0x008b}, {0x221f, 0x0005},
522 {0x2205, 0xfff6}, {0x2206, 0x0080}, {0x221f, 0x0005}, {0x2205, 0x8000},
523 {0x2206, 0x0280}, {0x2206, 0x2bf7}, {0x2206, 0x00e0}, {0x2206, 0xfff7},
524 {0x2206, 0xa080}, {0x2206, 0x02ae}, {0x2206, 0xf602}, {0x2206, 0x804e},
525 {0x2206, 0x0201}, {0x2206, 0x5002}, {0x2206, 0x0163}, {0x2206, 0x0201},
526 {0x2206, 0x79e0}, {0x2206, 0x8b8c}, {0x2206, 0xe18b}, {0x2206, 0x8d1e},
527 {0x2206, 0x01e1}, {0x2206, 0x8b8e}, {0x2206, 0x1e01}, {0x2206, 0xa000},
528 {0x2206, 0xe4ae}, {0x2206, 0xd8bf}, {0x2206, 0x8b88}, {0x2206, 0xec00},
529 {0x2206, 0x19a9}, {0x2206, 0x8b90}, {0x2206, 0xf9ee}, {0x2206, 0xfff6},
530 {0x2206, 0x00ee}, {0x2206, 0xfff7}, {0x2206, 0xfce0}, {0x2206, 0xe140},
531 {0x2206, 0xe1e1}, {0x2206, 0x41f7}, {0x2206, 0x2ff6}, {0x2206, 0x28e4},
532 {0x2206, 0xe140}, {0x2206, 0xe5e1}, {0x2206, 0x4104}, {0x2206, 0xf8fa},
533 {0x2206, 0xef69}, {0x2206, 0xe08b}, {0x2206, 0x86ac}, {0x2206, 0x201a},
534 {0x2206, 0xbf80}, {0x2206, 0x77d0}, {0x2206, 0x6c02}, {0x2206, 0x2978},
535 {0x2206, 0xe0e0}, {0x2206, 0xe4e1}, {0x2206, 0xe0e5}, {0x2206, 0x5806},
536 {0x2206, 0x68c0}, {0x2206, 0xd1d2}, {0x2206, 0xe4e0}, {0x2206, 0xe4e5},
537 {0x2206, 0xe0e5}, {0x2206, 0xef96}, {0x2206, 0xfefc}, {0x2206, 0x0425},
538 {0x2206, 0x0807}, {0x2206, 0x2640}, {0x2206, 0x7227}, {0x2206, 0x267e},
539 {0x2206, 0x2804}, {0x2206, 0xb729}, {0x2206, 0x2576}, {0x2206, 0x2a68},
540 {0x2206, 0xe52b}, {0x2206, 0xad00}, {0x2206, 0x2cdb}, {0x2206, 0xf02d},
541 {0x2206, 0x67bb}, {0x2206, 0x2e7b}, {0x2206, 0x0f2f}, {0x2206, 0x7365},
542 {0x2206, 0x31ac}, {0x2206, 0xcc32}, {0x2206, 0x2300}, {0x2206, 0x332d},
543 {0x2206, 0x1734}, {0x2206, 0x7f52}, {0x2206, 0x3510}, {0x2206, 0x0036},
544 {0x2206, 0x0600}, {0x2206, 0x370c}, {0x2206, 0xc038}, {0x2206, 0x7fce},
545 {0x2206, 0x3ce5}, {0x2206, 0xf73d}, {0x2206, 0x3da4}, {0x2206, 0x6530},
546 {0x2206, 0x3e67}, {0x2206, 0x0053}, {0x2206, 0x69d2}, {0x2206, 0x0f6a},
547 {0x2206, 0x012c}, {0x2206, 0x6c2b}, {0x2206, 0x136e}, {0x2206, 0xe100},
548 {0x2206, 0x6f12}, {0x2206, 0xf771}, {0x2206, 0x006b}, {0x2206, 0x7306},
549 {0x2206, 0xeb74}, {0x2206, 0x94c7}, {0x2206, 0x7698}, {0x2206, 0x0a77},
550 {0x2206, 0x5000}, {0x2206, 0x788a}, {0x2206, 0x1579}, {0x2206, 0x7f6f},
551 {0x2206, 0x7a06}, {0x2206, 0xa600}, {0x2201, 0x0701}, {0x2200, 0x0405},
552 {0x221f, 0x0000}, {0x2200, 0x1340}, {0x221f, 0x0000}, {0x133f, 0x0010},
553 {0x133e, 0x0ffe}, {0x1203, 0xff00}, {0x1200, 0x7fc4}, {0x121d, 0x7D16},
554 {0x121e, 0x03e8}, {0x121f, 0x024e}, {0x1220, 0x0230}, {0x1221, 0x0244},
555 {0x1222, 0x0226}, {0x1223, 0x024e}, {0x1224, 0x0230}, {0x1225, 0x0244},
556 {0x1226, 0x0226}, {0x1227, 0x00c0}, {0x1228, 0x00b4}, {0x122f, 0x00c0},
557 {0x1230, 0x00b4}, {0x0208, 0x03e8}, {0x0209, 0x03e8}, {0x020a, 0x03e8},
558 {0x020b, 0x03e8}, {0x020c, 0x03e8}, {0x020d, 0x03e8}, {0x020e, 0x03e8},
559 {0x020f, 0x03e8}, {0x0210, 0x03e8}, {0x0211, 0x03e8}, {0x0212, 0x03e8},
560 {0x0213, 0x03e8}, {0x0214, 0x03e8}, {0x0215, 0x03e8}, {0x0216, 0x03e8},
561 {0x0217, 0x03e8}, {0x0900, 0x0000}, {0x0901, 0x0000}, {0x0902, 0x0000},
562 {0x0903, 0x0000}, {0x0865, 0x3210}, {0x087b, 0x0000}, {0x087c, 0xff00},
563 {0x087d, 0x0000}, {0x087e, 0x0000}, {0x0801, 0x0100}, {0x0802, 0x0100},
564 {0x0A20, 0x2040}, {0x0A21, 0x2040}, {0x0A22, 0x2040}, {0x0A23, 0x2040},
565 {0x0A24, 0x2040}, {0x0A28, 0x2040}, {0x0A29, 0x2040}, {0x20A0, 0x1940},
566 {0x20C0, 0x1940}, {0x20E0, 0x1940}, {0x130c, 0x0050},
569 static const struct rtl8367_initval rtl8367_initvals_2_1
[] = {
570 {0x1b24, 0x0000}, {0x1b25, 0x0000}, {0x1b26, 0x0000}, {0x1b27, 0x0000},
571 {0x133f, 0x0030}, {0x133e, 0x000e}, {0x221f, 0x0007}, {0x221e, 0x0048},
572 {0x2219, 0x4012}, {0x221f, 0x0003}, {0x2201, 0x3554}, {0x2202, 0x63e8},
573 {0x2203, 0x99c2}, {0x2204, 0x0113}, {0x2205, 0x303e}, {0x220d, 0x0207},
574 {0x220e, 0xe100}, {0x221f, 0x0007}, {0x221e, 0x0040}, {0x2218, 0x0000},
575 {0x221f, 0x0007}, {0x221e, 0x002c}, {0x2218, 0x008b}, {0x221f, 0x0005},
576 {0x2205, 0xfff6}, {0x2206, 0x0080}, {0x221f, 0x0005}, {0x2205, 0x8000},
577 {0x2206, 0x0280}, {0x2206, 0x2bf7}, {0x2206, 0x00e0}, {0x2206, 0xfff7},
578 {0x2206, 0xa080}, {0x2206, 0x02ae}, {0x2206, 0xf602}, {0x2206, 0x804e},
579 {0x2206, 0x0201}, {0x2206, 0x5002}, {0x2206, 0x0163}, {0x2206, 0x0201},
580 {0x2206, 0x79e0}, {0x2206, 0x8b8c}, {0x2206, 0xe18b}, {0x2206, 0x8d1e},
581 {0x2206, 0x01e1}, {0x2206, 0x8b8e}, {0x2206, 0x1e01}, {0x2206, 0xa000},
582 {0x2206, 0xe4ae}, {0x2206, 0xd8bf}, {0x2206, 0x8b88}, {0x2206, 0xec00},
583 {0x2206, 0x19a9}, {0x2206, 0x8b90}, {0x2206, 0xf9ee}, {0x2206, 0xfff6},
584 {0x2206, 0x00ee}, {0x2206, 0xfff7}, {0x2206, 0xfce0}, {0x2206, 0xe140},
585 {0x2206, 0xe1e1}, {0x2206, 0x41f7}, {0x2206, 0x2ff6}, {0x2206, 0x28e4},
586 {0x2206, 0xe140}, {0x2206, 0xe5e1}, {0x2206, 0x4104}, {0x2206, 0xf8fa},
587 {0x2206, 0xef69}, {0x2206, 0xe08b}, {0x2206, 0x86ac}, {0x2206, 0x201a},
588 {0x2206, 0xbf80}, {0x2206, 0x77d0}, {0x2206, 0x6c02}, {0x2206, 0x2978},
589 {0x2206, 0xe0e0}, {0x2206, 0xe4e1}, {0x2206, 0xe0e5}, {0x2206, 0x5806},
590 {0x2206, 0x68c0}, {0x2206, 0xd1d2}, {0x2206, 0xe4e0}, {0x2206, 0xe4e5},
591 {0x2206, 0xe0e5}, {0x2206, 0xef96}, {0x2206, 0xfefc}, {0x2206, 0x0425},
592 {0x2206, 0x0807}, {0x2206, 0x2640}, {0x2206, 0x7227}, {0x2206, 0x267e},
593 {0x2206, 0x2804}, {0x2206, 0xb729}, {0x2206, 0x2576}, {0x2206, 0x2a68},
594 {0x2206, 0xe52b}, {0x2206, 0xad00}, {0x2206, 0x2cdb}, {0x2206, 0xf02d},
595 {0x2206, 0x67bb}, {0x2206, 0x2e7b}, {0x2206, 0x0f2f}, {0x2206, 0x7365},
596 {0x2206, 0x31ac}, {0x2206, 0xcc32}, {0x2206, 0x2300}, {0x2206, 0x332d},
597 {0x2206, 0x1734}, {0x2206, 0x7f52}, {0x2206, 0x3510}, {0x2206, 0x0036},
598 {0x2206, 0x0600}, {0x2206, 0x370c}, {0x2206, 0xc038}, {0x2206, 0x7fce},
599 {0x2206, 0x3ce5}, {0x2206, 0xf73d}, {0x2206, 0x3da4}, {0x2206, 0x6530},
600 {0x2206, 0x3e67}, {0x2206, 0x0053}, {0x2206, 0x69d2}, {0x2206, 0x0f6a},
601 {0x2206, 0x012c}, {0x2206, 0x6c2b}, {0x2206, 0x136e}, {0x2206, 0xe100},
602 {0x2206, 0x6f12}, {0x2206, 0xf771}, {0x2206, 0x006b}, {0x2206, 0x7306},
603 {0x2206, 0xeb74}, {0x2206, 0x94c7}, {0x2206, 0x7698}, {0x2206, 0x0a77},
604 {0x2206, 0x5000}, {0x2206, 0x788a}, {0x2206, 0x1579}, {0x2206, 0x7f6f},
605 {0x2206, 0x7a06}, {0x2206, 0xa600}, {0x2201, 0x0701}, {0x2200, 0x0405},
606 {0x221f, 0x0000}, {0x2200, 0x1340}, {0x221f, 0x0000}, {0x133f, 0x0010},
607 {0x133e, 0x0ffe}, {0x1203, 0xff00}, {0x1200, 0x7fc4}, {0x0900, 0x0000},
608 {0x0901, 0x0000}, {0x0902, 0x0000}, {0x0903, 0x0000}, {0x0865, 0x3210},
609 {0x087b, 0x0000}, {0x087c, 0xff00}, {0x087d, 0x0000}, {0x087e, 0x0000},
610 {0x0801, 0x0100}, {0x0802, 0x0100}, {0x0A20, 0x2040}, {0x0A21, 0x2040},
611 {0x0A22, 0x2040}, {0x0A23, 0x2040}, {0x0A24, 0x2040}, {0x0A25, 0x2040},
612 {0x0A26, 0x2040}, {0x0A27, 0x2040}, {0x0A28, 0x2040}, {0x0A29, 0x2040},
616 static int rtl8367_write_initvals(struct rtl8366_smi
*smi
,
617 const struct rtl8367_initval
*initvals
,
623 for (i
= 0; i
< count
; i
++)
624 REG_WR(smi
, initvals
[i
].reg
, initvals
[i
].val
);
629 static int rtl8367_read_phy_reg(struct rtl8366_smi
*smi
,
630 u32 phy_addr
, u32 phy_reg
, u32
*val
)
636 if (phy_addr
> RTL8367_PHY_ADDR_MAX
)
639 if (phy_reg
> RTL8367_PHY_REG_MAX
)
642 REG_RD(smi
, RTL8367_IA_STATUS_REG
, &data
);
643 if (data
& RTL8367_IA_STATUS_PHY_BUSY
)
646 /* prepare address */
647 REG_WR(smi
, RTL8367_IA_ADDRESS_REG
,
648 RTL8367_INTERNAL_PHY_REG(phy_addr
, phy_reg
));
650 /* send read command */
651 REG_WR(smi
, RTL8367_IA_CTRL_REG
,
652 RTL8367_IA_CTRL_CMD_MASK
| RTL8367_IA_CTRL_RW_READ
);
656 REG_RD(smi
, RTL8367_IA_STATUS_REG
, &data
);
657 if ((data
& RTL8367_IA_STATUS_PHY_BUSY
) == 0)
661 dev_err(smi
->parent
, "phy read timed out\n");
669 REG_RD(smi
, RTL8367_IA_READ_DATA_REG
, val
);
671 dev_dbg(smi
->parent
, "phy_read: addr:%02x, reg:%02x, val:%04x\n",
672 phy_addr
, phy_reg
, *val
);
676 static int rtl8367_write_phy_reg(struct rtl8366_smi
*smi
,
677 u32 phy_addr
, u32 phy_reg
, u32 val
)
683 dev_dbg(smi
->parent
, "phy_write: addr:%02x, reg:%02x, val:%04x\n",
684 phy_addr
, phy_reg
, val
);
686 if (phy_addr
> RTL8367_PHY_ADDR_MAX
)
689 if (phy_reg
> RTL8367_PHY_REG_MAX
)
692 REG_RD(smi
, RTL8367_IA_STATUS_REG
, &data
);
693 if (data
& RTL8367_IA_STATUS_PHY_BUSY
)
697 REG_WR(smi
, RTL8367_IA_WRITE_DATA_REG
, val
);
699 /* prepare address */
700 REG_WR(smi
, RTL8367_IA_ADDRESS_REG
,
701 RTL8367_INTERNAL_PHY_REG(phy_addr
, phy_reg
));
703 /* send write command */
704 REG_WR(smi
, RTL8367_IA_CTRL_REG
,
705 RTL8367_IA_CTRL_CMD_MASK
| RTL8367_IA_CTRL_RW_WRITE
);
709 REG_RD(smi
, RTL8367_IA_STATUS_REG
, &data
);
710 if ((data
& RTL8367_IA_STATUS_PHY_BUSY
) == 0)
714 dev_err(smi
->parent
, "phy write timed out\n");
724 static int rtl8367_init_regs0(struct rtl8366_smi
*smi
, unsigned mode
)
726 const struct rtl8367_initval
*initvals
;
732 initvals
= rtl8367_initvals_0_0
;
733 count
= ARRAY_SIZE(rtl8367_initvals_0_0
);
738 initvals
= rtl8367_initvals_0_1
;
739 count
= ARRAY_SIZE(rtl8367_initvals_0_1
);
743 dev_err(smi
->parent
, "%s: unknow mode %u\n", __func__
, mode
);
747 err
= rtl8367_write_initvals(smi
, initvals
, count
);
751 /* TODO: complete this */
756 static int rtl8367_init_regs1(struct rtl8366_smi
*smi
, unsigned mode
)
758 const struct rtl8367_initval
*initvals
;
763 initvals
= rtl8367_initvals_1_0
;
764 count
= ARRAY_SIZE(rtl8367_initvals_1_0
);
769 initvals
= rtl8367_initvals_1_1
;
770 count
= ARRAY_SIZE(rtl8367_initvals_1_1
);
774 dev_err(smi
->parent
, "%s: unknow mode %u\n", __func__
, mode
);
778 return rtl8367_write_initvals(smi
, initvals
, count
);
781 static int rtl8367_init_regs2(struct rtl8366_smi
*smi
, unsigned mode
)
783 const struct rtl8367_initval
*initvals
;
788 initvals
= rtl8367_initvals_2_0
;
789 count
= ARRAY_SIZE(rtl8367_initvals_2_0
);
794 initvals
= rtl8367_initvals_2_1
;
795 count
= ARRAY_SIZE(rtl8367_initvals_2_1
);
799 dev_err(smi
->parent
, "%s: unknow mode %u\n", __func__
, mode
);
803 return rtl8367_write_initvals(smi
, initvals
, count
);
806 static int rtl8367_init_regs(struct rtl8366_smi
*smi
)
813 REG_WR(smi
, RTL8367_RTL_MAGIC_ID_REG
, RTL8367_RTL_MAGIC_ID_VAL
);
815 REG_RD(smi
, RTL8367_CHIP_VER_REG
, &data
);
816 rlvid
= (data
>> RTL8367_CHIP_VER_RLVID_SHIFT
) &
817 RTL8367_CHIP_VER_RLVID_MASK
;
819 REG_RD(smi
, RTL8367_CHIP_MODE_REG
, &data
);
820 mode
= data
& RTL8367_CHIP_MODE_MASK
;
824 err
= rtl8367_init_regs0(smi
, mode
);
828 err
= rtl8367_write_phy_reg(smi
, 0, 31, 5);
832 err
= rtl8367_write_phy_reg(smi
, 0, 5, 0x3ffe);
836 err
= rtl8367_read_phy_reg(smi
, 0, 6, &data
);
840 if (data
== 0x94eb) {
841 err
= rtl8367_init_regs1(smi
, mode
);
842 } else if (data
== 0x2104) {
843 err
= rtl8367_init_regs2(smi
, mode
);
845 dev_err(smi
->parent
, "unknow phy data %04x\n", data
);
852 dev_err(smi
->parent
, "unknow rlvid %u\n", rlvid
);
860 static int rtl8367_reset_chip(struct rtl8366_smi
*smi
)
866 REG_WR(smi
, RTL8367_CHIP_RESET_REG
, RTL8367_CHIP_RESET_HW
);
867 msleep(RTL8367_RESET_DELAY
);
870 REG_RD(smi
, RTL8367_CHIP_RESET_REG
, &data
);
871 if (!(data
& RTL8367_CHIP_RESET_HW
))
878 dev_err(smi
->parent
, "chip reset timed out\n");
885 static int rtl8367_extif_set_mode(struct rtl8366_smi
*smi
, int id
,
886 enum rtl8367_extif_mode mode
)
892 case RTL8367_EXTIF_MODE_RGMII
:
893 case RTL8367_EXTIF_MODE_RGMII_33V
:
894 REG_WR(smi
, RTL8367_CHIP_DEBUG0_REG
, 0x0367);
895 REG_WR(smi
, RTL8367_CHIP_DEBUG1_REG
, 0x7777);
898 case RTL8367_EXTIF_MODE_TMII_MAC
:
899 case RTL8367_EXTIF_MODE_TMII_PHY
:
900 REG_RMW(smi
, RTL8367_BYPASS_LINE_RATE_REG
,
901 BIT((id
+ 1) % 2), BIT((id
+ 1) % 2));
904 case RTL8367_EXTIF_MODE_GMII
:
905 REG_RMW(smi
, RTL8367_CHIP_DEBUG0_REG
,
906 RTL8367_CHIP_DEBUG0_DUMMY0(id
),
907 RTL8367_CHIP_DEBUG0_DUMMY0(id
));
908 REG_RMW(smi
, RTL8367_EXT_RGMXF_REG(id
), BIT(6), BIT(6));
911 case RTL8367_EXTIF_MODE_MII_MAC
:
912 case RTL8367_EXTIF_MODE_MII_PHY
:
913 case RTL8367_EXTIF_MODE_DISABLED
:
914 REG_RMW(smi
, RTL8367_BYPASS_LINE_RATE_REG
,
915 BIT((id
+ 1) % 2), 0);
916 REG_RMW(smi
, RTL8367_EXT_RGMXF_REG(id
), BIT(6), 0);
921 "invalid mode for external interface %d\n", id
);
925 REG_RMW(smi
, RTL8367_DIS_REG
,
926 RTL8367_DIS_RGMII_MASK
<< RTL8367_DIS_RGMII_SHIFT(id
),
927 mode
<< RTL8367_DIS_RGMII_SHIFT(id
));
932 static int rtl8367_extif_set_force(struct rtl8366_smi
*smi
, int id
,
933 struct rtl8367_port_ability
*pa
)
939 mask
= (RTL8367_DI_FORCE_MODE
|
940 RTL8367_DI_FORCE_NWAY
|
941 RTL8367_DI_FORCE_TXPAUSE
|
942 RTL8367_DI_FORCE_RXPAUSE
|
943 RTL8367_DI_FORCE_LINK
|
944 RTL8367_DI_FORCE_DUPLEX
|
945 RTL8367_DI_FORCE_SPEED_MASK
);
948 val
|= pa
->force_mode
? RTL8367_DI_FORCE_MODE
: 0;
949 val
|= pa
->nway
? RTL8367_DI_FORCE_NWAY
: 0;
950 val
|= pa
->txpause
? RTL8367_DI_FORCE_TXPAUSE
: 0;
951 val
|= pa
->rxpause
? RTL8367_DI_FORCE_RXPAUSE
: 0;
952 val
|= pa
->link
? RTL8367_DI_FORCE_LINK
: 0;
953 val
|= pa
->duplex
? RTL8367_DI_FORCE_DUPLEX
: 0;
955 REG_RMW(smi
, RTL8367_DI_FORCE_REG(id
), mask
, val
);
960 static int rtl8367_extif_set_rgmii_delay(struct rtl8366_smi
*smi
, int id
,
961 unsigned txdelay
, unsigned rxdelay
)
967 mask
= (RTL8367_EXT_RGMXF_RXDELAY_MASK
|
968 (RTL8367_EXT_RGMXF_TXDELAY_MASK
<<
969 RTL8367_EXT_RGMXF_TXDELAY_SHIFT
));
972 val
|= txdelay
<< RTL8367_EXT_RGMXF_TXDELAY_SHIFT
;
974 REG_RMW(smi
, RTL8367_EXT_RGMXF_REG(id
), mask
, val
);
979 static int rtl8367_extif_init(struct rtl8366_smi
*smi
, int id
,
980 struct rtl8367_extif_config
*cfg
)
982 enum rtl8367_extif_mode mode
;
985 mode
= (cfg
) ? cfg
->mode
: RTL8367_EXTIF_MODE_DISABLED
;
987 err
= rtl8367_extif_set_mode(smi
, id
, mode
);
991 if (mode
!= RTL8367_EXTIF_MODE_DISABLED
) {
992 err
= rtl8367_extif_set_force(smi
, id
, &cfg
->ability
);
996 err
= rtl8367_extif_set_rgmii_delay(smi
, id
, cfg
->txdelay
,
1005 static int rtl8367_led_group_set_ports(struct rtl8366_smi
*smi
,
1006 unsigned int group
, u16 port_mask
)
1012 port_mask
&= RTL8367_PARA_LED_IO_EN_PMASK
;
1013 s
= (group
% 2) * 8;
1014 reg
= RTL8367_PARA_LED_IO_EN1_REG
+ (group
/ 2);
1016 REG_RMW(smi
, reg
, (RTL8367_PARA_LED_IO_EN_PMASK
<< s
), port_mask
<< s
);
1021 static int rtl8367_led_group_set_mode(struct rtl8366_smi
*smi
,
1028 mode
&= RTL8367_LED_CONFIG_DATA_M
;
1030 mask
= (RTL8367_LED_CONFIG_DATA_M
<< RTL8367_LED_CONFIG_DATA_S
) |
1031 RTL8367_LED_CONFIG_SEL
;
1032 set
= (mode
<< RTL8367_LED_CONFIG_DATA_S
) | RTL8367_LED_CONFIG_SEL
;
1034 REG_RMW(smi
, RTL8367_LED_CONFIG_REG
, mask
, set
);
1039 static int rtl8367_led_group_set_config(struct rtl8366_smi
*smi
,
1040 unsigned int led
, unsigned int cfg
)
1046 mask
= (RTL8367_LED_CONFIG_LED_CFG_M
<< (led
* 4)) |
1047 RTL8367_LED_CONFIG_SEL
;
1048 set
= (cfg
& RTL8367_LED_CONFIG_LED_CFG_M
) << (led
* 4);
1050 REG_RMW(smi
, RTL8367_LED_CONFIG_REG
, mask
, set
);
1054 static int rtl8367_led_op_select_parallel(struct rtl8366_smi
*smi
)
1058 REG_WR(smi
, RTL8367_LED_SYS_CONFIG_REG
, 0x1472);
1062 static int rtl8367_led_blinkrate_set(struct rtl8366_smi
*smi
, unsigned int rate
)
1068 mask
= RTL8367_LED_MODE_RATE_M
<< RTL8367_LED_MODE_RATE_S
;
1069 set
= (rate
& RTL8367_LED_MODE_RATE_M
) << RTL8367_LED_MODE_RATE_S
;
1070 REG_RMW(smi
, RTL8367_LED_MODE_REG
, mask
, set
);
1075 static int rtl8367_setup(struct rtl8366_smi
*smi
)
1077 struct rtl8367_platform_data
*pdata
;
1081 pdata
= smi
->parent
->platform_data
;
1083 err
= rtl8367_init_regs(smi
);
1087 /* initialize external interfaces */
1088 err
= rtl8367_extif_init(smi
, 0, pdata
->extif0_cfg
);
1092 err
= rtl8367_extif_init(smi
, 1, pdata
->extif1_cfg
);
1096 /* set maximum packet length to 1536 bytes */
1097 REG_RMW(smi
, RTL8367_SWC0_REG
, RTL8367_SWC0_MAX_LENGTH_MASK
,
1098 RTL8367_SWC0_MAX_LENGTH_1536
);
1101 * discard VLAN tagged packets if the port is not a member of
1102 * the VLAN with which the packets is associated.
1104 REG_WR(smi
, RTL8367_VLAN_INGRESS_REG
, RTL8367_PORTS_ALL
);
1107 * Setup egress tag mode for each port.
1109 for (i
= 0; i
< RTL8367_NUM_PORTS
; i
++)
1111 RTL8367_PORT_CFG_REG(i
),
1112 RTL8367_PORT_CFG_EGRESS_MODE_MASK
<<
1113 RTL8367_PORT_CFG_EGRESS_MODE_SHIFT
,
1114 RTL8367_PORT_CFG_EGRESS_MODE_ORIGINAL
<<
1115 RTL8367_PORT_CFG_EGRESS_MODE_SHIFT
);
1118 err
= rtl8367_led_group_set_ports(smi
, 0, RTL8367_PORTS_ALL
);
1122 err
= rtl8367_led_group_set_mode(smi
, 0);
1126 err
= rtl8367_led_op_select_parallel(smi
);
1130 err
= rtl8367_led_blinkrate_set(smi
, 1);
1134 err
= rtl8367_led_group_set_config(smi
, 0, 2);
1141 static int rtl8367_get_mib_counter(struct rtl8366_smi
*smi
, int counter
,
1142 int port
, unsigned long long *val
)
1144 struct rtl8366_mib_counter
*mib
;
1151 if (port
> RTL8367_NUM_PORTS
|| counter
>= RTL8367_MIB_COUNT
)
1154 mib
= &rtl8367_mib_counters
[counter
];
1155 addr
= RTL8367_MIB_COUNTER_PORT_OFFSET
* port
+ mib
->offset
;
1158 * Writing access counter address first
1159 * then ASIC will prepare 64bits counter wait for being retrived
1161 REG_WR(smi
, RTL8367_MIB_ADDRESS_REG
, addr
>> 2);
1163 /* read MIB control register */
1164 REG_RD(smi
, RTL8367_MIB_CTRL_REG(0), &data
);
1166 if (data
& RTL8367_MIB_CTRL_BUSY_MASK
)
1169 if (data
& RTL8367_MIB_CTRL_RESET_MASK
)
1172 if (mib
->length
== 4)
1175 offset
= (mib
->offset
+ 1) % 4;
1178 for (i
= 0; i
< mib
->length
; i
++) {
1179 REG_RD(smi
, RTL8367_MIB_COUNTER_REG(offset
- i
), &data
);
1180 mibvalue
= (mibvalue
<< 16) | (data
& 0xFFFF);
1187 static int rtl8367_get_vlan_4k(struct rtl8366_smi
*smi
, u32 vid
,
1188 struct rtl8366_vlan_4k
*vlan4k
)
1190 u32 data
[RTL8367_TA_VLAN_DATA_SIZE
];
1194 memset(vlan4k
, '\0', sizeof(struct rtl8366_vlan_4k
));
1196 if (vid
>= RTL8367_NUM_VIDS
)
1200 REG_WR(smi
, RTL8367_TA_ADDR_REG
, vid
);
1202 /* write table access control word */
1203 REG_WR(smi
, RTL8367_TA_CTRL_REG
, RTL8367_TA_CTRL_CVLAN_READ
);
1205 for (i
= 0; i
< ARRAY_SIZE(data
); i
++)
1206 REG_RD(smi
, RTL8367_TA_DATA_REG(i
), &data
[i
]);
1209 vlan4k
->member
= (data
[0] >> RTL8367_TA_VLAN_MEMBER_SHIFT
) &
1210 RTL8367_TA_VLAN_MEMBER_MASK
;
1211 vlan4k
->fid
= (data
[1] >> RTL8367_TA_VLAN_FID_SHIFT
) &
1212 RTL8367_TA_VLAN_FID_MASK
;
1213 vlan4k
->untag
= (data
[2] >> RTL8367_TA_VLAN_UNTAG1_SHIFT
) &
1214 RTL8367_TA_VLAN_UNTAG1_MASK
;
1215 vlan4k
->untag
|= ((data
[3] >> RTL8367_TA_VLAN_UNTAG2_SHIFT
) &
1216 RTL8367_TA_VLAN_UNTAG2_MASK
) << 2;
1221 static int rtl8367_set_vlan_4k(struct rtl8366_smi
*smi
,
1222 const struct rtl8366_vlan_4k
*vlan4k
)
1224 u32 data
[RTL8367_TA_VLAN_DATA_SIZE
];
1228 if (vlan4k
->vid
>= RTL8367_NUM_VIDS
||
1229 vlan4k
->member
> RTL8367_TA_VLAN_MEMBER_MASK
||
1230 vlan4k
->untag
> RTL8367_UNTAG_MASK
||
1231 vlan4k
->fid
> RTL8367_FIDMAX
)
1234 data
[0] = (vlan4k
->member
& RTL8367_TA_VLAN_MEMBER_MASK
) <<
1235 RTL8367_TA_VLAN_MEMBER_SHIFT
;
1236 data
[1] = (vlan4k
->fid
& RTL8367_TA_VLAN_FID_MASK
) <<
1237 RTL8367_TA_VLAN_FID_SHIFT
;
1238 data
[2] = (vlan4k
->untag
& RTL8367_TA_VLAN_UNTAG1_MASK
) <<
1239 RTL8367_TA_VLAN_UNTAG1_SHIFT
;
1240 data
[3] = ((vlan4k
->untag
>> 2) & RTL8367_TA_VLAN_UNTAG2_MASK
) <<
1241 RTL8367_TA_VLAN_UNTAG2_SHIFT
;
1243 for (i
= 0; i
< ARRAY_SIZE(data
); i
++)
1244 REG_WR(smi
, RTL8367_TA_DATA_REG(i
), data
[i
]);
1247 REG_WR(smi
, RTL8367_TA_ADDR_REG
,
1248 vlan4k
->vid
& RTL8367_TA_VLAN_VID_MASK
);
1250 /* write table access control word */
1251 REG_WR(smi
, RTL8367_TA_CTRL_REG
, RTL8367_TA_CTRL_CVLAN_WRITE
);
1256 static int rtl8367_get_vlan_mc(struct rtl8366_smi
*smi
, u32 index
,
1257 struct rtl8366_vlan_mc
*vlanmc
)
1259 u32 data
[RTL8367_VLAN_MC_DATA_SIZE
];
1263 memset(vlanmc
, '\0', sizeof(struct rtl8366_vlan_mc
));
1265 if (index
>= RTL8367_NUM_VLANS
)
1268 for (i
= 0; i
< ARRAY_SIZE(data
); i
++)
1269 REG_RD(smi
, RTL8367_VLAN_MC_BASE(index
) + i
, &data
[i
]);
1271 vlanmc
->member
= (data
[0] >> RTL8367_VLAN_MC_MEMBER_SHIFT
) &
1272 RTL8367_VLAN_MC_MEMBER_MASK
;
1273 vlanmc
->fid
= (data
[1] >> RTL8367_VLAN_MC_FID_SHIFT
) &
1274 RTL8367_VLAN_MC_FID_MASK
;
1275 vlanmc
->vid
= (data
[3] >> RTL8367_VLAN_MC_EVID_SHIFT
) &
1276 RTL8367_VLAN_MC_EVID_MASK
;
1281 static int rtl8367_set_vlan_mc(struct rtl8366_smi
*smi
, u32 index
,
1282 const struct rtl8366_vlan_mc
*vlanmc
)
1284 u32 data
[RTL8367_VLAN_MC_DATA_SIZE
];
1288 if (index
>= RTL8367_NUM_VLANS
||
1289 vlanmc
->vid
>= RTL8367_NUM_VIDS
||
1290 vlanmc
->priority
> RTL8367_PRIORITYMAX
||
1291 vlanmc
->member
> RTL8367_VLAN_MC_MEMBER_MASK
||
1292 vlanmc
->untag
> RTL8367_UNTAG_MASK
||
1293 vlanmc
->fid
> RTL8367_FIDMAX
)
1296 data
[0] = (vlanmc
->member
& RTL8367_VLAN_MC_MEMBER_MASK
) <<
1297 RTL8367_VLAN_MC_MEMBER_SHIFT
;
1298 data
[1] = (vlanmc
->fid
& RTL8367_VLAN_MC_FID_MASK
) <<
1299 RTL8367_VLAN_MC_FID_SHIFT
;
1301 data
[3] = (vlanmc
->vid
& RTL8367_VLAN_MC_EVID_MASK
) <<
1302 RTL8367_VLAN_MC_EVID_SHIFT
;
1304 for (i
= 0; i
< ARRAY_SIZE(data
); i
++)
1305 REG_WR(smi
, RTL8367_VLAN_MC_BASE(index
) + i
, data
[i
]);
1310 static int rtl8367_get_mc_index(struct rtl8366_smi
*smi
, int port
, int *val
)
1315 if (port
>= RTL8367_NUM_PORTS
)
1318 REG_RD(smi
, RTL8367_VLAN_PVID_CTRL_REG(port
), &data
);
1320 *val
= (data
>> RTL8367_VLAN_PVID_CTRL_SHIFT(port
)) &
1321 RTL8367_VLAN_PVID_CTRL_MASK
;
1326 static int rtl8367_set_mc_index(struct rtl8366_smi
*smi
, int port
, int index
)
1328 if (port
>= RTL8367_NUM_PORTS
|| index
>= RTL8367_NUM_VLANS
)
1331 return rtl8366_smi_rmwr(smi
, RTL8367_VLAN_PVID_CTRL_REG(port
),
1332 RTL8367_VLAN_PVID_CTRL_MASK
<<
1333 RTL8367_VLAN_PVID_CTRL_SHIFT(port
),
1334 (index
& RTL8367_VLAN_PVID_CTRL_MASK
) <<
1335 RTL8367_VLAN_PVID_CTRL_SHIFT(port
));
1338 static int rtl8367_enable_vlan(struct rtl8366_smi
*smi
, int enable
)
1340 return rtl8366_smi_rmwr(smi
, RTL8367_VLAN_CTRL_REG
,
1341 RTL8367_VLAN_CTRL_ENABLE
,
1342 (enable
) ? RTL8367_VLAN_CTRL_ENABLE
: 0);
1345 static int rtl8367_enable_vlan4k(struct rtl8366_smi
*smi
, int enable
)
1350 static int rtl8367_is_vlan_valid(struct rtl8366_smi
*smi
, unsigned vlan
)
1352 unsigned max
= RTL8367_NUM_VLANS
;
1354 if (smi
->vlan4k_enabled
)
1355 max
= RTL8367_NUM_VIDS
- 1;
1357 if (vlan
== 0 || vlan
>= max
)
1363 static int rtl8367_enable_port(struct rtl8366_smi
*smi
, int port
, int enable
)
1367 REG_WR(smi
, RTL8367_PORT_ISOLATION_REG(port
),
1368 (enable
) ? RTL8367_PORTS_ALL
: 0);
1373 static int rtl8367_sw_reset_mibs(struct switch_dev
*dev
,
1374 const struct switch_attr
*attr
,
1375 struct switch_val
*val
)
1377 struct rtl8366_smi
*smi
= sw_to_rtl8366_smi(dev
);
1379 return rtl8366_smi_rmwr(smi
, RTL8367_MIB_CTRL_REG(0), 0,
1380 RTL8367_MIB_CTRL_GLOBAL_RESET_MASK
);
1383 static int rtl8367_sw_get_port_link(struct switch_dev
*dev
,
1385 struct switch_port_link
*link
)
1387 struct rtl8366_smi
*smi
= sw_to_rtl8366_smi(dev
);
1391 if (port
>= RTL8367_NUM_PORTS
)
1394 rtl8366_smi_read_reg(smi
, RTL8367_PORT_STATUS_REG(port
), &data
);
1396 link
->link
= !!(data
& RTL8367_PORT_STATUS_LINK
);
1400 link
->duplex
= !!(data
& RTL8367_PORT_STATUS_DUPLEX
);
1401 link
->rx_flow
= !!(data
& RTL8367_PORT_STATUS_RXPAUSE
);
1402 link
->tx_flow
= !!(data
& RTL8367_PORT_STATUS_TXPAUSE
);
1403 link
->aneg
= !!(data
& RTL8367_PORT_STATUS_NWAY
);
1405 speed
= (data
& RTL8367_PORT_STATUS_SPEED_MASK
);
1408 link
->speed
= SWITCH_PORT_SPEED_10
;
1411 link
->speed
= SWITCH_PORT_SPEED_100
;
1414 link
->speed
= SWITCH_PORT_SPEED_1000
;
1417 link
->speed
= SWITCH_PORT_SPEED_UNKNOWN
;
1424 static int rtl8367_sw_get_max_length(struct switch_dev
*dev
,
1425 const struct switch_attr
*attr
,
1426 struct switch_val
*val
)
1428 struct rtl8366_smi
*smi
= sw_to_rtl8366_smi(dev
);
1431 rtl8366_smi_read_reg(smi
, RTL8367_SWC0_REG
, &data
);
1432 val
->value
.i
= (data
& RTL8367_SWC0_MAX_LENGTH_MASK
) >>
1433 RTL8367_SWC0_MAX_LENGTH_SHIFT
;
1438 static int rtl8367_sw_set_max_length(struct switch_dev
*dev
,
1439 const struct switch_attr
*attr
,
1440 struct switch_val
*val
)
1442 struct rtl8366_smi
*smi
= sw_to_rtl8366_smi(dev
);
1445 switch (val
->value
.i
) {
1447 max_len
= RTL8367_SWC0_MAX_LENGTH_1522
;
1450 max_len
= RTL8367_SWC0_MAX_LENGTH_1536
;
1453 max_len
= RTL8367_SWC0_MAX_LENGTH_1552
;
1456 max_len
= RTL8367_SWC0_MAX_LENGTH_16000
;
1462 return rtl8366_smi_rmwr(smi
, RTL8367_SWC0_REG
,
1463 RTL8367_SWC0_MAX_LENGTH_MASK
, max_len
);
1467 static int rtl8367_sw_reset_port_mibs(struct switch_dev
*dev
,
1468 const struct switch_attr
*attr
,
1469 struct switch_val
*val
)
1471 struct rtl8366_smi
*smi
= sw_to_rtl8366_smi(dev
);
1474 port
= val
->port_vlan
;
1475 if (port
>= RTL8367_NUM_PORTS
)
1478 return rtl8366_smi_rmwr(smi
, RTL8367_MIB_CTRL_REG(port
/ 8), 0,
1479 RTL8367_MIB_CTRL_PORT_RESET_MASK(port
% 8));
1482 static struct switch_attr rtl8367_globals
[] = {
1484 .type
= SWITCH_TYPE_INT
,
1485 .name
= "enable_vlan",
1486 .description
= "Enable VLAN mode",
1487 .set
= rtl8366_sw_set_vlan_enable
,
1488 .get
= rtl8366_sw_get_vlan_enable
,
1492 .type
= SWITCH_TYPE_INT
,
1493 .name
= "enable_vlan4k",
1494 .description
= "Enable VLAN 4K mode",
1495 .set
= rtl8366_sw_set_vlan_enable
,
1496 .get
= rtl8366_sw_get_vlan_enable
,
1500 .type
= SWITCH_TYPE_NOVAL
,
1501 .name
= "reset_mibs",
1502 .description
= "Reset all MIB counters",
1503 .set
= rtl8367_sw_reset_mibs
,
1505 .type
= SWITCH_TYPE_INT
,
1506 .name
= "max_length",
1507 .description
= "Get/Set the maximum length of valid packets"
1508 "(0:1522, 1:1536, 2:1552, 3:16000)",
1509 .set
= rtl8367_sw_set_max_length
,
1510 .get
= rtl8367_sw_get_max_length
,
1515 static struct switch_attr rtl8367_port
[] = {
1517 .type
= SWITCH_TYPE_NOVAL
,
1518 .name
= "reset_mib",
1519 .description
= "Reset single port MIB counters",
1520 .set
= rtl8367_sw_reset_port_mibs
,
1522 .type
= SWITCH_TYPE_STRING
,
1524 .description
= "Get MIB counters for port",
1527 .get
= rtl8366_sw_get_port_mib
,
1531 static struct switch_attr rtl8367_vlan
[] = {
1533 .type
= SWITCH_TYPE_STRING
,
1535 .description
= "Get vlan information",
1538 .get
= rtl8366_sw_get_vlan_info
,
1542 static const struct switch_dev_ops rtl8367_sw_ops
= {
1544 .attr
= rtl8367_globals
,
1545 .n_attr
= ARRAY_SIZE(rtl8367_globals
),
1548 .attr
= rtl8367_port
,
1549 .n_attr
= ARRAY_SIZE(rtl8367_port
),
1552 .attr
= rtl8367_vlan
,
1553 .n_attr
= ARRAY_SIZE(rtl8367_vlan
),
1556 .get_vlan_ports
= rtl8366_sw_get_vlan_ports
,
1557 .set_vlan_ports
= rtl8366_sw_set_vlan_ports
,
1558 .get_port_pvid
= rtl8366_sw_get_port_pvid
,
1559 .set_port_pvid
= rtl8366_sw_set_port_pvid
,
1560 .reset_switch
= rtl8366_sw_reset_switch
,
1561 .get_port_link
= rtl8367_sw_get_port_link
,
1564 static int rtl8367_switch_init(struct rtl8366_smi
*smi
)
1566 struct switch_dev
*dev
= &smi
->sw_dev
;
1569 dev
->name
= "RTL8367";
1570 dev
->cpu_port
= RTL8367_CPU_PORT_NUM
;
1571 dev
->ports
= RTL8367_NUM_PORTS
;
1572 dev
->vlans
= RTL8367_NUM_VIDS
;
1573 dev
->ops
= &rtl8367_sw_ops
;
1574 dev
->alias
= dev_name(smi
->parent
);
1576 err
= register_switch(dev
, NULL
);
1578 dev_err(smi
->parent
, "switch registration failed\n");
1583 static void rtl8367_switch_cleanup(struct rtl8366_smi
*smi
)
1585 unregister_switch(&smi
->sw_dev
);
1588 static int rtl8367_mii_read(struct mii_bus
*bus
, int addr
, int reg
)
1590 struct rtl8366_smi
*smi
= bus
->priv
;
1594 err
= rtl8367_read_phy_reg(smi
, addr
, reg
, &val
);
1601 static int rtl8367_mii_write(struct mii_bus
*bus
, int addr
, int reg
, u16 val
)
1603 struct rtl8366_smi
*smi
= bus
->priv
;
1607 err
= rtl8367_write_phy_reg(smi
, addr
, reg
, val
);
1612 (void) rtl8367_read_phy_reg(smi
, addr
, reg
, &t
);
1617 static int rtl8367_detect(struct rtl8366_smi
*smi
)
1624 ret
= rtl8366_smi_read_reg(smi
, RTL8367_RTL_NO_REG
, &rtl_no
);
1626 dev_err(smi
->parent
, "unable to read chip number\n");
1631 case RTL8367_RTL_NO_8367R
:
1632 chip_name
= "8367R";
1634 case RTL8367_RTL_NO_8367M
:
1635 chip_name
= "8367M";
1638 dev_err(smi
->parent
, "unknown chip number (%04x)\n", rtl_no
);
1642 ret
= rtl8366_smi_read_reg(smi
, RTL8367_RTL_VER_REG
, &rtl_ver
);
1644 dev_err(smi
->parent
, "unable to read chip version\n");
1648 dev_info(smi
->parent
, "RTL%s ver. %u chip found\n",
1649 chip_name
, rtl_ver
& RTL8367_RTL_VER_MASK
);
1654 static struct rtl8366_smi_ops rtl8367_smi_ops
= {
1655 .detect
= rtl8367_detect
,
1656 .reset_chip
= rtl8367_reset_chip
,
1657 .setup
= rtl8367_setup
,
1659 .mii_read
= rtl8367_mii_read
,
1660 .mii_write
= rtl8367_mii_write
,
1662 .get_vlan_mc
= rtl8367_get_vlan_mc
,
1663 .set_vlan_mc
= rtl8367_set_vlan_mc
,
1664 .get_vlan_4k
= rtl8367_get_vlan_4k
,
1665 .set_vlan_4k
= rtl8367_set_vlan_4k
,
1666 .get_mc_index
= rtl8367_get_mc_index
,
1667 .set_mc_index
= rtl8367_set_mc_index
,
1668 .get_mib_counter
= rtl8367_get_mib_counter
,
1669 .is_vlan_valid
= rtl8367_is_vlan_valid
,
1670 .enable_vlan
= rtl8367_enable_vlan
,
1671 .enable_vlan4k
= rtl8367_enable_vlan4k
,
1672 .enable_port
= rtl8367_enable_port
,
1675 static int __devinit
rtl8367_probe(struct platform_device
*pdev
)
1677 struct rtl8367_platform_data
*pdata
;
1678 struct rtl8366_smi
*smi
;
1681 smi
= rtl8366_smi_probe(pdev
);
1685 smi
->clk_delay
= 1500;
1686 smi
->cmd_read
= 0xb9;
1687 smi
->cmd_write
= 0xb8;
1688 smi
->ops
= &rtl8367_smi_ops
;
1689 smi
->cpu_port
= RTL8367_CPU_PORT_NUM
;
1690 smi
->num_ports
= RTL8367_NUM_PORTS
;
1691 smi
->num_vlan_mc
= RTL8367_NUM_VLANS
;
1692 smi
->mib_counters
= rtl8367_mib_counters
;
1693 smi
->num_mib_counters
= ARRAY_SIZE(rtl8367_mib_counters
);
1695 err
= rtl8366_smi_init(smi
);
1699 platform_set_drvdata(pdev
, smi
);
1701 err
= rtl8367_switch_init(smi
);
1703 goto err_clear_drvdata
;
1708 platform_set_drvdata(pdev
, NULL
);
1709 rtl8366_smi_cleanup(smi
);
1716 static int __devexit
rtl8367_remove(struct platform_device
*pdev
)
1718 struct rtl8366_smi
*smi
= platform_get_drvdata(pdev
);
1721 rtl8367_switch_cleanup(smi
);
1722 platform_set_drvdata(pdev
, NULL
);
1723 rtl8366_smi_cleanup(smi
);
1730 static void rtl8367_shutdown(struct platform_device
*pdev
)
1732 struct rtl8366_smi
*smi
= platform_get_drvdata(pdev
);
1735 rtl8367_reset_chip(smi
);
1739 static const struct of_device_id rtl8367_match
[] = {
1740 { .compatible
= "rtl8367" },
1743 MODULE_DEVICE_TABLE(of
, rtl83767_match
);
1746 static struct platform_driver rtl8367_driver
= {
1748 .name
= RTL8367_DRIVER_NAME
,
1749 .owner
= THIS_MODULE
,
1751 .of_match_table
= of_match_ptr(rtl8367_match
),
1754 .probe
= rtl8367_probe
,
1755 .remove
= __devexit_p(rtl8367_remove
),
1756 .shutdown
= rtl8367_shutdown
,
1759 static int __init
rtl8367_module_init(void)
1761 return platform_driver_register(&rtl8367_driver
);
1763 module_init(rtl8367_module_init
);
1765 static void __exit
rtl8367_module_exit(void)
1767 platform_driver_unregister(&rtl8367_driver
);
1769 module_exit(rtl8367_module_exit
);
1771 MODULE_DESCRIPTION(RTL8367_DRIVER_DESC
);
1772 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1773 MODULE_LICENSE("GPL v2");
1774 MODULE_ALIAS("platform:" RTL8367_DRIVER_NAME
);