2 * Kernel relocation stub for MIPS devices
4 * Copyright (C) 2015 Felix Fietkau <nbd@openwrt.org>
8 * LZMA compressed kernel loader for Atheros AR7XXX/AR9XXX based boards
10 * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
12 * Some parts of this code was based on the OpenWrt specific lzma-loader
13 * for the BCM47xx and ADM5120 based boards:
14 * Copyright (C) 2004 Manuel Novoa III (mjn3@codepoet.org)
15 * Copyright (C) 2005 by Oleg I. Vdovikin <oleg@cs.msu.su>
17 * This program is free software; you can redistribute it and/or modify it
18 * under the terms of the GNU General Public License version 2 as published
19 * by the Free Software Foundation.
23 #include <asm/regdef.h>
24 #include "cp0regdef.h"
27 #define KSEG0 0x80000000
48 mtc0 zero, CP0_WATCHLO # clear watch registers
49 mtc0 zero, CP0_WATCHHI
50 mtc0 zero, CP0_CAUSE # clear before writing status register
60 mtc0 zero, CP0_COMPARE
63 la t0, __reloc_label # get linked address of label
64 bal __reloc_label # branch and link to label to
65 nop # get actual address
67 subu t0, ra, t0 # get reloc_delta
69 /* Copy our code to the right place */
70 la t1, _code_start # get linked address of _code_start
71 la t2, _code_end # get linked address of _code_end
73 addu t4, t2, t0 # calculate actual address of _code_end
74 lw t5, 0(t4) # get extra data size
79 add t0, t1 # calculate actual address of _code_start
85 blt t1, t2, __reloc_copy
92 li t2, ~(CONFIG_CACHELINE_SIZE - 1)
95 li t2, CONFIG_CACHELINE_SIZE
101 cache Hit_Writeback_Inv_D, 0(t0)
102 cache Hit_Invalidate_I, 0(t0)
106 bne t0, t1, __flush_line
127 blt t0, t1, __kernel_copy
134 add t1, CONFIG_CACHELINE_SIZE - 1
135 li t2, ~(CONFIG_CACHELINE_SIZE - 1)
138 li t2, CONFIG_CACHELINE_SIZE
140 b __kernel_flush_check
144 cache Hit_Writeback_Inv_D, 0(t0)
145 cache Hit_Invalidate_I, 0(t0)
148 __kernel_flush_check:
149 bne t0, t1, __kernel_flush_line