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linux/2.6.30: R.I.P.
[openwrt/staging/dedeckeh.git] / target / linux / generic / patches-2.6.31 / 941-ssb_update.patch
1 --- a/drivers/ssb/Kconfig
2 +++ b/drivers/ssb/Kconfig
3 @@ -66,6 +66,20 @@ config SSB_PCMCIAHOST
4
5 If unsure, say N
6
7 +config SSB_SDIOHOST_POSSIBLE
8 + bool
9 + depends on SSB && (MMC = y || MMC = SSB)
10 + default y
11 +
12 +config SSB_SDIOHOST
13 + bool "Support for SSB on SDIO-bus host"
14 + depends on SSB_SDIOHOST_POSSIBLE
15 + help
16 + Support for a Sonics Silicon Backplane on top
17 + of a SDIO device.
18 +
19 + If unsure, say N
20 +
21 config SSB_SILENT
22 bool "No SSB kernel messages"
23 depends on SSB && EMBEDDED
24 --- a/drivers/ssb/Makefile
25 +++ b/drivers/ssb/Makefile
26 @@ -6,6 +6,7 @@ ssb-$(CONFIG_SSB_SPROM) += sprom.o
27 # host support
28 ssb-$(CONFIG_SSB_PCIHOST) += pci.o pcihost_wrapper.o
29 ssb-$(CONFIG_SSB_PCMCIAHOST) += pcmcia.o
30 +ssb-$(CONFIG_SSB_SDIOHOST) += sdio.o
31
32 # built-in drivers
33 ssb-y += driver_chipcommon.o
34 --- a/drivers/ssb/b43_pci_bridge.c
35 +++ b/drivers/ssb/b43_pci_bridge.c
36 @@ -5,12 +5,13 @@
37 * because of its small size we include it in the SSB core
38 * instead of creating a standalone module.
39 *
40 - * Copyright 2007 Michael Buesch <mb@bu3sch.de>
41 + * Copyright 2007 Michael Buesch <m@bues.ch>
42 *
43 * Licensed under the GNU/GPL. See COPYING for details.
44 */
45
46 #include <linux/pci.h>
47 +#include <linux/module.h>
48 #include <linux/ssb/ssb.h>
49
50 #include "ssb_private.h"
51 @@ -24,6 +25,7 @@ static const struct pci_device_id b43_pc
52 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4312) },
53 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4315) },
54 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4318) },
55 + { PCI_DEVICE(PCI_VENDOR_ID_BCM_GVC, 0x4318) },
56 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4319) },
57 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4320) },
58 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4321) },
59 --- a/drivers/ssb/driver_chipcommon.c
60 +++ b/drivers/ssb/driver_chipcommon.c
61 @@ -3,7 +3,7 @@
62 * Broadcom ChipCommon core driver
63 *
64 * Copyright 2005, Broadcom Corporation
65 - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
66 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
67 *
68 * Licensed under the GNU/GPL. See COPYING for details.
69 */
70 @@ -46,40 +46,66 @@ void ssb_chipco_set_clockmode(struct ssb
71 if (!ccdev)
72 return;
73 bus = ccdev->bus;
74 +
75 + /* We support SLOW only on 6..9 */
76 + if (ccdev->id.revision >= 10 && mode == SSB_CLKMODE_SLOW)
77 + mode = SSB_CLKMODE_DYNAMIC;
78 +
79 + if (cc->capabilities & SSB_CHIPCO_CAP_PMU)
80 + return; /* PMU controls clockmode, separated function needed */
81 + SSB_WARN_ON(ccdev->id.revision >= 20);
82 +
83 /* chipcommon cores prior to rev6 don't support dynamic clock control */
84 if (ccdev->id.revision < 6)
85 return;
86 - /* chipcommon cores rev10 are a whole new ball game */
87 +
88 + /* ChipCommon cores rev10+ need testing */
89 if (ccdev->id.revision >= 10)
90 return;
91 +
92 if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
93 return;
94
95 switch (mode) {
96 - case SSB_CLKMODE_SLOW:
97 + case SSB_CLKMODE_SLOW: /* For revs 6..9 only */
98 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
99 tmp |= SSB_CHIPCO_SLOWCLKCTL_FSLOW;
100 chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
101 break;
102 case SSB_CLKMODE_FAST:
103 - ssb_pci_xtal(bus, SSB_GPIO_XTAL, 1); /* Force crystal on */
104 - tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
105 - tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
106 - tmp |= SSB_CHIPCO_SLOWCLKCTL_IPLL;
107 - chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
108 + if (ccdev->id.revision < 10) {
109 + ssb_pci_xtal(bus, SSB_GPIO_XTAL, 1); /* Force crystal on */
110 + tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
111 + tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
112 + tmp |= SSB_CHIPCO_SLOWCLKCTL_IPLL;
113 + chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
114 + } else {
115 + chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL,
116 + (chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) |
117 + SSB_CHIPCO_SYSCLKCTL_FORCEHT));
118 + /* udelay(150); TODO: not available in early init */
119 + }
120 break;
121 case SSB_CLKMODE_DYNAMIC:
122 - tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
123 - tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
124 - tmp &= ~SSB_CHIPCO_SLOWCLKCTL_IPLL;
125 - tmp &= ~SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
126 - if ((tmp & SSB_CHIPCO_SLOWCLKCTL_SRC) != SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL)
127 - tmp |= SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
128 - chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
129 -
130 - /* for dynamic control, we have to release our xtal_pu "force on" */
131 - if (tmp & SSB_CHIPCO_SLOWCLKCTL_ENXTAL)
132 - ssb_pci_xtal(bus, SSB_GPIO_XTAL, 0);
133 + if (ccdev->id.revision < 10) {
134 + tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
135 + tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
136 + tmp &= ~SSB_CHIPCO_SLOWCLKCTL_IPLL;
137 + tmp &= ~SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
138 + if ((tmp & SSB_CHIPCO_SLOWCLKCTL_SRC) !=
139 + SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL)
140 + tmp |= SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
141 + chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
142 +
143 + /* For dynamic control, we have to release our xtal_pu
144 + * "force on" */
145 + if (tmp & SSB_CHIPCO_SLOWCLKCTL_ENXTAL)
146 + ssb_pci_xtal(bus, SSB_GPIO_XTAL, 0);
147 + } else {
148 + chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL,
149 + (chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) &
150 + ~SSB_CHIPCO_SYSCLKCTL_FORCEHT));
151 + }
152 break;
153 default:
154 SSB_WARN_ON(1);
155 @@ -209,6 +235,24 @@ static void chipco_powercontrol_init(str
156 }
157 }
158
159 +/* http://bcm-v4.sipsolutions.net/802.11/PmuFastPwrupDelay */
160 +static u16 pmu_fast_powerup_delay(struct ssb_chipcommon *cc)
161 +{
162 + struct ssb_bus *bus = cc->dev->bus;
163 +
164 + switch (bus->chip_id) {
165 + case 0x4312:
166 + case 0x4322:
167 + case 0x4328:
168 + return 7000;
169 + case 0x4325:
170 + /* TODO: */
171 + default:
172 + return 15000;
173 + }
174 +}
175 +
176 +/* http://bcm-v4.sipsolutions.net/802.11/ClkctlFastPwrupDelay */
177 static void calc_fast_powerup_delay(struct ssb_chipcommon *cc)
178 {
179 struct ssb_bus *bus = cc->dev->bus;
180 @@ -218,6 +262,12 @@ static void calc_fast_powerup_delay(stru
181
182 if (bus->bustype != SSB_BUSTYPE_PCI)
183 return;
184 +
185 + if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
186 + cc->fast_pwrup_delay = pmu_fast_powerup_delay(cc);
187 + return;
188 + }
189 +
190 if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
191 return;
192
193 @@ -233,6 +283,15 @@ void ssb_chipcommon_init(struct ssb_chip
194 {
195 if (!cc->dev)
196 return; /* We don't have a ChipCommon */
197 + if (cc->dev->id.revision >= 11)
198 + cc->status = chipco_read32(cc, SSB_CHIPCO_CHIPSTAT);
199 + ssb_dprintk(KERN_INFO PFX "chipcommon status is 0x%x\n", cc->status);
200 +
201 + if (cc->dev->id.revision >= 20) {
202 + chipco_write32(cc, SSB_CHIPCO_GPIOPULLUP, 0);
203 + chipco_write32(cc, SSB_CHIPCO_GPIOPULLDOWN, 0);
204 + }
205 +
206 ssb_pmu_init(cc);
207 chipco_powercontrol_init(cc);
208 ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
209 @@ -370,6 +429,7 @@ u32 ssb_chipco_gpio_control(struct ssb_c
210 {
211 return chipco_write32_masked(cc, SSB_CHIPCO_GPIOCTL, mask, value);
212 }
213 +EXPORT_SYMBOL(ssb_chipco_gpio_control);
214
215 u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value)
216 {
217 --- a/drivers/ssb/driver_chipcommon_pmu.c
218 +++ b/drivers/ssb/driver_chipcommon_pmu.c
219 @@ -2,7 +2,7 @@
220 * Sonics Silicon Backplane
221 * Broadcom ChipCommon Power Management Unit driver
222 *
223 - * Copyright 2009, Michael Buesch <mb@bu3sch.de>
224 + * Copyright 2009, Michael Buesch <m@bues.ch>
225 * Copyright 2007, Broadcom Corporation
226 *
227 * Licensed under the GNU/GPL. See COPYING for details.
228 @@ -12,6 +12,9 @@
229 #include <linux/ssb/ssb_regs.h>
230 #include <linux/ssb/ssb_driver_chipcommon.h>
231 #include <linux/delay.h>
232 +#ifdef CONFIG_BCM47XX
233 +#include <asm/mach-bcm47xx/nvram.h>
234 +#endif
235
236 #include "ssb_private.h"
237
238 @@ -28,6 +31,21 @@ static void ssb_chipco_pll_write(struct
239 chipco_write32(cc, SSB_CHIPCO_PLLCTL_DATA, value);
240 }
241
242 +static void ssb_chipco_regctl_maskset(struct ssb_chipcommon *cc,
243 + u32 offset, u32 mask, u32 set)
244 +{
245 + u32 value;
246 +
247 + chipco_read32(cc, SSB_CHIPCO_REGCTL_ADDR);
248 + chipco_write32(cc, SSB_CHIPCO_REGCTL_ADDR, offset);
249 + chipco_read32(cc, SSB_CHIPCO_REGCTL_ADDR);
250 + value = chipco_read32(cc, SSB_CHIPCO_REGCTL_DATA);
251 + value &= mask;
252 + value |= set;
253 + chipco_write32(cc, SSB_CHIPCO_REGCTL_DATA, value);
254 + chipco_read32(cc, SSB_CHIPCO_REGCTL_DATA);
255 +}
256 +
257 struct pmu0_plltab_entry {
258 u16 freq; /* Crystal frequency in kHz.*/
259 u8 xf; /* Crystal frequency value for PMU control */
260 @@ -76,10 +94,6 @@ static void ssb_pmu0_pllinit_r0(struct s
261 u32 pmuctl, tmp, pllctl;
262 unsigned int i;
263
264 - if ((bus->chip_id == 0x5354) && !crystalfreq) {
265 - /* The 5354 crystal freq is 25MHz */
266 - crystalfreq = 25000;
267 - }
268 if (crystalfreq)
269 e = pmu0_plltab_find_entry(crystalfreq);
270 if (!e)
271 @@ -305,7 +319,11 @@ static void ssb_pmu_pll_init(struct ssb_
272 u32 crystalfreq = 0; /* in kHz. 0 = keep default freq. */
273
274 if (bus->bustype == SSB_BUSTYPE_SSB) {
275 - /* TODO: The user may override the crystal frequency. */
276 +#ifdef CONFIG_BCM47XX
277 + char buf[20];
278 + if (nvram_getenv("xtalfreq", buf, sizeof(buf)) >= 0)
279 + crystalfreq = simple_strtoul(buf, NULL, 0);
280 +#endif
281 }
282
283 switch (bus->chip_id) {
284 @@ -314,9 +332,19 @@ static void ssb_pmu_pll_init(struct ssb_
285 ssb_pmu1_pllinit_r0(cc, crystalfreq);
286 break;
287 case 0x4328:
288 + ssb_pmu0_pllinit_r0(cc, crystalfreq);
289 + break;
290 case 0x5354:
291 + if (crystalfreq == 0)
292 + crystalfreq = 25000;
293 ssb_pmu0_pllinit_r0(cc, crystalfreq);
294 break;
295 + case 0x4322:
296 + if (cc->pmu.rev == 2) {
297 + chipco_write32(cc, SSB_CHIPCO_PLLCTL_ADDR, 0x0000000A);
298 + chipco_write32(cc, SSB_CHIPCO_PLLCTL_DATA, 0x380005C0);
299 + }
300 + break;
301 default:
302 ssb_printk(KERN_ERR PFX
303 "ERROR: PLL init unknown for device %04X\n",
304 @@ -396,12 +424,15 @@ static void ssb_pmu_resources_init(struc
305 u32 min_msk = 0, max_msk = 0;
306 unsigned int i;
307 const struct pmu_res_updown_tab_entry *updown_tab = NULL;
308 - unsigned int updown_tab_size;
309 + unsigned int updown_tab_size = 0;
310 const struct pmu_res_depend_tab_entry *depend_tab = NULL;
311 - unsigned int depend_tab_size;
312 + unsigned int depend_tab_size = 0;
313
314 switch (bus->chip_id) {
315 case 0x4312:
316 + min_msk = 0xCBB;
317 + break;
318 + case 0x4322:
319 /* We keep the default settings:
320 * min_msk = 0xCBB
321 * max_msk = 0x7FFFF
322 @@ -480,9 +511,9 @@ static void ssb_pmu_resources_init(struc
323 chipco_write32(cc, SSB_CHIPCO_PMU_MAXRES_MSK, max_msk);
324 }
325
326 +/* http://bcm-v4.sipsolutions.net/802.11/SSB/PmuInit */
327 void ssb_pmu_init(struct ssb_chipcommon *cc)
328 {
329 - struct ssb_bus *bus = cc->dev->bus;
330 u32 pmucap;
331
332 if (!(cc->capabilities & SSB_CHIPCO_CAP_PMU))
333 @@ -494,15 +525,122 @@ void ssb_pmu_init(struct ssb_chipcommon
334 ssb_dprintk(KERN_DEBUG PFX "Found rev %u PMU (capabilities 0x%08X)\n",
335 cc->pmu.rev, pmucap);
336
337 - if (cc->pmu.rev >= 1) {
338 - if ((bus->chip_id == 0x4325) && (bus->chip_rev < 2)) {
339 - chipco_mask32(cc, SSB_CHIPCO_PMU_CTL,
340 - ~SSB_CHIPCO_PMU_CTL_NOILPONW);
341 - } else {
342 - chipco_set32(cc, SSB_CHIPCO_PMU_CTL,
343 - SSB_CHIPCO_PMU_CTL_NOILPONW);
344 - }
345 - }
346 + if (cc->pmu.rev == 1)
347 + chipco_mask32(cc, SSB_CHIPCO_PMU_CTL,
348 + ~SSB_CHIPCO_PMU_CTL_NOILPONW);
349 + else
350 + chipco_set32(cc, SSB_CHIPCO_PMU_CTL,
351 + SSB_CHIPCO_PMU_CTL_NOILPONW);
352 ssb_pmu_pll_init(cc);
353 ssb_pmu_resources_init(cc);
354 }
355 +
356 +void ssb_pmu_set_ldo_voltage(struct ssb_chipcommon *cc,
357 + enum ssb_pmu_ldo_volt_id id, u32 voltage)
358 +{
359 + struct ssb_bus *bus = cc->dev->bus;
360 + u32 addr, shift, mask;
361 +
362 + switch (bus->chip_id) {
363 + case 0x4328:
364 + case 0x5354:
365 + switch (id) {
366 + case LDO_VOLT1:
367 + addr = 2;
368 + shift = 25;
369 + mask = 0xF;
370 + break;
371 + case LDO_VOLT2:
372 + addr = 3;
373 + shift = 1;
374 + mask = 0xF;
375 + break;
376 + case LDO_VOLT3:
377 + addr = 3;
378 + shift = 9;
379 + mask = 0xF;
380 + break;
381 + case LDO_PAREF:
382 + addr = 3;
383 + shift = 17;
384 + mask = 0x3F;
385 + break;
386 + default:
387 + SSB_WARN_ON(1);
388 + return;
389 + }
390 + break;
391 + case 0x4312:
392 + if (SSB_WARN_ON(id != LDO_PAREF))
393 + return;
394 + addr = 0;
395 + shift = 21;
396 + mask = 0x3F;
397 + break;
398 + default:
399 + return;
400 + }
401 +
402 + ssb_chipco_regctl_maskset(cc, addr, ~(mask << shift),
403 + (voltage & mask) << shift);
404 +}
405 +
406 +void ssb_pmu_set_ldo_paref(struct ssb_chipcommon *cc, bool on)
407 +{
408 + struct ssb_bus *bus = cc->dev->bus;
409 + int ldo;
410 +
411 + switch (bus->chip_id) {
412 + case 0x4312:
413 + ldo = SSB_PMURES_4312_PA_REF_LDO;
414 + break;
415 + case 0x4328:
416 + ldo = SSB_PMURES_4328_PA_REF_LDO;
417 + break;
418 + case 0x5354:
419 + ldo = SSB_PMURES_5354_PA_REF_LDO;
420 + break;
421 + default:
422 + return;
423 + }
424 +
425 + if (on)
426 + chipco_set32(cc, SSB_CHIPCO_PMU_MINRES_MSK, 1 << ldo);
427 + else
428 + chipco_mask32(cc, SSB_CHIPCO_PMU_MINRES_MSK, ~(1 << ldo));
429 + chipco_read32(cc, SSB_CHIPCO_PMU_MINRES_MSK); //SPEC FIXME found via mmiotrace - dummy read?
430 +}
431 +
432 +EXPORT_SYMBOL(ssb_pmu_set_ldo_voltage);
433 +EXPORT_SYMBOL(ssb_pmu_set_ldo_paref);
434 +
435 +u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc)
436 +{
437 + struct ssb_bus *bus = cc->dev->bus;
438 +
439 + switch (bus->chip_id) {
440 + case 0x5354:
441 + /* 5354 chip uses a non programmable PLL of frequency 240MHz */
442 + return 240000000;
443 + default:
444 + ssb_printk(KERN_ERR PFX
445 + "ERROR: PMU cpu clock unknown for device %04X\n",
446 + bus->chip_id);
447 + return 0;
448 + }
449 +}
450 +
451 +u32 ssb_pmu_get_controlclock(struct ssb_chipcommon *cc)
452 +{
453 + struct ssb_bus *bus = cc->dev->bus;
454 +
455 + switch (bus->chip_id) {
456 + case 0x5354:
457 + return 120000000;
458 + default:
459 + ssb_printk(KERN_ERR PFX
460 + "ERROR: PMU controlclock unknown for device %04X\n",
461 + bus->chip_id);
462 + return 0;
463 + }
464 +}
465 --- a/drivers/ssb/driver_gige.c
466 +++ b/drivers/ssb/driver_gige.c
467 @@ -3,7 +3,7 @@
468 * Broadcom Gigabit Ethernet core driver
469 *
470 * Copyright 2008, Broadcom Corporation
471 - * Copyright 2008, Michael Buesch <mb@bu3sch.de>
472 + * Copyright 2008, Michael Buesch <m@bues.ch>
473 *
474 * Licensed under the GNU/GPL. See COPYING for details.
475 */
476 @@ -12,6 +12,7 @@
477 #include <linux/ssb/ssb_driver_gige.h>
478 #include <linux/pci.h>
479 #include <linux/pci_regs.h>
480 +#include <linux/slab.h>
481
482
483 /*
484 @@ -105,8 +106,9 @@ void gige_pcicfg_write32(struct ssb_gige
485 gige_write32(dev, SSB_GIGE_PCICFG + offset, value);
486 }
487
488 -static int ssb_gige_pci_read_config(struct pci_bus *bus, unsigned int devfn,
489 - int reg, int size, u32 *val)
490 +static int __devinit ssb_gige_pci_read_config(struct pci_bus *bus,
491 + unsigned int devfn, int reg,
492 + int size, u32 *val)
493 {
494 struct ssb_gige *dev = container_of(bus->ops, struct ssb_gige, pci_ops);
495 unsigned long flags;
496 @@ -135,8 +137,9 @@ static int ssb_gige_pci_read_config(stru
497 return PCIBIOS_SUCCESSFUL;
498 }
499
500 -static int ssb_gige_pci_write_config(struct pci_bus *bus, unsigned int devfn,
501 - int reg, int size, u32 val)
502 +static int __devinit ssb_gige_pci_write_config(struct pci_bus *bus,
503 + unsigned int devfn, int reg,
504 + int size, u32 val)
505 {
506 struct ssb_gige *dev = container_of(bus->ops, struct ssb_gige, pci_ops);
507 unsigned long flags;
508 @@ -165,7 +168,8 @@ static int ssb_gige_pci_write_config(str
509 return PCIBIOS_SUCCESSFUL;
510 }
511
512 -static int ssb_gige_probe(struct ssb_device *sdev, const struct ssb_device_id *id)
513 +static int __devinit ssb_gige_probe(struct ssb_device *sdev,
514 + const struct ssb_device_id *id)
515 {
516 struct ssb_gige *dev;
517 u32 base, tmslow, tmshigh;
518 --- a/drivers/ssb/driver_mipscore.c
519 +++ b/drivers/ssb/driver_mipscore.c
520 @@ -3,7 +3,7 @@
521 * Broadcom MIPS core driver
522 *
523 * Copyright 2005, Broadcom Corporation
524 - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
525 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
526 *
527 * Licensed under the GNU/GPL. See COPYING for details.
528 */
529 @@ -208,6 +208,9 @@ u32 ssb_cpu_clock(struct ssb_mipscore *m
530 struct ssb_bus *bus = mcore->dev->bus;
531 u32 pll_type, n, m, rate = 0;
532
533 + if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
534 + return ssb_pmu_get_cpu_clock(&bus->chipco);
535 +
536 if (bus->extif.dev) {
537 ssb_extif_get_clockcontrol(&bus->extif, &pll_type, &n, &m);
538 } else if (bus->chipco.dev) {
539 @@ -270,7 +273,6 @@ void ssb_mipscore_init(struct ssb_mipsco
540 set_irq(dev, irq++);
541 }
542 break;
543 - /* fallthrough */
544 case SSB_DEV_PCI:
545 case SSB_DEV_ETHERNET:
546 case SSB_DEV_ETHERNET_GBIT:
547 @@ -281,6 +283,10 @@ void ssb_mipscore_init(struct ssb_mipsco
548 set_irq(dev, irq++);
549 break;
550 }
551 + /* fallthrough */
552 + case SSB_DEV_EXTIF:
553 + set_irq(dev, 0);
554 + break;
555 }
556 }
557 ssb_dprintk(KERN_INFO PFX "after irq reconfiguration\n");
558 --- a/drivers/ssb/driver_pcicore.c
559 +++ b/drivers/ssb/driver_pcicore.c
560 @@ -3,7 +3,7 @@
561 * Broadcom PCI-core driver
562 *
563 * Copyright 2005, Broadcom Corporation
564 - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
565 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
566 *
567 * Licensed under the GNU/GPL. See COPYING for details.
568 */
569 @@ -15,6 +15,11 @@
570
571 #include "ssb_private.h"
572
573 +static u32 ssb_pcie_read(struct ssb_pcicore *pc, u32 address);
574 +static void ssb_pcie_write(struct ssb_pcicore *pc, u32 address, u32 data);
575 +static u16 ssb_pcie_mdio_read(struct ssb_pcicore *pc, u8 device, u8 address);
576 +static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
577 + u8 address, u16 data);
578
579 static inline
580 u32 pcicore_read32(struct ssb_pcicore *pc, u16 offset)
581 @@ -69,7 +74,7 @@ static u32 get_cfgspace_addr(struct ssb_
582 u32 tmp;
583
584 /* We do only have one cardbus device behind the bridge. */
585 - if (pc->cardbusmode && (dev >= 1))
586 + if (pc->cardbusmode && (dev > 1))
587 goto out;
588
589 if (bus == 0) {
590 @@ -246,20 +251,12 @@ static struct pci_controller ssb_pcicore
591 .pci_ops = &ssb_pcicore_pciops,
592 .io_resource = &ssb_pcicore_io_resource,
593 .mem_resource = &ssb_pcicore_mem_resource,
594 - .mem_offset = 0x24000000,
595 };
596
597 -static u32 ssb_pcicore_pcibus_iobase = 0x100;
598 -static u32 ssb_pcicore_pcibus_membase = SSB_PCI_DMA;
599 -
600 /* This function is called when doing a pci_enable_device().
601 * We must first check if the device is a device on the PCI-core bridge. */
602 int ssb_pcicore_plat_dev_init(struct pci_dev *d)
603 {
604 - struct resource *res;
605 - int pos, size;
606 - u32 *base;
607 -
608 if (d->bus->ops != &ssb_pcicore_pciops) {
609 /* This is not a device on the PCI-core bridge. */
610 return -ENODEV;
611 @@ -268,27 +265,6 @@ int ssb_pcicore_plat_dev_init(struct pci
612 ssb_printk(KERN_INFO "PCI: Fixing up device %s\n",
613 pci_name(d));
614
615 - /* Fix up resource bases */
616 - for (pos = 0; pos < 6; pos++) {
617 - res = &d->resource[pos];
618 - if (res->flags & IORESOURCE_IO)
619 - base = &ssb_pcicore_pcibus_iobase;
620 - else
621 - base = &ssb_pcicore_pcibus_membase;
622 - res->flags |= IORESOURCE_PCI_FIXED;
623 - if (res->end) {
624 - size = res->end - res->start + 1;
625 - if (*base & (size - 1))
626 - *base = (*base + size) & ~(size - 1);
627 - res->start = *base;
628 - res->end = res->start + size - 1;
629 - *base += size;
630 - pci_write_config_dword(d, PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
631 - }
632 - /* Fix up PCI bridge BAR0 only */
633 - if (d->bus->number == 0 && PCI_SLOT(d->devfn) == 0)
634 - break;
635 - }
636 /* Fix up interrupt lines */
637 d->irq = ssb_mips_irq(extpci_core->dev) + 2;
638 pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
639 @@ -338,7 +314,7 @@ int ssb_pcicore_pcibios_map_irq(const st
640 return ssb_mips_irq(extpci_core->dev) + 2;
641 }
642
643 -static void ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
644 +static void __devinit ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
645 {
646 u32 val;
647
648 @@ -403,7 +379,7 @@ static void ssb_pcicore_init_hostmode(st
649 register_pci_controller(&ssb_pcicore_controller);
650 }
651
652 -static int pcicore_is_in_hostmode(struct ssb_pcicore *pc)
653 +static int __devinit pcicore_is_in_hostmode(struct ssb_pcicore *pc)
654 {
655 struct ssb_bus *bus = pc->dev->bus;
656 u16 chipid_top;
657 @@ -432,25 +408,137 @@ static int pcicore_is_in_hostmode(struct
658 }
659 #endif /* CONFIG_SSB_PCICORE_HOSTMODE */
660
661 +/**************************************************
662 + * Workarounds.
663 + **************************************************/
664 +
665 +static void __devinit ssb_pcicore_fix_sprom_core_index(struct ssb_pcicore *pc)
666 +{
667 + u16 tmp = pcicore_read16(pc, SSB_PCICORE_SPROM(0));
668 + if (((tmp & 0xF000) >> 12) != pc->dev->core_index) {
669 + tmp &= ~0xF000;
670 + tmp |= (pc->dev->core_index << 12);
671 + pcicore_write16(pc, SSB_PCICORE_SPROM(0), tmp);
672 + }
673 +}
674 +
675 +static u8 ssb_pcicore_polarity_workaround(struct ssb_pcicore *pc)
676 +{
677 + return (ssb_pcie_read(pc, 0x204) & 0x10) ? 0xC0 : 0x80;
678 +}
679 +
680 +static void ssb_pcicore_serdes_workaround(struct ssb_pcicore *pc)
681 +{
682 + const u8 serdes_pll_device = 0x1D;
683 + const u8 serdes_rx_device = 0x1F;
684 + u16 tmp;
685 +
686 + ssb_pcie_mdio_write(pc, serdes_rx_device, 1 /* Control */,
687 + ssb_pcicore_polarity_workaround(pc));
688 + tmp = ssb_pcie_mdio_read(pc, serdes_pll_device, 1 /* Control */);
689 + if (tmp & 0x4000)
690 + ssb_pcie_mdio_write(pc, serdes_pll_device, 1, tmp & ~0x4000);
691 +}
692 +
693 +static void ssb_pcicore_pci_setup_workarounds(struct ssb_pcicore *pc)
694 +{
695 + struct ssb_device *pdev = pc->dev;
696 + struct ssb_bus *bus = pdev->bus;
697 + u32 tmp;
698 +
699 + tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
700 + tmp |= SSB_PCICORE_SBTOPCI_PREF;
701 + tmp |= SSB_PCICORE_SBTOPCI_BURST;
702 + pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
703 +
704 + if (pdev->id.revision < 5) {
705 + tmp = ssb_read32(pdev, SSB_IMCFGLO);
706 + tmp &= ~SSB_IMCFGLO_SERTO;
707 + tmp |= 2;
708 + tmp &= ~SSB_IMCFGLO_REQTO;
709 + tmp |= 3 << SSB_IMCFGLO_REQTO_SHIFT;
710 + ssb_write32(pdev, SSB_IMCFGLO, tmp);
711 + ssb_commit_settings(bus);
712 + } else if (pdev->id.revision >= 11) {
713 + tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
714 + tmp |= SSB_PCICORE_SBTOPCI_MRM;
715 + pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
716 + }
717 +}
718 +
719 +static void ssb_pcicore_pcie_setup_workarounds(struct ssb_pcicore *pc)
720 +{
721 + u32 tmp;
722 + u8 rev = pc->dev->id.revision;
723 +
724 + if (rev == 0 || rev == 1) {
725 + /* TLP Workaround register. */
726 + tmp = ssb_pcie_read(pc, 0x4);
727 + tmp |= 0x8;
728 + ssb_pcie_write(pc, 0x4, tmp);
729 + }
730 + if (rev == 1) {
731 + /* DLLP Link Control register. */
732 + tmp = ssb_pcie_read(pc, 0x100);
733 + tmp |= 0x40;
734 + ssb_pcie_write(pc, 0x100, tmp);
735 + }
736 +
737 + if (rev == 0) {
738 + const u8 serdes_rx_device = 0x1F;
739 +
740 + ssb_pcie_mdio_write(pc, serdes_rx_device,
741 + 2 /* Timer */, 0x8128);
742 + ssb_pcie_mdio_write(pc, serdes_rx_device,
743 + 6 /* CDR */, 0x0100);
744 + ssb_pcie_mdio_write(pc, serdes_rx_device,
745 + 7 /* CDR BW */, 0x1466);
746 + } else if (rev == 3 || rev == 4 || rev == 5) {
747 + /* TODO: DLLP Power Management Threshold */
748 + ssb_pcicore_serdes_workaround(pc);
749 + /* TODO: ASPM */
750 + } else if (rev == 7) {
751 + /* TODO: No PLL down */
752 + }
753 +
754 + if (rev >= 6) {
755 + /* Miscellaneous Configuration Fixup */
756 + tmp = pcicore_read16(pc, SSB_PCICORE_SPROM(5));
757 + if (!(tmp & 0x8000))
758 + pcicore_write16(pc, SSB_PCICORE_SPROM(5),
759 + tmp | 0x8000);
760 + }
761 +}
762
763 /**************************************************
764 * Generic and Clientmode operation code.
765 **************************************************/
766
767 -static void ssb_pcicore_init_clientmode(struct ssb_pcicore *pc)
768 +static void __devinit ssb_pcicore_init_clientmode(struct ssb_pcicore *pc)
769 {
770 + struct ssb_device *pdev = pc->dev;
771 + struct ssb_bus *bus = pdev->bus;
772 +
773 + if (bus->bustype == SSB_BUSTYPE_PCI)
774 + ssb_pcicore_fix_sprom_core_index(pc);
775 +
776 /* Disable PCI interrupts. */
777 - ssb_write32(pc->dev, SSB_INTVEC, 0);
778 + ssb_write32(pdev, SSB_INTVEC, 0);
779 +
780 + /* Additional PCIe always once-executed workarounds */
781 + if (pc->dev->id.coreid == SSB_DEV_PCIE) {
782 + ssb_pcicore_serdes_workaround(pc);
783 + /* TODO: ASPM */
784 + /* TODO: Clock Request Update */
785 + }
786 }
787
788 -void ssb_pcicore_init(struct ssb_pcicore *pc)
789 +void __devinit ssb_pcicore_init(struct ssb_pcicore *pc)
790 {
791 struct ssb_device *dev = pc->dev;
792 - struct ssb_bus *bus;
793
794 if (!dev)
795 return;
796 - bus = dev->bus;
797 if (!ssb_device_is_enabled(dev))
798 ssb_device_enable(dev, 0);
799
800 @@ -475,58 +563,104 @@ static void ssb_pcie_write(struct ssb_pc
801 pcicore_write32(pc, 0x134, data);
802 }
803
804 -static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
805 - u8 address, u16 data)
806 +static void ssb_pcie_mdio_set_phy(struct ssb_pcicore *pc, u8 phy)
807 {
808 const u16 mdio_control = 0x128;
809 const u16 mdio_data = 0x12C;
810 u32 v;
811 int i;
812
813 + v = (1 << 30); /* Start of Transaction */
814 + v |= (1 << 28); /* Write Transaction */
815 + v |= (1 << 17); /* Turnaround */
816 + v |= (0x1F << 18);
817 + v |= (phy << 4);
818 + pcicore_write32(pc, mdio_data, v);
819 +
820 + udelay(10);
821 + for (i = 0; i < 200; i++) {
822 + v = pcicore_read32(pc, mdio_control);
823 + if (v & 0x100 /* Trans complete */)
824 + break;
825 + msleep(1);
826 + }
827 +}
828 +
829 +static u16 ssb_pcie_mdio_read(struct ssb_pcicore *pc, u8 device, u8 address)
830 +{
831 + const u16 mdio_control = 0x128;
832 + const u16 mdio_data = 0x12C;
833 + int max_retries = 10;
834 + u16 ret = 0;
835 + u32 v;
836 + int i;
837 +
838 v = 0x80; /* Enable Preamble Sequence */
839 v |= 0x2; /* MDIO Clock Divisor */
840 pcicore_write32(pc, mdio_control, v);
841
842 + if (pc->dev->id.revision >= 10) {
843 + max_retries = 200;
844 + ssb_pcie_mdio_set_phy(pc, device);
845 + }
846 +
847 v = (1 << 30); /* Start of Transaction */
848 - v |= (1 << 28); /* Write Transaction */
849 + v |= (1 << 29); /* Read Transaction */
850 v |= (1 << 17); /* Turnaround */
851 - v |= (u32)device << 22;
852 + if (pc->dev->id.revision < 10)
853 + v |= (u32)device << 22;
854 v |= (u32)address << 18;
855 - v |= data;
856 pcicore_write32(pc, mdio_data, v);
857 /* Wait for the device to complete the transaction */
858 udelay(10);
859 - for (i = 0; i < 10; i++) {
860 + for (i = 0; i < max_retries; i++) {
861 v = pcicore_read32(pc, mdio_control);
862 - if (v & 0x100 /* Trans complete */)
863 + if (v & 0x100 /* Trans complete */) {
864 + udelay(10);
865 + ret = pcicore_read32(pc, mdio_data);
866 break;
867 + }
868 msleep(1);
869 }
870 pcicore_write32(pc, mdio_control, 0);
871 + return ret;
872 }
873
874 -static void ssb_broadcast_value(struct ssb_device *dev,
875 - u32 address, u32 data)
876 +static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
877 + u8 address, u16 data)
878 {
879 - /* This is used for both, PCI and ChipCommon core, so be careful. */
880 - BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
881 - BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
882 + const u16 mdio_control = 0x128;
883 + const u16 mdio_data = 0x12C;
884 + int max_retries = 10;
885 + u32 v;
886 + int i;
887
888 - ssb_write32(dev, SSB_PCICORE_BCAST_ADDR, address);
889 - ssb_read32(dev, SSB_PCICORE_BCAST_ADDR); /* flush */
890 - ssb_write32(dev, SSB_PCICORE_BCAST_DATA, data);
891 - ssb_read32(dev, SSB_PCICORE_BCAST_DATA); /* flush */
892 -}
893 + v = 0x80; /* Enable Preamble Sequence */
894 + v |= 0x2; /* MDIO Clock Divisor */
895 + pcicore_write32(pc, mdio_control, v);
896
897 -static void ssb_commit_settings(struct ssb_bus *bus)
898 -{
899 - struct ssb_device *dev;
900 + if (pc->dev->id.revision >= 10) {
901 + max_retries = 200;
902 + ssb_pcie_mdio_set_phy(pc, device);
903 + }
904
905 - dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
906 - if (WARN_ON(!dev))
907 - return;
908 - /* This forces an update of the cached registers. */
909 - ssb_broadcast_value(dev, 0xFD8, 0);
910 + v = (1 << 30); /* Start of Transaction */
911 + v |= (1 << 28); /* Write Transaction */
912 + v |= (1 << 17); /* Turnaround */
913 + if (pc->dev->id.revision < 10)
914 + v |= (u32)device << 22;
915 + v |= (u32)address << 18;
916 + v |= data;
917 + pcicore_write32(pc, mdio_data, v);
918 + /* Wait for the device to complete the transaction */
919 + udelay(10);
920 + for (i = 0; i < max_retries; i++) {
921 + v = pcicore_read32(pc, mdio_control);
922 + if (v & 0x100 /* Trans complete */)
923 + break;
924 + msleep(1);
925 + }
926 + pcicore_write32(pc, mdio_control, 0);
927 }
928
929 int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc,
930 @@ -551,13 +685,13 @@ int ssb_pcicore_dev_irqvecs_enable(struc
931 might_sleep_if(pdev->id.coreid != SSB_DEV_PCI);
932
933 /* Enable interrupts for this device. */
934 - if (bus->host_pci &&
935 - ((pdev->id.revision >= 6) || (pdev->id.coreid == SSB_DEV_PCIE))) {
936 + if ((pdev->id.revision >= 6) || (pdev->id.coreid == SSB_DEV_PCIE)) {
937 u32 coremask;
938
939 /* Calculate the "coremask" for the device. */
940 coremask = (1 << dev->core_index);
941
942 + SSB_WARN_ON(bus->bustype != SSB_BUSTYPE_PCI);
943 err = pci_read_config_dword(bus->host_pci, SSB_PCI_IRQMASK, &tmp);
944 if (err)
945 goto out;
946 @@ -579,48 +713,10 @@ int ssb_pcicore_dev_irqvecs_enable(struc
947 if (pc->setup_done)
948 goto out;
949 if (pdev->id.coreid == SSB_DEV_PCI) {
950 - tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
951 - tmp |= SSB_PCICORE_SBTOPCI_PREF;
952 - tmp |= SSB_PCICORE_SBTOPCI_BURST;
953 - pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
954 -
955 - if (pdev->id.revision < 5) {
956 - tmp = ssb_read32(pdev, SSB_IMCFGLO);
957 - tmp &= ~SSB_IMCFGLO_SERTO;
958 - tmp |= 2;
959 - tmp &= ~SSB_IMCFGLO_REQTO;
960 - tmp |= 3 << SSB_IMCFGLO_REQTO_SHIFT;
961 - ssb_write32(pdev, SSB_IMCFGLO, tmp);
962 - ssb_commit_settings(bus);
963 - } else if (pdev->id.revision >= 11) {
964 - tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
965 - tmp |= SSB_PCICORE_SBTOPCI_MRM;
966 - pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
967 - }
968 + ssb_pcicore_pci_setup_workarounds(pc);
969 } else {
970 WARN_ON(pdev->id.coreid != SSB_DEV_PCIE);
971 - //TODO: Better make defines for all these magic PCIE values.
972 - if ((pdev->id.revision == 0) || (pdev->id.revision == 1)) {
973 - /* TLP Workaround register. */
974 - tmp = ssb_pcie_read(pc, 0x4);
975 - tmp |= 0x8;
976 - ssb_pcie_write(pc, 0x4, tmp);
977 - }
978 - if (pdev->id.revision == 0) {
979 - const u8 serdes_rx_device = 0x1F;
980 -
981 - ssb_pcie_mdio_write(pc, serdes_rx_device,
982 - 2 /* Timer */, 0x8128);
983 - ssb_pcie_mdio_write(pc, serdes_rx_device,
984 - 6 /* CDR */, 0x0100);
985 - ssb_pcie_mdio_write(pc, serdes_rx_device,
986 - 7 /* CDR BW */, 0x1466);
987 - } else if (pdev->id.revision == 1) {
988 - /* DLLP Link Control register. */
989 - tmp = ssb_pcie_read(pc, 0x100);
990 - tmp |= 0x40;
991 - ssb_pcie_write(pc, 0x100, tmp);
992 - }
993 + ssb_pcicore_pcie_setup_workarounds(pc);
994 }
995 pc->setup_done = 1;
996 out:
997 --- a/drivers/ssb/main.c
998 +++ b/drivers/ssb/main.c
999 @@ -3,7 +3,7 @@
1000 * Subsystem core
1001 *
1002 * Copyright 2005, Broadcom Corporation
1003 - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
1004 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
1005 *
1006 * Licensed under the GNU/GPL. See COPYING for details.
1007 */
1008 @@ -12,11 +12,14 @@
1009
1010 #include <linux/delay.h>
1011 #include <linux/io.h>
1012 +#include <linux/module.h>
1013 #include <linux/ssb/ssb.h>
1014 #include <linux/ssb/ssb_regs.h>
1015 #include <linux/ssb/ssb_driver_gige.h>
1016 #include <linux/dma-mapping.h>
1017 #include <linux/pci.h>
1018 +#include <linux/mmc/sdio_func.h>
1019 +#include <linux/slab.h>
1020
1021 #include <pcmcia/cs_types.h>
1022 #include <pcmcia/cs.h>
1023 @@ -88,6 +91,25 @@ found:
1024 }
1025 #endif /* CONFIG_SSB_PCMCIAHOST */
1026
1027 +#ifdef CONFIG_SSB_SDIOHOST
1028 +struct ssb_bus *ssb_sdio_func_to_bus(struct sdio_func *func)
1029 +{
1030 + struct ssb_bus *bus;
1031 +
1032 + ssb_buses_lock();
1033 + list_for_each_entry(bus, &buses, list) {
1034 + if (bus->bustype == SSB_BUSTYPE_SDIO &&
1035 + bus->host_sdio == func)
1036 + goto found;
1037 + }
1038 + bus = NULL;
1039 +found:
1040 + ssb_buses_unlock();
1041 +
1042 + return bus;
1043 +}
1044 +#endif /* CONFIG_SSB_SDIOHOST */
1045 +
1046 int ssb_for_each_bus_call(unsigned long data,
1047 int (*func)(struct ssb_bus *bus, unsigned long data))
1048 {
1049 @@ -190,90 +212,78 @@ int ssb_bus_suspend(struct ssb_bus *bus)
1050 EXPORT_SYMBOL(ssb_bus_suspend);
1051
1052 #ifdef CONFIG_SSB_SPROM
1053 -int ssb_devices_freeze(struct ssb_bus *bus)
1054 +/** ssb_devices_freeze - Freeze all devices on the bus.
1055 + *
1056 + * After freezing no device driver will be handling a device
1057 + * on this bus anymore. ssb_devices_thaw() must be called after
1058 + * a successful freeze to reactivate the devices.
1059 + *
1060 + * @bus: The bus.
1061 + * @ctx: Context structure. Pass this to ssb_devices_thaw().
1062 + */
1063 +int ssb_devices_freeze(struct ssb_bus *bus, struct ssb_freeze_context *ctx)
1064 {
1065 - struct ssb_device *dev;
1066 - struct ssb_driver *drv;
1067 - int err = 0;
1068 - int i;
1069 - pm_message_t state = PMSG_FREEZE;
1070 + struct ssb_device *sdev;
1071 + struct ssb_driver *sdrv;
1072 + unsigned int i;
1073 +
1074 + memset(ctx, 0, sizeof(*ctx));
1075 + ctx->bus = bus;
1076 + SSB_WARN_ON(bus->nr_devices > ARRAY_SIZE(ctx->device_frozen));
1077
1078 - /* First check that we are capable to freeze all devices. */
1079 for (i = 0; i < bus->nr_devices; i++) {
1080 - dev = &(bus->devices[i]);
1081 - if (!dev->dev ||
1082 - !dev->dev->driver ||
1083 - !device_is_registered(dev->dev))
1084 - continue;
1085 - drv = drv_to_ssb_drv(dev->dev->driver);
1086 - if (!drv)
1087 + sdev = ssb_device_get(&bus->devices[i]);
1088 +
1089 + if (!sdev->dev || !sdev->dev->driver ||
1090 + !device_is_registered(sdev->dev)) {
1091 + ssb_device_put(sdev);
1092 continue;
1093 - if (!drv->suspend) {
1094 - /* Nope, can't suspend this one. */
1095 - return -EOPNOTSUPP;
1096 }
1097 - }
1098 - /* Now suspend all devices */
1099 - for (i = 0; i < bus->nr_devices; i++) {
1100 - dev = &(bus->devices[i]);
1101 - if (!dev->dev ||
1102 - !dev->dev->driver ||
1103 - !device_is_registered(dev->dev))
1104 - continue;
1105 - drv = drv_to_ssb_drv(dev->dev->driver);
1106 - if (!drv)
1107 + sdrv = drv_to_ssb_drv(sdev->dev->driver);
1108 + if (SSB_WARN_ON(!sdrv->remove))
1109 continue;
1110 - err = drv->suspend(dev, state);
1111 - if (err) {
1112 - ssb_printk(KERN_ERR PFX "Failed to freeze device %s\n",
1113 - dev_name(dev->dev));
1114 - goto err_unwind;
1115 - }
1116 + sdrv->remove(sdev);
1117 + ctx->device_frozen[i] = 1;
1118 }
1119
1120 return 0;
1121 -err_unwind:
1122 - for (i--; i >= 0; i--) {
1123 - dev = &(bus->devices[i]);
1124 - if (!dev->dev ||
1125 - !dev->dev->driver ||
1126 - !device_is_registered(dev->dev))
1127 - continue;
1128 - drv = drv_to_ssb_drv(dev->dev->driver);
1129 - if (!drv)
1130 - continue;
1131 - if (drv->resume)
1132 - drv->resume(dev);
1133 - }
1134 - return err;
1135 }
1136
1137 -int ssb_devices_thaw(struct ssb_bus *bus)
1138 +/** ssb_devices_thaw - Unfreeze all devices on the bus.
1139 + *
1140 + * This will re-attach the device drivers and re-init the devices.
1141 + *
1142 + * @ctx: The context structure from ssb_devices_freeze()
1143 + */
1144 +int ssb_devices_thaw(struct ssb_freeze_context *ctx)
1145 {
1146 - struct ssb_device *dev;
1147 - struct ssb_driver *drv;
1148 - int err;
1149 - int i;
1150 + struct ssb_bus *bus = ctx->bus;
1151 + struct ssb_device *sdev;
1152 + struct ssb_driver *sdrv;
1153 + unsigned int i;
1154 + int err, result = 0;
1155
1156 for (i = 0; i < bus->nr_devices; i++) {
1157 - dev = &(bus->devices[i]);
1158 - if (!dev->dev ||
1159 - !dev->dev->driver ||
1160 - !device_is_registered(dev->dev))
1161 + if (!ctx->device_frozen[i])
1162 continue;
1163 - drv = drv_to_ssb_drv(dev->dev->driver);
1164 - if (!drv)
1165 + sdev = &bus->devices[i];
1166 +
1167 + if (SSB_WARN_ON(!sdev->dev || !sdev->dev->driver))
1168 continue;
1169 - if (SSB_WARN_ON(!drv->resume))
1170 + sdrv = drv_to_ssb_drv(sdev->dev->driver);
1171 + if (SSB_WARN_ON(!sdrv || !sdrv->probe))
1172 continue;
1173 - err = drv->resume(dev);
1174 +
1175 + err = sdrv->probe(sdev, &sdev->id);
1176 if (err) {
1177 ssb_printk(KERN_ERR PFX "Failed to thaw device %s\n",
1178 - dev_name(dev->dev));
1179 + dev_name(sdev->dev));
1180 + result = err;
1181 }
1182 + ssb_device_put(sdev);
1183 }
1184
1185 - return 0;
1186 + return result;
1187 }
1188 #endif /* CONFIG_SSB_SPROM */
1189
1190 @@ -360,6 +370,35 @@ static int ssb_device_uevent(struct devi
1191 ssb_dev->id.revision);
1192 }
1193
1194 +#define ssb_config_attr(attrib, field, format_string) \
1195 +static ssize_t \
1196 +attrib##_show(struct device *dev, struct device_attribute *attr, char *buf) \
1197 +{ \
1198 + return sprintf(buf, format_string, dev_to_ssb_dev(dev)->field); \
1199 +}
1200 +
1201 +ssb_config_attr(core_num, core_index, "%u\n")
1202 +ssb_config_attr(coreid, id.coreid, "0x%04x\n")
1203 +ssb_config_attr(vendor, id.vendor, "0x%04x\n")
1204 +ssb_config_attr(revision, id.revision, "%u\n")
1205 +ssb_config_attr(irq, irq, "%u\n")
1206 +static ssize_t
1207 +name_show(struct device *dev, struct device_attribute *attr, char *buf)
1208 +{
1209 + return sprintf(buf, "%s\n",
1210 + ssb_core_name(dev_to_ssb_dev(dev)->id.coreid));
1211 +}
1212 +
1213 +static struct device_attribute ssb_device_attrs[] = {
1214 + __ATTR_RO(name),
1215 + __ATTR_RO(core_num),
1216 + __ATTR_RO(coreid),
1217 + __ATTR_RO(vendor),
1218 + __ATTR_RO(revision),
1219 + __ATTR_RO(irq),
1220 + __ATTR_NULL,
1221 +};
1222 +
1223 static struct bus_type ssb_bustype = {
1224 .name = "ssb",
1225 .match = ssb_bus_match,
1226 @@ -369,6 +408,7 @@ static struct bus_type ssb_bustype = {
1227 .suspend = ssb_device_suspend,
1228 .resume = ssb_device_resume,
1229 .uevent = ssb_device_uevent,
1230 + .dev_attrs = ssb_device_attrs,
1231 };
1232
1233 static void ssb_buses_lock(void)
1234 @@ -461,6 +501,7 @@ static int ssb_devices_register(struct s
1235 #ifdef CONFIG_SSB_PCIHOST
1236 sdev->irq = bus->host_pci->irq;
1237 dev->parent = &bus->host_pci->dev;
1238 + sdev->dma_dev = dev->parent;
1239 #endif
1240 break;
1241 case SSB_BUSTYPE_PCMCIA:
1242 @@ -469,8 +510,14 @@ static int ssb_devices_register(struct s
1243 dev->parent = &bus->host_pcmcia->dev;
1244 #endif
1245 break;
1246 + case SSB_BUSTYPE_SDIO:
1247 +#ifdef CONFIG_SSB_SDIOHOST
1248 + dev->parent = &bus->host_sdio->dev;
1249 +#endif
1250 + break;
1251 case SSB_BUSTYPE_SSB:
1252 dev->dma_mask = &dev->coherent_dma_mask;
1253 + sdev->dma_dev = dev;
1254 break;
1255 }
1256
1257 @@ -497,7 +544,7 @@ error:
1258 }
1259
1260 /* Needs ssb_buses_lock() */
1261 -static int ssb_attach_queued_buses(void)
1262 +static int __devinit ssb_attach_queued_buses(void)
1263 {
1264 struct ssb_bus *bus, *n;
1265 int err = 0;
1266 @@ -708,9 +755,9 @@ out:
1267 return err;
1268 }
1269
1270 -static int ssb_bus_register(struct ssb_bus *bus,
1271 - ssb_invariants_func_t get_invariants,
1272 - unsigned long baseaddr)
1273 +static int __devinit ssb_bus_register(struct ssb_bus *bus,
1274 + ssb_invariants_func_t get_invariants,
1275 + unsigned long baseaddr)
1276 {
1277 int err;
1278
1279 @@ -724,12 +771,18 @@ static int ssb_bus_register(struct ssb_b
1280 err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
1281 if (err)
1282 goto out;
1283 +
1284 + /* Init SDIO-host device (if any), before the scan */
1285 + err = ssb_sdio_init(bus);
1286 + if (err)
1287 + goto err_disable_xtal;
1288 +
1289 ssb_buses_lock();
1290 bus->busnumber = next_busnumber;
1291 /* Scan for devices (cores) */
1292 err = ssb_bus_scan(bus, baseaddr);
1293 if (err)
1294 - goto err_disable_xtal;
1295 + goto err_sdio_exit;
1296
1297 /* Init PCI-host device (if any) */
1298 err = ssb_pci_init(bus);
1299 @@ -776,6 +829,8 @@ err_pci_exit:
1300 ssb_pci_exit(bus);
1301 err_unmap:
1302 ssb_iounmap(bus);
1303 +err_sdio_exit:
1304 + ssb_sdio_exit(bus);
1305 err_disable_xtal:
1306 ssb_buses_unlock();
1307 ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0);
1308 @@ -783,8 +838,8 @@ err_disable_xtal:
1309 }
1310
1311 #ifdef CONFIG_SSB_PCIHOST
1312 -int ssb_bus_pcibus_register(struct ssb_bus *bus,
1313 - struct pci_dev *host_pci)
1314 +int __devinit ssb_bus_pcibus_register(struct ssb_bus *bus,
1315 + struct pci_dev *host_pci)
1316 {
1317 int err;
1318
1319 @@ -796,6 +851,9 @@ int ssb_bus_pcibus_register(struct ssb_b
1320 if (!err) {
1321 ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
1322 "PCI device %s\n", dev_name(&host_pci->dev));
1323 + } else {
1324 + ssb_printk(KERN_ERR PFX "Failed to register PCI version"
1325 + " of SSB with error %d\n", err);
1326 }
1327
1328 return err;
1329 @@ -804,9 +862,9 @@ EXPORT_SYMBOL(ssb_bus_pcibus_register);
1330 #endif /* CONFIG_SSB_PCIHOST */
1331
1332 #ifdef CONFIG_SSB_PCMCIAHOST
1333 -int ssb_bus_pcmciabus_register(struct ssb_bus *bus,
1334 - struct pcmcia_device *pcmcia_dev,
1335 - unsigned long baseaddr)
1336 +int __devinit ssb_bus_pcmciabus_register(struct ssb_bus *bus,
1337 + struct pcmcia_device *pcmcia_dev,
1338 + unsigned long baseaddr)
1339 {
1340 int err;
1341
1342 @@ -825,9 +883,32 @@ int ssb_bus_pcmciabus_register(struct ss
1343 EXPORT_SYMBOL(ssb_bus_pcmciabus_register);
1344 #endif /* CONFIG_SSB_PCMCIAHOST */
1345
1346 -int ssb_bus_ssbbus_register(struct ssb_bus *bus,
1347 - unsigned long baseaddr,
1348 - ssb_invariants_func_t get_invariants)
1349 +#ifdef CONFIG_SSB_SDIOHOST
1350 +int __devinit ssb_bus_sdiobus_register(struct ssb_bus *bus,
1351 + struct sdio_func *func,
1352 + unsigned int quirks)
1353 +{
1354 + int err;
1355 +
1356 + bus->bustype = SSB_BUSTYPE_SDIO;
1357 + bus->host_sdio = func;
1358 + bus->ops = &ssb_sdio_ops;
1359 + bus->quirks = quirks;
1360 +
1361 + err = ssb_bus_register(bus, ssb_sdio_get_invariants, ~0);
1362 + if (!err) {
1363 + ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
1364 + "SDIO device %s\n", sdio_func_id(func));
1365 + }
1366 +
1367 + return err;
1368 +}
1369 +EXPORT_SYMBOL(ssb_bus_sdiobus_register);
1370 +#endif /* CONFIG_SSB_PCMCIAHOST */
1371 +
1372 +int __devinit ssb_bus_ssbbus_register(struct ssb_bus *bus,
1373 + unsigned long baseaddr,
1374 + ssb_invariants_func_t get_invariants)
1375 {
1376 int err;
1377
1378 @@ -908,8 +989,8 @@ u32 ssb_calc_clock_rate(u32 plltype, u32
1379 switch (plltype) {
1380 case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */
1381 if (m & SSB_CHIPCO_CLK_T6_MMASK)
1382 - return SSB_CHIPCO_CLK_T6_M0;
1383 - return SSB_CHIPCO_CLK_T6_M1;
1384 + return SSB_CHIPCO_CLK_T6_M1;
1385 + return SSB_CHIPCO_CLK_T6_M0;
1386 case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */
1387 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
1388 case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */
1389 @@ -999,6 +1080,9 @@ u32 ssb_clockspeed(struct ssb_bus *bus)
1390 u32 plltype;
1391 u32 clkctl_n, clkctl_m;
1392
1393 + if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
1394 + return ssb_pmu_get_controlclock(&bus->chipco);
1395 +
1396 if (ssb_extif_available(&bus->extif))
1397 ssb_extif_get_clockcontrol(&bus->extif, &plltype,
1398 &clkctl_n, &clkctl_m);
1399 @@ -1024,23 +1108,22 @@ static u32 ssb_tmslow_reject_bitmask(str
1400 {
1401 u32 rev = ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_SSBREV;
1402
1403 - /* The REJECT bit changed position in TMSLOW between
1404 - * Backplane revisions. */
1405 + /* The REJECT bit seems to be different for Backplane rev 2.3 */
1406 switch (rev) {
1407 case SSB_IDLOW_SSBREV_22:
1408 - return SSB_TMSLOW_REJECT_22;
1409 + case SSB_IDLOW_SSBREV_24:
1410 + case SSB_IDLOW_SSBREV_26:
1411 + return SSB_TMSLOW_REJECT;
1412 case SSB_IDLOW_SSBREV_23:
1413 return SSB_TMSLOW_REJECT_23;
1414 - case SSB_IDLOW_SSBREV_24: /* TODO - find the proper REJECT bits */
1415 - case SSB_IDLOW_SSBREV_25: /* same here */
1416 - case SSB_IDLOW_SSBREV_26: /* same here */
1417 + case SSB_IDLOW_SSBREV_25: /* TODO - find the proper REJECT bit */
1418 case SSB_IDLOW_SSBREV_27: /* same here */
1419 - return SSB_TMSLOW_REJECT_23; /* this is a guess */
1420 + return SSB_TMSLOW_REJECT; /* this is a guess */
1421 default:
1422 printk(KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev);
1423 WARN_ON(1);
1424 }
1425 - return (SSB_TMSLOW_REJECT_22 | SSB_TMSLOW_REJECT_23);
1426 + return (SSB_TMSLOW_REJECT | SSB_TMSLOW_REJECT_23);
1427 }
1428
1429 int ssb_device_is_enabled(struct ssb_device *dev)
1430 @@ -1099,10 +1182,10 @@ void ssb_device_enable(struct ssb_device
1431 }
1432 EXPORT_SYMBOL(ssb_device_enable);
1433
1434 -/* Wait for a bit in a register to get set or unset.
1435 +/* Wait for bitmask in a register to get set or cleared.
1436 * timeout is in units of ten-microseconds */
1437 -static int ssb_wait_bit(struct ssb_device *dev, u16 reg, u32 bitmask,
1438 - int timeout, int set)
1439 +static int ssb_wait_bits(struct ssb_device *dev, u16 reg, u32 bitmask,
1440 + int timeout, int set)
1441 {
1442 int i;
1443 u32 val;
1444 @@ -1110,7 +1193,7 @@ static int ssb_wait_bit(struct ssb_devic
1445 for (i = 0; i < timeout; i++) {
1446 val = ssb_read32(dev, reg);
1447 if (set) {
1448 - if (val & bitmask)
1449 + if ((val & bitmask) == bitmask)
1450 return 0;
1451 } else {
1452 if (!(val & bitmask))
1453 @@ -1127,20 +1210,38 @@ static int ssb_wait_bit(struct ssb_devic
1454
1455 void ssb_device_disable(struct ssb_device *dev, u32 core_specific_flags)
1456 {
1457 - u32 reject;
1458 + u32 reject, val;
1459
1460 if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_RESET)
1461 return;
1462
1463 reject = ssb_tmslow_reject_bitmask(dev);
1464 - ssb_write32(dev, SSB_TMSLOW, reject | SSB_TMSLOW_CLOCK);
1465 - ssb_wait_bit(dev, SSB_TMSLOW, reject, 1000, 1);
1466 - ssb_wait_bit(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0);
1467 - ssb_write32(dev, SSB_TMSLOW,
1468 - SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
1469 - reject | SSB_TMSLOW_RESET |
1470 - core_specific_flags);
1471 - ssb_flush_tmslow(dev);
1472 +
1473 + if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_CLOCK) {
1474 + ssb_write32(dev, SSB_TMSLOW, reject | SSB_TMSLOW_CLOCK);
1475 + ssb_wait_bits(dev, SSB_TMSLOW, reject, 1000, 1);
1476 + ssb_wait_bits(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0);
1477 +
1478 + if (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_INITIATOR) {
1479 + val = ssb_read32(dev, SSB_IMSTATE);
1480 + val |= SSB_IMSTATE_REJECT;
1481 + ssb_write32(dev, SSB_IMSTATE, val);
1482 + ssb_wait_bits(dev, SSB_IMSTATE, SSB_IMSTATE_BUSY, 1000,
1483 + 0);
1484 + }
1485 +
1486 + ssb_write32(dev, SSB_TMSLOW,
1487 + SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
1488 + reject | SSB_TMSLOW_RESET |
1489 + core_specific_flags);
1490 + ssb_flush_tmslow(dev);
1491 +
1492 + if (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_INITIATOR) {
1493 + val = ssb_read32(dev, SSB_IMSTATE);
1494 + val &= ~SSB_IMSTATE_REJECT;
1495 + ssb_write32(dev, SSB_IMSTATE, val);
1496 + }
1497 + }
1498
1499 ssb_write32(dev, SSB_TMSLOW,
1500 reject | SSB_TMSLOW_RESET |
1501 @@ -1149,13 +1250,34 @@ void ssb_device_disable(struct ssb_devic
1502 }
1503 EXPORT_SYMBOL(ssb_device_disable);
1504
1505 +/* Some chipsets need routing known for PCIe and 64-bit DMA */
1506 +static bool ssb_dma_translation_special_bit(struct ssb_device *dev)
1507 +{
1508 + u16 chip_id = dev->bus->chip_id;
1509 +
1510 + if (dev->id.coreid == SSB_DEV_80211) {
1511 + return (chip_id == 0x4322 || chip_id == 43221 ||
1512 + chip_id == 43231 || chip_id == 43222);
1513 + }
1514 +
1515 + return 0;
1516 +}
1517 +
1518 u32 ssb_dma_translation(struct ssb_device *dev)
1519 {
1520 switch (dev->bus->bustype) {
1521 case SSB_BUSTYPE_SSB:
1522 return 0;
1523 case SSB_BUSTYPE_PCI:
1524 - return SSB_PCI_DMA;
1525 + if (dev->bus->host_pci->is_pcie &&
1526 + ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_DMA64) {
1527 + return SSB_PCIE_DMA_H32;
1528 + } else {
1529 + if (ssb_dma_translation_special_bit(dev))
1530 + return SSB_PCIE_DMA_H32;
1531 + else
1532 + return SSB_PCI_DMA;
1533 + }
1534 default:
1535 __ssb_dma_not_implemented(dev);
1536 }
1537 @@ -1272,20 +1394,20 @@ EXPORT_SYMBOL(ssb_bus_may_powerdown);
1538
1539 int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl)
1540 {
1541 - struct ssb_chipcommon *cc;
1542 int err;
1543 enum ssb_clkmode mode;
1544
1545 err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
1546 if (err)
1547 goto error;
1548 - cc = &bus->chipco;
1549 - mode = dynamic_pctl ? SSB_CLKMODE_DYNAMIC : SSB_CLKMODE_FAST;
1550 - ssb_chipco_set_clockmode(cc, mode);
1551
1552 #ifdef CONFIG_SSB_DEBUG
1553 bus->powered_up = 1;
1554 #endif
1555 +
1556 + mode = dynamic_pctl ? SSB_CLKMODE_DYNAMIC : SSB_CLKMODE_FAST;
1557 + ssb_chipco_set_clockmode(&bus->chipco, mode);
1558 +
1559 return 0;
1560 error:
1561 ssb_printk(KERN_ERR PFX "Bus powerup failed\n");
1562 @@ -1293,6 +1415,37 @@ error:
1563 }
1564 EXPORT_SYMBOL(ssb_bus_powerup);
1565
1566 +static void ssb_broadcast_value(struct ssb_device *dev,
1567 + u32 address, u32 data)
1568 +{
1569 +#ifdef CONFIG_SSB_DRIVER_PCICORE
1570 + /* This is used for both, PCI and ChipCommon core, so be careful. */
1571 + BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
1572 + BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
1573 +#endif
1574 +
1575 + ssb_write32(dev, SSB_CHIPCO_BCAST_ADDR, address);
1576 + ssb_read32(dev, SSB_CHIPCO_BCAST_ADDR); /* flush */
1577 + ssb_write32(dev, SSB_CHIPCO_BCAST_DATA, data);
1578 + ssb_read32(dev, SSB_CHIPCO_BCAST_DATA); /* flush */
1579 +}
1580 +
1581 +void ssb_commit_settings(struct ssb_bus *bus)
1582 +{
1583 + struct ssb_device *dev;
1584 +
1585 +#ifdef CONFIG_SSB_DRIVER_PCICORE
1586 + dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
1587 +#else
1588 + dev = bus->chipco.dev;
1589 +#endif
1590 + if (WARN_ON(!dev))
1591 + return;
1592 + /* This forces an update of the cached registers. */
1593 + ssb_broadcast_value(dev, 0xFD8, 0);
1594 +}
1595 +EXPORT_SYMBOL(ssb_commit_settings);
1596 +
1597 u32 ssb_admatch_base(u32 adm)
1598 {
1599 u32 base = 0;
1600 @@ -1358,8 +1511,10 @@ static int __init ssb_modinit(void)
1601 ssb_buses_lock();
1602 err = ssb_attach_queued_buses();
1603 ssb_buses_unlock();
1604 - if (err)
1605 + if (err) {
1606 bus_unregister(&ssb_bustype);
1607 + goto out;
1608 + }
1609
1610 err = b43_pci_ssb_bridge_init();
1611 if (err) {
1612 @@ -1375,7 +1530,7 @@ static int __init ssb_modinit(void)
1613 /* don't fail SSB init because of this */
1614 err = 0;
1615 }
1616 -
1617 +out:
1618 return err;
1619 }
1620 /* ssb must be initialized after PCI but before the ssb drivers.
1621 --- a/drivers/ssb/pci.c
1622 +++ b/drivers/ssb/pci.c
1623 @@ -1,7 +1,7 @@
1624 /*
1625 * Sonics Silicon Backplane PCI-Hostbus related functions.
1626 *
1627 - * Copyright (C) 2005-2006 Michael Buesch <mb@bu3sch.de>
1628 + * Copyright (C) 2005-2006 Michael Buesch <m@bues.ch>
1629 * Copyright (C) 2005 Martin Langer <martin-langer@gmx.de>
1630 * Copyright (C) 2005 Stefano Brivio <st3@riseup.net>
1631 * Copyright (C) 2005 Danny van Dyk <kugelfang@gentoo.org>
1632 @@ -17,6 +17,7 @@
1633
1634 #include <linux/ssb/ssb.h>
1635 #include <linux/ssb/ssb_regs.h>
1636 +#include <linux/slab.h>
1637 #include <linux/pci.h>
1638 #include <linux/delay.h>
1639
1640 @@ -167,10 +168,16 @@ err_pci:
1641 }
1642
1643 /* Get the word-offset for a SSB_SPROM_XXX define. */
1644 -#define SPOFF(offset) (((offset) - SSB_SPROM_BASE) / sizeof(u16))
1645 +#define SPOFF(offset) ((offset) / sizeof(u16))
1646 /* Helper to extract some _offset, which is one of the SSB_SPROM_XXX defines. */
1647 -#define SPEX(_outvar, _offset, _mask, _shift) \
1648 +#define SPEX16(_outvar, _offset, _mask, _shift) \
1649 out->_outvar = ((in[SPOFF(_offset)] & (_mask)) >> (_shift))
1650 +#define SPEX32(_outvar, _offset, _mask, _shift) \
1651 + out->_outvar = ((((u32)in[SPOFF((_offset)+2)] << 16 | \
1652 + in[SPOFF(_offset)]) & (_mask)) >> (_shift))
1653 +#define SPEX(_outvar, _offset, _mask, _shift) \
1654 + SPEX16(_outvar, _offset, _mask, _shift)
1655 +
1656
1657 static inline u8 ssb_crc8(u8 crc, u8 data)
1658 {
1659 @@ -247,7 +254,7 @@ static int sprom_do_read(struct ssb_bus
1660 int i;
1661
1662 for (i = 0; i < bus->sprom_size; i++)
1663 - sprom[i] = ioread16(bus->mmio + SSB_SPROM_BASE + (i * 2));
1664 + sprom[i] = ioread16(bus->mmio + bus->sprom_offset + (i * 2));
1665
1666 return 0;
1667 }
1668 @@ -278,7 +285,7 @@ static int sprom_do_write(struct ssb_bus
1669 ssb_printk("75%%");
1670 else if (i % 2)
1671 ssb_printk(".");
1672 - writew(sprom[i], bus->mmio + SSB_SPROM_BASE + (i * 2));
1673 + writew(sprom[i], bus->mmio + bus->sprom_offset + (i * 2));
1674 mmiowb();
1675 msleep(20);
1676 }
1677 @@ -324,7 +331,6 @@ static void sprom_extract_r123(struct ss
1678 {
1679 int i;
1680 u16 v;
1681 - s8 gain;
1682 u16 loc[3];
1683
1684 if (out->revision == 3) /* rev 3 moved MAC */
1685 @@ -383,20 +389,52 @@ static void sprom_extract_r123(struct ss
1686 SPEX(boardflags_hi, SSB_SPROM2_BFLHI, 0xFFFF, 0);
1687
1688 /* Extract the antenna gain values. */
1689 - gain = r123_extract_antgain(out->revision, in,
1690 - SSB_SPROM1_AGAIN_BG,
1691 - SSB_SPROM1_AGAIN_BG_SHIFT);
1692 - out->antenna_gain.ghz24.a0 = gain;
1693 - out->antenna_gain.ghz24.a1 = gain;
1694 - out->antenna_gain.ghz24.a2 = gain;
1695 - out->antenna_gain.ghz24.a3 = gain;
1696 - gain = r123_extract_antgain(out->revision, in,
1697 - SSB_SPROM1_AGAIN_A,
1698 - SSB_SPROM1_AGAIN_A_SHIFT);
1699 - out->antenna_gain.ghz5.a0 = gain;
1700 - out->antenna_gain.ghz5.a1 = gain;
1701 - out->antenna_gain.ghz5.a2 = gain;
1702 - out->antenna_gain.ghz5.a3 = gain;
1703 + out->antenna_gain.a0 = r123_extract_antgain(out->revision, in,
1704 + SSB_SPROM1_AGAIN_BG,
1705 + SSB_SPROM1_AGAIN_BG_SHIFT);
1706 + out->antenna_gain.a1 = r123_extract_antgain(out->revision, in,
1707 + SSB_SPROM1_AGAIN_A,
1708 + SSB_SPROM1_AGAIN_A_SHIFT);
1709 +}
1710 +
1711 +/* Revs 4 5 and 8 have partially shared layout */
1712 +static void sprom_extract_r458(struct ssb_sprom *out, const u16 *in)
1713 +{
1714 + SPEX(txpid2g[0], SSB_SPROM4_TXPID2G01,
1715 + SSB_SPROM4_TXPID2G0, SSB_SPROM4_TXPID2G0_SHIFT);
1716 + SPEX(txpid2g[1], SSB_SPROM4_TXPID2G01,
1717 + SSB_SPROM4_TXPID2G1, SSB_SPROM4_TXPID2G1_SHIFT);
1718 + SPEX(txpid2g[2], SSB_SPROM4_TXPID2G23,
1719 + SSB_SPROM4_TXPID2G2, SSB_SPROM4_TXPID2G2_SHIFT);
1720 + SPEX(txpid2g[3], SSB_SPROM4_TXPID2G23,
1721 + SSB_SPROM4_TXPID2G3, SSB_SPROM4_TXPID2G3_SHIFT);
1722 +
1723 + SPEX(txpid5gl[0], SSB_SPROM4_TXPID5GL01,
1724 + SSB_SPROM4_TXPID5GL0, SSB_SPROM4_TXPID5GL0_SHIFT);
1725 + SPEX(txpid5gl[1], SSB_SPROM4_TXPID5GL01,
1726 + SSB_SPROM4_TXPID5GL1, SSB_SPROM4_TXPID5GL1_SHIFT);
1727 + SPEX(txpid5gl[2], SSB_SPROM4_TXPID5GL23,
1728 + SSB_SPROM4_TXPID5GL2, SSB_SPROM4_TXPID5GL2_SHIFT);
1729 + SPEX(txpid5gl[3], SSB_SPROM4_TXPID5GL23,
1730 + SSB_SPROM4_TXPID5GL3, SSB_SPROM4_TXPID5GL3_SHIFT);
1731 +
1732 + SPEX(txpid5g[0], SSB_SPROM4_TXPID5G01,
1733 + SSB_SPROM4_TXPID5G0, SSB_SPROM4_TXPID5G0_SHIFT);
1734 + SPEX(txpid5g[1], SSB_SPROM4_TXPID5G01,
1735 + SSB_SPROM4_TXPID5G1, SSB_SPROM4_TXPID5G1_SHIFT);
1736 + SPEX(txpid5g[2], SSB_SPROM4_TXPID5G23,
1737 + SSB_SPROM4_TXPID5G2, SSB_SPROM4_TXPID5G2_SHIFT);
1738 + SPEX(txpid5g[3], SSB_SPROM4_TXPID5G23,
1739 + SSB_SPROM4_TXPID5G3, SSB_SPROM4_TXPID5G3_SHIFT);
1740 +
1741 + SPEX(txpid5gh[0], SSB_SPROM4_TXPID5GH01,
1742 + SSB_SPROM4_TXPID5GH0, SSB_SPROM4_TXPID5GH0_SHIFT);
1743 + SPEX(txpid5gh[1], SSB_SPROM4_TXPID5GH01,
1744 + SSB_SPROM4_TXPID5GH1, SSB_SPROM4_TXPID5GH1_SHIFT);
1745 + SPEX(txpid5gh[2], SSB_SPROM4_TXPID5GH23,
1746 + SSB_SPROM4_TXPID5GH2, SSB_SPROM4_TXPID5GH2_SHIFT);
1747 + SPEX(txpid5gh[3], SSB_SPROM4_TXPID5GH23,
1748 + SSB_SPROM4_TXPID5GH3, SSB_SPROM4_TXPID5GH3_SHIFT);
1749 }
1750
1751 static void sprom_extract_r45(struct ssb_sprom *out, const u16 *in)
1752 @@ -421,10 +459,14 @@ static void sprom_extract_r45(struct ssb
1753 SPEX(country_code, SSB_SPROM4_CCODE, 0xFFFF, 0);
1754 SPEX(boardflags_lo, SSB_SPROM4_BFLLO, 0xFFFF, 0);
1755 SPEX(boardflags_hi, SSB_SPROM4_BFLHI, 0xFFFF, 0);
1756 + SPEX(boardflags2_lo, SSB_SPROM4_BFL2LO, 0xFFFF, 0);
1757 + SPEX(boardflags2_hi, SSB_SPROM4_BFL2HI, 0xFFFF, 0);
1758 } else {
1759 SPEX(country_code, SSB_SPROM5_CCODE, 0xFFFF, 0);
1760 SPEX(boardflags_lo, SSB_SPROM5_BFLLO, 0xFFFF, 0);
1761 SPEX(boardflags_hi, SSB_SPROM5_BFLHI, 0xFFFF, 0);
1762 + SPEX(boardflags2_lo, SSB_SPROM5_BFL2LO, 0xFFFF, 0);
1763 + SPEX(boardflags2_hi, SSB_SPROM5_BFL2HI, 0xFFFF, 0);
1764 }
1765 SPEX(ant_available_a, SSB_SPROM4_ANTAVAIL, SSB_SPROM4_ANTAVAIL_A,
1766 SSB_SPROM4_ANTAVAIL_A_SHIFT);
1767 @@ -453,16 +495,16 @@ static void sprom_extract_r45(struct ssb
1768 }
1769
1770 /* Extract the antenna gain values. */
1771 - SPEX(antenna_gain.ghz24.a0, SSB_SPROM4_AGAIN01,
1772 + SPEX(antenna_gain.a0, SSB_SPROM4_AGAIN01,
1773 SSB_SPROM4_AGAIN0, SSB_SPROM4_AGAIN0_SHIFT);
1774 - SPEX(antenna_gain.ghz24.a1, SSB_SPROM4_AGAIN01,
1775 + SPEX(antenna_gain.a1, SSB_SPROM4_AGAIN01,
1776 SSB_SPROM4_AGAIN1, SSB_SPROM4_AGAIN1_SHIFT);
1777 - SPEX(antenna_gain.ghz24.a2, SSB_SPROM4_AGAIN23,
1778 + SPEX(antenna_gain.a2, SSB_SPROM4_AGAIN23,
1779 SSB_SPROM4_AGAIN2, SSB_SPROM4_AGAIN2_SHIFT);
1780 - SPEX(antenna_gain.ghz24.a3, SSB_SPROM4_AGAIN23,
1781 + SPEX(antenna_gain.a3, SSB_SPROM4_AGAIN23,
1782 SSB_SPROM4_AGAIN3, SSB_SPROM4_AGAIN3_SHIFT);
1783 - memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
1784 - sizeof(out->antenna_gain.ghz5));
1785 +
1786 + sprom_extract_r458(out, in);
1787
1788 /* TODO - get remaining rev 4 stuff needed */
1789 }
1790 @@ -470,16 +512,24 @@ static void sprom_extract_r45(struct ssb
1791 static void sprom_extract_r8(struct ssb_sprom *out, const u16 *in)
1792 {
1793 int i;
1794 - u16 v;
1795 + u16 v, o;
1796 + u16 pwr_info_offset[] = {
1797 + SSB_SROM8_PWR_INFO_CORE0, SSB_SROM8_PWR_INFO_CORE1,
1798 + SSB_SROM8_PWR_INFO_CORE2, SSB_SROM8_PWR_INFO_CORE3
1799 + };
1800 + BUILD_BUG_ON(ARRAY_SIZE(pwr_info_offset) !=
1801 + ARRAY_SIZE(out->core_pwr_info));
1802
1803 /* extract the MAC address */
1804 for (i = 0; i < 3; i++) {
1805 - v = in[SPOFF(SSB_SPROM1_IL0MAC) + i];
1806 + v = in[SPOFF(SSB_SPROM8_IL0MAC) + i];
1807 *(((__be16 *)out->il0mac) + i) = cpu_to_be16(v);
1808 }
1809 SPEX(country_code, SSB_SPROM8_CCODE, 0xFFFF, 0);
1810 SPEX(boardflags_lo, SSB_SPROM8_BFLLO, 0xFFFF, 0);
1811 SPEX(boardflags_hi, SSB_SPROM8_BFLHI, 0xFFFF, 0);
1812 + SPEX(boardflags2_lo, SSB_SPROM8_BFL2LO, 0xFFFF, 0);
1813 + SPEX(boardflags2_hi, SSB_SPROM8_BFL2HI, 0xFFFF, 0);
1814 SPEX(ant_available_a, SSB_SPROM8_ANTAVAIL, SSB_SPROM8_ANTAVAIL_A,
1815 SSB_SPROM8_ANTAVAIL_A_SHIFT);
1816 SPEX(ant_available_bg, SSB_SPROM8_ANTAVAIL, SSB_SPROM8_ANTAVAIL_BG,
1817 @@ -490,24 +540,122 @@ static void sprom_extract_r8(struct ssb_
1818 SPEX(maxpwr_a, SSB_SPROM8_MAXP_A, SSB_SPROM8_MAXP_A_MASK, 0);
1819 SPEX(itssi_a, SSB_SPROM8_MAXP_A, SSB_SPROM8_ITSSI_A,
1820 SSB_SPROM8_ITSSI_A_SHIFT);
1821 + SPEX(maxpwr_ah, SSB_SPROM8_MAXP_AHL, SSB_SPROM8_MAXP_AH_MASK, 0);
1822 + SPEX(maxpwr_al, SSB_SPROM8_MAXP_AHL, SSB_SPROM8_MAXP_AL_MASK,
1823 + SSB_SPROM8_MAXP_AL_SHIFT);
1824 SPEX(gpio0, SSB_SPROM8_GPIOA, SSB_SPROM8_GPIOA_P0, 0);
1825 SPEX(gpio1, SSB_SPROM8_GPIOA, SSB_SPROM8_GPIOA_P1,
1826 SSB_SPROM8_GPIOA_P1_SHIFT);
1827 SPEX(gpio2, SSB_SPROM8_GPIOB, SSB_SPROM8_GPIOB_P2, 0);
1828 SPEX(gpio3, SSB_SPROM8_GPIOB, SSB_SPROM8_GPIOB_P3,
1829 SSB_SPROM8_GPIOB_P3_SHIFT);
1830 + SPEX(tri2g, SSB_SPROM8_TRI25G, SSB_SPROM8_TRI2G, 0);
1831 + SPEX(tri5g, SSB_SPROM8_TRI25G, SSB_SPROM8_TRI5G,
1832 + SSB_SPROM8_TRI5G_SHIFT);
1833 + SPEX(tri5gl, SSB_SPROM8_TRI5GHL, SSB_SPROM8_TRI5GL, 0);
1834 + SPEX(tri5gh, SSB_SPROM8_TRI5GHL, SSB_SPROM8_TRI5GH,
1835 + SSB_SPROM8_TRI5GH_SHIFT);
1836 + SPEX(rxpo2g, SSB_SPROM8_RXPO, SSB_SPROM8_RXPO2G, 0);
1837 + SPEX(rxpo5g, SSB_SPROM8_RXPO, SSB_SPROM8_RXPO5G,
1838 + SSB_SPROM8_RXPO5G_SHIFT);
1839 + SPEX(rssismf2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISMF2G, 0);
1840 + SPEX(rssismc2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISMC2G,
1841 + SSB_SPROM8_RSSISMC2G_SHIFT);
1842 + SPEX(rssisav2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISAV2G,
1843 + SSB_SPROM8_RSSISAV2G_SHIFT);
1844 + SPEX(bxa2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_BXA2G,
1845 + SSB_SPROM8_BXA2G_SHIFT);
1846 + SPEX(rssismf5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISMF5G, 0);
1847 + SPEX(rssismc5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISMC5G,
1848 + SSB_SPROM8_RSSISMC5G_SHIFT);
1849 + SPEX(rssisav5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISAV5G,
1850 + SSB_SPROM8_RSSISAV5G_SHIFT);
1851 + SPEX(bxa5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_BXA5G,
1852 + SSB_SPROM8_BXA5G_SHIFT);
1853 + SPEX(pa0b0, SSB_SPROM8_PA0B0, 0xFFFF, 0);
1854 + SPEX(pa0b1, SSB_SPROM8_PA0B1, 0xFFFF, 0);
1855 + SPEX(pa0b2, SSB_SPROM8_PA0B2, 0xFFFF, 0);
1856 + SPEX(pa1b0, SSB_SPROM8_PA1B0, 0xFFFF, 0);
1857 + SPEX(pa1b1, SSB_SPROM8_PA1B1, 0xFFFF, 0);
1858 + SPEX(pa1b2, SSB_SPROM8_PA1B2, 0xFFFF, 0);
1859 + SPEX(pa1lob0, SSB_SPROM8_PA1LOB0, 0xFFFF, 0);
1860 + SPEX(pa1lob1, SSB_SPROM8_PA1LOB1, 0xFFFF, 0);
1861 + SPEX(pa1lob2, SSB_SPROM8_PA1LOB2, 0xFFFF, 0);
1862 + SPEX(pa1hib0, SSB_SPROM8_PA1HIB0, 0xFFFF, 0);
1863 + SPEX(pa1hib1, SSB_SPROM8_PA1HIB1, 0xFFFF, 0);
1864 + SPEX(pa1hib2, SSB_SPROM8_PA1HIB2, 0xFFFF, 0);
1865 + SPEX(cck2gpo, SSB_SPROM8_CCK2GPO, 0xFFFF, 0);
1866 + SPEX32(ofdm2gpo, SSB_SPROM8_OFDM2GPO, 0xFFFFFFFF, 0);
1867 + SPEX32(ofdm5glpo, SSB_SPROM8_OFDM5GLPO, 0xFFFFFFFF, 0);
1868 + SPEX32(ofdm5gpo, SSB_SPROM8_OFDM5GPO, 0xFFFFFFFF, 0);
1869 + SPEX32(ofdm5ghpo, SSB_SPROM8_OFDM5GHPO, 0xFFFFFFFF, 0);
1870
1871 /* Extract the antenna gain values. */
1872 - SPEX(antenna_gain.ghz24.a0, SSB_SPROM8_AGAIN01,
1873 + SPEX(antenna_gain.a0, SSB_SPROM8_AGAIN01,
1874 SSB_SPROM8_AGAIN0, SSB_SPROM8_AGAIN0_SHIFT);
1875 - SPEX(antenna_gain.ghz24.a1, SSB_SPROM8_AGAIN01,
1876 + SPEX(antenna_gain.a1, SSB_SPROM8_AGAIN01,
1877 SSB_SPROM8_AGAIN1, SSB_SPROM8_AGAIN1_SHIFT);
1878 - SPEX(antenna_gain.ghz24.a2, SSB_SPROM8_AGAIN23,
1879 + SPEX(antenna_gain.a2, SSB_SPROM8_AGAIN23,
1880 SSB_SPROM8_AGAIN2, SSB_SPROM8_AGAIN2_SHIFT);
1881 - SPEX(antenna_gain.ghz24.a3, SSB_SPROM8_AGAIN23,
1882 + SPEX(antenna_gain.a3, SSB_SPROM8_AGAIN23,
1883 SSB_SPROM8_AGAIN3, SSB_SPROM8_AGAIN3_SHIFT);
1884 - memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
1885 - sizeof(out->antenna_gain.ghz5));
1886 +
1887 + /* Extract cores power info info */
1888 + for (i = 0; i < ARRAY_SIZE(pwr_info_offset); i++) {
1889 + o = pwr_info_offset[i];
1890 + SPEX(core_pwr_info[i].itssi_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
1891 + SSB_SPROM8_2G_ITSSI, SSB_SPROM8_2G_ITSSI_SHIFT);
1892 + SPEX(core_pwr_info[i].maxpwr_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
1893 + SSB_SPROM8_2G_MAXP, 0);
1894 +
1895 + SPEX(core_pwr_info[i].pa_2g[0], o + SSB_SROM8_2G_PA_0, ~0, 0);
1896 + SPEX(core_pwr_info[i].pa_2g[1], o + SSB_SROM8_2G_PA_1, ~0, 0);
1897 + SPEX(core_pwr_info[i].pa_2g[2], o + SSB_SROM8_2G_PA_2, ~0, 0);
1898 +
1899 + SPEX(core_pwr_info[i].itssi_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
1900 + SSB_SPROM8_5G_ITSSI, SSB_SPROM8_5G_ITSSI_SHIFT);
1901 + SPEX(core_pwr_info[i].maxpwr_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
1902 + SSB_SPROM8_5G_MAXP, 0);
1903 + SPEX(core_pwr_info[i].maxpwr_5gh, o + SSB_SPROM8_5GHL_MAXP,
1904 + SSB_SPROM8_5GH_MAXP, 0);
1905 + SPEX(core_pwr_info[i].maxpwr_5gl, o + SSB_SPROM8_5GHL_MAXP,
1906 + SSB_SPROM8_5GL_MAXP, SSB_SPROM8_5GL_MAXP_SHIFT);
1907 +
1908 + SPEX(core_pwr_info[i].pa_5gl[0], o + SSB_SROM8_5GL_PA_0, ~0, 0);
1909 + SPEX(core_pwr_info[i].pa_5gl[1], o + SSB_SROM8_5GL_PA_1, ~0, 0);
1910 + SPEX(core_pwr_info[i].pa_5gl[2], o + SSB_SROM8_5GL_PA_2, ~0, 0);
1911 + SPEX(core_pwr_info[i].pa_5g[0], o + SSB_SROM8_5G_PA_0, ~0, 0);
1912 + SPEX(core_pwr_info[i].pa_5g[1], o + SSB_SROM8_5G_PA_1, ~0, 0);
1913 + SPEX(core_pwr_info[i].pa_5g[2], o + SSB_SROM8_5G_PA_2, ~0, 0);
1914 + SPEX(core_pwr_info[i].pa_5gh[0], o + SSB_SROM8_5GH_PA_0, ~0, 0);
1915 + SPEX(core_pwr_info[i].pa_5gh[1], o + SSB_SROM8_5GH_PA_1, ~0, 0);
1916 + SPEX(core_pwr_info[i].pa_5gh[2], o + SSB_SROM8_5GH_PA_2, ~0, 0);
1917 + }
1918 +
1919 + /* Extract FEM info */
1920 + SPEX(fem.ghz2.tssipos, SSB_SPROM8_FEM2G,
1921 + SSB_SROM8_FEM_TSSIPOS, SSB_SROM8_FEM_TSSIPOS_SHIFT);
1922 + SPEX(fem.ghz2.extpa_gain, SSB_SPROM8_FEM2G,
1923 + SSB_SROM8_FEM_EXTPA_GAIN, SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
1924 + SPEX(fem.ghz2.pdet_range, SSB_SPROM8_FEM2G,
1925 + SSB_SROM8_FEM_PDET_RANGE, SSB_SROM8_FEM_PDET_RANGE_SHIFT);
1926 + SPEX(fem.ghz2.tr_iso, SSB_SPROM8_FEM2G,
1927 + SSB_SROM8_FEM_TR_ISO, SSB_SROM8_FEM_TR_ISO_SHIFT);
1928 + SPEX(fem.ghz2.antswlut, SSB_SPROM8_FEM2G,
1929 + SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT);
1930 +
1931 + SPEX(fem.ghz5.tssipos, SSB_SPROM8_FEM5G,
1932 + SSB_SROM8_FEM_TSSIPOS, SSB_SROM8_FEM_TSSIPOS_SHIFT);
1933 + SPEX(fem.ghz5.extpa_gain, SSB_SPROM8_FEM5G,
1934 + SSB_SROM8_FEM_EXTPA_GAIN, SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
1935 + SPEX(fem.ghz5.pdet_range, SSB_SPROM8_FEM5G,
1936 + SSB_SROM8_FEM_PDET_RANGE, SSB_SROM8_FEM_PDET_RANGE_SHIFT);
1937 + SPEX(fem.ghz5.tr_iso, SSB_SPROM8_FEM5G,
1938 + SSB_SROM8_FEM_TR_ISO, SSB_SROM8_FEM_TR_ISO_SHIFT);
1939 + SPEX(fem.ghz5.antswlut, SSB_SPROM8_FEM5G,
1940 + SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT);
1941 +
1942 + sprom_extract_r458(out, in);
1943
1944 /* TODO - get remaining rev 8 stuff needed */
1945 }
1946 @@ -521,36 +669,34 @@ static int sprom_extract(struct ssb_bus
1947 ssb_dprintk(KERN_DEBUG PFX "SPROM revision %d detected.\n", out->revision);
1948 memset(out->et0mac, 0xFF, 6); /* preset et0 and et1 mac */
1949 memset(out->et1mac, 0xFF, 6);
1950 +
1951 if ((bus->chip_id & 0xFF00) == 0x4400) {
1952 /* Workaround: The BCM44XX chip has a stupid revision
1953 * number stored in the SPROM.
1954 * Always extract r1. */
1955 out->revision = 1;
1956 + ssb_dprintk(KERN_DEBUG PFX "SPROM treated as revision %d\n", out->revision);
1957 + }
1958 +
1959 + switch (out->revision) {
1960 + case 1:
1961 + case 2:
1962 + case 3:
1963 sprom_extract_r123(out, in);
1964 - } else if (bus->chip_id == 0x4321) {
1965 - /* the BCM4328 has a chipid == 0x4321 and a rev 4 SPROM */
1966 - out->revision = 4;
1967 + break;
1968 + case 4:
1969 + case 5:
1970 sprom_extract_r45(out, in);
1971 - } else {
1972 - switch (out->revision) {
1973 - case 1:
1974 - case 2:
1975 - case 3:
1976 - sprom_extract_r123(out, in);
1977 - break;
1978 - case 4:
1979 - case 5:
1980 - sprom_extract_r45(out, in);
1981 - break;
1982 - case 8:
1983 - sprom_extract_r8(out, in);
1984 - break;
1985 - default:
1986 - ssb_printk(KERN_WARNING PFX "Unsupported SPROM"
1987 - " revision %d detected. Will extract"
1988 - " v1\n", out->revision);
1989 - sprom_extract_r123(out, in);
1990 - }
1991 + break;
1992 + case 8:
1993 + sprom_extract_r8(out, in);
1994 + break;
1995 + default:
1996 + ssb_printk(KERN_WARNING PFX "Unsupported SPROM"
1997 + " revision %d detected. Will extract"
1998 + " v1\n", out->revision);
1999 + out->revision = 1;
2000 + sprom_extract_r123(out, in);
2001 }
2002
2003 if (out->boardflags_lo == 0xFFFF)
2004 @@ -564,13 +710,34 @@ static int sprom_extract(struct ssb_bus
2005 static int ssb_pci_sprom_get(struct ssb_bus *bus,
2006 struct ssb_sprom *sprom)
2007 {
2008 - const struct ssb_sprom *fallback;
2009 - int err = -ENOMEM;
2010 + int err;
2011 u16 *buf;
2012
2013 + if (!ssb_is_sprom_available(bus)) {
2014 + ssb_printk(KERN_ERR PFX "No SPROM available!\n");
2015 + return -ENODEV;
2016 + }
2017 + if (bus->chipco.dev) { /* can be unavailable! */
2018 + /*
2019 + * get SPROM offset: SSB_SPROM_BASE1 except for
2020 + * chipcommon rev >= 31 or chip ID is 0x4312 and
2021 + * chipcommon status & 3 == 2
2022 + */
2023 + if (bus->chipco.dev->id.revision >= 31)
2024 + bus->sprom_offset = SSB_SPROM_BASE31;
2025 + else if (bus->chip_id == 0x4312 &&
2026 + (bus->chipco.status & 0x03) == 2)
2027 + bus->sprom_offset = SSB_SPROM_BASE31;
2028 + else
2029 + bus->sprom_offset = SSB_SPROM_BASE1;
2030 + } else {
2031 + bus->sprom_offset = SSB_SPROM_BASE1;
2032 + }
2033 + ssb_dprintk(KERN_INFO PFX "SPROM offset is 0x%x\n", bus->sprom_offset);
2034 +
2035 buf = kcalloc(SSB_SPROMSIZE_WORDS_R123, sizeof(u16), GFP_KERNEL);
2036 if (!buf)
2037 - goto out;
2038 + return -ENOMEM;
2039 bus->sprom_size = SSB_SPROMSIZE_WORDS_R123;
2040 sprom_do_read(bus, buf);
2041 err = sprom_check_crc(buf, bus->sprom_size);
2042 @@ -580,17 +747,24 @@ static int ssb_pci_sprom_get(struct ssb_
2043 buf = kcalloc(SSB_SPROMSIZE_WORDS_R4, sizeof(u16),
2044 GFP_KERNEL);
2045 if (!buf)
2046 - goto out;
2047 + return -ENOMEM;
2048 bus->sprom_size = SSB_SPROMSIZE_WORDS_R4;
2049 sprom_do_read(bus, buf);
2050 err = sprom_check_crc(buf, bus->sprom_size);
2051 if (err) {
2052 /* All CRC attempts failed.
2053 * Maybe there is no SPROM on the device?
2054 - * If we have a fallback, use that. */
2055 - fallback = ssb_get_fallback_sprom();
2056 - if (fallback) {
2057 - memcpy(sprom, fallback, sizeof(*sprom));
2058 + * Now we ask the arch code if there is some sprom
2059 + * available for this device in some other storage */
2060 + err = ssb_fill_sprom_with_fallback(bus, sprom);
2061 + if (err) {
2062 + ssb_printk(KERN_WARNING PFX "WARNING: Using"
2063 + " fallback SPROM failed (err %d)\n",
2064 + err);
2065 + } else {
2066 + ssb_dprintk(KERN_DEBUG PFX "Using SPROM"
2067 + " revision %d provided by"
2068 + " platform.\n", sprom->revision);
2069 err = 0;
2070 goto out_free;
2071 }
2072 @@ -602,19 +776,15 @@ static int ssb_pci_sprom_get(struct ssb_
2073
2074 out_free:
2075 kfree(buf);
2076 -out:
2077 return err;
2078 }
2079
2080 static void ssb_pci_get_boardinfo(struct ssb_bus *bus,
2081 struct ssb_boardinfo *bi)
2082 {
2083 - pci_read_config_word(bus->host_pci, PCI_SUBSYSTEM_VENDOR_ID,
2084 - &bi->vendor);
2085 - pci_read_config_word(bus->host_pci, PCI_SUBSYSTEM_ID,
2086 - &bi->type);
2087 - pci_read_config_word(bus->host_pci, PCI_REVISION_ID,
2088 - &bi->rev);
2089 + bi->vendor = bus->host_pci->subsystem_vendor;
2090 + bi->type = bus->host_pci->subsystem_device;
2091 + bi->rev = bus->host_pci->revision;
2092 }
2093
2094 int ssb_pci_get_invariants(struct ssb_bus *bus,
2095 --- a/drivers/ssb/pcihost_wrapper.c
2096 +++ b/drivers/ssb/pcihost_wrapper.c
2097 @@ -6,12 +6,13 @@
2098 * Copyright (c) 2005 Stefano Brivio <st3@riseup.net>
2099 * Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
2100 * Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
2101 - * Copyright (c) 2005-2007 Michael Buesch <mbuesch@freenet.de>
2102 + * Copyright (c) 2005-2007 Michael Buesch <m@bues.ch>
2103 *
2104 * Licensed under the GNU/GPL. See COPYING for details.
2105 */
2106
2107 #include <linux/pci.h>
2108 +#include <linux/slab.h>
2109 #include <linux/ssb/ssb.h>
2110
2111
2112 @@ -52,12 +53,13 @@ static int ssb_pcihost_resume(struct pci
2113 # define ssb_pcihost_resume NULL
2114 #endif /* CONFIG_PM */
2115
2116 -static int ssb_pcihost_probe(struct pci_dev *dev,
2117 - const struct pci_device_id *id)
2118 +static int __devinit ssb_pcihost_probe(struct pci_dev *dev,
2119 + const struct pci_device_id *id)
2120 {
2121 struct ssb_bus *ssb;
2122 int err = -ENOMEM;
2123 const char *name;
2124 + u32 val;
2125
2126 ssb = kzalloc(sizeof(*ssb), GFP_KERNEL);
2127 if (!ssb)
2128 @@ -73,6 +75,12 @@ static int ssb_pcihost_probe(struct pci_
2129 goto err_pci_disable;
2130 pci_set_master(dev);
2131
2132 + /* Disable the RETRY_TIMEOUT register (0x41) to keep
2133 + * PCI Tx retries from interfering with C3 CPU state */
2134 + pci_read_config_dword(dev, 0x40, &val);
2135 + if ((val & 0x0000ff00) != 0)
2136 + pci_write_config_dword(dev, 0x40, val & 0xffff00ff);
2137 +
2138 err = ssb_bus_pcibus_register(ssb, dev);
2139 if (err)
2140 goto err_pci_release_regions;
2141 @@ -102,7 +110,7 @@ static void ssb_pcihost_remove(struct pc
2142 pci_set_drvdata(dev, NULL);
2143 }
2144
2145 -int ssb_pcihost_register(struct pci_driver *driver)
2146 +int __devinit ssb_pcihost_register(struct pci_driver *driver)
2147 {
2148 driver->probe = ssb_pcihost_probe;
2149 driver->remove = ssb_pcihost_remove;
2150 --- a/drivers/ssb/pcmcia.c
2151 +++ b/drivers/ssb/pcmcia.c
2152 @@ -3,7 +3,7 @@
2153 * PCMCIA-Hostbus related functions
2154 *
2155 * Copyright 2006 Johannes Berg <johannes@sipsolutions.net>
2156 - * Copyright 2007-2008 Michael Buesch <mb@bu3sch.de>
2157 + * Copyright 2007-2008 Michael Buesch <m@bues.ch>
2158 *
2159 * Licensed under the GNU/GPL. See COPYING for details.
2160 */
2161 @@ -617,136 +617,136 @@ static int ssb_pcmcia_sprom_check_crc(co
2162 } \
2163 } while (0)
2164
2165 -int ssb_pcmcia_get_invariants(struct ssb_bus *bus,
2166 - struct ssb_init_invariants *iv)
2167 +static int ssb_pcmcia_get_mac(struct pcmcia_device *p_dev,
2168 + tuple_t *tuple,
2169 + void *priv)
2170 +{
2171 + struct ssb_sprom *sprom = priv;
2172 +
2173 + if (tuple->TupleData[0] != CISTPL_FUNCE_LAN_NODE_ID)
2174 + return -EINVAL;
2175 + if (tuple->TupleDataLen != ETH_ALEN + 2)
2176 + return -EINVAL;
2177 + if (tuple->TupleData[1] != ETH_ALEN)
2178 + return -EINVAL;
2179 + memcpy(sprom->il0mac, &tuple->TupleData[2], ETH_ALEN);
2180 + return 0;
2181 +};
2182 +
2183 +static int ssb_pcmcia_do_get_invariants(struct pcmcia_device *p_dev,
2184 + tuple_t *tuple,
2185 + void *priv)
2186 {
2187 - tuple_t tuple;
2188 - int res;
2189 - unsigned char buf[32];
2190 + struct ssb_init_invariants *iv = priv;
2191 struct ssb_sprom *sprom = &iv->sprom;
2192 struct ssb_boardinfo *bi = &iv->boardinfo;
2193 const char *error_description;
2194
2195 + GOTO_ERROR_ON(tuple->TupleDataLen < 1, "VEN tpl < 1");
2196 + switch (tuple->TupleData[0]) {
2197 + case SSB_PCMCIA_CIS_ID:
2198 + GOTO_ERROR_ON((tuple->TupleDataLen != 5) &&
2199 + (tuple->TupleDataLen != 7),
2200 + "id tpl size");
2201 + bi->vendor = tuple->TupleData[1] |
2202 + ((u16)tuple->TupleData[2] << 8);
2203 + break;
2204 + case SSB_PCMCIA_CIS_BOARDREV:
2205 + GOTO_ERROR_ON(tuple->TupleDataLen != 2,
2206 + "boardrev tpl size");
2207 + sprom->board_rev = tuple->TupleData[1];
2208 + break;
2209 + case SSB_PCMCIA_CIS_PA:
2210 + GOTO_ERROR_ON((tuple->TupleDataLen != 9) &&
2211 + (tuple->TupleDataLen != 10),
2212 + "pa tpl size");
2213 + sprom->pa0b0 = tuple->TupleData[1] |
2214 + ((u16)tuple->TupleData[2] << 8);
2215 + sprom->pa0b1 = tuple->TupleData[3] |
2216 + ((u16)tuple->TupleData[4] << 8);
2217 + sprom->pa0b2 = tuple->TupleData[5] |
2218 + ((u16)tuple->TupleData[6] << 8);
2219 + sprom->itssi_a = tuple->TupleData[7];
2220 + sprom->itssi_bg = tuple->TupleData[7];
2221 + sprom->maxpwr_a = tuple->TupleData[8];
2222 + sprom->maxpwr_bg = tuple->TupleData[8];
2223 + break;
2224 + case SSB_PCMCIA_CIS_OEMNAME:
2225 + /* We ignore this. */
2226 + break;
2227 + case SSB_PCMCIA_CIS_CCODE:
2228 + GOTO_ERROR_ON(tuple->TupleDataLen != 2,
2229 + "ccode tpl size");
2230 + sprom->country_code = tuple->TupleData[1];
2231 + break;
2232 + case SSB_PCMCIA_CIS_ANTENNA:
2233 + GOTO_ERROR_ON(tuple->TupleDataLen != 2,
2234 + "ant tpl size");
2235 + sprom->ant_available_a = tuple->TupleData[1];
2236 + sprom->ant_available_bg = tuple->TupleData[1];
2237 + break;
2238 + case SSB_PCMCIA_CIS_ANTGAIN:
2239 + GOTO_ERROR_ON(tuple->TupleDataLen != 2,
2240 + "antg tpl size");
2241 + sprom->antenna_gain.a0 = tuple->TupleData[1];
2242 + sprom->antenna_gain.a1 = tuple->TupleData[1];
2243 + sprom->antenna_gain.a2 = tuple->TupleData[1];
2244 + sprom->antenna_gain.a3 = tuple->TupleData[1];
2245 + break;
2246 + case SSB_PCMCIA_CIS_BFLAGS:
2247 + GOTO_ERROR_ON((tuple->TupleDataLen != 3) &&
2248 + (tuple->TupleDataLen != 5),
2249 + "bfl tpl size");
2250 + sprom->boardflags_lo = tuple->TupleData[1] |
2251 + ((u16)tuple->TupleData[2] << 8);
2252 + break;
2253 + case SSB_PCMCIA_CIS_LEDS:
2254 + GOTO_ERROR_ON(tuple->TupleDataLen != 5,
2255 + "leds tpl size");
2256 + sprom->gpio0 = tuple->TupleData[1];
2257 + sprom->gpio1 = tuple->TupleData[2];
2258 + sprom->gpio2 = tuple->TupleData[3];
2259 + sprom->gpio3 = tuple->TupleData[4];
2260 + break;
2261 + }
2262 + return -ENOSPC; /* continue with next entry */
2263 +
2264 +error:
2265 + ssb_printk(KERN_ERR PFX
2266 + "PCMCIA: Failed to fetch device invariants: %s\n",
2267 + error_description);
2268 + return -ENODEV;
2269 +}
2270 +
2271 +
2272 +int ssb_pcmcia_get_invariants(struct ssb_bus *bus,
2273 + struct ssb_init_invariants *iv)
2274 +{
2275 + struct ssb_sprom *sprom = &iv->sprom;
2276 + int res;
2277 +
2278 memset(sprom, 0xFF, sizeof(*sprom));
2279 sprom->revision = 1;
2280 sprom->boardflags_lo = 0;
2281 sprom->boardflags_hi = 0;
2282
2283 /* First fetch the MAC address. */
2284 - memset(&tuple, 0, sizeof(tuple));
2285 - tuple.DesiredTuple = CISTPL_FUNCE;
2286 - tuple.TupleData = buf;
2287 - tuple.TupleDataMax = sizeof(buf);
2288 - res = pcmcia_get_first_tuple(bus->host_pcmcia, &tuple);
2289 - GOTO_ERROR_ON(res != 0, "MAC first tpl");
2290 - res = pcmcia_get_tuple_data(bus->host_pcmcia, &tuple);
2291 - GOTO_ERROR_ON(res != 0, "MAC first tpl data");
2292 - while (1) {
2293 - GOTO_ERROR_ON(tuple.TupleDataLen < 1, "MAC tpl < 1");
2294 - if (tuple.TupleData[0] == CISTPL_FUNCE_LAN_NODE_ID)
2295 - break;
2296 - res = pcmcia_get_next_tuple(bus->host_pcmcia, &tuple);
2297 - GOTO_ERROR_ON(res != 0, "MAC next tpl");
2298 - res = pcmcia_get_tuple_data(bus->host_pcmcia, &tuple);
2299 - GOTO_ERROR_ON(res != 0, "MAC next tpl data");
2300 + res = pcmcia_loop_tuple(bus->host_pcmcia, CISTPL_FUNCE,
2301 + ssb_pcmcia_get_mac, sprom);
2302 + if (res != 0) {
2303 + ssb_printk(KERN_ERR PFX
2304 + "PCMCIA: Failed to fetch MAC address\n");
2305 + return -ENODEV;
2306 }
2307 - GOTO_ERROR_ON(tuple.TupleDataLen != ETH_ALEN + 2, "MAC tpl size");
2308 - memcpy(sprom->il0mac, &tuple.TupleData[2], ETH_ALEN);
2309
2310 /* Fetch the vendor specific tuples. */
2311 - memset(&tuple, 0, sizeof(tuple));
2312 - tuple.DesiredTuple = SSB_PCMCIA_CIS;
2313 - tuple.TupleData = buf;
2314 - tuple.TupleDataMax = sizeof(buf);
2315 - res = pcmcia_get_first_tuple(bus->host_pcmcia, &tuple);
2316 - GOTO_ERROR_ON(res != 0, "VEN first tpl");
2317 - res = pcmcia_get_tuple_data(bus->host_pcmcia, &tuple);
2318 - GOTO_ERROR_ON(res != 0, "VEN first tpl data");
2319 - while (1) {
2320 - GOTO_ERROR_ON(tuple.TupleDataLen < 1, "VEN tpl < 1");
2321 - switch (tuple.TupleData[0]) {
2322 - case SSB_PCMCIA_CIS_ID:
2323 - GOTO_ERROR_ON((tuple.TupleDataLen != 5) &&
2324 - (tuple.TupleDataLen != 7),
2325 - "id tpl size");
2326 - bi->vendor = tuple.TupleData[1] |
2327 - ((u16)tuple.TupleData[2] << 8);
2328 - break;
2329 - case SSB_PCMCIA_CIS_BOARDREV:
2330 - GOTO_ERROR_ON(tuple.TupleDataLen != 2,
2331 - "boardrev tpl size");
2332 - sprom->board_rev = tuple.TupleData[1];
2333 - break;
2334 - case SSB_PCMCIA_CIS_PA:
2335 - GOTO_ERROR_ON((tuple.TupleDataLen != 9) &&
2336 - (tuple.TupleDataLen != 10),
2337 - "pa tpl size");
2338 - sprom->pa0b0 = tuple.TupleData[1] |
2339 - ((u16)tuple.TupleData[2] << 8);
2340 - sprom->pa0b1 = tuple.TupleData[3] |
2341 - ((u16)tuple.TupleData[4] << 8);
2342 - sprom->pa0b2 = tuple.TupleData[5] |
2343 - ((u16)tuple.TupleData[6] << 8);
2344 - sprom->itssi_a = tuple.TupleData[7];
2345 - sprom->itssi_bg = tuple.TupleData[7];
2346 - sprom->maxpwr_a = tuple.TupleData[8];
2347 - sprom->maxpwr_bg = tuple.TupleData[8];
2348 - break;
2349 - case SSB_PCMCIA_CIS_OEMNAME:
2350 - /* We ignore this. */
2351 - break;
2352 - case SSB_PCMCIA_CIS_CCODE:
2353 - GOTO_ERROR_ON(tuple.TupleDataLen != 2,
2354 - "ccode tpl size");
2355 - sprom->country_code = tuple.TupleData[1];
2356 - break;
2357 - case SSB_PCMCIA_CIS_ANTENNA:
2358 - GOTO_ERROR_ON(tuple.TupleDataLen != 2,
2359 - "ant tpl size");
2360 - sprom->ant_available_a = tuple.TupleData[1];
2361 - sprom->ant_available_bg = tuple.TupleData[1];
2362 - break;
2363 - case SSB_PCMCIA_CIS_ANTGAIN:
2364 - GOTO_ERROR_ON(tuple.TupleDataLen != 2,
2365 - "antg tpl size");
2366 - sprom->antenna_gain.ghz24.a0 = tuple.TupleData[1];
2367 - sprom->antenna_gain.ghz24.a1 = tuple.TupleData[1];
2368 - sprom->antenna_gain.ghz24.a2 = tuple.TupleData[1];
2369 - sprom->antenna_gain.ghz24.a3 = tuple.TupleData[1];
2370 - sprom->antenna_gain.ghz5.a0 = tuple.TupleData[1];
2371 - sprom->antenna_gain.ghz5.a1 = tuple.TupleData[1];
2372 - sprom->antenna_gain.ghz5.a2 = tuple.TupleData[1];
2373 - sprom->antenna_gain.ghz5.a3 = tuple.TupleData[1];
2374 - break;
2375 - case SSB_PCMCIA_CIS_BFLAGS:
2376 - GOTO_ERROR_ON((tuple.TupleDataLen != 3) &&
2377 - (tuple.TupleDataLen != 5),
2378 - "bfl tpl size");
2379 - sprom->boardflags_lo = tuple.TupleData[1] |
2380 - ((u16)tuple.TupleData[2] << 8);
2381 - break;
2382 - case SSB_PCMCIA_CIS_LEDS:
2383 - GOTO_ERROR_ON(tuple.TupleDataLen != 5,
2384 - "leds tpl size");
2385 - sprom->gpio0 = tuple.TupleData[1];
2386 - sprom->gpio1 = tuple.TupleData[2];
2387 - sprom->gpio2 = tuple.TupleData[3];
2388 - sprom->gpio3 = tuple.TupleData[4];
2389 - break;
2390 - }
2391 - res = pcmcia_get_next_tuple(bus->host_pcmcia, &tuple);
2392 - if (res == -ENOSPC)
2393 - break;
2394 - GOTO_ERROR_ON(res != 0, "VEN next tpl");
2395 - res = pcmcia_get_tuple_data(bus->host_pcmcia, &tuple);
2396 - GOTO_ERROR_ON(res != 0, "VEN next tpl data");
2397 - }
2398 + res = pcmcia_loop_tuple(bus->host_pcmcia, SSB_PCMCIA_CIS,
2399 + ssb_pcmcia_do_get_invariants, iv);
2400 + if ((res == 0) || (res == -ENOSPC))
2401 + return 0;
2402
2403 - return 0;
2404 -error:
2405 ssb_printk(KERN_ERR PFX
2406 - "PCMCIA: Failed to fetch device invariants: %s\n",
2407 - error_description);
2408 + "PCMCIA: Failed to fetch device invariants\n");
2409 return -ENODEV;
2410 }
2411
2412 --- a/drivers/ssb/scan.c
2413 +++ b/drivers/ssb/scan.c
2414 @@ -2,7 +2,7 @@
2415 * Sonics Silicon Backplane
2416 * Bus scanning
2417 *
2418 - * Copyright (C) 2005-2007 Michael Buesch <mb@bu3sch.de>
2419 + * Copyright (C) 2005-2007 Michael Buesch <m@bues.ch>
2420 * Copyright (C) 2005 Martin Langer <martin-langer@gmx.de>
2421 * Copyright (C) 2005 Stefano Brivio <st3@riseup.net>
2422 * Copyright (C) 2005 Danny van Dyk <kugelfang@gentoo.org>
2423 @@ -162,6 +162,8 @@ static u8 chipid_to_nrcores(u16 chipid)
2424 static u32 scan_read32(struct ssb_bus *bus, u8 current_coreidx,
2425 u16 offset)
2426 {
2427 + u32 lo, hi;
2428 +
2429 switch (bus->bustype) {
2430 case SSB_BUSTYPE_SSB:
2431 offset += current_coreidx * SSB_CORE_SIZE;
2432 @@ -174,7 +176,12 @@ static u32 scan_read32(struct ssb_bus *b
2433 offset -= 0x800;
2434 } else
2435 ssb_pcmcia_switch_segment(bus, 0);
2436 - break;
2437 + lo = readw(bus->mmio + offset);
2438 + hi = readw(bus->mmio + offset + 2);
2439 + return lo | (hi << 16);
2440 + case SSB_BUSTYPE_SDIO:
2441 + offset += current_coreidx * SSB_CORE_SIZE;
2442 + return ssb_sdio_scan_read32(bus, offset);
2443 }
2444 return readl(bus->mmio + offset);
2445 }
2446 @@ -188,6 +195,8 @@ static int scan_switchcore(struct ssb_bu
2447 return ssb_pci_switch_coreidx(bus, coreidx);
2448 case SSB_BUSTYPE_PCMCIA:
2449 return ssb_pcmcia_switch_coreidx(bus, coreidx);
2450 + case SSB_BUSTYPE_SDIO:
2451 + return ssb_sdio_scan_switch_coreidx(bus, coreidx);
2452 }
2453 return 0;
2454 }
2455 @@ -206,6 +215,8 @@ void ssb_iounmap(struct ssb_bus *bus)
2456 SSB_BUG_ON(1); /* Can't reach this code. */
2457 #endif
2458 break;
2459 + case SSB_BUSTYPE_SDIO:
2460 + break;
2461 }
2462 bus->mmio = NULL;
2463 bus->mapped_device = NULL;
2464 @@ -230,6 +241,10 @@ static void __iomem *ssb_ioremap(struct
2465 SSB_BUG_ON(1); /* Can't reach this code. */
2466 #endif
2467 break;
2468 + case SSB_BUSTYPE_SDIO:
2469 + /* Nothing to ioremap in the SDIO case, just fake it */
2470 + mmio = (void __iomem *)baseaddr;
2471 + break;
2472 }
2473
2474 return mmio;
2475 @@ -245,7 +260,10 @@ static int we_support_multiple_80211_cor
2476 #ifdef CONFIG_SSB_PCIHOST
2477 if (bus->bustype == SSB_BUSTYPE_PCI) {
2478 if (bus->host_pci->vendor == PCI_VENDOR_ID_BROADCOM &&
2479 - bus->host_pci->device == 0x4324)
2480 + ((bus->host_pci->device == 0x4313) ||
2481 + (bus->host_pci->device == 0x431A) ||
2482 + (bus->host_pci->device == 0x4321) ||
2483 + (bus->host_pci->device == 0x4324)))
2484 return 1;
2485 }
2486 #endif /* CONFIG_SSB_PCIHOST */
2487 @@ -294,8 +312,7 @@ int ssb_bus_scan(struct ssb_bus *bus,
2488 } else {
2489 if (bus->bustype == SSB_BUSTYPE_PCI) {
2490 bus->chip_id = pcidev_to_chipid(bus->host_pci);
2491 - pci_read_config_word(bus->host_pci, PCI_REVISION_ID,
2492 - &bus->chip_rev);
2493 + bus->chip_rev = bus->host_pci->revision;
2494 bus->chip_package = 0;
2495 } else {
2496 bus->chip_id = 0x4710;
2497 @@ -303,6 +320,9 @@ int ssb_bus_scan(struct ssb_bus *bus,
2498 bus->chip_package = 0;
2499 }
2500 }
2501 + ssb_printk(KERN_INFO PFX "Found chip with id 0x%04X, rev 0x%02X and "
2502 + "package 0x%02X\n", bus->chip_id, bus->chip_rev,
2503 + bus->chip_package);
2504 if (!bus->nr_devices)
2505 bus->nr_devices = chipid_to_nrcores(bus->chip_id);
2506 if (bus->nr_devices > ARRAY_SIZE(bus->devices)) {
2507 @@ -339,7 +359,7 @@ int ssb_bus_scan(struct ssb_bus *bus,
2508 dev->bus = bus;
2509 dev->ops = bus->ops;
2510
2511 - ssb_dprintk(KERN_INFO PFX
2512 + printk(KERN_DEBUG PFX
2513 "Core %d found: %s "
2514 "(cc 0x%03X, rev 0x%02X, vendor 0x%04X)\n",
2515 i, ssb_core_name(dev->id.coreid),
2516 @@ -407,6 +427,16 @@ int ssb_bus_scan(struct ssb_bus *bus,
2517 bus->pcicore.dev = dev;
2518 #endif /* CONFIG_SSB_DRIVER_PCICORE */
2519 break;
2520 + case SSB_DEV_ETHERNET:
2521 + if (bus->bustype == SSB_BUSTYPE_PCI) {
2522 + if (bus->host_pci->vendor == PCI_VENDOR_ID_BROADCOM &&
2523 + (bus->host_pci->device & 0xFF00) == 0x4300) {
2524 + /* This is a dangling ethernet core on a
2525 + * wireless device. Ignore it. */
2526 + continue;
2527 + }
2528 + }
2529 + break;
2530 default:
2531 break;
2532 }
2533 --- /dev/null
2534 +++ b/drivers/ssb/sdio.c
2535 @@ -0,0 +1,606 @@
2536 +/*
2537 + * Sonics Silicon Backplane
2538 + * SDIO-Hostbus related functions
2539 + *
2540 + * Copyright 2009 Albert Herranz <albert_herranz@yahoo.es>
2541 + *
2542 + * Based on drivers/ssb/pcmcia.c
2543 + * Copyright 2006 Johannes Berg <johannes@sipsolutions.net>
2544 + * Copyright 2007-2008 Michael Buesch <m@bues.ch>
2545 + *
2546 + * Licensed under the GNU/GPL. See COPYING for details.
2547 + *
2548 + */
2549 +
2550 +#include <linux/ssb/ssb.h>
2551 +#include <linux/delay.h>
2552 +#include <linux/io.h>
2553 +#include <linux/etherdevice.h>
2554 +#include <linux/mmc/sdio_func.h>
2555 +
2556 +#include "ssb_private.h"
2557 +
2558 +/* Define the following to 1 to enable a printk on each coreswitch. */
2559 +#define SSB_VERBOSE_SDIOCORESWITCH_DEBUG 0
2560 +
2561 +
2562 +/* Hardware invariants CIS tuples */
2563 +#define SSB_SDIO_CIS 0x80
2564 +#define SSB_SDIO_CIS_SROMREV 0x00
2565 +#define SSB_SDIO_CIS_ID 0x01
2566 +#define SSB_SDIO_CIS_BOARDREV 0x02
2567 +#define SSB_SDIO_CIS_PA 0x03
2568 +#define SSB_SDIO_CIS_PA_PA0B0_LO 0
2569 +#define SSB_SDIO_CIS_PA_PA0B0_HI 1
2570 +#define SSB_SDIO_CIS_PA_PA0B1_LO 2
2571 +#define SSB_SDIO_CIS_PA_PA0B1_HI 3
2572 +#define SSB_SDIO_CIS_PA_PA0B2_LO 4
2573 +#define SSB_SDIO_CIS_PA_PA0B2_HI 5
2574 +#define SSB_SDIO_CIS_PA_ITSSI 6
2575 +#define SSB_SDIO_CIS_PA_MAXPOW 7
2576 +#define SSB_SDIO_CIS_OEMNAME 0x04
2577 +#define SSB_SDIO_CIS_CCODE 0x05
2578 +#define SSB_SDIO_CIS_ANTENNA 0x06
2579 +#define SSB_SDIO_CIS_ANTGAIN 0x07
2580 +#define SSB_SDIO_CIS_BFLAGS 0x08
2581 +#define SSB_SDIO_CIS_LEDS 0x09
2582 +
2583 +#define CISTPL_FUNCE_LAN_NODE_ID 0x04 /* same as in PCMCIA */
2584 +
2585 +
2586 +/*
2587 + * Function 1 miscellaneous registers.
2588 + *
2589 + * Definitions match src/include/sbsdio.h from the
2590 + * Android Open Source Project
2591 + * http://android.git.kernel.org/?p=platform/system/wlan/broadcom.git
2592 + *
2593 + */
2594 +#define SBSDIO_FUNC1_SBADDRLOW 0x1000a /* SB Address window Low (b15) */
2595 +#define SBSDIO_FUNC1_SBADDRMID 0x1000b /* SB Address window Mid (b23-b16) */
2596 +#define SBSDIO_FUNC1_SBADDRHIGH 0x1000c /* SB Address window High (b24-b31) */
2597 +
2598 +/* valid bits in SBSDIO_FUNC1_SBADDRxxx regs */
2599 +#define SBSDIO_SBADDRLOW_MASK 0x80 /* Valid address bits in SBADDRLOW */
2600 +#define SBSDIO_SBADDRMID_MASK 0xff /* Valid address bits in SBADDRMID */
2601 +#define SBSDIO_SBADDRHIGH_MASK 0xff /* Valid address bits in SBADDRHIGH */
2602 +
2603 +#define SBSDIO_SB_OFT_ADDR_MASK 0x7FFF /* sb offset addr is <= 15 bits, 32k */
2604 +
2605 +/* REVISIT: this flag doesn't seem to matter */
2606 +#define SBSDIO_SB_ACCESS_2_4B_FLAG 0x8000 /* forces 32-bit SB access */
2607 +
2608 +
2609 +/*
2610 + * Address map within the SDIO function address space (128K).
2611 + *
2612 + * Start End Description
2613 + * ------- ------- ------------------------------------------
2614 + * 0x00000 0x0ffff selected backplane address window (64K)
2615 + * 0x10000 0x1ffff backplane control registers (max 64K)
2616 + *
2617 + * The current address window is configured by writing to registers
2618 + * SBADDRLOW, SBADDRMID and SBADDRHIGH.
2619 + *
2620 + * In order to access the contents of a 32-bit Silicon Backplane address
2621 + * the backplane address window must be first loaded with the highest
2622 + * 16 bits of the target address. Then, an access must be done to the
2623 + * SDIO function address space using the lower 15 bits of the address.
2624 + * Bit 15 of the address must be set when doing 32 bit accesses.
2625 + *
2626 + * 10987654321098765432109876543210
2627 + * WWWWWWWWWWWWWWWWW SB Address Window
2628 + * OOOOOOOOOOOOOOOO Offset within SB Address Window
2629 + * a 32-bit access flag
2630 + */
2631 +
2632 +
2633 +/*
2634 + * SSB I/O via SDIO.
2635 + *
2636 + * NOTE: SDIO address @addr is 17 bits long (SDIO address space is 128K).
2637 + */
2638 +
2639 +static inline struct device *ssb_sdio_dev(struct ssb_bus *bus)
2640 +{
2641 + return &bus->host_sdio->dev;
2642 +}
2643 +
2644 +/* host claimed */
2645 +static int ssb_sdio_writeb(struct ssb_bus *bus, unsigned int addr, u8 val)
2646 +{
2647 + int error = 0;
2648 +
2649 + sdio_writeb(bus->host_sdio, val, addr, &error);
2650 + if (unlikely(error)) {
2651 + dev_dbg(ssb_sdio_dev(bus), "%08X <- %02x, error %d\n",
2652 + addr, val, error);
2653 + }
2654 +
2655 + return error;
2656 +}
2657 +
2658 +#if 0
2659 +static u8 ssb_sdio_readb(struct ssb_bus *bus, unsigned int addr)
2660 +{
2661 + u8 val;
2662 + int error = 0;
2663 +
2664 + val = sdio_readb(bus->host_sdio, addr, &error);
2665 + if (unlikely(error)) {
2666 + dev_dbg(ssb_sdio_dev(bus), "%08X -> %02x, error %d\n",
2667 + addr, val, error);
2668 + }
2669 +
2670 + return val;
2671 +}
2672 +#endif
2673 +
2674 +/* host claimed */
2675 +static int ssb_sdio_set_sbaddr_window(struct ssb_bus *bus, u32 address)
2676 +{
2677 + int error;
2678 +
2679 + error = ssb_sdio_writeb(bus, SBSDIO_FUNC1_SBADDRLOW,
2680 + (address >> 8) & SBSDIO_SBADDRLOW_MASK);
2681 + if (error)
2682 + goto out;
2683 + error = ssb_sdio_writeb(bus, SBSDIO_FUNC1_SBADDRMID,
2684 + (address >> 16) & SBSDIO_SBADDRMID_MASK);
2685 + if (error)
2686 + goto out;
2687 + error = ssb_sdio_writeb(bus, SBSDIO_FUNC1_SBADDRHIGH,
2688 + (address >> 24) & SBSDIO_SBADDRHIGH_MASK);
2689 + if (error)
2690 + goto out;
2691 + bus->sdio_sbaddr = address;
2692 +out:
2693 + if (error) {
2694 + dev_dbg(ssb_sdio_dev(bus), "failed to set address window"
2695 + " to 0x%08x, error %d\n", address, error);
2696 + }
2697 +
2698 + return error;
2699 +}
2700 +
2701 +/* for enumeration use only */
2702 +u32 ssb_sdio_scan_read32(struct ssb_bus *bus, u16 offset)
2703 +{
2704 + u32 val;
2705 + int error;
2706 +
2707 + sdio_claim_host(bus->host_sdio);
2708 + val = sdio_readl(bus->host_sdio, offset, &error);
2709 + sdio_release_host(bus->host_sdio);
2710 + if (unlikely(error)) {
2711 + dev_dbg(ssb_sdio_dev(bus), "%04X:%04X > %08x, error %d\n",
2712 + bus->sdio_sbaddr >> 16, offset, val, error);
2713 + }
2714 +
2715 + return val;
2716 +}
2717 +
2718 +/* for enumeration use only */
2719 +int ssb_sdio_scan_switch_coreidx(struct ssb_bus *bus, u8 coreidx)
2720 +{
2721 + u32 sbaddr;
2722 + int error;
2723 +
2724 + sbaddr = (coreidx * SSB_CORE_SIZE) + SSB_ENUM_BASE;
2725 + sdio_claim_host(bus->host_sdio);
2726 + error = ssb_sdio_set_sbaddr_window(bus, sbaddr);
2727 + sdio_release_host(bus->host_sdio);
2728 + if (error) {
2729 + dev_err(ssb_sdio_dev(bus), "failed to switch to core %u,"
2730 + " error %d\n", coreidx, error);
2731 + goto out;
2732 + }
2733 +out:
2734 + return error;
2735 +}
2736 +
2737 +/* host must be already claimed */
2738 +int ssb_sdio_switch_core(struct ssb_bus *bus, struct ssb_device *dev)
2739 +{
2740 + u8 coreidx = dev->core_index;
2741 + u32 sbaddr;
2742 + int error = 0;
2743 +
2744 + sbaddr = (coreidx * SSB_CORE_SIZE) + SSB_ENUM_BASE;
2745 + if (unlikely(bus->sdio_sbaddr != sbaddr)) {
2746 +#if SSB_VERBOSE_SDIOCORESWITCH_DEBUG
2747 + dev_info(ssb_sdio_dev(bus),
2748 + "switching to %s core, index %d\n",
2749 + ssb_core_name(dev->id.coreid), coreidx);
2750 +#endif
2751 + error = ssb_sdio_set_sbaddr_window(bus, sbaddr);
2752 + if (error) {
2753 + dev_dbg(ssb_sdio_dev(bus), "failed to switch to"
2754 + " core %u, error %d\n", coreidx, error);
2755 + goto out;
2756 + }
2757 + bus->mapped_device = dev;
2758 + }
2759 +
2760 +out:
2761 + return error;
2762 +}
2763 +
2764 +static u8 ssb_sdio_read8(struct ssb_device *dev, u16 offset)
2765 +{
2766 + struct ssb_bus *bus = dev->bus;
2767 + u8 val = 0xff;
2768 + int error = 0;
2769 +
2770 + sdio_claim_host(bus->host_sdio);
2771 + if (unlikely(ssb_sdio_switch_core(bus, dev)))
2772 + goto out;
2773 + offset |= bus->sdio_sbaddr & 0xffff;
2774 + offset &= SBSDIO_SB_OFT_ADDR_MASK;
2775 + val = sdio_readb(bus->host_sdio, offset, &error);
2776 + if (error) {
2777 + dev_dbg(ssb_sdio_dev(bus), "%04X:%04X > %02x, error %d\n",
2778 + bus->sdio_sbaddr >> 16, offset, val, error);
2779 + }
2780 +out:
2781 + sdio_release_host(bus->host_sdio);
2782 +
2783 + return val;
2784 +}
2785 +
2786 +static u16 ssb_sdio_read16(struct ssb_device *dev, u16 offset)
2787 +{
2788 + struct ssb_bus *bus = dev->bus;
2789 + u16 val = 0xffff;
2790 + int error = 0;
2791 +
2792 + sdio_claim_host(bus->host_sdio);
2793 + if (unlikely(ssb_sdio_switch_core(bus, dev)))
2794 + goto out;
2795 + offset |= bus->sdio_sbaddr & 0xffff;
2796 + offset &= SBSDIO_SB_OFT_ADDR_MASK;
2797 + val = sdio_readw(bus->host_sdio, offset, &error);
2798 + if (error) {
2799 + dev_dbg(ssb_sdio_dev(bus), "%04X:%04X > %04x, error %d\n",
2800 + bus->sdio_sbaddr >> 16, offset, val, error);
2801 + }
2802 +out:
2803 + sdio_release_host(bus->host_sdio);
2804 +
2805 + return val;
2806 +}
2807 +
2808 +static u32 ssb_sdio_read32(struct ssb_device *dev, u16 offset)
2809 +{
2810 + struct ssb_bus *bus = dev->bus;
2811 + u32 val = 0xffffffff;
2812 + int error = 0;
2813 +
2814 + sdio_claim_host(bus->host_sdio);
2815 + if (unlikely(ssb_sdio_switch_core(bus, dev)))
2816 + goto out;
2817 + offset |= bus->sdio_sbaddr & 0xffff;
2818 + offset &= SBSDIO_SB_OFT_ADDR_MASK;
2819 + offset |= SBSDIO_SB_ACCESS_2_4B_FLAG; /* 32 bit data access */
2820 + val = sdio_readl(bus->host_sdio, offset, &error);
2821 + if (error) {
2822 + dev_dbg(ssb_sdio_dev(bus), "%04X:%04X > %08x, error %d\n",
2823 + bus->sdio_sbaddr >> 16, offset, val, error);
2824 + }
2825 +out:
2826 + sdio_release_host(bus->host_sdio);
2827 +
2828 + return val;
2829 +}
2830 +
2831 +#ifdef CONFIG_SSB_BLOCKIO
2832 +static void ssb_sdio_block_read(struct ssb_device *dev, void *buffer,
2833 + size_t count, u16 offset, u8 reg_width)
2834 +{
2835 + size_t saved_count = count;
2836 + struct ssb_bus *bus = dev->bus;
2837 + int error = 0;
2838 +
2839 + sdio_claim_host(bus->host_sdio);
2840 + if (unlikely(ssb_sdio_switch_core(bus, dev))) {
2841 + error = -EIO;
2842 + memset(buffer, 0xff, count);
2843 + goto err_out;
2844 + }
2845 + offset |= bus->sdio_sbaddr & 0xffff;
2846 + offset &= SBSDIO_SB_OFT_ADDR_MASK;
2847 +
2848 + switch (reg_width) {
2849 + case sizeof(u8): {
2850 + error = sdio_readsb(bus->host_sdio, buffer, offset, count);
2851 + break;
2852 + }
2853 + case sizeof(u16): {
2854 + SSB_WARN_ON(count & 1);
2855 + error = sdio_readsb(bus->host_sdio, buffer, offset, count);
2856 + break;
2857 + }
2858 + case sizeof(u32): {
2859 + SSB_WARN_ON(count & 3);
2860 + offset |= SBSDIO_SB_ACCESS_2_4B_FLAG; /* 32 bit data access */
2861 + error = sdio_readsb(bus->host_sdio, buffer, offset, count);
2862 + break;
2863 + }
2864 + default:
2865 + SSB_WARN_ON(1);
2866 + }
2867 + if (!error)
2868 + goto out;
2869 +
2870 +err_out:
2871 + dev_dbg(ssb_sdio_dev(bus), "%04X:%04X (width=%u, len=%zu), error %d\n",
2872 + bus->sdio_sbaddr >> 16, offset, reg_width, saved_count, error);
2873 +out:
2874 + sdio_release_host(bus->host_sdio);
2875 +}
2876 +#endif /* CONFIG_SSB_BLOCKIO */
2877 +
2878 +static void ssb_sdio_write8(struct ssb_device *dev, u16 offset, u8 val)
2879 +{
2880 + struct ssb_bus *bus = dev->bus;
2881 + int error = 0;
2882 +
2883 + sdio_claim_host(bus->host_sdio);
2884 + if (unlikely(ssb_sdio_switch_core(bus, dev)))
2885 + goto out;
2886 + offset |= bus->sdio_sbaddr & 0xffff;
2887 + offset &= SBSDIO_SB_OFT_ADDR_MASK;
2888 + sdio_writeb(bus->host_sdio, val, offset, &error);
2889 + if (error) {
2890 + dev_dbg(ssb_sdio_dev(bus), "%04X:%04X < %02x, error %d\n",
2891 + bus->sdio_sbaddr >> 16, offset, val, error);
2892 + }
2893 +out:
2894 + sdio_release_host(bus->host_sdio);
2895 +}
2896 +
2897 +static void ssb_sdio_write16(struct ssb_device *dev, u16 offset, u16 val)
2898 +{
2899 + struct ssb_bus *bus = dev->bus;
2900 + int error = 0;
2901 +
2902 + sdio_claim_host(bus->host_sdio);
2903 + if (unlikely(ssb_sdio_switch_core(bus, dev)))
2904 + goto out;
2905 + offset |= bus->sdio_sbaddr & 0xffff;
2906 + offset &= SBSDIO_SB_OFT_ADDR_MASK;
2907 + sdio_writew(bus->host_sdio, val, offset, &error);
2908 + if (error) {
2909 + dev_dbg(ssb_sdio_dev(bus), "%04X:%04X < %04x, error %d\n",
2910 + bus->sdio_sbaddr >> 16, offset, val, error);
2911 + }
2912 +out:
2913 + sdio_release_host(bus->host_sdio);
2914 +}
2915 +
2916 +static void ssb_sdio_write32(struct ssb_device *dev, u16 offset, u32 val)
2917 +{
2918 + struct ssb_bus *bus = dev->bus;
2919 + int error = 0;
2920 +
2921 + sdio_claim_host(bus->host_sdio);
2922 + if (unlikely(ssb_sdio_switch_core(bus, dev)))
2923 + goto out;
2924 + offset |= bus->sdio_sbaddr & 0xffff;
2925 + offset &= SBSDIO_SB_OFT_ADDR_MASK;
2926 + offset |= SBSDIO_SB_ACCESS_2_4B_FLAG; /* 32 bit data access */
2927 + sdio_writel(bus->host_sdio, val, offset, &error);
2928 + if (error) {
2929 + dev_dbg(ssb_sdio_dev(bus), "%04X:%04X < %08x, error %d\n",
2930 + bus->sdio_sbaddr >> 16, offset, val, error);
2931 + }
2932 + if (bus->quirks & SSB_QUIRK_SDIO_READ_AFTER_WRITE32)
2933 + sdio_readl(bus->host_sdio, 0, &error);
2934 +out:
2935 + sdio_release_host(bus->host_sdio);
2936 +}
2937 +
2938 +#ifdef CONFIG_SSB_BLOCKIO
2939 +static void ssb_sdio_block_write(struct ssb_device *dev, const void *buffer,
2940 + size_t count, u16 offset, u8 reg_width)
2941 +{
2942 + size_t saved_count = count;
2943 + struct ssb_bus *bus = dev->bus;
2944 + int error = 0;
2945 +
2946 + sdio_claim_host(bus->host_sdio);
2947 + if (unlikely(ssb_sdio_switch_core(bus, dev))) {
2948 + error = -EIO;
2949 + memset((void *)buffer, 0xff, count);
2950 + goto err_out;
2951 + }
2952 + offset |= bus->sdio_sbaddr & 0xffff;
2953 + offset &= SBSDIO_SB_OFT_ADDR_MASK;
2954 +
2955 + switch (reg_width) {
2956 + case sizeof(u8):
2957 + error = sdio_writesb(bus->host_sdio, offset,
2958 + (void *)buffer, count);
2959 + break;
2960 + case sizeof(u16):
2961 + SSB_WARN_ON(count & 1);
2962 + error = sdio_writesb(bus->host_sdio, offset,
2963 + (void *)buffer, count);
2964 + break;
2965 + case sizeof(u32):
2966 + SSB_WARN_ON(count & 3);
2967 + offset |= SBSDIO_SB_ACCESS_2_4B_FLAG; /* 32 bit data access */
2968 + error = sdio_writesb(bus->host_sdio, offset,
2969 + (void *)buffer, count);
2970 + break;
2971 + default:
2972 + SSB_WARN_ON(1);
2973 + }
2974 + if (!error)
2975 + goto out;
2976 +
2977 +err_out:
2978 + dev_dbg(ssb_sdio_dev(bus), "%04X:%04X (width=%u, len=%zu), error %d\n",
2979 + bus->sdio_sbaddr >> 16, offset, reg_width, saved_count, error);
2980 +out:
2981 + sdio_release_host(bus->host_sdio);
2982 +}
2983 +
2984 +#endif /* CONFIG_SSB_BLOCKIO */
2985 +
2986 +/* Not "static", as it's used in main.c */
2987 +const struct ssb_bus_ops ssb_sdio_ops = {
2988 + .read8 = ssb_sdio_read8,
2989 + .read16 = ssb_sdio_read16,
2990 + .read32 = ssb_sdio_read32,
2991 + .write8 = ssb_sdio_write8,
2992 + .write16 = ssb_sdio_write16,
2993 + .write32 = ssb_sdio_write32,
2994 +#ifdef CONFIG_SSB_BLOCKIO
2995 + .block_read = ssb_sdio_block_read,
2996 + .block_write = ssb_sdio_block_write,
2997 +#endif
2998 +};
2999 +
3000 +#define GOTO_ERROR_ON(condition, description) do { \
3001 + if (unlikely(condition)) { \
3002 + error_description = description; \
3003 + goto error; \
3004 + } \
3005 + } while (0)
3006 +
3007 +int ssb_sdio_get_invariants(struct ssb_bus *bus,
3008 + struct ssb_init_invariants *iv)
3009 +{
3010 + struct ssb_sprom *sprom = &iv->sprom;
3011 + struct ssb_boardinfo *bi = &iv->boardinfo;
3012 + const char *error_description = "none";
3013 + struct sdio_func_tuple *tuple;
3014 + void *mac;
3015 +
3016 + memset(sprom, 0xFF, sizeof(*sprom));
3017 + sprom->boardflags_lo = 0;
3018 + sprom->boardflags_hi = 0;
3019 +
3020 + tuple = bus->host_sdio->tuples;
3021 + while (tuple) {
3022 + switch (tuple->code) {
3023 + case 0x22: /* extended function */
3024 + switch (tuple->data[0]) {
3025 + case CISTPL_FUNCE_LAN_NODE_ID:
3026 + GOTO_ERROR_ON((tuple->size != 7) &&
3027 + (tuple->data[1] != 6),
3028 + "mac tpl size");
3029 + /* fetch the MAC address. */
3030 + mac = tuple->data + 2;
3031 + memcpy(sprom->il0mac, mac, ETH_ALEN);
3032 + memcpy(sprom->et1mac, mac, ETH_ALEN);
3033 + break;
3034 + default:
3035 + break;
3036 + }
3037 + break;
3038 + case 0x80: /* vendor specific tuple */
3039 + switch (tuple->data[0]) {
3040 + case SSB_SDIO_CIS_SROMREV:
3041 + GOTO_ERROR_ON(tuple->size != 2,
3042 + "sromrev tpl size");
3043 + sprom->revision = tuple->data[1];
3044 + break;
3045 + case SSB_SDIO_CIS_ID:
3046 + GOTO_ERROR_ON((tuple->size != 5) &&
3047 + (tuple->size != 7),
3048 + "id tpl size");
3049 + bi->vendor = tuple->data[1] |
3050 + (tuple->data[2]<<8);
3051 + break;
3052 + case SSB_SDIO_CIS_BOARDREV:
3053 + GOTO_ERROR_ON(tuple->size != 2,
3054 + "boardrev tpl size");
3055 + sprom->board_rev = tuple->data[1];
3056 + break;
3057 + case SSB_SDIO_CIS_PA:
3058 + GOTO_ERROR_ON((tuple->size != 9) &&
3059 + (tuple->size != 10),
3060 + "pa tpl size");
3061 + sprom->pa0b0 = tuple->data[1] |
3062 + ((u16)tuple->data[2] << 8);
3063 + sprom->pa0b1 = tuple->data[3] |
3064 + ((u16)tuple->data[4] << 8);
3065 + sprom->pa0b2 = tuple->data[5] |
3066 + ((u16)tuple->data[6] << 8);
3067 + sprom->itssi_a = tuple->data[7];
3068 + sprom->itssi_bg = tuple->data[7];
3069 + sprom->maxpwr_a = tuple->data[8];
3070 + sprom->maxpwr_bg = tuple->data[8];
3071 + break;
3072 + case SSB_SDIO_CIS_OEMNAME:
3073 + /* Not present */
3074 + break;
3075 + case SSB_SDIO_CIS_CCODE:
3076 + GOTO_ERROR_ON(tuple->size != 2,
3077 + "ccode tpl size");
3078 + sprom->country_code = tuple->data[1];
3079 + break;
3080 + case SSB_SDIO_CIS_ANTENNA:
3081 + GOTO_ERROR_ON(tuple->size != 2,
3082 + "ant tpl size");
3083 + sprom->ant_available_a = tuple->data[1];
3084 + sprom->ant_available_bg = tuple->data[1];
3085 + break;
3086 + case SSB_SDIO_CIS_ANTGAIN:
3087 + GOTO_ERROR_ON(tuple->size != 2,
3088 + "antg tpl size");
3089 + sprom->antenna_gain.a0 = tuple->data[1];
3090 + sprom->antenna_gain.a1 = tuple->data[1];
3091 + sprom->antenna_gain.a2 = tuple->data[1];
3092 + sprom->antenna_gain.a3 = tuple->data[1];
3093 + break;
3094 + case SSB_SDIO_CIS_BFLAGS:
3095 + GOTO_ERROR_ON((tuple->size != 3) &&
3096 + (tuple->size != 5),
3097 + "bfl tpl size");
3098 + sprom->boardflags_lo = tuple->data[1] |
3099 + ((u16)tuple->data[2] << 8);
3100 + break;
3101 + case SSB_SDIO_CIS_LEDS:
3102 + GOTO_ERROR_ON(tuple->size != 5,
3103 + "leds tpl size");
3104 + sprom->gpio0 = tuple->data[1];
3105 + sprom->gpio1 = tuple->data[2];
3106 + sprom->gpio2 = tuple->data[3];
3107 + sprom->gpio3 = tuple->data[4];
3108 + break;
3109 + default:
3110 + break;
3111 + }
3112 + break;
3113 + default:
3114 + break;
3115 + }
3116 + tuple = tuple->next;
3117 + }
3118 +
3119 + return 0;
3120 +error:
3121 + dev_err(ssb_sdio_dev(bus), "failed to fetch device invariants: %s\n",
3122 + error_description);
3123 + return -ENODEV;
3124 +}
3125 +
3126 +void ssb_sdio_exit(struct ssb_bus *bus)
3127 +{
3128 + if (bus->bustype != SSB_BUSTYPE_SDIO)
3129 + return;
3130 + /* Nothing to do here. */
3131 +}
3132 +
3133 +int ssb_sdio_init(struct ssb_bus *bus)
3134 +{
3135 + if (bus->bustype != SSB_BUSTYPE_SDIO)
3136 + return 0;
3137 +
3138 + bus->sdio_sbaddr = ~0;
3139 +
3140 + return 0;
3141 +}
3142 --- a/drivers/ssb/sprom.c
3143 +++ b/drivers/ssb/sprom.c
3144 @@ -2,7 +2,7 @@
3145 * Sonics Silicon Backplane
3146 * Common SPROM support routines
3147 *
3148 - * Copyright (C) 2005-2008 Michael Buesch <mb@bu3sch.de>
3149 + * Copyright (C) 2005-2008 Michael Buesch <m@bues.ch>
3150 * Copyright (C) 2005 Martin Langer <martin-langer@gmx.de>
3151 * Copyright (C) 2005 Stefano Brivio <st3@riseup.net>
3152 * Copyright (C) 2005 Danny van Dyk <kugelfang@gentoo.org>
3153 @@ -14,9 +14,10 @@
3154 #include "ssb_private.h"
3155
3156 #include <linux/ctype.h>
3157 +#include <linux/slab.h>
3158
3159
3160 -static const struct ssb_sprom *fallback_sprom;
3161 +static int(*get_fallback_sprom)(struct ssb_bus *dev, struct ssb_sprom *out);
3162
3163
3164 static int sprom2hex(const u16 *sprom, char *buf, size_t buf_len,
3165 @@ -102,6 +103,7 @@ ssize_t ssb_attr_sprom_store(struct ssb_
3166 u16 *sprom;
3167 int res = 0, err = -ENOMEM;
3168 size_t sprom_size_words = bus->sprom_size;
3169 + struct ssb_freeze_context freeze;
3170
3171 sprom = kcalloc(bus->sprom_size, sizeof(u16), GFP_KERNEL);
3172 if (!sprom)
3173 @@ -123,18 +125,13 @@ ssize_t ssb_attr_sprom_store(struct ssb_
3174 err = -ERESTARTSYS;
3175 if (mutex_lock_interruptible(&bus->sprom_mutex))
3176 goto out_kfree;
3177 - err = ssb_devices_freeze(bus);
3178 - if (err == -EOPNOTSUPP) {
3179 - ssb_printk(KERN_ERR PFX "SPROM write: Could not freeze devices. "
3180 - "No suspend support. Is CONFIG_PM enabled?\n");
3181 - goto out_unlock;
3182 - }
3183 + err = ssb_devices_freeze(bus, &freeze);
3184 if (err) {
3185 ssb_printk(KERN_ERR PFX "SPROM write: Could not freeze all devices\n");
3186 goto out_unlock;
3187 }
3188 res = sprom_write(bus, sprom);
3189 - err = ssb_devices_thaw(bus);
3190 + err = ssb_devices_thaw(&freeze);
3191 if (err)
3192 ssb_printk(KERN_ERR PFX "SPROM write: Could not thaw all devices\n");
3193 out_unlock:
3194 @@ -148,34 +145,56 @@ out:
3195 }
3196
3197 /**
3198 - * ssb_arch_set_fallback_sprom - Set a fallback SPROM for use if no SPROM is found.
3199 - *
3200 - * @sprom: The SPROM data structure to register.
3201 + * ssb_arch_register_fallback_sprom - Registers a method providing a
3202 + * fallback SPROM if no SPROM is found.
3203 *
3204 - * With this function the architecture implementation may register a fallback
3205 - * SPROM data structure. The fallback is only used for PCI based SSB devices,
3206 - * where no valid SPROM can be found in the shadow registers.
3207 + * @sprom_callback: The callback function.
3208 *
3209 - * This function is useful for weird architectures that have a half-assed SSB device
3210 - * hardwired to their PCI bus.
3211 + * With this function the architecture implementation may register a
3212 + * callback handler which fills the SPROM data structure. The fallback is
3213 + * only used for PCI based SSB devices, where no valid SPROM can be found
3214 + * in the shadow registers.
3215 + *
3216 + * This function is useful for weird architectures that have a half-assed
3217 + * SSB device hardwired to their PCI bus.
3218 + *
3219 + * Note that it does only work with PCI attached SSB devices. PCMCIA
3220 + * devices currently don't use this fallback.
3221 + * Architectures must provide the SPROM for native SSB devices anyway, so
3222 + * the fallback also isn't used for native devices.
3223 *
3224 - * Note that it does only work with PCI attached SSB devices. PCMCIA devices currently
3225 - * don't use this fallback.
3226 - * Architectures must provide the SPROM for native SSB devices anyway,
3227 - * so the fallback also isn't used for native devices.
3228 - *
3229 - * This function is available for architecture code, only. So it is not exported.
3230 + * This function is available for architecture code, only. So it is not
3231 + * exported.
3232 */
3233 -int ssb_arch_set_fallback_sprom(const struct ssb_sprom *sprom)
3234 +int ssb_arch_register_fallback_sprom(int (*sprom_callback)(struct ssb_bus *bus,
3235 + struct ssb_sprom *out))
3236 {
3237 - if (fallback_sprom)
3238 + if (get_fallback_sprom)
3239 return -EEXIST;
3240 - fallback_sprom = sprom;
3241 + get_fallback_sprom = sprom_callback;
3242
3243 return 0;
3244 }
3245
3246 -const struct ssb_sprom *ssb_get_fallback_sprom(void)
3247 +int ssb_fill_sprom_with_fallback(struct ssb_bus *bus, struct ssb_sprom *out)
3248 {
3249 - return fallback_sprom;
3250 + if (!get_fallback_sprom)
3251 + return -ENOENT;
3252 +
3253 + return get_fallback_sprom(bus, out);
3254 +}
3255 +
3256 +/* http://bcm-v4.sipsolutions.net/802.11/IsSpromAvailable */
3257 +bool ssb_is_sprom_available(struct ssb_bus *bus)
3258 +{
3259 + /* status register only exists on chipcomon rev >= 11 and we need check
3260 + for >= 31 only */
3261 + /* this routine differs from specs as we do not access SPROM directly
3262 + on PCMCIA */
3263 + if (bus->bustype == SSB_BUSTYPE_PCI &&
3264 + bus->chipco.dev && /* can be unavailable! */
3265 + bus->chipco.dev->id.revision >= 31)
3266 + return bus->chipco.capabilities & SSB_CHIPCO_CAP_SPROM;
3267 +
3268 + return true;
3269 }
3270 --- a/drivers/ssb/ssb_private.h
3271 +++ b/drivers/ssb/ssb_private.h
3272 @@ -114,6 +114,46 @@ static inline int ssb_pcmcia_init(struct
3273 }
3274 #endif /* CONFIG_SSB_PCMCIAHOST */
3275
3276 +/* sdio.c */
3277 +#ifdef CONFIG_SSB_SDIOHOST
3278 +extern int ssb_sdio_get_invariants(struct ssb_bus *bus,
3279 + struct ssb_init_invariants *iv);
3280 +
3281 +extern u32 ssb_sdio_scan_read32(struct ssb_bus *bus, u16 offset);
3282 +extern int ssb_sdio_switch_core(struct ssb_bus *bus, struct ssb_device *dev);
3283 +extern int ssb_sdio_scan_switch_coreidx(struct ssb_bus *bus, u8 coreidx);
3284 +extern int ssb_sdio_hardware_setup(struct ssb_bus *bus);
3285 +extern void ssb_sdio_exit(struct ssb_bus *bus);
3286 +extern int ssb_sdio_init(struct ssb_bus *bus);
3287 +
3288 +extern const struct ssb_bus_ops ssb_sdio_ops;
3289 +#else /* CONFIG_SSB_SDIOHOST */
3290 +static inline u32 ssb_sdio_scan_read32(struct ssb_bus *bus, u16 offset)
3291 +{
3292 + return 0;
3293 +}
3294 +static inline int ssb_sdio_switch_core(struct ssb_bus *bus,
3295 + struct ssb_device *dev)
3296 +{
3297 + return 0;
3298 +}
3299 +static inline int ssb_sdio_scan_switch_coreidx(struct ssb_bus *bus, u8 coreidx)
3300 +{
3301 + return 0;
3302 +}
3303 +static inline int ssb_sdio_hardware_setup(struct ssb_bus *bus)
3304 +{
3305 + return 0;
3306 +}
3307 +static inline void ssb_sdio_exit(struct ssb_bus *bus)
3308 +{
3309 +}
3310 +static inline int ssb_sdio_init(struct ssb_bus *bus)
3311 +{
3312 + return 0;
3313 +}
3314 +#endif /* CONFIG_SSB_SDIOHOST */
3315 +
3316
3317 /* scan.c */
3318 extern const char *ssb_core_name(u16 coreid);
3319 @@ -131,24 +171,33 @@ ssize_t ssb_attr_sprom_store(struct ssb_
3320 const char *buf, size_t count,
3321 int (*sprom_check_crc)(const u16 *sprom, size_t size),
3322 int (*sprom_write)(struct ssb_bus *bus, const u16 *sprom));
3323 -extern const struct ssb_sprom *ssb_get_fallback_sprom(void);
3324 +extern int ssb_fill_sprom_with_fallback(struct ssb_bus *bus,
3325 + struct ssb_sprom *out);
3326
3327
3328 /* core.c */
3329 extern u32 ssb_calc_clock_rate(u32 plltype, u32 n, u32 m);
3330 -extern int ssb_devices_freeze(struct ssb_bus *bus);
3331 -extern int ssb_devices_thaw(struct ssb_bus *bus);
3332 extern struct ssb_bus *ssb_pci_dev_to_bus(struct pci_dev *pdev);
3333 int ssb_for_each_bus_call(unsigned long data,
3334 int (*func)(struct ssb_bus *bus, unsigned long data));
3335 extern struct ssb_bus *ssb_pcmcia_dev_to_bus(struct pcmcia_device *pdev);
3336
3337 +struct ssb_freeze_context {
3338 + /* Pointer to the bus */
3339 + struct ssb_bus *bus;
3340 + /* Boolean list to indicate whether a device is frozen on this bus. */
3341 + bool device_frozen[SSB_MAX_NR_CORES];
3342 +};
3343 +extern int ssb_devices_freeze(struct ssb_bus *bus, struct ssb_freeze_context *ctx);
3344 +extern int ssb_devices_thaw(struct ssb_freeze_context *ctx);
3345 +
3346 +
3347
3348 /* b43_pci_bridge.c */
3349 #ifdef CONFIG_SSB_B43_PCI_BRIDGE
3350 extern int __init b43_pci_ssb_bridge_init(void);
3351 extern void __exit b43_pci_ssb_bridge_exit(void);
3352 -#else /* CONFIG_SSB_B43_PCI_BRIDGR */
3353 +#else /* CONFIG_SSB_B43_PCI_BRIDGE */
3354 static inline int b43_pci_ssb_bridge_init(void)
3355 {
3356 return 0;
3357 @@ -156,6 +205,10 @@ static inline int b43_pci_ssb_bridge_ini
3358 static inline void b43_pci_ssb_bridge_exit(void)
3359 {
3360 }
3361 -#endif /* CONFIG_SSB_PCIHOST */
3362 +#endif /* CONFIG_SSB_B43_PCI_BRIDGE */
3363 +
3364 +/* driver_chipcommon_pmu.c */
3365 +extern u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc);
3366 +extern u32 ssb_pmu_get_controlclock(struct ssb_chipcommon *cc);
3367
3368 #endif /* LINUX_SSB_PRIVATE_H_ */
3369 --- a/include/linux/pci_ids.h
3370 +++ b/include/linux/pci_ids.h
3371 @@ -2017,6 +2017,7 @@
3372 #define PCI_DEVICE_ID_AFAVLAB_P030 0x2182
3373 #define PCI_SUBDEVICE_ID_AFAVLAB_P061 0x2150
3374
3375 +#define PCI_VENDOR_ID_BCM_GVC 0x14a4
3376 #define PCI_VENDOR_ID_BROADCOM 0x14e4
3377 #define PCI_DEVICE_ID_TIGON3_5752 0x1600
3378 #define PCI_DEVICE_ID_TIGON3_5752M 0x1601
3379 --- a/include/linux/ssb/ssb.h
3380 +++ b/include/linux/ssb/ssb.h
3381 @@ -16,6 +16,12 @@ struct pcmcia_device;
3382 struct ssb_bus;
3383 struct ssb_driver;
3384
3385 +struct ssb_sprom_core_pwr_info {
3386 + u8 itssi_2g, itssi_5g;
3387 + u8 maxpwr_2g, maxpwr_5gl, maxpwr_5g, maxpwr_5gh;
3388 + u16 pa_2g[4], pa_5gl[4], pa_5g[4], pa_5gh[4];
3389 +};
3390 +
3391 struct ssb_sprom {
3392 u8 revision;
3393 u8 il0mac[6]; /* MAC address for 802.11b/g */
3394 @@ -25,47 +31,164 @@ struct ssb_sprom {
3395 u8 et1phyaddr; /* MII address for enet1 */
3396 u8 et0mdcport; /* MDIO for enet0 */
3397 u8 et1mdcport; /* MDIO for enet1 */
3398 - u8 board_rev; /* Board revision number from SPROM. */
3399 + u16 board_rev; /* Board revision number from SPROM. */
3400 + u16 board_num; /* Board number from SPROM. */
3401 + u16 board_type; /* Board type from SPROM. */
3402 u8 country_code; /* Country Code */
3403 - u8 ant_available_a; /* A-PHY antenna available bits (up to 4) */
3404 - u8 ant_available_bg; /* B/G-PHY antenna available bits (up to 4) */
3405 + char alpha2[2]; /* Country Code as two chars like EU or US */
3406 + u8 leddc_on_time; /* LED Powersave Duty Cycle On Count */
3407 + u8 leddc_off_time; /* LED Powersave Duty Cycle Off Count */
3408 + u8 ant_available_a; /* 2GHz antenna available bits (up to 4) */
3409 + u8 ant_available_bg; /* 5GHz antenna available bits (up to 4) */
3410 u16 pa0b0;
3411 u16 pa0b1;
3412 u16 pa0b2;
3413 u16 pa1b0;
3414 u16 pa1b1;
3415 u16 pa1b2;
3416 + u16 pa1lob0;
3417 + u16 pa1lob1;
3418 + u16 pa1lob2;
3419 + u16 pa1hib0;
3420 + u16 pa1hib1;
3421 + u16 pa1hib2;
3422 u8 gpio0; /* GPIO pin 0 */
3423 u8 gpio1; /* GPIO pin 1 */
3424 u8 gpio2; /* GPIO pin 2 */
3425 u8 gpio3; /* GPIO pin 3 */
3426 - u16 maxpwr_a; /* A-PHY Amplifier Max Power (in dBm Q5.2) */
3427 - u16 maxpwr_bg; /* B/G-PHY Amplifier Max Power (in dBm Q5.2) */
3428 + u8 maxpwr_bg; /* 2.4GHz Amplifier Max Power (in dBm Q5.2) */
3429 + u8 maxpwr_al; /* 5.2GHz Amplifier Max Power (in dBm Q5.2) */
3430 + u8 maxpwr_a; /* 5.3GHz Amplifier Max Power (in dBm Q5.2) */
3431 + u8 maxpwr_ah; /* 5.8GHz Amplifier Max Power (in dBm Q5.2) */
3432 u8 itssi_a; /* Idle TSSI Target for A-PHY */
3433 u8 itssi_bg; /* Idle TSSI Target for B/G-PHY */
3434 - u16 boardflags_lo; /* Boardflags (low 16 bits) */
3435 - u16 boardflags_hi; /* Boardflags (high 16 bits) */
3436 + u8 tri2g; /* 2.4GHz TX isolation */
3437 + u8 tri5gl; /* 5.2GHz TX isolation */
3438 + u8 tri5g; /* 5.3GHz TX isolation */
3439 + u8 tri5gh; /* 5.8GHz TX isolation */
3440 + u8 txpid2g[4]; /* 2GHz TX power index */
3441 + u8 txpid5gl[4]; /* 4.9 - 5.1GHz TX power index */
3442 + u8 txpid5g[4]; /* 5.1 - 5.5GHz TX power index */
3443 + u8 txpid5gh[4]; /* 5.5 - ...GHz TX power index */
3444 + s8 rxpo2g; /* 2GHz RX power offset */
3445 + s8 rxpo5g; /* 5GHz RX power offset */
3446 + u8 rssisav2g; /* 2GHz RSSI params */
3447 + u8 rssismc2g;
3448 + u8 rssismf2g;
3449 + u8 bxa2g; /* 2GHz BX arch */
3450 + u8 rssisav5g; /* 5GHz RSSI params */
3451 + u8 rssismc5g;
3452 + u8 rssismf5g;
3453 + u8 bxa5g; /* 5GHz BX arch */
3454 + u16 cck2gpo; /* CCK power offset */
3455 + u32 ofdm2gpo; /* 2.4GHz OFDM power offset */
3456 + u32 ofdm5glpo; /* 5.2GHz OFDM power offset */
3457 + u32 ofdm5gpo; /* 5.3GHz OFDM power offset */
3458 + u32 ofdm5ghpo; /* 5.8GHz OFDM power offset */
3459 + u16 boardflags_lo; /* Board flags (bits 0-15) */
3460 + u16 boardflags_hi; /* Board flags (bits 16-31) */
3461 + u16 boardflags2_lo; /* Board flags (bits 32-47) */
3462 + u16 boardflags2_hi; /* Board flags (bits 48-63) */
3463 + /* TODO store board flags in a single u64 */
3464 +
3465 + struct ssb_sprom_core_pwr_info core_pwr_info[4];
3466
3467 /* Antenna gain values for up to 4 antennas
3468 * on each band. Values in dBm/4 (Q5.2). Negative gain means the
3469 * loss in the connectors is bigger than the gain. */
3470 struct {
3471 - struct {
3472 - s8 a0, a1, a2, a3;
3473 - } ghz24; /* 2.4GHz band */
3474 - struct {
3475 - s8 a0, a1, a2, a3;
3476 - } ghz5; /* 5GHz band */
3477 + s8 a0, a1, a2, a3;
3478 } antenna_gain;
3479
3480 - /* TODO - add any parameters needed from rev 2, 3, or 4 SPROMs */
3481 + struct {
3482 + struct {
3483 + u8 tssipos, extpa_gain, pdet_range, tr_iso, antswlut;
3484 + } ghz2;
3485 + struct {
3486 + u8 tssipos, extpa_gain, pdet_range, tr_iso, antswlut;
3487 + } ghz5;
3488 + } fem;
3489 +
3490 + u16 mcs2gpo[8];
3491 + u16 mcs5gpo[8];
3492 + u16 mcs5glpo[8];
3493 + u16 mcs5ghpo[8];
3494 + u8 opo;
3495 +
3496 + u8 rxgainerr2ga[3];
3497 + u8 rxgainerr5gla[3];
3498 + u8 rxgainerr5gma[3];
3499 + u8 rxgainerr5gha[3];
3500 + u8 rxgainerr5gua[3];
3501 +
3502 + u8 noiselvl2ga[3];
3503 + u8 noiselvl5gla[3];
3504 + u8 noiselvl5gma[3];
3505 + u8 noiselvl5gha[3];
3506 + u8 noiselvl5gua[3];
3507 +
3508 + u8 regrev;
3509 + u8 txchain;
3510 + u8 rxchain;
3511 + u8 antswitch;
3512 + u16 cddpo;
3513 + u16 stbcpo;
3514 + u16 bw40po;
3515 + u16 bwduppo;
3516 +
3517 + u8 tempthresh;
3518 + u8 tempoffset;
3519 + u16 rawtempsense;
3520 + u8 measpower;
3521 + u8 tempsense_slope;
3522 + u8 tempcorrx;
3523 + u8 tempsense_option;
3524 + u8 freqoffset_corr;
3525 + u8 iqcal_swp_dis;
3526 + u8 hw_iqcal_en;
3527 + u8 elna2g;
3528 + u8 elna5g;
3529 + u8 phycal_tempdelta;
3530 + u8 temps_period;
3531 + u8 temps_hysteresis;
3532 + u8 measpower1;
3533 + u8 measpower2;
3534 + u8 pcieingress_war;
3535 +
3536 + /* power per rate from sromrev 9 */
3537 + u16 cckbw202gpo;
3538 + u16 cckbw20ul2gpo;
3539 + u32 legofdmbw202gpo;
3540 + u32 legofdmbw20ul2gpo;
3541 + u32 legofdmbw205glpo;
3542 + u32 legofdmbw20ul5glpo;
3543 + u32 legofdmbw205gmpo;
3544 + u32 legofdmbw20ul5gmpo;
3545 + u32 legofdmbw205ghpo;
3546 + u32 legofdmbw20ul5ghpo;
3547 + u32 mcsbw202gpo;
3548 + u32 mcsbw20ul2gpo;
3549 + u32 mcsbw402gpo;
3550 + u32 mcsbw205glpo;
3551 + u32 mcsbw20ul5glpo;
3552 + u32 mcsbw405glpo;
3553 + u32 mcsbw205gmpo;
3554 + u32 mcsbw20ul5gmpo;
3555 + u32 mcsbw405gmpo;
3556 + u32 mcsbw205ghpo;
3557 + u32 mcsbw20ul5ghpo;
3558 + u32 mcsbw405ghpo;
3559 + u16 mcs32po;
3560 + u16 legofdm40duppo;
3561 + u8 sar2g;
3562 + u8 sar5g;
3563 };
3564
3565 /* Information about the PCB the circuitry is soldered on. */
3566 struct ssb_boardinfo {
3567 u16 vendor;
3568 u16 type;
3569 - u16 rev;
3570 + u8 rev;
3571 };
3572
3573
3574 @@ -137,7 +260,7 @@ struct ssb_device {
3575 * is an optimization. */
3576 const struct ssb_bus_ops *ops;
3577
3578 - struct device *dev;
3579 + struct device *dev, *dma_dev;
3580
3581 struct ssb_bus *bus;
3582 struct ssb_device_id id;
3583 @@ -195,10 +318,9 @@ struct ssb_driver {
3584 #define drv_to_ssb_drv(_drv) container_of(_drv, struct ssb_driver, drv)
3585
3586 extern int __ssb_driver_register(struct ssb_driver *drv, struct module *owner);
3587 -static inline int ssb_driver_register(struct ssb_driver *drv)
3588 -{
3589 - return __ssb_driver_register(drv, THIS_MODULE);
3590 -}
3591 +#define ssb_driver_register(drv) \
3592 + __ssb_driver_register(drv, THIS_MODULE)
3593 +
3594 extern void ssb_driver_unregister(struct ssb_driver *drv);
3595
3596
3597 @@ -208,6 +330,7 @@ enum ssb_bustype {
3598 SSB_BUSTYPE_SSB, /* This SSB bus is the system bus */
3599 SSB_BUSTYPE_PCI, /* SSB is connected to PCI bus */
3600 SSB_BUSTYPE_PCMCIA, /* SSB is connected to PCMCIA bus */
3601 + SSB_BUSTYPE_SDIO, /* SSB is connected to SDIO bus */
3602 };
3603
3604 /* board_vendor */
3605 @@ -238,20 +361,33 @@ struct ssb_bus {
3606
3607 const struct ssb_bus_ops *ops;
3608
3609 - /* The core in the basic address register window. (PCI bus only) */
3610 + /* The core currently mapped into the MMIO window.
3611 + * Not valid on all host-buses. So don't use outside of SSB. */
3612 struct ssb_device *mapped_device;
3613 - /* Currently mapped PCMCIA segment. (bustype == SSB_BUSTYPE_PCMCIA only) */
3614 - u8 mapped_pcmcia_seg;
3615 + union {
3616 + /* Currently mapped PCMCIA segment. (bustype == SSB_BUSTYPE_PCMCIA only) */
3617 + u8 mapped_pcmcia_seg;
3618 + /* Current SSB base address window for SDIO. */
3619 + u32 sdio_sbaddr;
3620 + };
3621 /* Lock for core and segment switching.
3622 * On PCMCIA-host busses this is used to protect the whole MMIO access. */
3623 spinlock_t bar_lock;
3624
3625 - /* The bus this backplane is running on. */
3626 + /* The host-bus this backplane is running on. */
3627 enum ssb_bustype bustype;
3628 - /* Pointer to the PCI bus (only valid if bustype == SSB_BUSTYPE_PCI). */
3629 - struct pci_dev *host_pci;
3630 - /* Pointer to the PCMCIA device (only if bustype == SSB_BUSTYPE_PCMCIA). */
3631 - struct pcmcia_device *host_pcmcia;
3632 + /* Pointers to the host-bus. Check bustype before using any of these pointers. */
3633 + union {
3634 + /* Pointer to the PCI bus (only valid if bustype == SSB_BUSTYPE_PCI). */
3635 + struct pci_dev *host_pci;
3636 + /* Pointer to the PCMCIA device (only if bustype == SSB_BUSTYPE_PCMCIA). */
3637 + struct pcmcia_device *host_pcmcia;
3638 + /* Pointer to the SDIO device (only if bustype == SSB_BUSTYPE_SDIO). */
3639 + struct sdio_func *host_sdio;
3640 + };
3641 +
3642 + /* See enum ssb_quirks */
3643 + unsigned int quirks;
3644
3645 #ifdef CONFIG_SSB_SPROM
3646 /* Mutex to protect the SPROM writing. */
3647 @@ -260,7 +396,8 @@ struct ssb_bus {
3648
3649 /* ID information about the Chip. */
3650 u16 chip_id;
3651 - u16 chip_rev;
3652 + u8 chip_rev;
3653 + u16 sprom_offset;
3654 u16 sprom_size; /* number of words in sprom */
3655 u8 chip_package;
3656
3657 @@ -306,6 +443,11 @@ struct ssb_bus {
3658 #endif /* DEBUG */
3659 };
3660
3661 +enum ssb_quirks {
3662 + /* SDIO connected card requires performing a read after writing a 32-bit value */
3663 + SSB_QUIRK_SDIO_READ_AFTER_WRITE32 = (1 << 0),
3664 +};
3665 +
3666 /* The initialization-invariants. */
3667 struct ssb_init_invariants {
3668 /* Versioning information about the PCB. */
3669 @@ -336,12 +478,23 @@ extern int ssb_bus_pcmciabus_register(st
3670 struct pcmcia_device *pcmcia_dev,
3671 unsigned long baseaddr);
3672 #endif /* CONFIG_SSB_PCMCIAHOST */
3673 +#ifdef CONFIG_SSB_SDIOHOST
3674 +extern int ssb_bus_sdiobus_register(struct ssb_bus *bus,
3675 + struct sdio_func *sdio_func,
3676 + unsigned int quirks);
3677 +#endif /* CONFIG_SSB_SDIOHOST */
3678 +
3679
3680 extern void ssb_bus_unregister(struct ssb_bus *bus);
3681
3682 +/* Does the device have an SPROM? */
3683 +extern bool ssb_is_sprom_available(struct ssb_bus *bus);
3684 +
3685 /* Set a fallback SPROM.
3686 * See kdoc at the function definition for complete documentation. */
3687 -extern int ssb_arch_set_fallback_sprom(const struct ssb_sprom *sprom);
3688 +extern int ssb_arch_register_fallback_sprom(
3689 + int (*sprom_callback)(struct ssb_bus *bus,
3690 + struct ssb_sprom *out));
3691
3692 /* Suspend a SSB bus.
3693 * Call this from the parent bus suspend routine. */
3694 @@ -612,6 +765,7 @@ extern int ssb_bus_may_powerdown(struct
3695 * Otherwise static always-on powercontrol will be used. */
3696 extern int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl);
3697
3698 +extern void ssb_commit_settings(struct ssb_bus *bus);
3699
3700 /* Various helper functions */
3701 extern u32 ssb_admatch_base(u32 adm);
3702 --- a/include/linux/ssb/ssb_driver_chipcommon.h
3703 +++ b/include/linux/ssb/ssb_driver_chipcommon.h
3704 @@ -8,7 +8,7 @@
3705 * gpio interface, extbus, and support for serial and parallel flashes.
3706 *
3707 * Copyright 2005, Broadcom Corporation
3708 - * Copyright 2006, Michael Buesch <mb@bu3sch.de>
3709 + * Copyright 2006, Michael Buesch <m@bues.ch>
3710 *
3711 * Licensed under the GPL version 2. See COPYING for details.
3712 */
3713 @@ -53,6 +53,7 @@
3714 #define SSB_CHIPCO_CAP_64BIT 0x08000000 /* 64-bit Backplane */
3715 #define SSB_CHIPCO_CAP_PMU 0x10000000 /* PMU available (rev >= 20) */
3716 #define SSB_CHIPCO_CAP_ECI 0x20000000 /* ECI available (rev >= 20) */
3717 +#define SSB_CHIPCO_CAP_SPROM 0x40000000 /* SPROM present */
3718 #define SSB_CHIPCO_CORECTL 0x0008
3719 #define SSB_CHIPCO_CORECTL_UARTCLK0 0x00000001 /* Drive UART with internal clock */
3720 #define SSB_CHIPCO_CORECTL_SE 0x00000002 /* sync clk out enable (corerev >= 3) */
3721 @@ -122,6 +123,8 @@
3722 #define SSB_CHIPCO_FLASHDATA 0x0048
3723 #define SSB_CHIPCO_BCAST_ADDR 0x0050
3724 #define SSB_CHIPCO_BCAST_DATA 0x0054
3725 +#define SSB_CHIPCO_GPIOPULLUP 0x0058 /* Rev >= 20 only */
3726 +#define SSB_CHIPCO_GPIOPULLDOWN 0x005C /* Rev >= 20 only */
3727 #define SSB_CHIPCO_GPIOIN 0x0060
3728 #define SSB_CHIPCO_GPIOOUT 0x0064
3729 #define SSB_CHIPCO_GPIOOUTEN 0x0068
3730 @@ -130,6 +133,9 @@
3731 #define SSB_CHIPCO_GPIOIRQ 0x0074
3732 #define SSB_CHIPCO_WATCHDOG 0x0080
3733 #define SSB_CHIPCO_GPIOTIMER 0x0088 /* LED powersave (corerev >= 16) */
3734 +#define SSB_CHIPCO_GPIOTIMER_OFFTIME 0x0000FFFF
3735 +#define SSB_CHIPCO_GPIOTIMER_OFFTIME_SHIFT 0
3736 +#define SSB_CHIPCO_GPIOTIMER_ONTIME 0xFFFF0000
3737 #define SSB_CHIPCO_GPIOTIMER_ONTIME_SHIFT 16
3738 #define SSB_CHIPCO_GPIOTOUTM 0x008C /* LED powersave (corerev >= 16) */
3739 #define SSB_CHIPCO_CLOCK_N 0x0090
3740 @@ -188,8 +194,10 @@
3741 #define SSB_CHIPCO_CLKCTLST_HAVEALPREQ 0x00000008 /* ALP available request */
3742 #define SSB_CHIPCO_CLKCTLST_HAVEHTREQ 0x00000010 /* HT available request */
3743 #define SSB_CHIPCO_CLKCTLST_HWCROFF 0x00000020 /* Force HW clock request off */
3744 -#define SSB_CHIPCO_CLKCTLST_HAVEHT 0x00010000 /* HT available */
3745 -#define SSB_CHIPCO_CLKCTLST_HAVEALP 0x00020000 /* APL available */
3746 +#define SSB_CHIPCO_CLKCTLST_HAVEALP 0x00010000 /* ALP available */
3747 +#define SSB_CHIPCO_CLKCTLST_HAVEHT 0x00020000 /* HT available */
3748 +#define SSB_CHIPCO_CLKCTLST_4328A0_HAVEHT 0x00010000 /* 4328a0 has reversed bits */
3749 +#define SSB_CHIPCO_CLKCTLST_4328A0_HAVEALP 0x00020000 /* 4328a0 has reversed bits */
3750 #define SSB_CHIPCO_HW_WORKAROUND 0x01E4 /* Hardware workaround (rev >= 20) */
3751 #define SSB_CHIPCO_UART0_DATA 0x0300
3752 #define SSB_CHIPCO_UART0_IMR 0x0304
3753 @@ -385,6 +393,7 @@
3754
3755
3756 /** Chip specific Chip-Status register contents. */
3757 +#define SSB_CHIPCO_CHST_4322_SPROM_EXISTS 0x00000040 /* SPROM present */
3758 #define SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL 0x00000003
3759 #define SSB_CHIPCO_CHST_4325_DEFCIS_SEL 0 /* OTP is powered up, use def. CIS, no SPROM */
3760 #define SSB_CHIPCO_CHST_4325_SPROM_SEL 1 /* OTP is powered up, SPROM is present */
3761 @@ -398,6 +407,18 @@
3762 #define SSB_CHIPCO_CHST_4325_RCAL_VALUE_SHIFT 4
3763 #define SSB_CHIPCO_CHST_4325_PMUTOP_2B 0x00000200 /* 1 for 2b, 0 for to 2a */
3764
3765 +/** Macros to determine SPROM presence based on Chip-Status register. */
3766 +#define SSB_CHIPCO_CHST_4312_SPROM_PRESENT(status) \
3767 + ((status & SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL) != \
3768 + SSB_CHIPCO_CHST_4325_OTP_SEL)
3769 +#define SSB_CHIPCO_CHST_4322_SPROM_PRESENT(status) \
3770 + (status & SSB_CHIPCO_CHST_4322_SPROM_EXISTS)
3771 +#define SSB_CHIPCO_CHST_4325_SPROM_PRESENT(status) \
3772 + (((status & SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL) != \
3773 + SSB_CHIPCO_CHST_4325_DEFCIS_SEL) && \
3774 + ((status & SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL) != \
3775 + SSB_CHIPCO_CHST_4325_OTP_SEL))
3776 +
3777
3778
3779 /** Clockcontrol masks and values **/
3780 @@ -564,6 +585,7 @@ struct ssb_chipcommon_pmu {
3781 struct ssb_chipcommon {
3782 struct ssb_device *dev;
3783 u32 capabilities;
3784 + u32 status;
3785 /* Fast Powerup Delay constant */
3786 u16 fast_pwrup_delay;
3787 struct ssb_chipcommon_pmu pmu;
3788 @@ -629,5 +651,15 @@ extern int ssb_chipco_serial_init(struct
3789 /* PMU support */
3790 extern void ssb_pmu_init(struct ssb_chipcommon *cc);
3791
3792 +enum ssb_pmu_ldo_volt_id {
3793 + LDO_PAREF = 0,
3794 + LDO_VOLT1,
3795 + LDO_VOLT2,
3796 + LDO_VOLT3,
3797 +};
3798 +
3799 +void ssb_pmu_set_ldo_voltage(struct ssb_chipcommon *cc,
3800 + enum ssb_pmu_ldo_volt_id id, u32 voltage);
3801 +void ssb_pmu_set_ldo_paref(struct ssb_chipcommon *cc, bool on);
3802
3803 #endif /* LINUX_SSB_CHIPCO_H_ */
3804 --- a/include/linux/ssb/ssb_regs.h
3805 +++ b/include/linux/ssb/ssb_regs.h
3806 @@ -85,6 +85,8 @@
3807 #define SSB_IMSTATE_AP_RSV 0x00000030 /* Reserved */
3808 #define SSB_IMSTATE_IBE 0x00020000 /* In Band Error */
3809 #define SSB_IMSTATE_TO 0x00040000 /* Timeout */
3810 +#define SSB_IMSTATE_BUSY 0x01800000 /* Busy (Backplane rev >= 2.3 only) */
3811 +#define SSB_IMSTATE_REJECT 0x02000000 /* Reject (Backplane rev >= 2.3 only) */
3812 #define SSB_INTVEC 0x0F94 /* SB Interrupt Mask */
3813 #define SSB_INTVEC_PCI 0x00000001 /* Enable interrupts for PCI */
3814 #define SSB_INTVEC_ENET0 0x00000002 /* Enable interrupts for enet 0 */
3815 @@ -95,7 +97,7 @@
3816 #define SSB_INTVEC_ENET1 0x00000040 /* Enable interrupts for enet 1 */
3817 #define SSB_TMSLOW 0x0F98 /* SB Target State Low */
3818 #define SSB_TMSLOW_RESET 0x00000001 /* Reset */
3819 -#define SSB_TMSLOW_REJECT_22 0x00000002 /* Reject (Backplane rev 2.2) */
3820 +#define SSB_TMSLOW_REJECT 0x00000002 /* Reject (Standard Backplane) */
3821 #define SSB_TMSLOW_REJECT_23 0x00000004 /* Reject (Backplane rev 2.3) */
3822 #define SSB_TMSLOW_CLOCK 0x00010000 /* Clock Enable */
3823 #define SSB_TMSLOW_FGC 0x00020000 /* Force Gated Clocks On */
3824 @@ -162,7 +164,7 @@
3825
3826 /* SPROM shadow area. If not otherwise noted, fields are
3827 * two bytes wide. Note that the SPROM can _only_ be read
3828 - * in two-byte quantinies.
3829 + * in two-byte quantities.
3830 */
3831 #define SSB_SPROMSIZE_WORDS 64
3832 #define SSB_SPROMSIZE_BYTES (SSB_SPROMSIZE_WORDS * sizeof(u16))
3833 @@ -170,26 +172,27 @@
3834 #define SSB_SPROMSIZE_WORDS_R4 220
3835 #define SSB_SPROMSIZE_BYTES_R123 (SSB_SPROMSIZE_WORDS_R123 * sizeof(u16))
3836 #define SSB_SPROMSIZE_BYTES_R4 (SSB_SPROMSIZE_WORDS_R4 * sizeof(u16))
3837 -#define SSB_SPROM_BASE 0x1000
3838 -#define SSB_SPROM_REVISION 0x107E
3839 +#define SSB_SPROM_BASE1 0x1000
3840 +#define SSB_SPROM_BASE31 0x0800
3841 +#define SSB_SPROM_REVISION 0x007E
3842 #define SSB_SPROM_REVISION_REV 0x00FF /* SPROM Revision number */
3843 #define SSB_SPROM_REVISION_CRC 0xFF00 /* SPROM CRC8 value */
3844 #define SSB_SPROM_REVISION_CRC_SHIFT 8
3845
3846 /* SPROM Revision 1 */
3847 -#define SSB_SPROM1_SPID 0x1004 /* Subsystem Product ID for PCI */
3848 -#define SSB_SPROM1_SVID 0x1006 /* Subsystem Vendor ID for PCI */
3849 -#define SSB_SPROM1_PID 0x1008 /* Product ID for PCI */
3850 -#define SSB_SPROM1_IL0MAC 0x1048 /* 6 bytes MAC address for 802.11b/g */
3851 -#define SSB_SPROM1_ET0MAC 0x104E /* 6 bytes MAC address for Ethernet */
3852 -#define SSB_SPROM1_ET1MAC 0x1054 /* 6 bytes MAC address for 802.11a */
3853 -#define SSB_SPROM1_ETHPHY 0x105A /* Ethernet PHY settings */
3854 +#define SSB_SPROM1_SPID 0x0004 /* Subsystem Product ID for PCI */
3855 +#define SSB_SPROM1_SVID 0x0006 /* Subsystem Vendor ID for PCI */
3856 +#define SSB_SPROM1_PID 0x0008 /* Product ID for PCI */
3857 +#define SSB_SPROM1_IL0MAC 0x0048 /* 6 bytes MAC address for 802.11b/g */
3858 +#define SSB_SPROM1_ET0MAC 0x004E /* 6 bytes MAC address for Ethernet */
3859 +#define SSB_SPROM1_ET1MAC 0x0054 /* 6 bytes MAC address for 802.11a */
3860 +#define SSB_SPROM1_ETHPHY 0x005A /* Ethernet PHY settings */
3861 #define SSB_SPROM1_ETHPHY_ET0A 0x001F /* MII Address for enet0 */
3862 #define SSB_SPROM1_ETHPHY_ET1A 0x03E0 /* MII Address for enet1 */
3863 #define SSB_SPROM1_ETHPHY_ET1A_SHIFT 5
3864 #define SSB_SPROM1_ETHPHY_ET0M (1<<14) /* MDIO for enet0 */
3865 #define SSB_SPROM1_ETHPHY_ET1M (1<<15) /* MDIO for enet1 */
3866 -#define SSB_SPROM1_BINF 0x105C /* Board info */
3867 +#define SSB_SPROM1_BINF 0x005C /* Board info */
3868 #define SSB_SPROM1_BINF_BREV 0x00FF /* Board Revision */
3869 #define SSB_SPROM1_BINF_CCODE 0x0F00 /* Country Code */
3870 #define SSB_SPROM1_BINF_CCODE_SHIFT 8
3871 @@ -197,63 +200,63 @@
3872 #define SSB_SPROM1_BINF_ANTBG_SHIFT 12
3873 #define SSB_SPROM1_BINF_ANTA 0xC000 /* Available A-PHY antennas */
3874 #define SSB_SPROM1_BINF_ANTA_SHIFT 14
3875 -#define SSB_SPROM1_PA0B0 0x105E
3876 -#define SSB_SPROM1_PA0B1 0x1060
3877 -#define SSB_SPROM1_PA0B2 0x1062
3878 -#define SSB_SPROM1_GPIOA 0x1064 /* General Purpose IO pins 0 and 1 */
3879 +#define SSB_SPROM1_PA0B0 0x005E
3880 +#define SSB_SPROM1_PA0B1 0x0060
3881 +#define SSB_SPROM1_PA0B2 0x0062
3882 +#define SSB_SPROM1_GPIOA 0x0064 /* General Purpose IO pins 0 and 1 */
3883 #define SSB_SPROM1_GPIOA_P0 0x00FF /* Pin 0 */
3884 #define SSB_SPROM1_GPIOA_P1 0xFF00 /* Pin 1 */
3885 #define SSB_SPROM1_GPIOA_P1_SHIFT 8
3886 -#define SSB_SPROM1_GPIOB 0x1066 /* General Purpuse IO pins 2 and 3 */
3887 +#define SSB_SPROM1_GPIOB 0x0066 /* General Purpuse IO pins 2 and 3 */
3888 #define SSB_SPROM1_GPIOB_P2 0x00FF /* Pin 2 */
3889 #define SSB_SPROM1_GPIOB_P3 0xFF00 /* Pin 3 */
3890 #define SSB_SPROM1_GPIOB_P3_SHIFT 8
3891 -#define SSB_SPROM1_MAXPWR 0x1068 /* Power Amplifier Max Power */
3892 +#define SSB_SPROM1_MAXPWR 0x0068 /* Power Amplifier Max Power */
3893 #define SSB_SPROM1_MAXPWR_BG 0x00FF /* B-PHY and G-PHY (in dBm Q5.2) */
3894 #define SSB_SPROM1_MAXPWR_A 0xFF00 /* A-PHY (in dBm Q5.2) */
3895 #define SSB_SPROM1_MAXPWR_A_SHIFT 8
3896 -#define SSB_SPROM1_PA1B0 0x106A
3897 -#define SSB_SPROM1_PA1B1 0x106C
3898 -#define SSB_SPROM1_PA1B2 0x106E
3899 -#define SSB_SPROM1_ITSSI 0x1070 /* Idle TSSI Target */
3900 +#define SSB_SPROM1_PA1B0 0x006A
3901 +#define SSB_SPROM1_PA1B1 0x006C
3902 +#define SSB_SPROM1_PA1B2 0x006E
3903 +#define SSB_SPROM1_ITSSI 0x0070 /* Idle TSSI Target */
3904 #define SSB_SPROM1_ITSSI_BG 0x00FF /* B-PHY and G-PHY*/
3905 #define SSB_SPROM1_ITSSI_A 0xFF00 /* A-PHY */
3906 #define SSB_SPROM1_ITSSI_A_SHIFT 8
3907 -#define SSB_SPROM1_BFLLO 0x1072 /* Boardflags (low 16 bits) */
3908 -#define SSB_SPROM1_AGAIN 0x1074 /* Antenna Gain (in dBm Q5.2) */
3909 +#define SSB_SPROM1_BFLLO 0x0072 /* Boardflags (low 16 bits) */
3910 +#define SSB_SPROM1_AGAIN 0x0074 /* Antenna Gain (in dBm Q5.2) */
3911 #define SSB_SPROM1_AGAIN_BG 0x00FF /* B-PHY and G-PHY */
3912 #define SSB_SPROM1_AGAIN_BG_SHIFT 0
3913 #define SSB_SPROM1_AGAIN_A 0xFF00 /* A-PHY */
3914 #define SSB_SPROM1_AGAIN_A_SHIFT 8
3915
3916 /* SPROM Revision 2 (inherits from rev 1) */
3917 -#define SSB_SPROM2_BFLHI 0x1038 /* Boardflags (high 16 bits) */
3918 -#define SSB_SPROM2_MAXP_A 0x103A /* A-PHY Max Power */
3919 +#define SSB_SPROM2_BFLHI 0x0038 /* Boardflags (high 16 bits) */
3920 +#define SSB_SPROM2_MAXP_A 0x003A /* A-PHY Max Power */
3921 #define SSB_SPROM2_MAXP_A_HI 0x00FF /* Max Power High */
3922 #define SSB_SPROM2_MAXP_A_LO 0xFF00 /* Max Power Low */
3923 #define SSB_SPROM2_MAXP_A_LO_SHIFT 8
3924 -#define SSB_SPROM2_PA1LOB0 0x103C /* A-PHY PowerAmplifier Low Settings */
3925 -#define SSB_SPROM2_PA1LOB1 0x103E /* A-PHY PowerAmplifier Low Settings */
3926 -#define SSB_SPROM2_PA1LOB2 0x1040 /* A-PHY PowerAmplifier Low Settings */
3927 -#define SSB_SPROM2_PA1HIB0 0x1042 /* A-PHY PowerAmplifier High Settings */
3928 -#define SSB_SPROM2_PA1HIB1 0x1044 /* A-PHY PowerAmplifier High Settings */
3929 -#define SSB_SPROM2_PA1HIB2 0x1046 /* A-PHY PowerAmplifier High Settings */
3930 -#define SSB_SPROM2_OPO 0x1078 /* OFDM Power Offset from CCK Level */
3931 +#define SSB_SPROM2_PA1LOB0 0x003C /* A-PHY PowerAmplifier Low Settings */
3932 +#define SSB_SPROM2_PA1LOB1 0x003E /* A-PHY PowerAmplifier Low Settings */
3933 +#define SSB_SPROM2_PA1LOB2 0x0040 /* A-PHY PowerAmplifier Low Settings */
3934 +#define SSB_SPROM2_PA1HIB0 0x0042 /* A-PHY PowerAmplifier High Settings */
3935 +#define SSB_SPROM2_PA1HIB1 0x0044 /* A-PHY PowerAmplifier High Settings */
3936 +#define SSB_SPROM2_PA1HIB2 0x0046 /* A-PHY PowerAmplifier High Settings */
3937 +#define SSB_SPROM2_OPO 0x0078 /* OFDM Power Offset from CCK Level */
3938 #define SSB_SPROM2_OPO_VALUE 0x00FF
3939 #define SSB_SPROM2_OPO_UNUSED 0xFF00
3940 -#define SSB_SPROM2_CCODE 0x107C /* Two char Country Code */
3941 +#define SSB_SPROM2_CCODE 0x007C /* Two char Country Code */
3942
3943 /* SPROM Revision 3 (inherits most data from rev 2) */
3944 -#define SSB_SPROM3_IL0MAC 0x104A /* 6 bytes MAC address for 802.11b/g */
3945 -#define SSB_SPROM3_OFDMAPO 0x102C /* A-PHY OFDM Mid Power Offset (4 bytes, BigEndian) */
3946 -#define SSB_SPROM3_OFDMALPO 0x1030 /* A-PHY OFDM Low Power Offset (4 bytes, BigEndian) */
3947 -#define SSB_SPROM3_OFDMAHPO 0x1034 /* A-PHY OFDM High Power Offset (4 bytes, BigEndian) */
3948 -#define SSB_SPROM3_GPIOLDC 0x1042 /* GPIO LED Powersave Duty Cycle (4 bytes, BigEndian) */
3949 +#define SSB_SPROM3_OFDMAPO 0x002C /* A-PHY OFDM Mid Power Offset (4 bytes, BigEndian) */
3950 +#define SSB_SPROM3_OFDMALPO 0x0030 /* A-PHY OFDM Low Power Offset (4 bytes, BigEndian) */
3951 +#define SSB_SPROM3_OFDMAHPO 0x0034 /* A-PHY OFDM High Power Offset (4 bytes, BigEndian) */
3952 +#define SSB_SPROM3_GPIOLDC 0x0042 /* GPIO LED Powersave Duty Cycle (4 bytes, BigEndian) */
3953 #define SSB_SPROM3_GPIOLDC_OFF 0x0000FF00 /* Off Count */
3954 #define SSB_SPROM3_GPIOLDC_OFF_SHIFT 8
3955 #define SSB_SPROM3_GPIOLDC_ON 0x00FF0000 /* On Count */
3956 #define SSB_SPROM3_GPIOLDC_ON_SHIFT 16
3957 -#define SSB_SPROM3_CCKPO 0x1078 /* CCK Power Offset */
3958 +#define SSB_SPROM3_IL0MAC 0x004A /* 6 bytes MAC address for 802.11b/g */
3959 +#define SSB_SPROM3_CCKPO 0x0078 /* CCK Power Offset */
3960 #define SSB_SPROM3_CCKPO_1M 0x000F /* 1M Rate PO */
3961 #define SSB_SPROM3_CCKPO_2M 0x00F0 /* 2M Rate PO */
3962 #define SSB_SPROM3_CCKPO_2M_SHIFT 4
3963 @@ -264,104 +267,291 @@
3964 #define SSB_SPROM3_OFDMGPO 0x107A /* G-PHY OFDM Power Offset (4 bytes, BigEndian) */
3965
3966 /* SPROM Revision 4 */
3967 -#define SSB_SPROM4_IL0MAC 0x104C /* 6 byte MAC address for a/b/g/n */
3968 -#define SSB_SPROM4_ETHPHY 0x105A /* Ethernet PHY settings ?? */
3969 +#define SSB_SPROM4_BFLLO 0x0044 /* Boardflags (low 16 bits) */
3970 +#define SSB_SPROM4_BFLHI 0x0046 /* Board Flags Hi */
3971 +#define SSB_SPROM4_BFL2LO 0x0048 /* Board flags 2 (low 16 bits) */
3972 +#define SSB_SPROM4_BFL2HI 0x004A /* Board flags 2 Hi */
3973 +#define SSB_SPROM4_IL0MAC 0x004C /* 6 byte MAC address for a/b/g/n */
3974 +#define SSB_SPROM4_CCODE 0x0052 /* Country Code (2 bytes) */
3975 +#define SSB_SPROM4_GPIOA 0x0056 /* Gen. Purpose IO # 0 and 1 */
3976 +#define SSB_SPROM4_GPIOA_P0 0x00FF /* Pin 0 */
3977 +#define SSB_SPROM4_GPIOA_P1 0xFF00 /* Pin 1 */
3978 +#define SSB_SPROM4_GPIOA_P1_SHIFT 8
3979 +#define SSB_SPROM4_GPIOB 0x0058 /* Gen. Purpose IO # 2 and 3 */
3980 +#define SSB_SPROM4_GPIOB_P2 0x00FF /* Pin 2 */
3981 +#define SSB_SPROM4_GPIOB_P3 0xFF00 /* Pin 3 */
3982 +#define SSB_SPROM4_GPIOB_P3_SHIFT 8
3983 +#define SSB_SPROM4_ETHPHY 0x005A /* Ethernet PHY settings ?? */
3984 #define SSB_SPROM4_ETHPHY_ET0A 0x001F /* MII Address for enet0 */
3985 #define SSB_SPROM4_ETHPHY_ET1A 0x03E0 /* MII Address for enet1 */
3986 #define SSB_SPROM4_ETHPHY_ET1A_SHIFT 5
3987 #define SSB_SPROM4_ETHPHY_ET0M (1<<14) /* MDIO for enet0 */
3988 #define SSB_SPROM4_ETHPHY_ET1M (1<<15) /* MDIO for enet1 */
3989 -#define SSB_SPROM4_CCODE 0x1052 /* Country Code (2 bytes) */
3990 -#define SSB_SPROM4_ANTAVAIL 0x105D /* Antenna available bitfields */
3991 -#define SSB_SPROM4_ANTAVAIL_A 0x00FF /* A-PHY bitfield */
3992 -#define SSB_SPROM4_ANTAVAIL_A_SHIFT 0
3993 -#define SSB_SPROM4_ANTAVAIL_BG 0xFF00 /* B-PHY and G-PHY bitfield */
3994 -#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 8
3995 -#define SSB_SPROM4_BFLLO 0x1044 /* Boardflags (low 16 bits) */
3996 -#define SSB_SPROM4_AGAIN01 0x105E /* Antenna Gain (in dBm Q5.2) */
3997 +#define SSB_SPROM4_ANTAVAIL 0x005D /* Antenna available bitfields */
3998 +#define SSB_SPROM4_ANTAVAIL_A 0x00FF /* A-PHY bitfield */
3999 +#define SSB_SPROM4_ANTAVAIL_A_SHIFT 0
4000 +#define SSB_SPROM4_ANTAVAIL_BG 0xFF00 /* B-PHY and G-PHY bitfield */
4001 +#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 8
4002 +#define SSB_SPROM4_AGAIN01 0x005E /* Antenna Gain (in dBm Q5.2) */
4003 #define SSB_SPROM4_AGAIN0 0x00FF /* Antenna 0 */
4004 #define SSB_SPROM4_AGAIN0_SHIFT 0
4005 #define SSB_SPROM4_AGAIN1 0xFF00 /* Antenna 1 */
4006 #define SSB_SPROM4_AGAIN1_SHIFT 8
4007 -#define SSB_SPROM4_AGAIN23 0x1060
4008 +#define SSB_SPROM4_AGAIN23 0x0060
4009 #define SSB_SPROM4_AGAIN2 0x00FF /* Antenna 2 */
4010 #define SSB_SPROM4_AGAIN2_SHIFT 0
4011 #define SSB_SPROM4_AGAIN3 0xFF00 /* Antenna 3 */
4012 #define SSB_SPROM4_AGAIN3_SHIFT 8
4013 -#define SSB_SPROM4_BFLHI 0x1046 /* Board Flags Hi */
4014 -#define SSB_SPROM4_MAXP_BG 0x1080 /* Max Power BG in path 1 */
4015 +#define SSB_SPROM4_TXPID2G01 0x0062 /* TX Power Index 2GHz */
4016 +#define SSB_SPROM4_TXPID2G0 0x00FF
4017 +#define SSB_SPROM4_TXPID2G0_SHIFT 0
4018 +#define SSB_SPROM4_TXPID2G1 0xFF00
4019 +#define SSB_SPROM4_TXPID2G1_SHIFT 8
4020 +#define SSB_SPROM4_TXPID2G23 0x0064 /* TX Power Index 2GHz */
4021 +#define SSB_SPROM4_TXPID2G2 0x00FF
4022 +#define SSB_SPROM4_TXPID2G2_SHIFT 0
4023 +#define SSB_SPROM4_TXPID2G3 0xFF00
4024 +#define SSB_SPROM4_TXPID2G3_SHIFT 8
4025 +#define SSB_SPROM4_TXPID5G01 0x0066 /* TX Power Index 5GHz middle subband */
4026 +#define SSB_SPROM4_TXPID5G0 0x00FF
4027 +#define SSB_SPROM4_TXPID5G0_SHIFT 0
4028 +#define SSB_SPROM4_TXPID5G1 0xFF00
4029 +#define SSB_SPROM4_TXPID5G1_SHIFT 8
4030 +#define SSB_SPROM4_TXPID5G23 0x0068 /* TX Power Index 5GHz middle subband */
4031 +#define SSB_SPROM4_TXPID5G2 0x00FF
4032 +#define SSB_SPROM4_TXPID5G2_SHIFT 0
4033 +#define SSB_SPROM4_TXPID5G3 0xFF00
4034 +#define SSB_SPROM4_TXPID5G3_SHIFT 8
4035 +#define SSB_SPROM4_TXPID5GL01 0x006A /* TX Power Index 5GHz low subband */
4036 +#define SSB_SPROM4_TXPID5GL0 0x00FF
4037 +#define SSB_SPROM4_TXPID5GL0_SHIFT 0
4038 +#define SSB_SPROM4_TXPID5GL1 0xFF00
4039 +#define SSB_SPROM4_TXPID5GL1_SHIFT 8
4040 +#define SSB_SPROM4_TXPID5GL23 0x006C /* TX Power Index 5GHz low subband */
4041 +#define SSB_SPROM4_TXPID5GL2 0x00FF
4042 +#define SSB_SPROM4_TXPID5GL2_SHIFT 0
4043 +#define SSB_SPROM4_TXPID5GL3 0xFF00
4044 +#define SSB_SPROM4_TXPID5GL3_SHIFT 8
4045 +#define SSB_SPROM4_TXPID5GH01 0x006E /* TX Power Index 5GHz high subband */
4046 +#define SSB_SPROM4_TXPID5GH0 0x00FF
4047 +#define SSB_SPROM4_TXPID5GH0_SHIFT 0
4048 +#define SSB_SPROM4_TXPID5GH1 0xFF00
4049 +#define SSB_SPROM4_TXPID5GH1_SHIFT 8
4050 +#define SSB_SPROM4_TXPID5GH23 0x0070 /* TX Power Index 5GHz high subband */
4051 +#define SSB_SPROM4_TXPID5GH2 0x00FF
4052 +#define SSB_SPROM4_TXPID5GH2_SHIFT 0
4053 +#define SSB_SPROM4_TXPID5GH3 0xFF00
4054 +#define SSB_SPROM4_TXPID5GH3_SHIFT 8
4055 +#define SSB_SPROM4_MAXP_BG 0x0080 /* Max Power BG in path 1 */
4056 #define SSB_SPROM4_MAXP_BG_MASK 0x00FF /* Mask for Max Power BG */
4057 #define SSB_SPROM4_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
4058 #define SSB_SPROM4_ITSSI_BG_SHIFT 8
4059 -#define SSB_SPROM4_MAXP_A 0x108A /* Max Power A in path 1 */
4060 +#define SSB_SPROM4_MAXP_A 0x008A /* Max Power A in path 1 */
4061 #define SSB_SPROM4_MAXP_A_MASK 0x00FF /* Mask for Max Power A */
4062 #define SSB_SPROM4_ITSSI_A 0xFF00 /* Mask for path 1 itssi_a */
4063 #define SSB_SPROM4_ITSSI_A_SHIFT 8
4064 -#define SSB_SPROM4_GPIOA 0x1056 /* Gen. Purpose IO # 0 and 1 */
4065 -#define SSB_SPROM4_GPIOA_P0 0x00FF /* Pin 0 */
4066 -#define SSB_SPROM4_GPIOA_P1 0xFF00 /* Pin 1 */
4067 -#define SSB_SPROM4_GPIOA_P1_SHIFT 8
4068 -#define SSB_SPROM4_GPIOB 0x1058 /* Gen. Purpose IO # 2 and 3 */
4069 -#define SSB_SPROM4_GPIOB_P2 0x00FF /* Pin 2 */
4070 -#define SSB_SPROM4_GPIOB_P3 0xFF00 /* Pin 3 */
4071 -#define SSB_SPROM4_GPIOB_P3_SHIFT 8
4072 -#define SSB_SPROM4_PA0B0 0x1082 /* The paXbY locations are */
4073 -#define SSB_SPROM4_PA0B1 0x1084 /* only guesses */
4074 -#define SSB_SPROM4_PA0B2 0x1086
4075 -#define SSB_SPROM4_PA1B0 0x108E
4076 -#define SSB_SPROM4_PA1B1 0x1090
4077 -#define SSB_SPROM4_PA1B2 0x1092
4078 +#define SSB_SPROM4_PA0B0 0x0082 /* The paXbY locations are */
4079 +#define SSB_SPROM4_PA0B1 0x0084 /* only guesses */
4080 +#define SSB_SPROM4_PA0B2 0x0086
4081 +#define SSB_SPROM4_PA1B0 0x008E
4082 +#define SSB_SPROM4_PA1B1 0x0090
4083 +#define SSB_SPROM4_PA1B2 0x0092
4084
4085 /* SPROM Revision 5 (inherits most data from rev 4) */
4086 -#define SSB_SPROM5_BFLLO 0x104A /* Boardflags (low 16 bits) */
4087 -#define SSB_SPROM5_BFLHI 0x104C /* Board Flags Hi */
4088 -#define SSB_SPROM5_IL0MAC 0x1052 /* 6 byte MAC address for a/b/g/n */
4089 -#define SSB_SPROM5_CCODE 0x1044 /* Country Code (2 bytes) */
4090 -#define SSB_SPROM5_GPIOA 0x1076 /* Gen. Purpose IO # 0 and 1 */
4091 +#define SSB_SPROM5_CCODE 0x0044 /* Country Code (2 bytes) */
4092 +#define SSB_SPROM5_BFLLO 0x004A /* Boardflags (low 16 bits) */
4093 +#define SSB_SPROM5_BFLHI 0x004C /* Board Flags Hi */
4094 +#define SSB_SPROM5_BFL2LO 0x004E /* Board flags 2 (low 16 bits) */
4095 +#define SSB_SPROM5_BFL2HI 0x0050 /* Board flags 2 Hi */
4096 +#define SSB_SPROM5_IL0MAC 0x0052 /* 6 byte MAC address for a/b/g/n */
4097 +#define SSB_SPROM5_GPIOA 0x0076 /* Gen. Purpose IO # 0 and 1 */
4098 #define SSB_SPROM5_GPIOA_P0 0x00FF /* Pin 0 */
4099 #define SSB_SPROM5_GPIOA_P1 0xFF00 /* Pin 1 */
4100 #define SSB_SPROM5_GPIOA_P1_SHIFT 8
4101 -#define SSB_SPROM5_GPIOB 0x1078 /* Gen. Purpose IO # 2 and 3 */
4102 +#define SSB_SPROM5_GPIOB 0x0078 /* Gen. Purpose IO # 2 and 3 */
4103 #define SSB_SPROM5_GPIOB_P2 0x00FF /* Pin 2 */
4104 #define SSB_SPROM5_GPIOB_P3 0xFF00 /* Pin 3 */
4105 #define SSB_SPROM5_GPIOB_P3_SHIFT 8
4106
4107 /* SPROM Revision 8 */
4108 -#define SSB_SPROM8_BFLLO 0x1084 /* Boardflags (low 16 bits) */
4109 -#define SSB_SPROM8_BFLHI 0x1086 /* Boardflags Hi */
4110 -#define SSB_SPROM8_IL0MAC 0x108C /* 6 byte MAC address */
4111 -#define SSB_SPROM8_CCODE 0x1092 /* 2 byte country code */
4112 -#define SSB_SPROM8_ANTAVAIL 0x109C /* Antenna available bitfields*/
4113 -#define SSB_SPROM8_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */
4114 -#define SSB_SPROM8_ANTAVAIL_A_SHIFT 8
4115 -#define SSB_SPROM8_ANTAVAIL_BG 0x00FF /* B-PHY and G-PHY bitfield */
4116 -#define SSB_SPROM8_ANTAVAIL_BG_SHIFT 0
4117 -#define SSB_SPROM8_AGAIN01 0x109E /* Antenna Gain (in dBm Q5.2) */
4118 +#define SSB_SPROM8_BOARDREV 0x0082 /* Board revision */
4119 +#define SSB_SPROM8_BFLLO 0x0084 /* Board flags (bits 0-15) */
4120 +#define SSB_SPROM8_BFLHI 0x0086 /* Board flags (bits 16-31) */
4121 +#define SSB_SPROM8_BFL2LO 0x0088 /* Board flags (bits 32-47) */
4122 +#define SSB_SPROM8_BFL2HI 0x008A /* Board flags (bits 48-63) */
4123 +#define SSB_SPROM8_IL0MAC 0x008C /* 6 byte MAC address */
4124 +#define SSB_SPROM8_CCODE 0x0092 /* 2 byte country code */
4125 +#define SSB_SPROM8_GPIOA 0x0096 /*Gen. Purpose IO # 0 and 1 */
4126 +#define SSB_SPROM8_GPIOA_P0 0x00FF /* Pin 0 */
4127 +#define SSB_SPROM8_GPIOA_P1 0xFF00 /* Pin 1 */
4128 +#define SSB_SPROM8_GPIOA_P1_SHIFT 8
4129 +#define SSB_SPROM8_GPIOB 0x0098 /* Gen. Purpose IO # 2 and 3 */
4130 +#define SSB_SPROM8_GPIOB_P2 0x00FF /* Pin 2 */
4131 +#define SSB_SPROM8_GPIOB_P3 0xFF00 /* Pin 3 */
4132 +#define SSB_SPROM8_GPIOB_P3_SHIFT 8
4133 +#define SSB_SPROM8_ANTAVAIL 0x009C /* Antenna available bitfields*/
4134 +#define SSB_SPROM8_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */
4135 +#define SSB_SPROM8_ANTAVAIL_A_SHIFT 8
4136 +#define SSB_SPROM8_ANTAVAIL_BG 0x00FF /* B-PHY and G-PHY bitfield */
4137 +#define SSB_SPROM8_ANTAVAIL_BG_SHIFT 0
4138 +#define SSB_SPROM8_AGAIN01 0x009E /* Antenna Gain (in dBm Q5.2) */
4139 #define SSB_SPROM8_AGAIN0 0x00FF /* Antenna 0 */
4140 #define SSB_SPROM8_AGAIN0_SHIFT 0
4141 #define SSB_SPROM8_AGAIN1 0xFF00 /* Antenna 1 */
4142 #define SSB_SPROM8_AGAIN1_SHIFT 8
4143 -#define SSB_SPROM8_AGAIN23 0x10A0
4144 +#define SSB_SPROM8_AGAIN23 0x00A0
4145 #define SSB_SPROM8_AGAIN2 0x00FF /* Antenna 2 */
4146 #define SSB_SPROM8_AGAIN2_SHIFT 0
4147 #define SSB_SPROM8_AGAIN3 0xFF00 /* Antenna 3 */
4148 #define SSB_SPROM8_AGAIN3_SHIFT 8
4149 -#define SSB_SPROM8_GPIOA 0x1096 /*Gen. Purpose IO # 0 and 1 */
4150 -#define SSB_SPROM8_GPIOA_P0 0x00FF /* Pin 0 */
4151 -#define SSB_SPROM8_GPIOA_P1 0xFF00 /* Pin 1 */
4152 -#define SSB_SPROM8_GPIOA_P1_SHIFT 8
4153 -#define SSB_SPROM8_GPIOB 0x1098 /* Gen. Purpose IO # 2 and 3 */
4154 -#define SSB_SPROM8_GPIOB_P2 0x00FF /* Pin 2 */
4155 -#define SSB_SPROM8_GPIOB_P3 0xFF00 /* Pin 3 */
4156 -#define SSB_SPROM8_GPIOB_P3_SHIFT 8
4157 -#define SSB_SPROM8_MAXP_BG 0x10C0 /* Max Power BG in path 1 */
4158 -#define SSB_SPROM8_MAXP_BG_MASK 0x00FF /* Mask for Max Power BG */
4159 +#define SSB_SPROM8_RSSIPARM2G 0x00A4 /* RSSI params for 2GHz */
4160 +#define SSB_SPROM8_RSSISMF2G 0x000F
4161 +#define SSB_SPROM8_RSSISMC2G 0x00F0
4162 +#define SSB_SPROM8_RSSISMC2G_SHIFT 4
4163 +#define SSB_SPROM8_RSSISAV2G 0x0700
4164 +#define SSB_SPROM8_RSSISAV2G_SHIFT 8
4165 +#define SSB_SPROM8_BXA2G 0x1800
4166 +#define SSB_SPROM8_BXA2G_SHIFT 11
4167 +#define SSB_SPROM8_RSSIPARM5G 0x00A6 /* RSSI params for 5GHz */
4168 +#define SSB_SPROM8_RSSISMF5G 0x000F
4169 +#define SSB_SPROM8_RSSISMC5G 0x00F0
4170 +#define SSB_SPROM8_RSSISMC5G_SHIFT 4
4171 +#define SSB_SPROM8_RSSISAV5G 0x0700
4172 +#define SSB_SPROM8_RSSISAV5G_SHIFT 8
4173 +#define SSB_SPROM8_BXA5G 0x1800
4174 +#define SSB_SPROM8_BXA5G_SHIFT 11
4175 +#define SSB_SPROM8_TRI25G 0x00A8 /* TX isolation 2.4&5.3GHz */
4176 +#define SSB_SPROM8_TRI2G 0x00FF /* TX isolation 2.4GHz */
4177 +#define SSB_SPROM8_TRI5G 0xFF00 /* TX isolation 5.3GHz */
4178 +#define SSB_SPROM8_TRI5G_SHIFT 8
4179 +#define SSB_SPROM8_TRI5GHL 0x00AA /* TX isolation 5.2/5.8GHz */
4180 +#define SSB_SPROM8_TRI5GL 0x00FF /* TX isolation 5.2GHz */
4181 +#define SSB_SPROM8_TRI5GH 0xFF00 /* TX isolation 5.8GHz */
4182 +#define SSB_SPROM8_TRI5GH_SHIFT 8
4183 +#define SSB_SPROM8_RXPO 0x00AC /* RX power offsets */
4184 +#define SSB_SPROM8_RXPO2G 0x00FF /* 2GHz RX power offset */
4185 +#define SSB_SPROM8_RXPO5G 0xFF00 /* 5GHz RX power offset */
4186 +#define SSB_SPROM8_RXPO5G_SHIFT 8
4187 +#define SSB_SPROM8_FEM2G 0x00AE
4188 +#define SSB_SPROM8_FEM5G 0x00B0
4189 +#define SSB_SROM8_FEM_TSSIPOS 0x0001
4190 +#define SSB_SROM8_FEM_TSSIPOS_SHIFT 0
4191 +#define SSB_SROM8_FEM_EXTPA_GAIN 0x0006
4192 +#define SSB_SROM8_FEM_EXTPA_GAIN_SHIFT 1
4193 +#define SSB_SROM8_FEM_PDET_RANGE 0x00F8
4194 +#define SSB_SROM8_FEM_PDET_RANGE_SHIFT 3
4195 +#define SSB_SROM8_FEM_TR_ISO 0x0700
4196 +#define SSB_SROM8_FEM_TR_ISO_SHIFT 8
4197 +#define SSB_SROM8_FEM_ANTSWLUT 0xF800
4198 +#define SSB_SROM8_FEM_ANTSWLUT_SHIFT 11
4199 +#define SSB_SPROM8_THERMAL 0x00B2
4200 +#define SSB_SPROM8_MPWR_RAWTS 0x00B4
4201 +#define SSB_SPROM8_TS_SLP_OPT_CORRX 0x00B6
4202 +#define SSB_SPROM8_FOC_HWIQ_IQSWP 0x00B8
4203 +#define SSB_SPROM8_PHYCAL_TEMPDELTA 0x00BA
4204 +
4205 +/* There are 4 blocks with power info sharing the same layout */
4206 +#define SSB_SROM8_PWR_INFO_CORE0 0x00C0
4207 +#define SSB_SROM8_PWR_INFO_CORE1 0x00E0
4208 +#define SSB_SROM8_PWR_INFO_CORE2 0x0100
4209 +#define SSB_SROM8_PWR_INFO_CORE3 0x0120
4210 +
4211 +#define SSB_SROM8_2G_MAXP_ITSSI 0x00
4212 +#define SSB_SPROM8_2G_MAXP 0x00FF
4213 +#define SSB_SPROM8_2G_ITSSI 0xFF00
4214 +#define SSB_SPROM8_2G_ITSSI_SHIFT 8
4215 +#define SSB_SROM8_2G_PA_0 0x02 /* 2GHz power amp settings */
4216 +#define SSB_SROM8_2G_PA_1 0x04
4217 +#define SSB_SROM8_2G_PA_2 0x06
4218 +#define SSB_SROM8_5G_MAXP_ITSSI 0x08 /* 5GHz ITSSI and 5.3GHz Max Power */
4219 +#define SSB_SPROM8_5G_MAXP 0x00FF
4220 +#define SSB_SPROM8_5G_ITSSI 0xFF00
4221 +#define SSB_SPROM8_5G_ITSSI_SHIFT 8
4222 +#define SSB_SPROM8_5GHL_MAXP 0x0A /* 5.2GHz and 5.8GHz Max Power */
4223 +#define SSB_SPROM8_5GH_MAXP 0x00FF
4224 +#define SSB_SPROM8_5GL_MAXP 0xFF00
4225 +#define SSB_SPROM8_5GL_MAXP_SHIFT 8
4226 +#define SSB_SROM8_5G_PA_0 0x0C /* 5.3GHz power amp settings */
4227 +#define SSB_SROM8_5G_PA_1 0x0E
4228 +#define SSB_SROM8_5G_PA_2 0x10
4229 +#define SSB_SROM8_5GL_PA_0 0x12 /* 5.2GHz power amp settings */
4230 +#define SSB_SROM8_5GL_PA_1 0x14
4231 +#define SSB_SROM8_5GL_PA_2 0x16
4232 +#define SSB_SROM8_5GH_PA_0 0x18 /* 5.8GHz power amp settings */
4233 +#define SSB_SROM8_5GH_PA_1 0x1A
4234 +#define SSB_SROM8_5GH_PA_2 0x1C
4235 +
4236 +/* TODO: Make it deprecated */
4237 +#define SSB_SPROM8_MAXP_BG 0x00C0 /* Max Power 2GHz in path 1 */
4238 +#define SSB_SPROM8_MAXP_BG_MASK 0x00FF /* Mask for Max Power 2GHz */
4239 #define SSB_SPROM8_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
4240 #define SSB_SPROM8_ITSSI_BG_SHIFT 8
4241 -#define SSB_SPROM8_MAXP_A 0x10C8 /* Max Power A in path 1 */
4242 -#define SSB_SPROM8_MAXP_A_MASK 0x00FF /* Mask for Max Power A */
4243 +#define SSB_SPROM8_PA0B0 0x00C2 /* 2GHz power amp settings */
4244 +#define SSB_SPROM8_PA0B1 0x00C4
4245 +#define SSB_SPROM8_PA0B2 0x00C6
4246 +#define SSB_SPROM8_MAXP_A 0x00C8 /* Max Power 5.3GHz */
4247 +#define SSB_SPROM8_MAXP_A_MASK 0x00FF /* Mask for Max Power 5.3GHz */
4248 #define SSB_SPROM8_ITSSI_A 0xFF00 /* Mask for path 1 itssi_a */
4249 #define SSB_SPROM8_ITSSI_A_SHIFT 8
4250 +#define SSB_SPROM8_MAXP_AHL 0x00CA /* Max Power 5.2/5.8GHz */
4251 +#define SSB_SPROM8_MAXP_AH_MASK 0x00FF /* Mask for Max Power 5.8GHz */
4252 +#define SSB_SPROM8_MAXP_AL_MASK 0xFF00 /* Mask for Max Power 5.2GHz */
4253 +#define SSB_SPROM8_MAXP_AL_SHIFT 8
4254 +#define SSB_SPROM8_PA1B0 0x00CC /* 5.3GHz power amp settings */
4255 +#define SSB_SPROM8_PA1B1 0x00CE
4256 +#define SSB_SPROM8_PA1B2 0x00D0
4257 +#define SSB_SPROM8_PA1LOB0 0x00D2 /* 5.2GHz power amp settings */
4258 +#define SSB_SPROM8_PA1LOB1 0x00D4
4259 +#define SSB_SPROM8_PA1LOB2 0x00D6
4260 +#define SSB_SPROM8_PA1HIB0 0x00D8 /* 5.8GHz power amp settings */
4261 +#define SSB_SPROM8_PA1HIB1 0x00DA
4262 +#define SSB_SPROM8_PA1HIB2 0x00DC
4263 +
4264 +#define SSB_SPROM8_CCK2GPO 0x0140 /* CCK power offset */
4265 +#define SSB_SPROM8_OFDM2GPO 0x0142 /* 2.4GHz OFDM power offset */
4266 +#define SSB_SPROM8_OFDM5GPO 0x0146 /* 5.3GHz OFDM power offset */
4267 +#define SSB_SPROM8_OFDM5GLPO 0x014A /* 5.2GHz OFDM power offset */
4268 +#define SSB_SPROM8_OFDM5GHPO 0x014E /* 5.8GHz OFDM power offset */
4269 +
4270 +/* Values for boardflags_lo read from SPROM */
4271 +#define SSB_BFL_BTCOEXIST 0x0001 /* implements Bluetooth coexistance */
4272 +#define SSB_BFL_PACTRL 0x0002 /* GPIO 9 controlling the PA */
4273 +#define SSB_BFL_AIRLINEMODE 0x0004 /* implements GPIO 13 radio disable indication */
4274 +#define SSB_BFL_RSSI 0x0008 /* software calculates nrssi slope. */
4275 +#define SSB_BFL_ENETSPI 0x0010 /* has ephy roboswitch spi */
4276 +#define SSB_BFL_XTAL_NOSLOW 0x0020 /* no slow clock available */
4277 +#define SSB_BFL_CCKHIPWR 0x0040 /* can do high power CCK transmission */
4278 +#define SSB_BFL_ENETADM 0x0080 /* has ADMtek switch */
4279 +#define SSB_BFL_ENETVLAN 0x0100 /* can do vlan */
4280 +#define SSB_BFL_AFTERBURNER 0x0200 /* supports Afterburner mode */
4281 +#define SSB_BFL_NOPCI 0x0400 /* board leaves PCI floating */
4282 +#define SSB_BFL_FEM 0x0800 /* supports the Front End Module */
4283 +#define SSB_BFL_EXTLNA 0x1000 /* has an external LNA */
4284 +#define SSB_BFL_HGPA 0x2000 /* had high gain PA */
4285 +#define SSB_BFL_BTCMOD 0x4000 /* BFL_BTCOEXIST is given in alternate GPIOs */
4286 +#define SSB_BFL_ALTIQ 0x8000 /* alternate I/Q settings */
4287 +
4288 +/* Values for boardflags_hi read from SPROM */
4289 +#define SSB_BFH_NOPA 0x0001 /* has no PA */
4290 +#define SSB_BFH_RSSIINV 0x0002 /* RSSI uses positive slope (not TSSI) */
4291 +#define SSB_BFH_PAREF 0x0004 /* uses the PARef LDO */
4292 +#define SSB_BFH_3TSWITCH 0x0008 /* uses a triple throw switch shared with bluetooth */
4293 +#define SSB_BFH_PHASESHIFT 0x0010 /* can support phase shifter */
4294 +#define SSB_BFH_BUCKBOOST 0x0020 /* has buck/booster */
4295 +#define SSB_BFH_FEM_BT 0x0040 /* has FEM and switch to share antenna with bluetooth */
4296 +
4297 +/* Values for boardflags2_lo read from SPROM */
4298 +#define SSB_BFL2_RXBB_INT_REG_DIS 0x0001 /* external RX BB regulator present */
4299 +#define SSB_BFL2_APLL_WAR 0x0002 /* alternative A-band PLL settings implemented */
4300 +#define SSB_BFL2_TXPWRCTRL_EN 0x0004 /* permits enabling TX Power Control */
4301 +#define SSB_BFL2_2X4_DIV 0x0008 /* 2x4 diversity switch */
4302 +#define SSB_BFL2_5G_PWRGAIN 0x0010 /* supports 5G band power gain */
4303 +#define SSB_BFL2_PCIEWAR_OVR 0x0020 /* overrides ASPM and Clkreq settings */
4304 +#define SSB_BFL2_CAESERS_BRD 0x0040 /* is Caesers board (unused) */
4305 +#define SSB_BFL2_BTC3WIRE 0x0080 /* used 3-wire bluetooth coexist */
4306 +#define SSB_BFL2_SKWRKFEM_BRD 0x0100 /* 4321mcm93 uses Skyworks FEM */
4307 +#define SSB_BFL2_SPUR_WAR 0x0200 /* has a workaround for clock-harmonic spurs */
4308 +#define SSB_BFL2_GPLL_WAR 0x0400 /* altenative G-band PLL settings implemented */
4309
4310 /* Values for SSB_SPROM1_BINF_CCODE */
4311 enum {
4312 --- a/drivers/ssb/driver_extif.c
4313 +++ b/drivers/ssb/driver_extif.c
4314 @@ -3,7 +3,7 @@
4315 * Broadcom EXTIF core driver
4316 *
4317 * Copyright 2005, Broadcom Corporation
4318 - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
4319 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
4320 * Copyright 2006, 2007, Felix Fietkau <nbd@openwrt.org>
4321 * Copyright 2007, Aurelien Jarno <aurelien@aurel32.net>
4322 *
4323 --- a/drivers/ssb/embedded.c
4324 +++ b/drivers/ssb/embedded.c
4325 @@ -3,7 +3,7 @@
4326 * Embedded systems support code
4327 *
4328 * Copyright 2005-2008, Broadcom Corporation
4329 - * Copyright 2006-2008, Michael Buesch <mb@bu3sch.de>
4330 + * Copyright 2006-2008, Michael Buesch <m@bues.ch>
4331 *
4332 * Licensed under the GNU/GPL. See COPYING for details.
4333 */
4334 --- a/include/linux/ssb/ssb_driver_gige.h
4335 +++ b/include/linux/ssb/ssb_driver_gige.h
4336 @@ -2,6 +2,7 @@
4337 #define LINUX_SSB_DRIVER_GIGE_H_
4338
4339 #include <linux/ssb/ssb.h>
4340 +#include <linux/bug.h>
4341 #include <linux/pci.h>
4342 #include <linux/spinlock.h>
4343
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