1 --- a/drivers/bcma/Kconfig
2 +++ b/drivers/bcma/Kconfig
3 @@ -26,6 +26,7 @@ config BCMA_HOST_PCI_POSSIBLE
5 bool "Support for BCMA on PCI-host bus"
6 depends on BCMA_HOST_PCI_POSSIBLE
9 config BCMA_DRIVER_PCI_HOSTMODE
10 bool "Driver for PCI core working in hostmode"
11 @@ -34,8 +35,14 @@ config BCMA_DRIVER_PCI_HOSTMODE
12 PCI core hostmode operation (external PCI bus).
16 - depends on BCMA_DRIVER_MIPS
17 + bool "Support for BCMA in a SoC"
20 + Host interface for a Broadcom AIX bus directly mapped into
21 + the memory. This only works with the Broadcom SoCs from the
26 config BCMA_DRIVER_MIPS
27 bool "BCMA Broadcom MIPS core driver"
28 @@ -68,6 +75,7 @@ config BCMA_DRIVER_GMAC_CMN
29 config BCMA_DRIVER_GPIO
30 bool "BCMA GPIO driver"
31 depends on BCMA && GPIOLIB
32 + select IRQ_DOMAIN if BCMA_HOST_SOC
34 Driver to provide access to the GPIO pins of the bcma bus.
36 --- a/drivers/bcma/Makefile
37 +++ b/drivers/bcma/Makefile
39 bcma-y += main.o scan.o core.o sprom.o
40 bcma-y += driver_chipcommon.o driver_chipcommon_pmu.o
41 +bcma-y += driver_chipcommon_b.o
42 bcma-$(CONFIG_BCMA_SFLASH) += driver_chipcommon_sflash.o
43 bcma-$(CONFIG_BCMA_NFLASH) += driver_chipcommon_nflash.o
44 bcma-y += driver_pci.o
45 +bcma-y += driver_pcie2.o
46 bcma-$(CONFIG_BCMA_DRIVER_PCI_HOSTMODE) += driver_pci_host.o
47 bcma-$(CONFIG_BCMA_DRIVER_MIPS) += driver_mips.o
48 bcma-$(CONFIG_BCMA_DRIVER_GMAC_CMN) += driver_gmac_cmn.o
49 --- a/drivers/bcma/bcma_private.h
50 +++ b/drivers/bcma/bcma_private.h
55 +bool bcma_wait_value(struct bcma_device *core, u16 reg, u32 mask, u32 value,
57 int bcma_bus_register(struct bcma_bus *bus);
58 void bcma_bus_unregister(struct bcma_bus *bus);
59 int __init bcma_bus_early_register(struct bcma_bus *bus,
60 @@ -31,8 +33,6 @@ int __init bcma_bus_early_register(struc
61 int bcma_bus_suspend(struct bcma_bus *bus);
62 int bcma_bus_resume(struct bcma_bus *bus);
64 -struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
68 int bcma_bus_scan(struct bcma_bus *bus);
69 @@ -50,6 +50,10 @@ void bcma_chipco_serial_init(struct bcma
70 extern struct platform_device bcma_pflash_dev;
71 #endif /* CONFIG_BCMA_DRIVER_MIPS */
73 +/* driver_chipcommon_b.c */
74 +int bcma_core_chipcommon_b_init(struct bcma_drv_cc_b *ccb);
75 +void bcma_core_chipcommon_b_free(struct bcma_drv_cc_b *ccb);
77 /* driver_chipcommon_pmu.c */
78 u32 bcma_pmu_get_alp_clock(struct bcma_drv_cc *cc);
79 u32 bcma_pmu_get_cpu_clock(struct bcma_drv_cc *cc);
80 --- a/drivers/bcma/core.c
81 +++ b/drivers/bcma/core.c
83 #include <linux/export.h>
84 #include <linux/bcma/bcma.h>
86 +static bool bcma_core_wait_value(struct bcma_device *core, u16 reg, u32 mask,
87 + u32 value, int timeout)
89 + unsigned long deadline = jiffies + timeout;
93 + val = bcma_aread32(core, reg);
94 + if ((val & mask) == value)
98 + } while (!time_after_eq(jiffies, deadline));
100 + bcma_warn(core->bus, "Timeout waiting for register 0x%04X!\n", reg);
105 bool bcma_core_is_enabled(struct bcma_device *core)
107 if ((bcma_aread32(core, BCMA_IOCTL) & (BCMA_IOCTL_CLK | BCMA_IOCTL_FGC))
108 @@ -25,13 +44,15 @@ void bcma_core_disable(struct bcma_devic
109 if (bcma_aread32(core, BCMA_RESET_CTL) & BCMA_RESET_CTL_RESET)
112 - bcma_awrite32(core, BCMA_IOCTL, flags);
113 - bcma_aread32(core, BCMA_IOCTL);
115 + bcma_core_wait_value(core, BCMA_RESET_ST, ~0, 0, 300);
117 bcma_awrite32(core, BCMA_RESET_CTL, BCMA_RESET_CTL_RESET);
118 bcma_aread32(core, BCMA_RESET_CTL);
121 + bcma_awrite32(core, BCMA_IOCTL, flags);
122 + bcma_aread32(core, BCMA_IOCTL);
125 EXPORT_SYMBOL_GPL(bcma_core_disable);
127 @@ -43,6 +64,7 @@ int bcma_core_enable(struct bcma_device
128 bcma_aread32(core, BCMA_IOCTL);
130 bcma_awrite32(core, BCMA_RESET_CTL, 0);
131 + bcma_aread32(core, BCMA_RESET_CTL);
134 bcma_awrite32(core, BCMA_IOCTL, (BCMA_IOCTL_CLK | flags));
135 --- a/drivers/bcma/driver_chipcommon.c
136 +++ b/drivers/bcma/driver_chipcommon.c
137 @@ -140,8 +140,15 @@ void bcma_core_chipcommon_init(struct bc
138 bcma_core_chipcommon_early_init(cc);
140 if (cc->core->id.rev >= 20) {
141 - bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, 0);
142 - bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, 0);
143 + u32 pullup = 0, pulldown = 0;
145 + if (cc->core->bus->chipinfo.id == BCMA_CHIP_ID_BCM43142) {
147 + pulldown = 0x20500;
150 + bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, pullup);
151 + bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, pulldown);
154 if (cc->capabilities & BCMA_CC_CAP_PMU)
155 --- a/drivers/bcma/driver_chipcommon_pmu.c
156 +++ b/drivers/bcma/driver_chipcommon_pmu.c
157 @@ -56,6 +56,109 @@ void bcma_chipco_regctl_maskset(struct b
159 EXPORT_SYMBOL_GPL(bcma_chipco_regctl_maskset);
161 +static u32 bcma_pmu_xtalfreq(struct bcma_drv_cc *cc)
163 + u32 ilp_ctl, alp_hz;
165 + if (!(bcma_cc_read32(cc, BCMA_CC_PMU_STAT) &
166 + BCMA_CC_PMU_STAT_EXT_LPO_AVAIL))
169 + bcma_cc_write32(cc, BCMA_CC_PMU_XTAL_FREQ,
170 + BIT(BCMA_CC_PMU_XTAL_FREQ_MEASURE_SHIFT));
171 + usleep_range(1000, 2000);
173 + ilp_ctl = bcma_cc_read32(cc, BCMA_CC_PMU_XTAL_FREQ);
174 + ilp_ctl &= BCMA_CC_PMU_XTAL_FREQ_ILPCTL_MASK;
176 + bcma_cc_write32(cc, BCMA_CC_PMU_XTAL_FREQ, 0);
178 + alp_hz = ilp_ctl * 32768 / 4;
179 + return (alp_hz + 50000) / 100000 * 100;
182 +static void bcma_pmu2_pll_init0(struct bcma_drv_cc *cc, u32 xtalfreq)
184 + struct bcma_bus *bus = cc->core->bus;
185 + u32 freq_tgt_target = 0, freq_tgt_current;
188 + switch (bus->chipinfo.id) {
189 + case BCMA_CHIP_ID_BCM43142:
190 + /* pmu2_xtaltab0_adfll_485 */
191 + switch (xtalfreq) {
193 + freq_tgt_target = 0x50D52;
196 + freq_tgt_target = 0x307FE;
199 + freq_tgt_target = 0x254EA;
202 + freq_tgt_target = 0x19EF8;
205 + freq_tgt_target = 0x12A75;
211 + if (!freq_tgt_target) {
212 + bcma_err(bus, "Unknown TGT frequency for xtalfreq %d\n",
217 + pll0 = bcma_chipco_pll_read(cc, BCMA_CC_PMU15_PLL_PLLCTL0);
218 + freq_tgt_current = (pll0 & BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK) >>
219 + BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT;
221 + if (freq_tgt_current == freq_tgt_target) {
222 + bcma_debug(bus, "Target TGT frequency already set\n");
227 + switch (bus->chipinfo.id) {
228 + case BCMA_CHIP_ID_BCM43142:
229 + mask = (u32)~(BCMA_RES_4314_HT_AVAIL |
230 + BCMA_RES_4314_MACPHY_CLK_AVAIL);
232 + bcma_cc_mask32(cc, BCMA_CC_PMU_MINRES_MSK, mask);
233 + bcma_cc_mask32(cc, BCMA_CC_PMU_MAXRES_MSK, mask);
234 + bcma_wait_value(cc->core, BCMA_CLKCTLST,
235 + BCMA_CLKCTLST_HAVEHT, 0, 20000);
239 + pll0 &= ~BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK;
240 + pll0 |= freq_tgt_target << BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT;
241 + bcma_chipco_pll_write(cc, BCMA_CC_PMU15_PLL_PLLCTL0, pll0);
244 + if (cc->pmu.rev >= 2)
245 + bcma_cc_set32(cc, BCMA_CC_PMU_CTL, BCMA_CC_PMU_CTL_PLL_UPD);
247 + /* TODO: Do we need to update OTP? */
250 +static void bcma_pmu_pll_init(struct bcma_drv_cc *cc)
252 + struct bcma_bus *bus = cc->core->bus;
253 + u32 xtalfreq = bcma_pmu_xtalfreq(cc);
255 + switch (bus->chipinfo.id) {
256 + case BCMA_CHIP_ID_BCM43142:
259 + bcma_pmu2_pll_init0(cc, xtalfreq);
264 static void bcma_pmu_resources_init(struct bcma_drv_cc *cc)
266 struct bcma_bus *bus = cc->core->bus;
267 @@ -66,6 +169,25 @@ static void bcma_pmu_resources_init(stru
271 + case BCMA_CHIP_ID_BCM43142:
272 + min_msk = BCMA_RES_4314_LPLDO_PU |
273 + BCMA_RES_4314_PMU_SLEEP_DIS |
274 + BCMA_RES_4314_PMU_BG_PU |
275 + BCMA_RES_4314_CBUCK_LPOM_PU |
276 + BCMA_RES_4314_CBUCK_PFM_PU |
277 + BCMA_RES_4314_CLDO_PU |
278 + BCMA_RES_4314_LPLDO2_LVM |
279 + BCMA_RES_4314_WL_PMU_PU |
280 + BCMA_RES_4314_LDO3P3_PU |
281 + BCMA_RES_4314_OTP_PU |
282 + BCMA_RES_4314_WL_PWRSW_PU |
283 + BCMA_RES_4314_LQ_AVAIL |
284 + BCMA_RES_4314_LOGIC_RET |
285 + BCMA_RES_4314_MEM_SLEEP |
286 + BCMA_RES_4314_MACPHY_RET |
287 + BCMA_RES_4314_WL_CORE_READY;
288 + max_msk = 0x3FFFFFFF;
291 bcma_debug(bus, "PMU resource config unknown or not needed for device 0x%04X\n",
293 @@ -165,6 +287,7 @@ void bcma_pmu_init(struct bcma_drv_cc *c
294 bcma_cc_set32(cc, BCMA_CC_PMU_CTL,
295 BCMA_CC_PMU_CTL_NOILPONW);
297 + bcma_pmu_pll_init(cc);
298 bcma_pmu_resources_init(cc);
299 bcma_pmu_workarounds(cc);
301 @@ -480,6 +603,8 @@ void bcma_pmu_spuravoid_pllupdate(struct
302 tmp = BCMA_CC_PMU_CTL_PLL_UPD | BCMA_CC_PMU_CTL_NOILPONW;
305 + case BCMA_CHIP_ID_BCM43131:
306 + case BCMA_CHIP_ID_BCM43217:
307 case BCMA_CHIP_ID_BCM43227:
308 case BCMA_CHIP_ID_BCM43228:
309 case BCMA_CHIP_ID_BCM43428:
310 --- a/drivers/bcma/driver_chipcommon_sflash.c
311 +++ b/drivers/bcma/driver_chipcommon_sflash.c
312 @@ -30,7 +30,7 @@ struct bcma_sflash_tbl_e {
316 -static struct bcma_sflash_tbl_e bcma_sflash_st_tbl[] = {
317 +static const struct bcma_sflash_tbl_e bcma_sflash_st_tbl[] = {
318 { "M25P20", 0x11, 0x10000, 4, },
319 { "M25P40", 0x12, 0x10000, 8, },
321 @@ -38,10 +38,10 @@ static struct bcma_sflash_tbl_e bcma_sfl
322 { "M25P32", 0x15, 0x10000, 64, },
323 { "M25P64", 0x16, 0x10000, 128, },
324 { "M25FL128", 0x17, 0x10000, 256, },
329 -static struct bcma_sflash_tbl_e bcma_sflash_sst_tbl[] = {
330 +static const struct bcma_sflash_tbl_e bcma_sflash_sst_tbl[] = {
331 { "SST25WF512", 1, 0x1000, 16, },
332 { "SST25VF512", 0x48, 0x1000, 16, },
333 { "SST25WF010", 2, 0x1000, 32, },
334 @@ -56,10 +56,10 @@ static struct bcma_sflash_tbl_e bcma_sfl
335 { "SST25VF016", 0x41, 0x1000, 512, },
336 { "SST25VF032", 0x4a, 0x1000, 1024, },
337 { "SST25VF064", 0x4b, 0x1000, 2048, },
342 -static struct bcma_sflash_tbl_e bcma_sflash_at_tbl[] = {
343 +static const struct bcma_sflash_tbl_e bcma_sflash_at_tbl[] = {
344 { "AT45DB011", 0xc, 256, 512, },
345 { "AT45DB021", 0x14, 256, 1024, },
346 { "AT45DB041", 0x1c, 256, 2048, },
347 @@ -67,7 +67,7 @@ static struct bcma_sflash_tbl_e bcma_sfl
348 { "AT45DB161", 0x2c, 512, 4096, },
349 { "AT45DB321", 0x34, 512, 8192, },
350 { "AT45DB642", 0x3c, 1024, 8192, },
355 static void bcma_sflash_cmd(struct bcma_drv_cc *cc, u32 opcode)
356 @@ -89,7 +89,7 @@ int bcma_sflash_init(struct bcma_drv_cc
358 struct bcma_bus *bus = cc->core->bus;
359 struct bcma_sflash *sflash = &cc->sflash;
360 - struct bcma_sflash_tbl_e *e;
361 + const struct bcma_sflash_tbl_e *e;
364 switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {
365 --- a/drivers/bcma/driver_gpio.c
366 +++ b/drivers/bcma/driver_gpio.c
370 #include <linux/gpio.h>
371 +#include <linux/irq.h>
372 +#include <linux/interrupt.h>
373 +#include <linux/irqdomain.h>
374 #include <linux/export.h>
375 #include <linux/bcma/bcma.h>
377 @@ -73,19 +76,136 @@ static void bcma_gpio_free(struct gpio_c
378 bcma_chipco_gpio_pullup(cc, 1 << gpio, 0);
381 +#if IS_BUILTIN(CONFIG_BCMA_HOST_SOC)
382 static int bcma_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
384 struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
386 if (cc->core->bus->hosttype == BCMA_HOSTTYPE_SOC)
387 - return bcma_core_irq(cc->core);
388 + return irq_find_mapping(cc->irq_domain, gpio);
393 +static void bcma_gpio_irq_unmask(struct irq_data *d)
395 + struct bcma_drv_cc *cc = irq_data_get_irq_chip_data(d);
396 + int gpio = irqd_to_hwirq(d);
397 + u32 val = bcma_chipco_gpio_in(cc, BIT(gpio));
399 + bcma_chipco_gpio_polarity(cc, BIT(gpio), val);
400 + bcma_chipco_gpio_intmask(cc, BIT(gpio), BIT(gpio));
403 +static void bcma_gpio_irq_mask(struct irq_data *d)
405 + struct bcma_drv_cc *cc = irq_data_get_irq_chip_data(d);
406 + int gpio = irqd_to_hwirq(d);
408 + bcma_chipco_gpio_intmask(cc, BIT(gpio), 0);
411 +static struct irq_chip bcma_gpio_irq_chip = {
412 + .name = "BCMA-GPIO",
413 + .irq_mask = bcma_gpio_irq_mask,
414 + .irq_unmask = bcma_gpio_irq_unmask,
417 +static irqreturn_t bcma_gpio_irq_handler(int irq, void *dev_id)
419 + struct bcma_drv_cc *cc = dev_id;
420 + u32 val = bcma_cc_read32(cc, BCMA_CC_GPIOIN);
421 + u32 mask = bcma_cc_read32(cc, BCMA_CC_GPIOIRQ);
422 + u32 pol = bcma_cc_read32(cc, BCMA_CC_GPIOPOL);
423 + unsigned long irqs = (val ^ pol) & mask;
429 + for_each_set_bit(gpio, &irqs, cc->gpio.ngpio)
430 + generic_handle_irq(bcma_gpio_to_irq(&cc->gpio, gpio));
431 + bcma_chipco_gpio_polarity(cc, irqs, val & irqs);
433 + return IRQ_HANDLED;
436 +static int bcma_gpio_irq_domain_init(struct bcma_drv_cc *cc)
438 + struct gpio_chip *chip = &cc->gpio;
439 + int gpio, hwirq, err;
441 + if (cc->core->bus->hosttype != BCMA_HOSTTYPE_SOC)
444 + cc->irq_domain = irq_domain_add_linear(NULL, chip->ngpio,
445 + &irq_domain_simple_ops, cc);
446 + if (!cc->irq_domain) {
448 + goto err_irq_domain;
450 + for (gpio = 0; gpio < chip->ngpio; gpio++) {
451 + int irq = irq_create_mapping(cc->irq_domain, gpio);
453 + irq_set_chip_data(irq, cc);
454 + irq_set_chip_and_handler(irq, &bcma_gpio_irq_chip,
455 + handle_simple_irq);
458 + hwirq = bcma_core_irq(cc->core);
459 + err = request_irq(hwirq, bcma_gpio_irq_handler, IRQF_SHARED, "gpio",
464 + bcma_chipco_gpio_intmask(cc, ~0, 0);
465 + bcma_cc_set32(cc, BCMA_CC_IRQMASK, BCMA_CC_IRQ_GPIO);
470 + for (gpio = 0; gpio < chip->ngpio; gpio++) {
471 + int irq = irq_find_mapping(cc->irq_domain, gpio);
473 + irq_dispose_mapping(irq);
475 + irq_domain_remove(cc->irq_domain);
480 +static void bcma_gpio_irq_domain_exit(struct bcma_drv_cc *cc)
482 + struct gpio_chip *chip = &cc->gpio;
485 + if (cc->core->bus->hosttype != BCMA_HOSTTYPE_SOC)
488 + bcma_cc_mask32(cc, BCMA_CC_IRQMASK, ~BCMA_CC_IRQ_GPIO);
489 + free_irq(bcma_core_irq(cc->core), cc);
490 + for (gpio = 0; gpio < chip->ngpio; gpio++) {
491 + int irq = irq_find_mapping(cc->irq_domain, gpio);
493 + irq_dispose_mapping(irq);
495 + irq_domain_remove(cc->irq_domain);
498 +static int bcma_gpio_irq_domain_init(struct bcma_drv_cc *cc)
503 +static void bcma_gpio_irq_domain_exit(struct bcma_drv_cc *cc)
508 int bcma_gpio_init(struct bcma_drv_cc *cc)
510 struct gpio_chip *chip = &cc->gpio;
513 chip->label = "bcma_gpio";
514 chip->owner = THIS_MODULE;
515 @@ -95,8 +215,18 @@ int bcma_gpio_init(struct bcma_drv_cc *c
516 chip->set = bcma_gpio_set_value;
517 chip->direction_input = bcma_gpio_direction_input;
518 chip->direction_output = bcma_gpio_direction_output;
519 +#if IS_BUILTIN(CONFIG_BCMA_HOST_SOC)
520 chip->to_irq = bcma_gpio_to_irq;
523 + switch (cc->core->bus->chipinfo.id) {
524 + case BCMA_CHIP_ID_BCM5357:
525 + case BCMA_CHIP_ID_BCM53572:
532 /* There is just one SoC in one device and its GPIO addresses should be
533 * deterministic to address them more easily. The other buses could get
534 * a random base number. */
535 @@ -105,10 +235,21 @@ int bcma_gpio_init(struct bcma_drv_cc *c
539 - return gpiochip_add(chip);
540 + err = bcma_gpio_irq_domain_init(cc);
544 + err = gpiochip_add(chip);
546 + bcma_gpio_irq_domain_exit(cc);
553 int bcma_gpio_unregister(struct bcma_drv_cc *cc)
555 + bcma_gpio_irq_domain_exit(cc);
556 return gpiochip_remove(&cc->gpio);
558 --- a/drivers/bcma/driver_pci.c
559 +++ b/drivers/bcma/driver_pci.c
560 @@ -31,7 +31,7 @@ static void bcma_pcie_write(struct bcma_
561 pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_DATA, data);
564 -static void bcma_pcie_mdio_set_phy(struct bcma_drv_pci *pc, u8 phy)
565 +static void bcma_pcie_mdio_set_phy(struct bcma_drv_pci *pc, u16 phy)
569 @@ -55,7 +55,7 @@ static void bcma_pcie_mdio_set_phy(struc
573 -static u16 bcma_pcie_mdio_read(struct bcma_drv_pci *pc, u8 device, u8 address)
574 +static u16 bcma_pcie_mdio_read(struct bcma_drv_pci *pc, u16 device, u8 address)
576 int max_retries = 10;
578 @@ -98,7 +98,7 @@ static u16 bcma_pcie_mdio_read(struct bc
582 -static void bcma_pcie_mdio_write(struct bcma_drv_pci *pc, u8 device,
583 +static void bcma_pcie_mdio_write(struct bcma_drv_pci *pc, u16 device,
584 u8 address, u16 data)
586 int max_retries = 10;
587 @@ -137,6 +137,13 @@ static void bcma_pcie_mdio_write(struct
588 pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0);
591 +static u16 bcma_pcie_mdio_writeread(struct bcma_drv_pci *pc, u16 device,
592 + u8 address, u16 data)
594 + bcma_pcie_mdio_write(pc, device, address, data);
595 + return bcma_pcie_mdio_read(pc, device, address);
598 /**************************************************
600 **************************************************/
601 @@ -229,6 +236,32 @@ void bcma_core_pci_init(struct bcma_drv_
602 bcma_core_pci_clientmode_init(pc);
605 +void bcma_core_pci_power_save(struct bcma_bus *bus, bool up)
607 + struct bcma_drv_pci *pc;
610 + if (bus->hosttype != BCMA_HOSTTYPE_PCI)
613 + pc = &bus->drv_pci[0];
615 + if (pc->core->id.rev >= 15 && pc->core->id.rev <= 20) {
616 + data = up ? 0x74 : 0x7C;
617 + bcma_pcie_mdio_writeread(pc, BCMA_CORE_PCI_MDIO_BLK1,
618 + BCMA_CORE_PCI_MDIO_BLK1_MGMT1, 0x7F64);
619 + bcma_pcie_mdio_writeread(pc, BCMA_CORE_PCI_MDIO_BLK1,
620 + BCMA_CORE_PCI_MDIO_BLK1_MGMT3, data);
621 + } else if (pc->core->id.rev >= 21 && pc->core->id.rev <= 22) {
622 + data = up ? 0x75 : 0x7D;
623 + bcma_pcie_mdio_writeread(pc, BCMA_CORE_PCI_MDIO_BLK1,
624 + BCMA_CORE_PCI_MDIO_BLK1_MGMT1, 0x7E65);
625 + bcma_pcie_mdio_writeread(pc, BCMA_CORE_PCI_MDIO_BLK1,
626 + BCMA_CORE_PCI_MDIO_BLK1_MGMT3, data);
629 +EXPORT_SYMBOL_GPL(bcma_core_pci_power_save);
631 int bcma_core_pci_irq_ctl(struct bcma_drv_pci *pc, struct bcma_device *core,
634 @@ -262,7 +295,7 @@ out:
636 EXPORT_SYMBOL_GPL(bcma_core_pci_irq_ctl);
638 -void bcma_core_pci_extend_L1timer(struct bcma_drv_pci *pc, bool extend)
639 +static void bcma_core_pci_extend_L1timer(struct bcma_drv_pci *pc, bool extend)
643 @@ -274,4 +307,29 @@ void bcma_core_pci_extend_L1timer(struct
644 bcma_pcie_write(pc, BCMA_CORE_PCI_DLLP_PMTHRESHREG, w);
645 bcma_pcie_read(pc, BCMA_CORE_PCI_DLLP_PMTHRESHREG);
647 -EXPORT_SYMBOL_GPL(bcma_core_pci_extend_L1timer);
649 +void bcma_core_pci_up(struct bcma_bus *bus)
651 + struct bcma_drv_pci *pc;
653 + if (bus->hosttype != BCMA_HOSTTYPE_PCI)
656 + pc = &bus->drv_pci[0];
658 + bcma_core_pci_extend_L1timer(pc, true);
660 +EXPORT_SYMBOL_GPL(bcma_core_pci_up);
662 +void bcma_core_pci_down(struct bcma_bus *bus)
664 + struct bcma_drv_pci *pc;
666 + if (bus->hosttype != BCMA_HOSTTYPE_PCI)
669 + pc = &bus->drv_pci[0];
671 + bcma_core_pci_extend_L1timer(pc, false);
673 +EXPORT_SYMBOL_GPL(bcma_core_pci_down);
674 --- a/drivers/bcma/driver_pci_host.c
675 +++ b/drivers/bcma/driver_pci_host.c
676 @@ -581,6 +581,7 @@ DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI
677 int bcma_core_pci_plat_dev_init(struct pci_dev *dev)
679 struct bcma_drv_pci_host *pc_host;
682 if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
683 /* This is not a device on the PCI-core bridge. */
684 @@ -595,6 +596,11 @@ int bcma_core_pci_plat_dev_init(struct p
685 dev->irq = bcma_core_irq(pc_host->pdev->core);
686 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
688 + readrq = pcie_get_readrq(dev);
689 + if (readrq > 128) {
690 + pr_info("change PCIe max read request size from %i to 128\n", readrq);
691 + pcie_set_readrq(dev, 128);
695 EXPORT_SYMBOL(bcma_core_pci_plat_dev_init);
697 +++ b/drivers/bcma/driver_pcie2.c
700 + * Broadcom specific AMBA
703 + * Copyright 2014, Broadcom Corporation
704 + * Copyright 2014, Rafał Miłecki <zajec5@gmail.com>
706 + * Licensed under the GNU/GPL. See COPYING for details.
709 +#include "bcma_private.h"
710 +#include <linux/bcma/bcma.h>
712 +/**************************************************
714 + **************************************************/
717 +static u32 bcma_core_pcie2_cfg_read(struct bcma_drv_pcie2 *pcie2, u32 addr)
719 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, addr);
720 + pcie2_read32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR);
721 + return pcie2_read32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA);
725 +static void bcma_core_pcie2_cfg_write(struct bcma_drv_pcie2 *pcie2, u32 addr,
728 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, addr);
729 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, val);
732 +/**************************************************
734 + **************************************************/
736 +static u32 bcma_core_pcie2_war_delay_perst_enab(struct bcma_drv_pcie2 *pcie2,
741 + /* restore back to default */
742 + val = pcie2_read32(pcie2, BCMA_CORE_PCIE2_CLK_CONTROL);
743 + val |= PCIE2_CLKC_DLYPERST;
744 + val &= ~PCIE2_CLKC_DISSPROMLD;
746 + val &= ~PCIE2_CLKC_DLYPERST;
747 + val |= PCIE2_CLKC_DISSPROMLD;
749 + pcie2_write32(pcie2, (BCMA_CORE_PCIE2_CLK_CONTROL), val);
751 + return pcie2_read32(pcie2, BCMA_CORE_PCIE2_CLK_CONTROL);
754 +static void bcma_core_pcie2_set_ltr_vals(struct bcma_drv_pcie2 *pcie2)
757 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, 0x844);
758 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x883c883c);
760 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, 0x848);
761 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x88648864);
763 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, 0x84C);
764 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x90039003);
767 +static void bcma_core_pcie2_hw_ltr_war(struct bcma_drv_pcie2 *pcie2)
769 + u8 core_rev = pcie2->core->id.rev;
772 + if (core_rev < 2 || core_rev == 10 || core_rev > 13)
775 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
776 + PCIE2_CAP_DEVSTSCTRL2_OFFSET);
777 + devstsctr2 = pcie2_read32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA);
778 + if (devstsctr2 & PCIE2_CAP_DEVSTSCTRL2_LTRENAB) {
779 + /* force the right LTR values */
780 + bcma_core_pcie2_set_ltr_vals(pcie2);
783 + si_core_wrapperreg(pcie2, 3, 0x60, 0x8080, 0); */
785 + /* enable the LTR */
786 + devstsctr2 |= PCIE2_CAP_DEVSTSCTRL2_LTRENAB;
787 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
788 + PCIE2_CAP_DEVSTSCTRL2_OFFSET);
789 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, devstsctr2);
791 + /* set the LTR state to be active */
792 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_LTR_STATE,
794 + usleep_range(1000, 2000);
796 + /* set the LTR state to be sleep */
797 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_LTR_STATE,
799 + usleep_range(1000, 2000);
803 +static void pciedev_crwlpciegen2(struct bcma_drv_pcie2 *pcie2)
805 + u8 core_rev = pcie2->core->id.rev;
806 + bool pciewar160, pciewar162;
808 + pciewar160 = core_rev == 7 || core_rev == 9 || core_rev == 11;
809 + pciewar162 = core_rev == 5 || core_rev == 7 || core_rev == 8 ||
810 + core_rev == 9 || core_rev == 11;
812 + if (!pciewar160 && !pciewar162)
817 + pcie2_set32(pcie2, BCMA_CORE_PCIE2_CLK_CONTROL,
818 + PCIE_DISABLE_L1CLK_GATING);
820 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
821 + PCIEGEN2_COE_PVT_TL_CTRL_0);
822 + pcie2_mask32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA,
823 + ~(1 << COE_PVT_TL_CTRL_0_PM_DIS_L1_REENTRY_BIT));
828 +static void pciedev_crwlpciegen2_180(struct bcma_drv_pcie2 *pcie2)
830 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, PCIE2_PMCR_REFUP);
831 + pcie2_set32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x1f);
834 +static void pciedev_crwlpciegen2_182(struct bcma_drv_pcie2 *pcie2)
836 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, PCIE2_SBMBX);
837 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 1 << 0);
840 +static void pciedev_reg_pm_clk_period(struct bcma_drv_pcie2 *pcie2)
842 + struct bcma_drv_cc *drv_cc = &pcie2->core->bus->drv_cc;
843 + u8 core_rev = pcie2->core->id.rev;
844 + u32 alp_khz, pm_value;
846 + if (core_rev <= 13) {
847 + alp_khz = bcma_pmu_get_alp_clock(drv_cc) / 1000;
848 + pm_value = (1000000 * 2) / alp_khz;
849 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
850 + PCIE2_PVT_REG_PM_CLK_PERIOD);
851 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, pm_value);
855 +void bcma_core_pcie2_init(struct bcma_drv_pcie2 *pcie2)
857 + struct bcma_chipinfo *ci = &pcie2->core->bus->chipinfo;
860 + tmp = pcie2_read32(pcie2, BCMA_CORE_PCIE2_SPROM(54));
861 + if ((tmp & 0xe) >> 1 == 2)
862 + bcma_core_pcie2_cfg_write(pcie2, 0x4e0, 0x17);
864 + /* TODO: Do we need pcie_reqsize? */
866 + if (ci->id == BCMA_CHIP_ID_BCM4360 && ci->rev > 3)
867 + bcma_core_pcie2_war_delay_perst_enab(pcie2, true);
868 + bcma_core_pcie2_hw_ltr_war(pcie2);
869 + pciedev_crwlpciegen2(pcie2);
870 + pciedev_reg_pm_clk_period(pcie2);
871 + pciedev_crwlpciegen2_180(pcie2);
872 + pciedev_crwlpciegen2_182(pcie2);
874 --- a/drivers/bcma/host_pci.c
875 +++ b/drivers/bcma/host_pci.c
876 @@ -188,8 +188,11 @@ static int bcma_host_pci_probe(struct pc
877 pci_write_config_dword(dev, 0x40, val & 0xffff00ff);
879 /* SSB needed additional powering up, do we have any AMBA PCI cards? */
880 - if (!pci_is_pcie(dev))
881 - bcma_err(bus, "PCI card detected, report problems.\n");
882 + if (!pci_is_pcie(dev)) {
883 + bcma_err(bus, "PCI card detected, they are not supported.\n");
885 + goto err_pci_release_regions;
890 @@ -205,6 +208,9 @@ static int bcma_host_pci_probe(struct pc
891 bus->boardinfo.vendor = bus->host_pci->subsystem_vendor;
892 bus->boardinfo.type = bus->host_pci->subsystem_device;
894 + /* Initialize struct, detect chip */
895 + bcma_init_bus(bus);
898 err = bcma_bus_register(bus);
900 @@ -235,7 +241,6 @@ static void bcma_host_pci_remove(struct
901 pci_release_regions(dev);
902 pci_disable_device(dev);
904 - pci_set_drvdata(dev, NULL);
907 #ifdef CONFIG_PM_SLEEP
908 @@ -267,15 +272,20 @@ static SIMPLE_DEV_PM_OPS(bcma_pm_ops, bc
910 #endif /* CONFIG_PM_SLEEP */
912 -static DEFINE_PCI_DEVICE_TABLE(bcma_pci_bridge_tbl) = {
913 +static const struct pci_device_id bcma_pci_bridge_tbl[] = {
914 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x0576) },
915 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4313) },
916 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 43224) },
917 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4331) },
918 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4353) },
919 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4357) },
920 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4358) },
921 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4359) },
922 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4365) },
923 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x43a9) },
924 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x43aa) },
925 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4727) },
926 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 43227) }, /* 0xA8DB */
929 MODULE_DEVICE_TABLE(pci, bcma_pci_bridge_tbl);
930 --- a/drivers/bcma/main.c
931 +++ b/drivers/bcma/main.c
932 @@ -69,28 +69,36 @@ static u16 bcma_cc_core_id(struct bcma_b
933 return BCMA_CORE_CHIPCOMMON;
936 -struct bcma_device *bcma_find_core(struct bcma_bus *bus, u16 coreid)
937 +struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
940 struct bcma_device *core;
942 list_for_each_entry(core, &bus->cores, list) {
943 - if (core->id.id == coreid)
944 + if (core->id.id == coreid && core->core_unit == unit)
949 -EXPORT_SYMBOL_GPL(bcma_find_core);
950 +EXPORT_SYMBOL_GPL(bcma_find_core_unit);
952 -struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
954 +bool bcma_wait_value(struct bcma_device *core, u16 reg, u32 mask, u32 value,
957 - struct bcma_device *core;
958 + unsigned long deadline = jiffies + timeout;
961 - list_for_each_entry(core, &bus->cores, list) {
962 - if (core->id.id == coreid && core->core_unit == unit)
967 + val = bcma_read32(core, reg);
968 + if ((val & mask) == value)
972 + } while (!time_after_eq(jiffies, deadline));
974 + bcma_warn(core->bus, "Timeout waiting for register 0x%04X!\n", reg);
979 static void bcma_release_core_dev(struct device *dev)
980 @@ -103,55 +111,78 @@ static void bcma_release_core_dev(struct
984 -static int bcma_register_cores(struct bcma_bus *bus)
985 +static bool bcma_is_core_needed_early(u16 core_id)
988 + case BCMA_CORE_NS_NAND:
989 + case BCMA_CORE_NS_QSPI:
996 +static void bcma_register_core(struct bcma_bus *bus, struct bcma_device *core)
1000 + core->dev.release = bcma_release_core_dev;
1001 + core->dev.bus = &bcma_bus_type;
1002 + dev_set_name(&core->dev, "bcma%d:%d", bus->num, core->core_index);
1004 + switch (bus->hosttype) {
1005 + case BCMA_HOSTTYPE_PCI:
1006 + core->dev.parent = &bus->host_pci->dev;
1007 + core->dma_dev = &bus->host_pci->dev;
1008 + core->irq = bus->host_pci->irq;
1010 + case BCMA_HOSTTYPE_SOC:
1011 + core->dev.dma_mask = &core->dev.coherent_dma_mask;
1012 + core->dma_dev = &core->dev;
1014 + case BCMA_HOSTTYPE_SDIO:
1018 + err = device_register(&core->dev);
1020 + bcma_err(bus, "Could not register dev for core 0x%03X\n",
1022 + put_device(&core->dev);
1025 + core->dev_registered = true;
1028 +static int bcma_register_devices(struct bcma_bus *bus)
1030 struct bcma_device *core;
1031 - int err, dev_id = 0;
1034 list_for_each_entry(core, &bus->cores, list) {
1035 /* We support that cores ourself */
1036 switch (core->id.id) {
1037 case BCMA_CORE_4706_CHIPCOMMON:
1038 case BCMA_CORE_CHIPCOMMON:
1039 + case BCMA_CORE_NS_CHIPCOMMON_B:
1041 case BCMA_CORE_PCIE:
1042 + case BCMA_CORE_PCIE2:
1043 case BCMA_CORE_MIPS_74K:
1044 case BCMA_CORE_4706_MAC_GBIT_COMMON:
1048 + /* Early cores were already registered */
1049 + if (bcma_is_core_needed_early(core->id.id))
1052 /* Only first GMAC core on BCM4706 is connected and working */
1053 if (core->id.id == BCMA_CORE_4706_MAC_GBIT &&
1054 core->core_unit > 0)
1057 - core->dev.release = bcma_release_core_dev;
1058 - core->dev.bus = &bcma_bus_type;
1059 - dev_set_name(&core->dev, "bcma%d:%d", bus->num, dev_id);
1061 - switch (bus->hosttype) {
1062 - case BCMA_HOSTTYPE_PCI:
1063 - core->dev.parent = &bus->host_pci->dev;
1064 - core->dma_dev = &bus->host_pci->dev;
1065 - core->irq = bus->host_pci->irq;
1067 - case BCMA_HOSTTYPE_SOC:
1068 - core->dev.dma_mask = &core->dev.coherent_dma_mask;
1069 - core->dma_dev = &core->dev;
1071 - case BCMA_HOSTTYPE_SDIO:
1075 - err = device_register(&core->dev);
1078 - "Could not register dev for core 0x%03X\n",
1082 - core->dev_registered = true;
1084 + bcma_register_core(bus, core);
1087 #ifdef CONFIG_BCMA_DRIVER_MIPS
1088 @@ -218,7 +249,7 @@ int bcma_bus_register(struct bcma_bus *b
1089 err = bcma_bus_scan(bus);
1091 bcma_err(bus, "Failed to scan: %d\n", err);
1096 /* Early init CC core */
1097 @@ -228,6 +259,12 @@ int bcma_bus_register(struct bcma_bus *b
1098 bcma_core_chipcommon_early_init(&bus->drv_cc);
1101 + /* Cores providing flash access go before SPROM init */
1102 + list_for_each_entry(core, &bus->cores, list) {
1103 + if (bcma_is_core_needed_early(core->id.id))
1104 + bcma_register_core(bus, core);
1107 /* Try to get SPROM */
1108 err = bcma_sprom_get(bus);
1109 if (err == -ENOENT) {
1110 @@ -242,6 +279,13 @@ int bcma_bus_register(struct bcma_bus *b
1111 bcma_core_chipcommon_init(&bus->drv_cc);
1114 + /* Init CC core */
1115 + core = bcma_find_core(bus, BCMA_CORE_NS_CHIPCOMMON_B);
1117 + bus->drv_cc_b.core = core;
1118 + bcma_core_chipcommon_b_init(&bus->drv_cc_b);
1121 /* Init MIPS core */
1122 core = bcma_find_core(bus, BCMA_CORE_MIPS_74K);
1124 @@ -263,6 +307,13 @@ int bcma_bus_register(struct bcma_bus *b
1125 bcma_core_pci_init(&bus->drv_pci[1]);
1128 + /* Init PCIe Gen 2 core */
1129 + core = bcma_find_core_unit(bus, BCMA_CORE_PCIE2, 0);
1131 + bus->drv_pcie2.core = core;
1132 + bcma_core_pcie2_init(&bus->drv_pcie2);
1135 /* Init GBIT MAC COMMON core */
1136 core = bcma_find_core(bus, BCMA_CORE_4706_MAC_GBIT_COMMON);
1138 @@ -271,7 +322,7 @@ int bcma_bus_register(struct bcma_bus *b
1141 /* Register found cores */
1142 - bcma_register_cores(bus);
1143 + bcma_register_devices(bus);
1145 bcma_info(bus, "Bus registered\n");
1147 @@ -289,6 +340,8 @@ void bcma_bus_unregister(struct bcma_bus
1149 bcma_err(bus, "Can not unregister GPIO driver: %i\n", err);
1151 + bcma_core_chipcommon_b_free(&bus->drv_cc_b);
1153 cores[0] = bcma_find_core(bus, BCMA_CORE_MIPS_74K);
1154 cores[1] = bcma_find_core(bus, BCMA_CORE_PCIE);
1155 cores[2] = bcma_find_core(bus, BCMA_CORE_4706_MAC_GBIT_COMMON);
1156 @@ -308,8 +361,6 @@ int __init bcma_bus_early_register(struc
1157 struct bcma_device *core;
1158 struct bcma_device_id match;
1160 - bcma_init_bus(bus);
1162 match.manuf = BCMA_MANUF_BCM;
1163 match.id = bcma_cc_core_id(bus);
1164 match.class = BCMA_CL_SIM;
1165 --- a/drivers/bcma/scan.c
1166 +++ b/drivers/bcma/scan.c
1167 @@ -32,6 +32,18 @@ static const struct bcma_device_id_name
1168 { BCMA_CORE_4706_CHIPCOMMON, "BCM4706 ChipCommon" },
1169 { BCMA_CORE_4706_SOC_RAM, "BCM4706 SOC RAM" },
1170 { BCMA_CORE_4706_MAC_GBIT, "BCM4706 GBit MAC" },
1171 + { BCMA_CORE_NS_PCIEG2, "PCIe Gen 2" },
1172 + { BCMA_CORE_NS_DMA, "DMA" },
1173 + { BCMA_CORE_NS_SDIO3, "SDIO3" },
1174 + { BCMA_CORE_NS_USB20, "USB 2.0" },
1175 + { BCMA_CORE_NS_USB30, "USB 3.0" },
1176 + { BCMA_CORE_NS_A9JTAG, "ARM Cortex A9 JTAG" },
1177 + { BCMA_CORE_NS_DDR23, "Denali DDR2/DDR3 memory controller" },
1178 + { BCMA_CORE_NS_ROM, "ROM" },
1179 + { BCMA_CORE_NS_NAND, "NAND flash controller" },
1180 + { BCMA_CORE_NS_QSPI, "SPI flash controller" },
1181 + { BCMA_CORE_NS_CHIPCOMMON_B, "Chipcommon B" },
1182 + { BCMA_CORE_ARMCA9, "ARM Cortex A9 core (ihost)" },
1183 { BCMA_CORE_AMEMC, "AMEMC (DDR)" },
1184 { BCMA_CORE_ALTA, "ALTA (I2S)" },
1185 { BCMA_CORE_INVALID, "Invalid" },
1186 @@ -201,7 +213,7 @@ static s32 bcma_erom_get_mst_port(struct
1190 -static s32 bcma_erom_get_addr_desc(struct bcma_bus *bus, u32 __iomem **eromptr,
1191 +static u32 bcma_erom_get_addr_desc(struct bcma_bus *bus, u32 __iomem **eromptr,
1194 u32 addrl, addrh, sizel, sizeh = 0;
1195 @@ -213,7 +225,7 @@ static s32 bcma_erom_get_addr_desc(struc
1196 ((ent & SCAN_ADDR_TYPE) != type) ||
1197 (((ent & SCAN_ADDR_PORT) >> SCAN_ADDR_PORT_SHIFT) != port)) {
1198 bcma_erom_push_ent(eromptr);
1200 + return (u32)-EINVAL;
1203 addrl = ent & SCAN_ADDR_ADDR;
1204 @@ -257,12 +269,14 @@ static struct bcma_device *bcma_find_cor
1208 +#define IS_ERR_VALUE_U32(x) ((x) >= (u32)-MAX_ERRNO)
1210 static int bcma_get_next_core(struct bcma_bus *bus, u32 __iomem **eromptr,
1211 struct bcma_device_id *match, int core_num,
1212 struct bcma_device *core)
1219 u8 ports[2], wrappers[2];
1221 @@ -300,6 +314,7 @@ static int bcma_get_next_core(struct bcm
1222 /* Some specific cores don't need wrappers */
1223 switch (core->id.id) {
1224 case BCMA_CORE_4706_MAC_GBIT_COMMON:
1225 + case BCMA_CORE_NS_CHIPCOMMON_B:
1226 /* Not used yet: case BCMA_CORE_OOB_ROUTER: */
1229 @@ -339,11 +354,11 @@ static int bcma_get_next_core(struct bcm
1230 * the main register space for the core
1232 tmp = bcma_erom_get_addr_desc(bus, eromptr, SCAN_ADDR_TYPE_SLAVE, 0);
1234 + if (tmp == 0 || IS_ERR_VALUE_U32(tmp)) {
1235 /* Try again to see if it is a bridge */
1236 tmp = bcma_erom_get_addr_desc(bus, eromptr,
1237 SCAN_ADDR_TYPE_BRIDGE, 0);
1239 + if (tmp == 0 || IS_ERR_VALUE_U32(tmp)) {
1242 bcma_info(bus, "Bridge found\n");
1243 @@ -353,18 +368,19 @@ static int bcma_get_next_core(struct bcm
1246 /* get & parse slave ports */
1248 for (i = 0; i < ports[1]; i++) {
1249 for (j = 0; ; j++) {
1250 tmp = bcma_erom_get_addr_desc(bus, eromptr,
1251 SCAN_ADDR_TYPE_SLAVE, i);
1253 + if (IS_ERR_VALUE_U32(tmp)) {
1254 /* no more entries for port _i_ */
1255 /* pr_debug("erom: slave port %d "
1256 * "has %d descriptors\n", i, j); */
1259 - if (i == 0 && j == 0)
1260 - core->addr1 = tmp;
1261 + } else if (k < ARRAY_SIZE(core->addr_s)) {
1262 + core->addr_s[k] = tmp;
1267 @@ -374,7 +390,7 @@ static int bcma_get_next_core(struct bcm
1268 for (j = 0; ; j++) {
1269 tmp = bcma_erom_get_addr_desc(bus, eromptr,
1270 SCAN_ADDR_TYPE_MWRAP, i);
1272 + if (IS_ERR_VALUE_U32(tmp)) {
1273 /* no more entries for port _i_ */
1274 /* pr_debug("erom: master wrapper %d "
1275 * "has %d descriptors\n", i, j); */
1276 @@ -392,7 +408,7 @@ static int bcma_get_next_core(struct bcm
1277 for (j = 0; ; j++) {
1278 tmp = bcma_erom_get_addr_desc(bus, eromptr,
1279 SCAN_ADDR_TYPE_SWRAP, i + hack);
1281 + if (IS_ERR_VALUE_U32(tmp)) {
1282 /* no more entries for port _i_ */
1283 /* pr_debug("erom: master wrapper %d "
1284 * has %d descriptors\n", i, j); */
1285 @@ -407,10 +423,13 @@ static int bcma_get_next_core(struct bcm
1286 core->io_addr = ioremap_nocache(core->addr, BCMA_CORE_SIZE);
1289 - core->io_wrap = ioremap_nocache(core->wrap, BCMA_CORE_SIZE);
1290 - if (!core->io_wrap) {
1291 - iounmap(core->io_addr);
1294 + core->io_wrap = ioremap_nocache(core->wrap,
1296 + if (!core->io_wrap) {
1297 + iounmap(core->io_addr);
1303 @@ -421,9 +440,6 @@ void bcma_init_bus(struct bcma_bus *bus)
1305 struct bcma_chipinfo *chipinfo = &(bus->chipinfo);
1307 - if (bus->init_done)
1310 INIT_LIST_HEAD(&bus->cores);
1313 @@ -435,8 +451,6 @@ void bcma_init_bus(struct bcma_bus *bus)
1314 chipinfo->pkg = (tmp & BCMA_CC_ID_PKG) >> BCMA_CC_ID_PKG_SHIFT;
1315 bcma_info(bus, "Found chip with id 0x%04X, rev 0x%02X and package 0x%02X\n",
1316 chipinfo->id, chipinfo->rev, chipinfo->pkg);
1318 - bus->init_done = true;
1321 int bcma_bus_scan(struct bcma_bus *bus)
1322 @@ -446,8 +460,6 @@ int bcma_bus_scan(struct bcma_bus *bus)
1324 int err, core_num = 0;
1326 - bcma_init_bus(bus);
1328 erombase = bcma_scan_read32(bus, 0, BCMA_CC_EROM);
1329 if (bus->hosttype == BCMA_HOSTTYPE_SOC) {
1330 eromptr = ioremap_nocache(erombase, BCMA_CORE_SIZE);
1331 --- a/drivers/bcma/sprom.c
1332 +++ b/drivers/bcma/sprom.c
1333 @@ -72,12 +72,12 @@ fail:
1335 **************************************************/
1337 -static void bcma_sprom_read(struct bcma_bus *bus, u16 offset, u16 *sprom)
1338 +static void bcma_sprom_read(struct bcma_bus *bus, u16 offset, u16 *sprom,
1342 - for (i = 0; i < SSB_SPROMSIZE_WORDS_R4; i++)
1343 - sprom[i] = bcma_read16(bus->drv_cc.core,
1344 - offset + (i * 2));
1345 + for (i = 0; i < words; i++)
1346 + sprom[i] = bcma_read16(bus->drv_cc.core, offset + (i * 2));
1349 /**************************************************
1350 @@ -124,29 +124,29 @@ static inline u8 bcma_crc8(u8 crc, u8 da
1351 return t[crc ^ data];
1354 -static u8 bcma_sprom_crc(const u16 *sprom)
1355 +static u8 bcma_sprom_crc(const u16 *sprom, size_t words)
1360 - for (word = 0; word < SSB_SPROMSIZE_WORDS_R4 - 1; word++) {
1361 + for (word = 0; word < words - 1; word++) {
1362 crc = bcma_crc8(crc, sprom[word] & 0x00FF);
1363 crc = bcma_crc8(crc, (sprom[word] & 0xFF00) >> 8);
1365 - crc = bcma_crc8(crc, sprom[SSB_SPROMSIZE_WORDS_R4 - 1] & 0x00FF);
1366 + crc = bcma_crc8(crc, sprom[words - 1] & 0x00FF);
1372 -static int bcma_sprom_check_crc(const u16 *sprom)
1373 +static int bcma_sprom_check_crc(const u16 *sprom, size_t words)
1379 - crc = bcma_sprom_crc(sprom);
1380 - tmp = sprom[SSB_SPROMSIZE_WORDS_R4 - 1] & SSB_SPROM_REVISION_CRC;
1381 + crc = bcma_sprom_crc(sprom, words);
1382 + tmp = sprom[words - 1] & SSB_SPROM_REVISION_CRC;
1383 expected_crc = tmp >> SSB_SPROM_REVISION_CRC_SHIFT;
1384 if (crc != expected_crc)
1386 @@ -154,21 +154,25 @@ static int bcma_sprom_check_crc(const u1
1390 -static int bcma_sprom_valid(const u16 *sprom)
1391 +static int bcma_sprom_valid(struct bcma_bus *bus, const u16 *sprom,
1397 - err = bcma_sprom_check_crc(sprom);
1398 + err = bcma_sprom_check_crc(sprom, words);
1402 - revision = sprom[SSB_SPROMSIZE_WORDS_R4 - 1] & SSB_SPROM_REVISION_REV;
1403 - if (revision != 8 && revision != 9) {
1404 + revision = sprom[words - 1] & SSB_SPROM_REVISION_REV;
1405 + if (revision != 8 && revision != 9 && revision != 10) {
1406 pr_err("Unsupported SPROM revision: %d\n", revision);
1410 + bus->sprom.revision = revision;
1411 + bcma_debug(bus, "Found SPROM revision %d\n", revision);
1416 @@ -197,6 +201,23 @@ static int bcma_sprom_valid(const u16 *s
1417 SPEX(_field[7], _offset + 14, _mask, _shift); \
1420 +static s8 sprom_extract_antgain(const u16 *in, u16 offset, u16 mask, u16 shift)
1425 + v = in[SPOFF(offset)];
1426 + gain = (v & mask) >> shift;
1427 + if (gain == 0xFF) {
1428 + gain = 8; /* If unset use 2dBm */
1430 + /* Q5.2 Fractional part is stored in 0xC0 */
1431 + gain = ((gain & 0xC0) >> 6) | ((gain & 0x3F) << 2);
1437 static void bcma_sprom_extract_r8(struct bcma_bus *bus, const u16 *sprom)
1440 @@ -208,9 +229,6 @@ static void bcma_sprom_extract_r8(struct
1441 BUILD_BUG_ON(ARRAY_SIZE(pwr_info_offset) !=
1442 ARRAY_SIZE(bus->sprom.core_pwr_info));
1444 - bus->sprom.revision = sprom[SSB_SPROMSIZE_WORDS_R4 - 1] &
1445 - SSB_SPROM_REVISION_REV;
1447 for (i = 0; i < 3; i++) {
1448 v = sprom[SPOFF(SSB_SPROM8_IL0MAC) + i];
1449 *(((__be16 *)bus->sprom.il0mac) + i) = cpu_to_be16(v);
1450 @@ -380,14 +398,22 @@ static void bcma_sprom_extract_r8(struct
1451 SPEX32(ofdm5ghpo, SSB_SPROM8_OFDM5GHPO, ~0, 0);
1453 /* Extract the antenna gain values. */
1454 - SPEX(antenna_gain.a0, SSB_SPROM8_AGAIN01,
1455 - SSB_SPROM8_AGAIN0, SSB_SPROM8_AGAIN0_SHIFT);
1456 - SPEX(antenna_gain.a1, SSB_SPROM8_AGAIN01,
1457 - SSB_SPROM8_AGAIN1, SSB_SPROM8_AGAIN1_SHIFT);
1458 - SPEX(antenna_gain.a2, SSB_SPROM8_AGAIN23,
1459 - SSB_SPROM8_AGAIN2, SSB_SPROM8_AGAIN2_SHIFT);
1460 - SPEX(antenna_gain.a3, SSB_SPROM8_AGAIN23,
1461 - SSB_SPROM8_AGAIN3, SSB_SPROM8_AGAIN3_SHIFT);
1462 + bus->sprom.antenna_gain.a0 = sprom_extract_antgain(sprom,
1463 + SSB_SPROM8_AGAIN01,
1464 + SSB_SPROM8_AGAIN0,
1465 + SSB_SPROM8_AGAIN0_SHIFT);
1466 + bus->sprom.antenna_gain.a1 = sprom_extract_antgain(sprom,
1467 + SSB_SPROM8_AGAIN01,
1468 + SSB_SPROM8_AGAIN1,
1469 + SSB_SPROM8_AGAIN1_SHIFT);
1470 + bus->sprom.antenna_gain.a2 = sprom_extract_antgain(sprom,
1471 + SSB_SPROM8_AGAIN23,
1472 + SSB_SPROM8_AGAIN2,
1473 + SSB_SPROM8_AGAIN2_SHIFT);
1474 + bus->sprom.antenna_gain.a3 = sprom_extract_antgain(sprom,
1475 + SSB_SPROM8_AGAIN23,
1476 + SSB_SPROM8_AGAIN3,
1477 + SSB_SPROM8_AGAIN3_SHIFT);
1479 SPEX(leddc_on_time, SSB_SPROM8_LEDDC, SSB_SPROM8_LEDDC_ON,
1480 SSB_SPROM8_LEDDC_ON_SHIFT);
1481 @@ -502,12 +528,14 @@ static bool bcma_sprom_onchip_available(
1482 case BCMA_CHIP_ID_BCM4331:
1483 present = chip_status & BCMA_CC_CHIPST_4331_OTP_PRESENT;
1486 + case BCMA_CHIP_ID_BCM43142:
1487 case BCMA_CHIP_ID_BCM43224:
1488 case BCMA_CHIP_ID_BCM43225:
1489 /* for these chips OTP is always available */
1492 + case BCMA_CHIP_ID_BCM43131:
1493 + case BCMA_CHIP_ID_BCM43217:
1494 case BCMA_CHIP_ID_BCM43227:
1495 case BCMA_CHIP_ID_BCM43228:
1496 case BCMA_CHIP_ID_BCM43428:
1497 @@ -550,7 +578,9 @@ int bcma_sprom_get(struct bcma_bus *bus)
1499 u16 offset = BCMA_CC_SPROM;
1502 + size_t sprom_sizes[] = { SSB_SPROMSIZE_WORDS_R4,
1503 + SSB_SPROMSIZE_WORDS_R10, };
1506 if (!bus->drv_cc.core)
1508 @@ -579,32 +609,37 @@ int bcma_sprom_get(struct bcma_bus *bus)
1512 - sprom = kcalloc(SSB_SPROMSIZE_WORDS_R4, sizeof(u16),
1517 if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4331 ||
1518 bus->chipinfo.id == BCMA_CHIP_ID_BCM43431)
1519 bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, false);
1521 bcma_debug(bus, "SPROM offset 0x%x\n", offset);
1522 - bcma_sprom_read(bus, offset, sprom);
1523 + for (i = 0; i < ARRAY_SIZE(sprom_sizes); i++) {
1524 + size_t words = sprom_sizes[i];
1526 + sprom = kcalloc(words, sizeof(u16), GFP_KERNEL);
1530 + bcma_sprom_read(bus, offset, sprom, words);
1531 + err = bcma_sprom_valid(bus, sprom, words);
1538 if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4331 ||
1539 bus->chipinfo.id == BCMA_CHIP_ID_BCM43431)
1540 bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, true);
1542 - err = bcma_sprom_valid(sprom);
1544 - bcma_warn(bus, "invalid sprom read from the PCIe card, try to use fallback sprom\n");
1545 + bcma_warn(bus, "Invalid SPROM read from the PCIe card, trying to use fallback SPROM\n");
1546 err = bcma_fill_sprom_with_fallback(bus, &bus->sprom);
1549 + bcma_sprom_extract_r8(bus, sprom);
1553 - bcma_sprom_extract_r8(bus, sprom);
1559 --- a/include/linux/bcma/bcma.h
1560 +++ b/include/linux/bcma/bcma.h
1563 #include <linux/bcma/bcma_driver_chipcommon.h>
1564 #include <linux/bcma/bcma_driver_pci.h>
1565 +#include <linux/bcma/bcma_driver_pcie2.h>
1566 #include <linux/bcma/bcma_driver_mips.h>
1567 #include <linux/bcma/bcma_driver_gmac_cmn.h>
1568 #include <linux/ssb/ssb.h> /* SPROM sharing */
1569 @@ -72,7 +73,19 @@ struct bcma_host_ops {
1570 /* Core-ID values. */
1571 #define BCMA_CORE_OOB_ROUTER 0x367 /* Out of band */
1572 #define BCMA_CORE_4706_CHIPCOMMON 0x500
1573 +#define BCMA_CORE_NS_PCIEG2 0x501
1574 +#define BCMA_CORE_NS_DMA 0x502
1575 +#define BCMA_CORE_NS_SDIO3 0x503
1576 +#define BCMA_CORE_NS_USB20 0x504
1577 +#define BCMA_CORE_NS_USB30 0x505
1578 +#define BCMA_CORE_NS_A9JTAG 0x506
1579 +#define BCMA_CORE_NS_DDR23 0x507
1580 +#define BCMA_CORE_NS_ROM 0x508
1581 +#define BCMA_CORE_NS_NAND 0x509
1582 +#define BCMA_CORE_NS_QSPI 0x50A
1583 +#define BCMA_CORE_NS_CHIPCOMMON_B 0x50B
1584 #define BCMA_CORE_4706_SOC_RAM 0x50E
1585 +#define BCMA_CORE_ARMCA9 0x510
1586 #define BCMA_CORE_4706_MAC_GBIT 0x52D
1587 #define BCMA_CORE_AMEMC 0x52E /* DDR1/2 memory controller core */
1588 #define BCMA_CORE_ALTA 0x534 /* I2S core */
1589 @@ -144,6 +157,10 @@ struct bcma_host_ops {
1591 /* Chip IDs of PCIe devices */
1592 #define BCMA_CHIP_ID_BCM4313 0x4313
1593 +#define BCMA_CHIP_ID_BCM43142 43142
1594 +#define BCMA_CHIP_ID_BCM43131 43131
1595 +#define BCMA_CHIP_ID_BCM43217 43217
1596 +#define BCMA_CHIP_ID_BCM43222 43222
1597 #define BCMA_CHIP_ID_BCM43224 43224
1598 #define BCMA_PKG_ID_BCM43224_FAB_CSM 0x8
1599 #define BCMA_PKG_ID_BCM43224_FAB_SMIC 0xa
1600 @@ -176,6 +193,11 @@ struct bcma_host_ops {
1601 #define BCMA_PKG_ID_BCM5357 11
1602 #define BCMA_CHIP_ID_BCM53572 53572
1603 #define BCMA_PKG_ID_BCM47188 9
1604 +#define BCMA_CHIP_ID_BCM4707 53010
1605 +#define BCMA_PKG_ID_BCM4707 1
1606 +#define BCMA_PKG_ID_BCM4708 2
1607 +#define BCMA_PKG_ID_BCM4709 0
1608 +#define BCMA_CHIP_ID_BCM53018 53018
1610 /* Board types (on PCI usually equals to the subsystem dev id) */
1612 @@ -245,7 +267,7 @@ struct bcma_device {
1620 void __iomem *io_addr;
1621 @@ -310,11 +332,12 @@ struct bcma_bus {
1622 struct bcma_device *mapped_core;
1623 struct list_head cores;
1628 struct bcma_drv_cc drv_cc;
1629 + struct bcma_drv_cc_b drv_cc_b;
1630 struct bcma_drv_pci drv_pci[2];
1631 + struct bcma_drv_pcie2 drv_pcie2;
1632 struct bcma_drv_mips drv_mips;
1633 struct bcma_drv_gmac_cmn drv_gmac_cmn;
1635 @@ -400,7 +423,14 @@ static inline void bcma_maskset16(struct
1636 bcma_write16(cc, offset, (bcma_read16(cc, offset) & mask) | set);
1639 -extern struct bcma_device *bcma_find_core(struct bcma_bus *bus, u16 coreid);
1640 +extern struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
1642 +static inline struct bcma_device *bcma_find_core(struct bcma_bus *bus,
1645 + return bcma_find_core_unit(bus, coreid, 0);
1648 extern bool bcma_core_is_enabled(struct bcma_device *core);
1649 extern void bcma_core_disable(struct bcma_device *core, u32 flags);
1650 extern int bcma_core_enable(struct bcma_device *core, u32 flags);
1651 --- a/include/linux/bcma/bcma_driver_chipcommon.h
1652 +++ b/include/linux/bcma/bcma_driver_chipcommon.h
1654 #define BCMA_CC_PMU_CAP 0x0604 /* PMU capabilities */
1655 #define BCMA_CC_PMU_CAP_REVISION 0x000000FF /* Revision mask */
1656 #define BCMA_CC_PMU_STAT 0x0608 /* PMU status */
1657 +#define BCMA_CC_PMU_STAT_EXT_LPO_AVAIL 0x00000100
1658 +#define BCMA_CC_PMU_STAT_WDRESET 0x00000080
1659 #define BCMA_CC_PMU_STAT_INTPEND 0x00000040 /* Interrupt pending */
1660 #define BCMA_CC_PMU_STAT_SBCLKST 0x00000030 /* Backplane clock status? */
1661 #define BCMA_CC_PMU_STAT_HAVEALP 0x00000008 /* ALP available */
1662 @@ -355,6 +357,11 @@
1663 #define BCMA_CC_REGCTL_DATA 0x065C
1664 #define BCMA_CC_PLLCTL_ADDR 0x0660
1665 #define BCMA_CC_PLLCTL_DATA 0x0664
1666 +#define BCMA_CC_PMU_STRAPOPT 0x0668 /* (corerev >= 28) */
1667 +#define BCMA_CC_PMU_XTAL_FREQ 0x066C /* (pmurev >= 10) */
1668 +#define BCMA_CC_PMU_XTAL_FREQ_ILPCTL_MASK 0x00001FFF
1669 +#define BCMA_CC_PMU_XTAL_FREQ_MEASURE_MASK 0x80000000
1670 +#define BCMA_CC_PMU_XTAL_FREQ_MEASURE_SHIFT 31
1671 #define BCMA_CC_SPROM 0x0800 /* SPROM beginning */
1672 /* NAND flash MLC controller registers (corerev >= 38) */
1673 #define BCMA_CC_NAND_REVISION 0x0C00
1674 @@ -435,6 +442,23 @@
1675 #define BCMA_CC_PMU6_4706_PROC_NDIV_MODE_MASK 0x00000007
1676 #define BCMA_CC_PMU6_4706_PROC_NDIV_MODE_SHIFT 0
1679 +#define BCMA_CC_PMU15_PLL_PLLCTL0 0
1680 +#define BCMA_CC_PMU15_PLL_PC0_CLKSEL_MASK 0x00000003
1681 +#define BCMA_CC_PMU15_PLL_PC0_CLKSEL_SHIFT 0
1682 +#define BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK 0x003FFFFC
1683 +#define BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT 2
1684 +#define BCMA_CC_PMU15_PLL_PC0_PRESCALE_MASK 0x00C00000
1685 +#define BCMA_CC_PMU15_PLL_PC0_PRESCALE_SHIFT 22
1686 +#define BCMA_CC_PMU15_PLL_PC0_KPCTRL_MASK 0x07000000
1687 +#define BCMA_CC_PMU15_PLL_PC0_KPCTRL_SHIFT 24
1688 +#define BCMA_CC_PMU15_PLL_PC0_FCNTCTRL_MASK 0x38000000
1689 +#define BCMA_CC_PMU15_PLL_PC0_FCNTCTRL_SHIFT 27
1690 +#define BCMA_CC_PMU15_PLL_PC0_FDCMODE_MASK 0x40000000
1691 +#define BCMA_CC_PMU15_PLL_PC0_FDCMODE_SHIFT 30
1692 +#define BCMA_CC_PMU15_PLL_PC0_CTRLBIAS_MASK 0x80000000
1693 +#define BCMA_CC_PMU15_PLL_PC0_CTRLBIAS_SHIFT 31
1695 /* ALP clock on pre-PMU chips */
1696 #define BCMA_CC_PMU_ALP_CLOCK 20000000
1697 /* HT clock for systems with PMU-enabled chipcommon */
1698 @@ -507,6 +531,37 @@
1699 #define BCMA_CHIPCTL_5357_I2S_PINS_ENABLE BIT(18)
1700 #define BCMA_CHIPCTL_5357_I2CSPI_PINS_ENABLE BIT(19)
1702 +#define BCMA_RES_4314_LPLDO_PU BIT(0)
1703 +#define BCMA_RES_4314_PMU_SLEEP_DIS BIT(1)
1704 +#define BCMA_RES_4314_PMU_BG_PU BIT(2)
1705 +#define BCMA_RES_4314_CBUCK_LPOM_PU BIT(3)
1706 +#define BCMA_RES_4314_CBUCK_PFM_PU BIT(4)
1707 +#define BCMA_RES_4314_CLDO_PU BIT(5)
1708 +#define BCMA_RES_4314_LPLDO2_LVM BIT(6)
1709 +#define BCMA_RES_4314_WL_PMU_PU BIT(7)
1710 +#define BCMA_RES_4314_LNLDO_PU BIT(8)
1711 +#define BCMA_RES_4314_LDO3P3_PU BIT(9)
1712 +#define BCMA_RES_4314_OTP_PU BIT(10)
1713 +#define BCMA_RES_4314_XTAL_PU BIT(11)
1714 +#define BCMA_RES_4314_WL_PWRSW_PU BIT(12)
1715 +#define BCMA_RES_4314_LQ_AVAIL BIT(13)
1716 +#define BCMA_RES_4314_LOGIC_RET BIT(14)
1717 +#define BCMA_RES_4314_MEM_SLEEP BIT(15)
1718 +#define BCMA_RES_4314_MACPHY_RET BIT(16)
1719 +#define BCMA_RES_4314_WL_CORE_READY BIT(17)
1720 +#define BCMA_RES_4314_ILP_REQ BIT(18)
1721 +#define BCMA_RES_4314_ALP_AVAIL BIT(19)
1722 +#define BCMA_RES_4314_MISC_PWRSW_PU BIT(20)
1723 +#define BCMA_RES_4314_SYNTH_PWRSW_PU BIT(21)
1724 +#define BCMA_RES_4314_RX_PWRSW_PU BIT(22)
1725 +#define BCMA_RES_4314_RADIO_PU BIT(23)
1726 +#define BCMA_RES_4314_VCO_LDO_PU BIT(24)
1727 +#define BCMA_RES_4314_AFE_LDO_PU BIT(25)
1728 +#define BCMA_RES_4314_RX_LDO_PU BIT(26)
1729 +#define BCMA_RES_4314_TX_LDO_PU BIT(27)
1730 +#define BCMA_RES_4314_HT_AVAIL BIT(28)
1731 +#define BCMA_RES_4314_MACPHY_CLK_AVAIL BIT(29)
1733 /* Data for the PMU, if available.
1734 * Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU)
1736 @@ -585,9 +640,16 @@ struct bcma_drv_cc {
1737 spinlock_t gpio_lock;
1738 #ifdef CONFIG_BCMA_DRIVER_GPIO
1739 struct gpio_chip gpio;
1740 + struct irq_domain *irq_domain;
1744 +struct bcma_drv_cc_b {
1745 + struct bcma_device *core;
1747 + void __iomem *mii;
1750 /* Register access */
1751 #define bcma_cc_read32(cc, offset) \
1752 bcma_read32((cc)->core, offset)
1753 @@ -643,4 +705,6 @@ extern void bcma_pmu_spuravoid_pllupdate
1755 extern u32 bcma_pmu_get_bus_clock(struct bcma_drv_cc *cc);
1757 +void bcma_chipco_b_mii_write(struct bcma_drv_cc_b *ccb, u32 offset, u32 value);
1759 #endif /* LINUX_BCMA_DRIVER_CC_H_ */
1760 --- a/include/linux/bcma/bcma_driver_pci.h
1761 +++ b/include/linux/bcma/bcma_driver_pci.h
1762 @@ -181,10 +181,31 @@ struct pci_dev;
1764 #define BCMA_CORE_PCI_CFG_DEVCTRL 0xd8
1766 +#define BCMA_CORE_PCI_
1768 +/* MDIO devices (SERDES modules) */
1769 +#define BCMA_CORE_PCI_MDIO_IEEE0 0x000
1770 +#define BCMA_CORE_PCI_MDIO_IEEE1 0x001
1771 +#define BCMA_CORE_PCI_MDIO_BLK0 0x800
1772 +#define BCMA_CORE_PCI_MDIO_BLK1 0x801
1773 +#define BCMA_CORE_PCI_MDIO_BLK1_MGMT0 0x16
1774 +#define BCMA_CORE_PCI_MDIO_BLK1_MGMT1 0x17
1775 +#define BCMA_CORE_PCI_MDIO_BLK1_MGMT2 0x18
1776 +#define BCMA_CORE_PCI_MDIO_BLK1_MGMT3 0x19
1777 +#define BCMA_CORE_PCI_MDIO_BLK1_MGMT4 0x1A
1778 +#define BCMA_CORE_PCI_MDIO_BLK2 0x802
1779 +#define BCMA_CORE_PCI_MDIO_BLK3 0x803
1780 +#define BCMA_CORE_PCI_MDIO_BLK4 0x804
1781 +#define BCMA_CORE_PCI_MDIO_TXPLL 0x808 /* TXPLL register block idx */
1782 +#define BCMA_CORE_PCI_MDIO_TXCTRL0 0x820
1783 +#define BCMA_CORE_PCI_MDIO_SERDESID 0x831
1784 +#define BCMA_CORE_PCI_MDIO_RXCTRL0 0x840
1786 /* PCIE Root Capability Register bits (Host mode only) */
1787 #define BCMA_CORE_PCI_RC_CRS_VISIBILITY 0x0001
1789 struct bcma_drv_pci;
1792 #ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
1793 struct bcma_drv_pci_host {
1794 @@ -219,7 +240,9 @@ struct bcma_drv_pci {
1795 extern void bcma_core_pci_init(struct bcma_drv_pci *pc);
1796 extern int bcma_core_pci_irq_ctl(struct bcma_drv_pci *pc,
1797 struct bcma_device *core, bool enable);
1798 -extern void bcma_core_pci_extend_L1timer(struct bcma_drv_pci *pc, bool extend);
1799 +extern void bcma_core_pci_up(struct bcma_bus *bus);
1800 +extern void bcma_core_pci_down(struct bcma_bus *bus);
1801 +extern void bcma_core_pci_power_save(struct bcma_bus *bus, bool up);
1803 extern int bcma_core_pci_pcibios_map_irq(const struct pci_dev *dev);
1804 extern int bcma_core_pci_plat_dev_init(struct pci_dev *dev);
1806 +++ b/include/linux/bcma/bcma_driver_pcie2.h
1808 +#ifndef LINUX_BCMA_DRIVER_PCIE2_H_
1809 +#define LINUX_BCMA_DRIVER_PCIE2_H_
1811 +#define BCMA_CORE_PCIE2_CLK_CONTROL 0x0000
1812 +#define PCIE2_CLKC_RST_OE 0x0001 /* When set, drives PCI_RESET out to pin */
1813 +#define PCIE2_CLKC_RST 0x0002 /* Value driven out to pin */
1814 +#define PCIE2_CLKC_SPERST 0x0004 /* SurvivePeRst */
1815 +#define PCIE2_CLKC_DISABLE_L1CLK_GATING 0x0010
1816 +#define PCIE2_CLKC_DLYPERST 0x0100 /* Delay PeRst to CoE Core */
1817 +#define PCIE2_CLKC_DISSPROMLD 0x0200 /* DisableSpromLoadOnPerst */
1818 +#define PCIE2_CLKC_WAKE_MODE_L2 0x1000 /* Wake on L2 */
1819 +#define BCMA_CORE_PCIE2_RC_PM_CONTROL 0x0004
1820 +#define BCMA_CORE_PCIE2_RC_PM_STATUS 0x0008
1821 +#define BCMA_CORE_PCIE2_EP_PM_CONTROL 0x000C
1822 +#define BCMA_CORE_PCIE2_EP_PM_STATUS 0x0010
1823 +#define BCMA_CORE_PCIE2_EP_LTR_CONTROL 0x0014
1824 +#define BCMA_CORE_PCIE2_EP_LTR_STATUS 0x0018
1825 +#define BCMA_CORE_PCIE2_EP_OBFF_STATUS 0x001C
1826 +#define BCMA_CORE_PCIE2_PCIE_ERR_STATUS 0x0020
1827 +#define BCMA_CORE_PCIE2_RC_AXI_CONFIG 0x0100
1828 +#define BCMA_CORE_PCIE2_EP_AXI_CONFIG 0x0104
1829 +#define BCMA_CORE_PCIE2_RXDEBUG_STATUS0 0x0108
1830 +#define BCMA_CORE_PCIE2_RXDEBUG_CONTROL0 0x010C
1831 +#define BCMA_CORE_PCIE2_CONFIGINDADDR 0x0120
1832 +#define BCMA_CORE_PCIE2_CONFIGINDDATA 0x0124
1833 +#define BCMA_CORE_PCIE2_MDIOCONTROL 0x0128
1834 +#define BCMA_CORE_PCIE2_MDIOWRDATA 0x012C
1835 +#define BCMA_CORE_PCIE2_MDIORDDATA 0x0130
1836 +#define BCMA_CORE_PCIE2_DATAINTF 0x0180
1837 +#define BCMA_CORE_PCIE2_D2H_INTRLAZY_0 0x0188
1838 +#define BCMA_CORE_PCIE2_H2D_INTRLAZY_0 0x018c
1839 +#define BCMA_CORE_PCIE2_H2D_INTSTAT_0 0x0190
1840 +#define BCMA_CORE_PCIE2_H2D_INTMASK_0 0x0194
1841 +#define BCMA_CORE_PCIE2_D2H_INTSTAT_0 0x0198
1842 +#define BCMA_CORE_PCIE2_D2H_INTMASK_0 0x019c
1843 +#define BCMA_CORE_PCIE2_LTR_STATE 0x01A0 /* Latency Tolerance Reporting */
1844 +#define PCIE2_LTR_ACTIVE 2
1845 +#define PCIE2_LTR_ACTIVE_IDLE 1
1846 +#define PCIE2_LTR_SLEEP 0
1847 +#define PCIE2_LTR_FINAL_MASK 0x300
1848 +#define PCIE2_LTR_FINAL_SHIFT 8
1849 +#define BCMA_CORE_PCIE2_PWR_INT_STATUS 0x01A4
1850 +#define BCMA_CORE_PCIE2_PWR_INT_MASK 0x01A8
1851 +#define BCMA_CORE_PCIE2_CFG_ADDR 0x01F8
1852 +#define BCMA_CORE_PCIE2_CFG_DATA 0x01FC
1853 +#define BCMA_CORE_PCIE2_SYS_EQ_PAGE 0x0200
1854 +#define BCMA_CORE_PCIE2_SYS_MSI_PAGE 0x0204
1855 +#define BCMA_CORE_PCIE2_SYS_MSI_INTREN 0x0208
1856 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL0 0x0210
1857 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL1 0x0214
1858 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL2 0x0218
1859 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL3 0x021C
1860 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL4 0x0220
1861 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL5 0x0224
1862 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD0 0x0250
1863 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL0 0x0254
1864 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD1 0x0258
1865 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL1 0x025C
1866 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD2 0x0260
1867 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL2 0x0264
1868 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD3 0x0268
1869 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL3 0x026C
1870 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD4 0x0270
1871 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL4 0x0274
1872 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD5 0x0278
1873 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL5 0x027C
1874 +#define BCMA_CORE_PCIE2_SYS_RC_INTX_EN 0x0330
1875 +#define BCMA_CORE_PCIE2_SYS_RC_INTX_CSR 0x0334
1876 +#define BCMA_CORE_PCIE2_SYS_MSI_REQ 0x0340
1877 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR_EN 0x0344
1878 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR_CSR 0x0348
1879 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR0 0x0350
1880 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR1 0x0354
1881 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR2 0x0358
1882 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR3 0x035C
1883 +#define BCMA_CORE_PCIE2_SYS_EP_INT_EN0 0x0360
1884 +#define BCMA_CORE_PCIE2_SYS_EP_INT_EN1 0x0364
1885 +#define BCMA_CORE_PCIE2_SYS_EP_INT_CSR0 0x0370
1886 +#define BCMA_CORE_PCIE2_SYS_EP_INT_CSR1 0x0374
1887 +#define BCMA_CORE_PCIE2_SPROM(wordoffset) (0x0800 + ((wordoffset) * 2))
1888 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_0 0x0C00
1889 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_1 0x0C04
1890 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_2 0x0C08
1891 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_3 0x0C0C
1892 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_4 0x0C10
1893 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_5 0x0C14
1894 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_6 0x0C18
1895 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_7 0x0C1C
1896 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_0 0x0C20
1897 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_1 0x0C24
1898 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_2 0x0C28
1899 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_3 0x0C2C
1900 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_4 0x0C30
1901 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_5 0x0C34
1902 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_6 0x0C38
1903 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_7 0x0C3C
1904 +#define BCMA_CORE_PCIE2_FUNC0_IMAP1 0x0C80
1905 +#define BCMA_CORE_PCIE2_FUNC1_IMAP1 0x0C88
1906 +#define BCMA_CORE_PCIE2_FUNC0_IMAP2 0x0CC0
1907 +#define BCMA_CORE_PCIE2_FUNC1_IMAP2 0x0CC8
1908 +#define BCMA_CORE_PCIE2_IARR0_LOWER 0x0D00
1909 +#define BCMA_CORE_PCIE2_IARR0_UPPER 0x0D04
1910 +#define BCMA_CORE_PCIE2_IARR1_LOWER 0x0D08
1911 +#define BCMA_CORE_PCIE2_IARR1_UPPER 0x0D0C
1912 +#define BCMA_CORE_PCIE2_IARR2_LOWER 0x0D10
1913 +#define BCMA_CORE_PCIE2_IARR2_UPPER 0x0D14
1914 +#define BCMA_CORE_PCIE2_OARR0 0x0D20
1915 +#define BCMA_CORE_PCIE2_OARR1 0x0D28
1916 +#define BCMA_CORE_PCIE2_OARR2 0x0D30
1917 +#define BCMA_CORE_PCIE2_OMAP0_LOWER 0x0D40
1918 +#define BCMA_CORE_PCIE2_OMAP0_UPPER 0x0D44
1919 +#define BCMA_CORE_PCIE2_OMAP1_LOWER 0x0D48
1920 +#define BCMA_CORE_PCIE2_OMAP1_UPPER 0x0D4C
1921 +#define BCMA_CORE_PCIE2_OMAP2_LOWER 0x0D50
1922 +#define BCMA_CORE_PCIE2_OMAP2_UPPER 0x0D54
1923 +#define BCMA_CORE_PCIE2_FUNC1_IARR1_SIZE 0x0D58
1924 +#define BCMA_CORE_PCIE2_FUNC1_IARR2_SIZE 0x0D5C
1925 +#define BCMA_CORE_PCIE2_MEM_CONTROL 0x0F00
1926 +#define BCMA_CORE_PCIE2_MEM_ECC_ERRLOG0 0x0F04
1927 +#define BCMA_CORE_PCIE2_MEM_ECC_ERRLOG1 0x0F08
1928 +#define BCMA_CORE_PCIE2_LINK_STATUS 0x0F0C
1929 +#define BCMA_CORE_PCIE2_STRAP_STATUS 0x0F10
1930 +#define BCMA_CORE_PCIE2_RESET_STATUS 0x0F14
1931 +#define BCMA_CORE_PCIE2_RESETEN_IN_LINKDOWN 0x0F18
1932 +#define BCMA_CORE_PCIE2_MISC_INTR_EN 0x0F1C
1933 +#define BCMA_CORE_PCIE2_TX_DEBUG_CFG 0x0F20
1934 +#define BCMA_CORE_PCIE2_MISC_CONFIG 0x0F24
1935 +#define BCMA_CORE_PCIE2_MISC_STATUS 0x0F28
1936 +#define BCMA_CORE_PCIE2_INTR_EN 0x0F30
1937 +#define BCMA_CORE_PCIE2_INTR_CLEAR 0x0F34
1938 +#define BCMA_CORE_PCIE2_INTR_STATUS 0x0F38
1940 +/* PCIE gen2 config regs */
1941 +#define PCIE2_INTSTATUS 0x090
1942 +#define PCIE2_INTMASK 0x094
1943 +#define PCIE2_SBMBX 0x098
1945 +#define PCIE2_PMCR_REFUP 0x1814 /* Trefup time */
1947 +#define PCIE2_CAP_DEVSTSCTRL2_OFFSET 0xD4
1948 +#define PCIE2_CAP_DEVSTSCTRL2_LTRENAB 0x400
1949 +#define PCIE2_PVT_REG_PM_CLK_PERIOD 0x184c
1951 +struct bcma_drv_pcie2 {
1952 + struct bcma_device *core;
1955 +#define pcie2_read16(pcie2, offset) bcma_read16((pcie2)->core, offset)
1956 +#define pcie2_read32(pcie2, offset) bcma_read32((pcie2)->core, offset)
1957 +#define pcie2_write16(pcie2, offset, val) bcma_write16((pcie2)->core, offset, val)
1958 +#define pcie2_write32(pcie2, offset, val) bcma_write32((pcie2)->core, offset, val)
1960 +#define pcie2_set32(pcie2, offset, set) bcma_set32((pcie2)->core, offset, set)
1961 +#define pcie2_mask32(pcie2, offset, mask) bcma_mask32((pcie2)->core, offset, mask)
1963 +void bcma_core_pcie2_init(struct bcma_drv_pcie2 *pcie2);
1965 +#endif /* LINUX_BCMA_DRIVER_PCIE2_H_ */
1966 --- a/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c
1967 +++ b/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c
1968 @@ -679,27 +679,6 @@ bool ai_clkctl_cc(struct si_pub *sih, en
1969 return mode == BCMA_CLKMODE_FAST;
1972 -void ai_pci_up(struct si_pub *sih)
1974 - struct si_info *sii;
1976 - sii = container_of(sih, struct si_info, pub);
1978 - if (sii->icbus->hosttype == BCMA_HOSTTYPE_PCI)
1979 - bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci[0], true);
1982 -/* Unconfigure and/or apply various WARs when going down */
1983 -void ai_pci_down(struct si_pub *sih)
1985 - struct si_info *sii;
1987 - sii = container_of(sih, struct si_info, pub);
1989 - if (sii->icbus->hosttype == BCMA_HOSTTYPE_PCI)
1990 - bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci[0], false);
1993 /* Enable BT-COEX & Ex-PA for 4313 */
1994 void ai_epa_4313war(struct si_pub *sih)
1996 --- a/drivers/net/wireless/brcm80211/brcmsmac/aiutils.h
1997 +++ b/drivers/net/wireless/brcm80211/brcmsmac/aiutils.h
1998 @@ -183,9 +183,6 @@ extern u16 ai_clkctl_fast_pwrup_delay(st
1999 extern bool ai_clkctl_cc(struct si_pub *sih, enum bcma_clkmode mode);
2000 extern bool ai_deviceremoved(struct si_pub *sih);
2002 -extern void ai_pci_down(struct si_pub *sih);
2003 -extern void ai_pci_up(struct si_pub *sih);
2005 /* Enable Ex-PA for 4313 */
2006 extern void ai_epa_4313war(struct si_pub *sih);
2008 --- a/drivers/net/wireless/brcm80211/brcmsmac/main.c
2009 +++ b/drivers/net/wireless/brcm80211/brcmsmac/main.c
2010 @@ -4667,7 +4667,7 @@ static int brcms_b_attach(struct brcms_c
2011 brcms_c_coredisable(wlc_hw);
2013 /* Match driver "down" state */
2014 - ai_pci_down(wlc_hw->sih);
2015 + bcma_core_pci_down(wlc_hw->d11core->bus);
2017 /* turn off pll and xtal to match driver "down" state */
2018 brcms_b_xtal(wlc_hw, OFF);
2019 @@ -5010,12 +5010,12 @@ static int brcms_b_up_prep(struct brcms_
2021 if (brcms_b_radio_read_hwdisabled(wlc_hw)) {
2022 /* put SB PCI in down state again */
2023 - ai_pci_down(wlc_hw->sih);
2024 + bcma_core_pci_down(wlc_hw->d11core->bus);
2025 brcms_b_xtal(wlc_hw, OFF);
2029 - ai_pci_up(wlc_hw->sih);
2030 + bcma_core_pci_up(wlc_hw->d11core->bus);
2032 /* reset the d11 core */
2033 brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS);
2034 @@ -5212,7 +5212,7 @@ static int brcms_b_down_finish(struct br
2036 /* turn off primary xtal and pll */
2037 if (!wlc_hw->noreset) {
2038 - ai_pci_down(wlc_hw->sih);
2039 + bcma_core_pci_down(wlc_hw->d11core->bus);
2040 brcms_b_xtal(wlc_hw, OFF);
2043 --- a/drivers/bcma/driver_mips.c
2044 +++ b/drivers/bcma/driver_mips.c
2046 #include <linux/serial_reg.h>
2047 #include <linux/time.h>
2049 +enum bcma_boot_dev {
2050 + BCMA_BOOT_DEV_UNK = 0,
2051 + BCMA_BOOT_DEV_ROM,
2052 + BCMA_BOOT_DEV_PARALLEL,
2053 + BCMA_BOOT_DEV_SERIAL,
2054 + BCMA_BOOT_DEV_NAND,
2057 static const char * const part_probes[] = { "bcm47xxpart", NULL };
2059 static struct physmap_flash_data bcma_pflash_data = {
2060 @@ -229,11 +237,51 @@ u32 bcma_cpu_clock(struct bcma_drv_mips
2062 EXPORT_SYMBOL(bcma_cpu_clock);
2064 +static enum bcma_boot_dev bcma_boot_dev(struct bcma_bus *bus)
2066 + struct bcma_drv_cc *cc = &bus->drv_cc;
2067 + u8 cc_rev = cc->core->id.rev;
2069 + if (cc_rev == 42) {
2070 + struct bcma_device *core;
2072 + core = bcma_find_core(bus, BCMA_CORE_NS_ROM);
2074 + switch (bcma_aread32(core, BCMA_IOST) &
2075 + BCMA_NS_ROM_IOST_BOOT_DEV_MASK) {
2076 + case BCMA_NS_ROM_IOST_BOOT_DEV_NOR:
2077 + return BCMA_BOOT_DEV_SERIAL;
2078 + case BCMA_NS_ROM_IOST_BOOT_DEV_NAND:
2079 + return BCMA_BOOT_DEV_NAND;
2080 + case BCMA_NS_ROM_IOST_BOOT_DEV_ROM:
2082 + return BCMA_BOOT_DEV_ROM;
2086 + if (cc_rev == 38) {
2087 + if (cc->status & BCMA_CC_CHIPST_5357_NAND_BOOT)
2088 + return BCMA_BOOT_DEV_NAND;
2089 + else if (cc->status & BIT(5))
2090 + return BCMA_BOOT_DEV_ROM;
2093 + if ((cc->capabilities & BCMA_CC_CAP_FLASHT) ==
2094 + BCMA_CC_FLASHT_PARA)
2095 + return BCMA_BOOT_DEV_PARALLEL;
2097 + return BCMA_BOOT_DEV_SERIAL;
2100 + return BCMA_BOOT_DEV_SERIAL;
2103 static void bcma_core_mips_flash_detect(struct bcma_drv_mips *mcore)
2105 struct bcma_bus *bus = mcore->core->bus;
2106 struct bcma_drv_cc *cc = &bus->drv_cc;
2107 struct bcma_pflash *pflash = &cc->pflash;
2108 + enum bcma_boot_dev boot_dev;
2110 switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {
2111 case BCMA_CC_FLASHT_STSER:
2112 @@ -269,6 +317,20 @@ static void bcma_core_mips_flash_detect(
2113 bcma_nflash_init(cc);
2117 + /* Determine flash type this SoC boots from */
2118 + boot_dev = bcma_boot_dev(bus);
2119 + switch (boot_dev) {
2120 + case BCMA_BOOT_DEV_PARALLEL:
2121 + case BCMA_BOOT_DEV_SERIAL:
2122 + /* TODO: Init NVRAM using BCMA_SOC_FLASH2 window */
2124 + case BCMA_BOOT_DEV_NAND:
2125 + /* TODO: Init NVRAM using BCMA_SOC_FLASH1 window */
2132 void bcma_core_mips_early_init(struct bcma_drv_mips *mcore)
2133 --- a/drivers/bcma/host_soc.c
2134 +++ b/drivers/bcma/host_soc.c
2135 @@ -134,12 +134,16 @@ static void bcma_host_soc_block_write(st
2137 static u32 bcma_host_soc_aread32(struct bcma_device *core, u16 offset)
2139 + if (WARN_ONCE(!core->io_wrap, "Accessed core has no wrapper/agent\n"))
2141 return readl(core->io_wrap + offset);
2144 static void bcma_host_soc_awrite32(struct bcma_device *core, u16 offset,
2147 + if (WARN_ONCE(!core->io_wrap, "Accessed core has no wrapper/agent\n"))
2149 writel(value, core->io_wrap + offset);
2152 @@ -161,7 +165,6 @@ static const struct bcma_host_ops bcma_h
2153 int __init bcma_host_soc_register(struct bcma_soc *soc)
2155 struct bcma_bus *bus = &soc->bus;
2158 /* iomap only first core. We have to read some register on this core
2160 @@ -174,7 +177,18 @@ int __init bcma_host_soc_register(struct
2161 bus->hosttype = BCMA_HOSTTYPE_SOC;
2162 bus->ops = &bcma_host_soc_ops;
2165 + /* Initialize struct, detect chip */
2166 + bcma_init_bus(bus);
2171 +int __init bcma_host_soc_init(struct bcma_soc *soc)
2173 + struct bcma_bus *bus = &soc->bus;
2176 + /* Scan bus and initialize it */
2177 err = bcma_bus_early_register(bus, &soc->core_cc, &soc->core_mips);
2180 --- a/include/linux/bcma/bcma_regs.h
2181 +++ b/include/linux/bcma/bcma_regs.h
2183 #define BCMA_RESET_CTL_RESET 0x0001
2184 #define BCMA_RESET_ST 0x0804
2186 +#define BCMA_NS_ROM_IOST_BOOT_DEV_MASK 0x0003
2187 +#define BCMA_NS_ROM_IOST_BOOT_DEV_NOR 0x0000
2188 +#define BCMA_NS_ROM_IOST_BOOT_DEV_NAND 0x0001
2189 +#define BCMA_NS_ROM_IOST_BOOT_DEV_ROM 0x0002
2191 /* BCMA PCI config space registers. */
2192 #define BCMA_PCI_PMCSR 0x44
2193 #define BCMA_PCI_PE 0x100
2194 --- a/drivers/usb/host/bcma-hcd.c
2195 +++ b/drivers/usb/host/bcma-hcd.c
2196 @@ -238,7 +238,7 @@ static int bcma_hcd_probe(struct bcma_de
2197 bcma_hcd_init_chip(dev);
2199 /* In AI chips EHCI is addrspace 0, OHCI is 1 */
2200 - ohci_addr = dev->addr1;
2201 + ohci_addr = dev->addr_s[0];
2202 if ((chipinfo->id == 0x5357 || chipinfo->id == 0x4749)
2203 && chipinfo->rev == 0)
2204 ohci_addr = 0x18009000;
2206 +++ b/drivers/bcma/driver_chipcommon_b.c
2209 + * Broadcom specific AMBA
2210 + * ChipCommon B Unit driver
2212 + * Copyright 2014, Hauke Mehrtens <hauke@hauke-m.de>
2214 + * Licensed under the GNU/GPL. See COPYING for details.
2217 +#include "bcma_private.h"
2218 +#include <linux/export.h>
2219 +#include <linux/bcma/bcma.h>
2221 +static bool bcma_wait_reg(struct bcma_bus *bus, void __iomem *addr, u32 mask,
2222 + u32 value, int timeout)
2224 + unsigned long deadline = jiffies + timeout;
2228 + val = readl(addr);
2229 + if ((val & mask) == value)
2233 + } while (!time_after_eq(jiffies, deadline));
2235 + bcma_err(bus, "Timeout waiting for register %p\n", addr);
2240 +void bcma_chipco_b_mii_write(struct bcma_drv_cc_b *ccb, u32 offset, u32 value)
2242 + struct bcma_bus *bus = ccb->core->bus;
2244 + writel(offset, ccb->mii + 0x00);
2245 + bcma_wait_reg(bus, ccb->mii + 0x00, 0x0100, 0x0000, 100);
2246 + writel(value, ccb->mii + 0x04);
2247 + bcma_wait_reg(bus, ccb->mii + 0x00, 0x0100, 0x0000, 100);
2249 +EXPORT_SYMBOL_GPL(bcma_chipco_b_mii_write);
2251 +int bcma_core_chipcommon_b_init(struct bcma_drv_cc_b *ccb)
2253 + if (ccb->setup_done)
2256 + ccb->setup_done = 1;
2257 + ccb->mii = ioremap_nocache(ccb->core->addr_s[1], BCMA_CORE_SIZE);
2264 +void bcma_core_chipcommon_b_free(struct bcma_drv_cc_b *ccb)
2267 + iounmap(ccb->mii);