target/linux/generic/patches-3.10/774-bgmac-add-some-workaround-for-rev-4.patch

   1 From adada33c4ee27efdec0b08e43768a68285a5710d Mon Sep 17 00:00:00 2001
   2 From: Hauke Mehrtens <hauke@hauke-m.de>
   3 Date: Thu, 2 Jan 2014 19:49:56 +0100
   4 Subject: [PATCH 2/5] bgmac: initialize the DMA controller of core rev >= 4
   5
   6 The DMA controller used in the device supported by GMAC with core rev
   7 >= 4 has some new options which are now set to the default values used
   8 in the Broadcom SDK.
   9
  10 Subject: [PATCH 3/5] bgmac: add support for new BGMAC_CMDCFG_SR position on
  11  core rev >= 4
  12
  13 The BGMAC_CMDCFG_SR register is at a different position on core rev >= 4
  14
  15 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
  16
  17 --- a/drivers/net/ethernet/broadcom/bgmac.c
  18 +++ b/drivers/net/ethernet/broadcom/bgmac.c
  19 @@ -97,6 +97,19 @@ static void bgmac_dma_tx_enable(struct b
  20         u32 ctl;
  21
  22         ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL);
  23 +       if (bgmac->core->id.rev >= 4) {
  24 +               ctl &= ~BGMAC_DMA_TX_BL_MASK;
  25 +               ctl |= BGMAC_DMA_TX_BL_128 << BGMAC_DMA_TX_BL_SHIFT;
  26 +
  27 +               ctl &= ~BGMAC_DMA_TX_MR_MASK;
  28 +               ctl |= BGMAC_DMA_TX_MR_2 << BGMAC_DMA_TX_MR_SHIFT;
  29 +
  30 +               ctl &= ~BGMAC_DMA_TX_PC_MASK;
  31 +               ctl |= BGMAC_DMA_TX_PC_16 << BGMAC_DMA_TX_PC_SHIFT;
  32 +
  33 +               ctl &= ~BGMAC_DMA_TX_PT_MASK;
  34 +               ctl |= BGMAC_DMA_TX_PT_8 << BGMAC_DMA_TX_PT_SHIFT;
  35 +       }
  36         ctl |= BGMAC_DMA_TX_ENABLE;
  37         ctl |= BGMAC_DMA_TX_PARITY_DISABLE;
  38         bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, ctl);
  39 @@ -241,6 +254,16 @@ static void bgmac_dma_rx_enable(struct b
  40         u32 ctl;
  41
  42         ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL);
  43 +       if (bgmac->core->id.rev >= 4) {
  44 +               ctl &= ~BGMAC_DMA_RX_BL_MASK;
  45 +               ctl |= BGMAC_DMA_RX_BL_128 << BGMAC_DMA_RX_BL_SHIFT;
  46 +
  47 +               ctl &= ~BGMAC_DMA_RX_PC_MASK;
  48 +               ctl |= BGMAC_DMA_RX_PC_8 << BGMAC_DMA_RX_PC_SHIFT;
  49 +
  50 +               ctl &= ~BGMAC_DMA_RX_PT_MASK;
  51 +               ctl |= BGMAC_DMA_RX_PT_1 << BGMAC_DMA_RX_PT_SHIFT;
  52 +       }
  53         ctl &= BGMAC_DMA_RX_ADDREXT_MASK;
  54         ctl |= BGMAC_DMA_RX_ENABLE;
  55         ctl |= BGMAC_DMA_RX_PARITY_DISABLE;
  56 @@ -746,13 +769,13 @@ static void bgmac_cmdcfg_maskset(struct
  57         u32 cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG);
  58         u32 new_val = (cmdcfg & mask) | set;
  59
  60 -       bgmac_set(bgmac, BGMAC_CMDCFG, BGMAC_CMDCFG_SR);
  61 +       bgmac_set(bgmac, BGMAC_CMDCFG, BGMAC_CMDCFG_SR(bgmac->core->id.rev));
  62         udelay(2);
  63
  64         if (new_val != cmdcfg || force)
  65                 bgmac_write(bgmac, BGMAC_CMDCFG, new_val);
  66
  67 -       bgmac_mask(bgmac, BGMAC_CMDCFG, ~BGMAC_CMDCFG_SR);
  68 +       bgmac_mask(bgmac, BGMAC_CMDCFG, ~BGMAC_CMDCFG_SR(bgmac->core->id.rev));
  69         udelay(2);
  70  }
  71
  72 @@ -977,7 +1000,7 @@ static void bgmac_chip_reset(struct bgma
  73                              BGMAC_CMDCFG_PROM |
  74                              BGMAC_CMDCFG_NLC |
  75                              BGMAC_CMDCFG_CFE |
  76 -                            BGMAC_CMDCFG_SR,
  77 +                            BGMAC_CMDCFG_SR(core->id.rev),
  78                              false);
  79         bgmac->mac_speed = SPEED_UNKNOWN;
  80         bgmac->mac_duplex = DUPLEX_UNKNOWN;
  81 @@ -1020,7 +1043,7 @@ static void bgmac_enable(struct bgmac *b
  82
  83         cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG);
  84         bgmac_cmdcfg_maskset(bgmac, ~(BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE),
  85 -                            BGMAC_CMDCFG_SR, true);
  86 +                            BGMAC_CMDCFG_SR(bgmac->core->id.rev), true);
  87         udelay(2);
  88         cmdcfg |= BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE;
  89         bgmac_write(bgmac, BGMAC_CMDCFG, cmdcfg);
  90 --- a/drivers/net/ethernet/broadcom/bgmac.h
  91 +++ b/drivers/net/ethernet/broadcom/bgmac.h
  92 @@ -198,7 +198,9 @@
  93  #define  BGMAC_CMDCFG_TAI                      0x00000200
  94  #define  BGMAC_CMDCFG_HD                       0x00000400      /* Set if in half duplex mode */
  95  #define  BGMAC_CMDCFG_HD_SHIFT                 10
  96 -#define  BGMAC_CMDCFG_SR                       0x00000800      /* Set to reset mode */
  97 +#define  BGMAC_CMDCFG_SR_REV0                  0x00000800      /* Set to reset mode, for other revs */
  98 +#define  BGMAC_CMDCFG_SR_REV4                  0x00002000      /* Set to reset mode, only for core rev 4 */
  99 +#define  BGMAC_CMDCFG_SR(rev)  ((rev == 4) ? BGMAC_CMDCFG_SR_REV4 : BGMAC_CMDCFG_SR_REV0)
 100  #define  BGMAC_CMDCFG_ML                       0x00008000      /* Set to activate mac loopback mode */
 101  #define  BGMAC_CMDCFG_AE                       0x00400000
 102  #define  BGMAC_CMDCFG_CFE                      0x00800000
 103 @@ -238,9 +240,34 @@
 104  #define  BGMAC_DMA_TX_SUSPEND                  0x00000002
 105  #define  BGMAC_DMA_TX_LOOPBACK                 0x00000004
 106  #define  BGMAC_DMA_TX_FLUSH                    0x00000010
 107 +#define  BGMAC_DMA_TX_MR_MASK                  0x000000C0      /* Multiple outstanding reads */
 108 +#define  BGMAC_DMA_TX_MR_SHIFT                 6
 109 +#define   BGMAC_DMA_TX_MR_1                    0
 110 +#define   BGMAC_DMA_TX_MR_2                    1
 111  #define  BGMAC_DMA_TX_PARITY_DISABLE           0x00000800
 112  #define  BGMAC_DMA_TX_ADDREXT_MASK             0x00030000
 113  #define  BGMAC_DMA_TX_ADDREXT_SHIFT            16
 114 +#define  BGMAC_DMA_TX_BL_MASK                  0x001C0000      /* BurstLen bits */
 115 +#define  BGMAC_DMA_TX_BL_SHIFT                 18
 116 +#define   BGMAC_DMA_TX_BL_16                   0
 117 +#define   BGMAC_DMA_TX_BL_32                   1
 118 +#define   BGMAC_DMA_TX_BL_64                   2
 119 +#define   BGMAC_DMA_TX_BL_128                  3
 120 +#define   BGMAC_DMA_TX_BL_256                  4
 121 +#define   BGMAC_DMA_TX_BL_512                  5
 122 +#define   BGMAC_DMA_TX_BL_1024                 6
 123 +#define  BGMAC_DMA_TX_PC_MASK                  0x00E00000      /* Prefetch control */
 124 +#define  BGMAC_DMA_TX_PC_SHIFT                 21
 125 +#define   BGMAC_DMA_TX_PC_0                    0
 126 +#define   BGMAC_DMA_TX_PC_4                    1
 127 +#define   BGMAC_DMA_TX_PC_8                    2
 128 +#define   BGMAC_DMA_TX_PC_16                   3
 129 +#define  BGMAC_DMA_TX_PT_MASK                  0x03000000      /* Prefetch threshold */
 130 +#define  BGMAC_DMA_TX_PT_SHIFT                 24
 131 +#define   BGMAC_DMA_TX_PT_1                    0
 132 +#define   BGMAC_DMA_TX_PT_2                    1
 133 +#define   BGMAC_DMA_TX_PT_4                    2
 134 +#define   BGMAC_DMA_TX_PT_8                    3
 135  #define BGMAC_DMA_TX_INDEX                     0x04
 136  #define BGMAC_DMA_TX_RINGLO                    0x08
 137  #define BGMAC_DMA_TX_RINGHI                    0x0C
 138 @@ -268,8 +295,33 @@
 139  #define  BGMAC_DMA_RX_DIRECT_FIFO              0x00000100
 140  #define  BGMAC_DMA_RX_OVERFLOW_CONT            0x00000400
 141  #define  BGMAC_DMA_RX_PARITY_DISABLE           0x00000800
 142 +#define  BGMAC_DMA_RX_MR_MASK                  0x000000C0      /* Multiple outstanding reads */
 143 +#define  BGMAC_DMA_RX_MR_SHIFT                 6
 144 +#define   BGMAC_DMA_TX_MR_1                    0
 145 +#define   BGMAC_DMA_TX_MR_2                    1
 146  #define  BGMAC_DMA_RX_ADDREXT_MASK             0x00030000
 147  #define  BGMAC_DMA_RX_ADDREXT_SHIFT            16
 148 +#define  BGMAC_DMA_RX_BL_MASK                  0x001C0000      /* BurstLen bits */
 149 +#define  BGMAC_DMA_RX_BL_SHIFT                 18
 150 +#define   BGMAC_DMA_RX_BL_16                   0
 151 +#define   BGMAC_DMA_RX_BL_32                   1
 152 +#define   BGMAC_DMA_RX_BL_64                   2
 153 +#define   BGMAC_DMA_RX_BL_128                  3
 154 +#define   BGMAC_DMA_RX_BL_256                  4
 155 +#define   BGMAC_DMA_RX_BL_512                  5
 156 +#define   BGMAC_DMA_RX_BL_1024                 6
 157 +#define  BGMAC_DMA_RX_PC_MASK                  0x00E00000      /* Prefetch control */
 158 +#define  BGMAC_DMA_RX_PC_SHIFT                 21
 159 +#define   BGMAC_DMA_RX_PC_0                    0
 160 +#define   BGMAC_DMA_RX_PC_4                    1
 161 +#define   BGMAC_DMA_RX_PC_8                    2
 162 +#define   BGMAC_DMA_RX_PC_16                   3
 163 +#define  BGMAC_DMA_RX_PT_MASK                  0x03000000      /* Prefetch threshold */
 164 +#define  BGMAC_DMA_RX_PT_SHIFT                 24
 165 +#define   BGMAC_DMA_RX_PT_1                    0
 166 +#define   BGMAC_DMA_RX_PT_2                    1
 167 +#define   BGMAC_DMA_RX_PT_4                    2
 168 +#define   BGMAC_DMA_RX_PT_8                    3
 169  #define BGMAC_DMA_RX_INDEX                     0x24
 170  #define BGMAC_DMA_RX_RINGLO                    0x28
 171  #define BGMAC_DMA_RX_RINGHI                    0x2C