kernel: backport upstream commit to fix MIPS cache shift with secondary cache enabled
[openwrt/staging/chunkeey.git] / target / linux / generic / patches-3.14 / 010-MIPS-Allow-MIPS_CPU_SCACHE-to-be-used-with-different.patch
1 From a7ef1eaddbf4bd50bfee92d9dfbecadc61467bbf Mon Sep 17 00:00:00 2001
2 From: Kevin Cernekee <cernekee@gmail.com>
3 Date: Mon, 20 Oct 2014 21:27:57 -0700
4 Subject: [PATCH] MIPS: Allow MIPS_CPU_SCACHE to be used with different line
5 sizes
6
7 CONFIG_MIPS_CPU_SCACHE determines whether to build sc-mips.c. However,
8 it is currently hardwired to use an L1_SHIFT of 6 (64 bytes). Move the
9 L1_SHIFT selection into the CPU or SoC section so that other SoCs can
10 select different values.
11
12 Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
13 Cc: f.fainelli@gmail.com
14 Cc: mbizon@freebox.fr
15 Cc: jogo@openwrt.org
16 Cc: jfraser@broadcom.com
17 Cc: linux-mips@linux-mips.org
18 Cc: devicetree@vger.kernel.org
19 Patchwork: https://patchwork.linux-mips.org/patch/8162/
20 Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
21 ---
22 arch/mips/Kconfig | 2 +-
23 1 file changed, 1 insertion(+), 1 deletion(-)
24
25 --- a/arch/mips/Kconfig
26 +++ b/arch/mips/Kconfig
27 @@ -315,6 +315,7 @@ config MIPS_MALTA
28 select I8259
29 select MIPS_BONITO64
30 select MIPS_CPU_SCACHE
31 + select MIPS_L1_CACHE_SHIFT_6
32 select PCI_GT64XXX_PCI0
33 select MIPS_MSC
34 select SWAP_IO_SPACE
35 @@ -1820,7 +1821,6 @@ config IP22_CPU_SCACHE
36 config MIPS_CPU_SCACHE
37 bool
38 select BOARD_SCACHE
39 - select MIPS_L1_CACHE_SHIFT_6
40
41 config R5000_CPU_SCACHE
42 bool