target/linux/generic/patches-3.2/309-optimize_mips_memcpy_memset_cache.patch

   1 --- a/arch/mips/lib/memset.S
   2 +++ b/arch/mips/lib/memset.S
   3 @@ -19,6 +19,8 @@
   4  #define LONG_S_R sdr
   5  #endif
   6
   7 +#include "prefetch.h"
   8 +
   9  #define EX(insn,reg,addr,handler)                      \
  10  9:     insn    reg, addr;                              \
  11         .section __ex_table,"a";                        \
  12 @@ -75,6 +77,8 @@ FEXPORT(__bzero)
  13         bnez            t0, .Lsmall_memset
  14          andi           t0, a0, LONGMASK        /* aligned? */
  15
  16 +       prefetch_store a0, a2, t2, t3, t4
  17 +
  18  #ifndef CONFIG_CPU_DADDI_WORKAROUNDS
  19         beqz            t0, 1f
  20          PTR_SUBU       t0, LONGSIZE            /* alignment in bytes */
  21 --- a/arch/mips/include/asm/processor.h
  22 +++ b/arch/mips/include/asm/processor.h
  23 @@ -354,7 +354,7 @@ unsigned long get_wchan(struct task_stru
  24  #define prefetch(x) __builtin_prefetch((x), 0, 1)
  25
  26  #define ARCH_HAS_PREFETCHW
  27 -#define prefetchw(x) __builtin_prefetch((x), 1, 1)
  28 +#define prefetchw(x) do {} while (0)
  29
  30  #endif
  31
  32 --- /dev/null
  33 +++ b/arch/mips/lib/prefetch.h
  34 @@ -0,0 +1,35 @@
  35 +/*
  36 + * This file is subject to the terms and conditions of the GNU General Public
  37 + * License.  See the file "COPYING" in the main directory of this archive
  38 + * for more details.
  39 + *
  40 + * Copyright (C) 2012  Felix Fietkau <nbd@openwrt.org>
  41 + */
  42 +
  43 +.macro prefetch_store  dst, size, temp1, temp2, temp3
  44 +#ifdef CONFIG_CPU_MIPS32
  45 +       li              \temp1, ((1 << CONFIG_MIPS_L1_CACHE_SHIFT) - 1)
  46 +       nor             \temp1, \temp1, \temp1
  47 +
  48 +       and             \temp2, \size, \temp1
  49 +       beqz            \temp2, 2f
  50 +        nop
  51 +
  52 +       move            \temp2, \dst
  53 +       PTR_ADDIU       \temp2, ((1 << CONFIG_MIPS_L1_CACHE_SHIFT) - 1)
  54 +       and             \temp2, \temp2, \temp1
  55 +
  56 +       move            \temp3, \dst
  57 +       PTR_ADDU        \temp3, \size
  58 +       and             \temp3, \temp3, \temp1
  59 +
  60 +1:     beq             \temp2, \temp3, 2f
  61 +        nop
  62 +
  63 +       pref            30, 0(\temp2)
  64 +
  65 +       b               1b
  66 +         PTR_ADDIU     \temp2, (1 << CONFIG_MIPS_L1_CACHE_SHIFT)
  67 +2:
  68 +#endif
  69 +.endm
  70 --- a/arch/mips/lib/memcpy.S
  71 +++ b/arch/mips/lib/memcpy.S
  72 @@ -182,6 +182,8 @@
  73         .set    at=v1
  74  #endif
  75
  76 +#include "prefetch.h"
  77 +
  78  /*
  79   * A combined memcpy/__copy_user
  80   * __copy_user sets len to 0 for success; else to an upper bound of
  81 @@ -199,6 +201,8 @@ FEXPORT(__copy_user)
  82          */
  83  #define rem t8
  84
  85 +       prefetch_store a0, a2, t0, t1, t2
  86 +
  87         R10KCBARRIER(0(ra))
  88         /*
  89          * The "issue break"s below are very approximate.
  90 --- a/arch/mips/lib/memcpy-inatomic.S
  91 +++ b/arch/mips/lib/memcpy-inatomic.S
  92 @@ -182,6 +182,8 @@
  93         .set    at=v1
  94  #endif
  95
  96 +#include "prefetch.h"
  97 +
  98  /*
  99   * A combined memcpy/__copy_user
 100   * __copy_user sets len to 0 for success; else to an upper bound of
 101 @@ -196,6 +198,8 @@ LEAF(__copy_user_inatomic)
 102          */
 103  #define rem t8
 104
 105 +       prefetch_store dst, len, t0, t1, t2
 106 +
 107         /*
 108          * The "issue break"s below are very approximate.
 109          * Issue delays for dcache fills will perturb the schedule, as will