projects / openwrt / staging / dedeckeh.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
kernel: update linux 3.6 to 3.6.5
[openwrt/staging/dedeckeh.git] / target / linux / generic / patches-3.6 / 025-bcma_backport.patch
1 --- a/drivers/bcma/Kconfig
2 +++ b/drivers/bcma/Kconfig
3 @@ -48,12 +48,12 @@ config BCMA_DRIVER_MIPS
4
5 config BCMA_SFLASH
6 bool
7 - depends on BCMA_DRIVER_MIPS && BROKEN
8 + depends on BCMA_DRIVER_MIPS
9 default y
10
11 config BCMA_NFLASH
12 bool
13 - depends on BCMA_DRIVER_MIPS && BROKEN
14 + depends on BCMA_DRIVER_MIPS
15 default y
16
17 config BCMA_DRIVER_GMAC_CMN
18 --- a/drivers/bcma/bcma_private.h
19 +++ b/drivers/bcma/bcma_private.h
20 @@ -54,6 +54,7 @@ u32 bcma_pmu_get_clockcpu(struct bcma_dr
21 #ifdef CONFIG_BCMA_SFLASH
22 /* driver_chipcommon_sflash.c */
23 int bcma_sflash_init(struct bcma_drv_cc *cc);
24 +extern struct platform_device bcma_sflash_dev;
25 #else
26 static inline int bcma_sflash_init(struct bcma_drv_cc *cc)
27 {
28 @@ -65,6 +66,7 @@ static inline int bcma_sflash_init(struc
29 #ifdef CONFIG_BCMA_NFLASH
30 /* driver_chipcommon_nflash.c */
31 int bcma_nflash_init(struct bcma_drv_cc *cc);
32 +extern struct platform_device bcma_nflash_dev;
33 #else
34 static inline int bcma_nflash_init(struct bcma_drv_cc *cc)
35 {
36 --- a/drivers/bcma/core.c
37 +++ b/drivers/bcma/core.c
38 @@ -65,7 +65,7 @@ void bcma_core_set_clockmode(struct bcma
39 switch (clkmode) {
40 case BCMA_CLKMODE_FAST:
41 bcma_set32(core, BCMA_CLKCTLST, BCMA_CLKCTLST_FORCEHT);
42 - udelay(64);
43 + usleep_range(64, 300);
44 for (i = 0; i < 1500; i++) {
45 if (bcma_read32(core, BCMA_CLKCTLST) &
46 BCMA_CLKCTLST_HAVEHT) {
47 --- a/drivers/bcma/driver_chipcommon.c
48 +++ b/drivers/bcma/driver_chipcommon.c
49 @@ -22,12 +22,9 @@ static inline u32 bcma_cc_write32_masked
50 return value;
51 }
52
53 -void bcma_core_chipcommon_init(struct bcma_drv_cc *cc)
54 +void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc)
55 {
56 - u32 leddc_on = 10;
57 - u32 leddc_off = 90;
58 -
59 - if (cc->setup_done)
60 + if (cc->early_setup_done)
61 return;
62
63 if (cc->core->id.rev >= 11)
64 @@ -36,6 +33,22 @@ void bcma_core_chipcommon_init(struct bc
65 if (cc->core->id.rev >= 35)
66 cc->capabilities_ext = bcma_cc_read32(cc, BCMA_CC_CAP_EXT);
67
68 + if (cc->capabilities & BCMA_CC_CAP_PMU)
69 + bcma_pmu_early_init(cc);
70 +
71 + cc->early_setup_done = true;
72 +}
73 +
74 +void bcma_core_chipcommon_init(struct bcma_drv_cc *cc)
75 +{
76 + u32 leddc_on = 10;
77 + u32 leddc_off = 90;
78 +
79 + if (cc->setup_done)
80 + return;
81 +
82 + bcma_core_chipcommon_early_init(cc);
83 +
84 if (cc->core->id.rev >= 20) {
85 bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, 0);
86 bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, 0);
87 --- a/drivers/bcma/driver_chipcommon_nflash.c
88 +++ b/drivers/bcma/driver_chipcommon_nflash.c
89 @@ -5,15 +5,40 @@
90 * Licensed under the GNU/GPL. See COPYING for details.
91 */
92
93 +#include <linux/platform_device.h>
94 #include <linux/bcma/bcma.h>
95 -#include <linux/bcma/bcma_driver_chipcommon.h>
96 -#include <linux/delay.h>
97
98 #include "bcma_private.h"
99
100 +struct platform_device bcma_nflash_dev = {
101 + .name = "bcma_nflash",
102 + .num_resources = 0,
103 +};
104 +
105 /* Initialize NAND flash access */
106 int bcma_nflash_init(struct bcma_drv_cc *cc)
107 {
108 - bcma_err(cc->core->bus, "NAND flash support is broken\n");
109 + struct bcma_bus *bus = cc->core->bus;
110 +
111 + if (bus->chipinfo.id != BCMA_CHIP_ID_BCM4706 &&
112 + cc->core->id.rev != 0x38) {
113 + bcma_err(bus, "NAND flash on unsupported board!\n");
114 + return -ENOTSUPP;
115 + }
116 +
117 + if (!(cc->capabilities & BCMA_CC_CAP_NFLASH)) {
118 + bcma_err(bus, "NAND flash not present according to ChipCommon\n");
119 + return -ENODEV;
120 + }
121 +
122 + cc->nflash.present = true;
123 + if (cc->core->id.rev == 38 &&
124 + (cc->status & BCMA_CC_CHIPST_5357_NAND_BOOT))
125 + cc->nflash.boot = true;
126 +
127 + /* Prepare platform device, but don't register it yet. It's too early,
128 + * malloc (required by device_private_init) is not available yet. */
129 + bcma_nflash_dev.dev.platform_data = &cc->nflash;
130 +
131 return 0;
132 }
133 --- a/drivers/bcma/driver_chipcommon_pmu.c
134 +++ b/drivers/bcma/driver_chipcommon_pmu.c
135 @@ -76,7 +76,10 @@ static void bcma_pmu_resources_init(stru
136 if (max_msk)
137 bcma_cc_write32(cc, BCMA_CC_PMU_MAXRES_MSK, max_msk);
138
139 - /* Add some delay; allow resources to come up and settle. */
140 + /*
141 + * Add some delay; allow resources to come up and settle.
142 + * Delay is required for SoC (early init).
143 + */
144 mdelay(2);
145 }
146
147 @@ -101,7 +104,7 @@ void bcma_chipco_bcm4331_ext_pa_lines_ct
148 bcma_cc_write32(cc, BCMA_CC_CHIPCTL, val);
149 }
150
151 -void bcma_pmu_workarounds(struct bcma_drv_cc *cc)
152 +static void bcma_pmu_workarounds(struct bcma_drv_cc *cc)
153 {
154 struct bcma_bus *bus = cc->core->bus;
155
156 @@ -141,7 +144,7 @@ void bcma_pmu_workarounds(struct bcma_dr
157 }
158 }
159
160 -void bcma_pmu_init(struct bcma_drv_cc *cc)
161 +void bcma_pmu_early_init(struct bcma_drv_cc *cc)
162 {
163 u32 pmucap;
164
165 @@ -150,7 +153,10 @@ void bcma_pmu_init(struct bcma_drv_cc *c
166
167 bcma_debug(cc->core->bus, "Found rev %u PMU (capabilities 0x%08X)\n",
168 cc->pmu.rev, pmucap);
169 +}
170
171 +void bcma_pmu_init(struct bcma_drv_cc *cc)
172 +{
173 if (cc->pmu.rev == 1)
174 bcma_cc_mask32(cc, BCMA_CC_PMU_CTL,
175 ~BCMA_CC_PMU_CTL_NOILPONW);
176 @@ -257,7 +263,7 @@ static u32 bcma_pmu_clock_bcm4706(struct
177 }
178
179 /* query bus clock frequency for PMU-enabled chipcommon */
180 -u32 bcma_pmu_get_clockcontrol(struct bcma_drv_cc *cc)
181 +static u32 bcma_pmu_get_clockcontrol(struct bcma_drv_cc *cc)
182 {
183 struct bcma_bus *bus = cc->core->bus;
184
185 --- a/drivers/bcma/driver_chipcommon_sflash.c
186 +++ b/drivers/bcma/driver_chipcommon_sflash.c
187 @@ -5,15 +5,161 @@
188 * Licensed under the GNU/GPL. See COPYING for details.
189 */
190
191 +#include <linux/platform_device.h>
192 #include <linux/bcma/bcma.h>
193 -#include <linux/bcma/bcma_driver_chipcommon.h>
194 -#include <linux/delay.h>
195
196 #include "bcma_private.h"
197
198 +static struct resource bcma_sflash_resource = {
199 + .name = "bcma_sflash",
200 + .start = BCMA_SOC_FLASH2,
201 + .end = 0,
202 + .flags = IORESOURCE_MEM | IORESOURCE_READONLY,
203 +};
204 +
205 +struct platform_device bcma_sflash_dev = {
206 + .name = "bcma_sflash",
207 + .resource = &bcma_sflash_resource,
208 + .num_resources = 1,
209 +};
210 +
211 +struct bcma_sflash_tbl_e {
212 + char *name;
213 + u32 id;
214 + u32 blocksize;
215 + u16 numblocks;
216 +};
217 +
218 +static struct bcma_sflash_tbl_e bcma_sflash_st_tbl[] = {
219 + { "M25P20", 0x11, 0x10000, 4, },
220 + { "M25P40", 0x12, 0x10000, 8, },
221 +
222 + { "M25P16", 0x14, 0x10000, 32, },
223 + { "M25P32", 0x14, 0x10000, 64, },
224 + { "M25P64", 0x16, 0x10000, 128, },
225 + { "M25FL128", 0x17, 0x10000, 256, },
226 + { 0 },
227 +};
228 +
229 +static struct bcma_sflash_tbl_e bcma_sflash_sst_tbl[] = {
230 + { "SST25WF512", 1, 0x1000, 16, },
231 + { "SST25VF512", 0x48, 0x1000, 16, },
232 + { "SST25WF010", 2, 0x1000, 32, },
233 + { "SST25VF010", 0x49, 0x1000, 32, },
234 + { "SST25WF020", 3, 0x1000, 64, },
235 + { "SST25VF020", 0x43, 0x1000, 64, },
236 + { "SST25WF040", 4, 0x1000, 128, },
237 + { "SST25VF040", 0x44, 0x1000, 128, },
238 + { "SST25VF040B", 0x8d, 0x1000, 128, },
239 + { "SST25WF080", 5, 0x1000, 256, },
240 + { "SST25VF080B", 0x8e, 0x1000, 256, },
241 + { "SST25VF016", 0x41, 0x1000, 512, },
242 + { "SST25VF032", 0x4a, 0x1000, 1024, },
243 + { "SST25VF064", 0x4b, 0x1000, 2048, },
244 + { 0 },
245 +};
246 +
247 +static struct bcma_sflash_tbl_e bcma_sflash_at_tbl[] = {
248 + { "AT45DB011", 0xc, 256, 512, },
249 + { "AT45DB021", 0x14, 256, 1024, },
250 + { "AT45DB041", 0x1c, 256, 2048, },
251 + { "AT45DB081", 0x24, 256, 4096, },
252 + { "AT45DB161", 0x2c, 512, 4096, },
253 + { "AT45DB321", 0x34, 512, 8192, },
254 + { "AT45DB642", 0x3c, 1024, 8192, },
255 + { 0 },
256 +};
257 +
258 +static void bcma_sflash_cmd(struct bcma_drv_cc *cc, u32 opcode)
259 +{
260 + int i;
261 + bcma_cc_write32(cc, BCMA_CC_FLASHCTL,
262 + BCMA_CC_FLASHCTL_START | opcode);
263 + for (i = 0; i < 1000; i++) {
264 + if (!(bcma_cc_read32(cc, BCMA_CC_FLASHCTL) &
265 + BCMA_CC_FLASHCTL_BUSY))
266 + return;
267 + cpu_relax();
268 + }
269 + bcma_err(cc->core->bus, "SFLASH control command failed (timeout)!\n");
270 +}
271 +
272 /* Initialize serial flash access */
273 int bcma_sflash_init(struct bcma_drv_cc *cc)
274 {
275 - bcma_err(cc->core->bus, "Serial flash support is broken\n");
276 + struct bcma_bus *bus = cc->core->bus;
277 + struct bcma_sflash *sflash = &cc->sflash;
278 + struct bcma_sflash_tbl_e *e;
279 + u32 id, id2;
280 +
281 + switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {
282 + case BCMA_CC_FLASHT_STSER:
283 + bcma_sflash_cmd(cc, BCMA_CC_FLASHCTL_ST_DP);
284 +
285 + bcma_cc_write32(cc, BCMA_CC_FLASHADDR, 0);
286 + bcma_sflash_cmd(cc, BCMA_CC_FLASHCTL_ST_RES);
287 + id = bcma_cc_read32(cc, BCMA_CC_FLASHDATA);
288 +
289 + bcma_cc_write32(cc, BCMA_CC_FLASHADDR, 1);
290 + bcma_sflash_cmd(cc, BCMA_CC_FLASHCTL_ST_RES);
291 + id2 = bcma_cc_read32(cc, BCMA_CC_FLASHDATA);
292 +
293 + switch (id) {
294 + case 0xbf:
295 + for (e = bcma_sflash_sst_tbl; e->name; e++) {
296 + if (e->id == id2)
297 + break;
298 + }
299 + break;
300 + case 0x13:
301 + return -ENOTSUPP;
302 + default:
303 + for (e = bcma_sflash_st_tbl; e->name; e++) {
304 + if (e->id == id)
305 + break;
306 + }
307 + break;
308 + }
309 + if (!e->name) {
310 + bcma_err(bus, "Unsupported ST serial flash (id: 0x%X, id2: 0x%X)\n", id, id2);
311 + return -ENOTSUPP;
312 + }
313 +
314 + break;
315 + case BCMA_CC_FLASHT_ATSER:
316 + bcma_sflash_cmd(cc, BCMA_CC_FLASHCTL_AT_STATUS);
317 + id = bcma_cc_read32(cc, BCMA_CC_FLASHDATA) & 0x3c;
318 +
319 + for (e = bcma_sflash_at_tbl; e->name; e++) {
320 + if (e->id == id)
321 + break;
322 + }
323 + if (!e->name) {
324 + bcma_err(bus, "Unsupported Atmel serial flash (id: 0x%X)\n", id);
325 + return -ENOTSUPP;
326 + }
327 +
328 + break;
329 + default:
330 + bcma_err(bus, "Unsupported flash type\n");
331 + return -ENOTSUPP;
332 + }
333 +
334 + sflash->window = BCMA_SOC_FLASH2;
335 + sflash->blocksize = e->blocksize;
336 + sflash->numblocks = e->numblocks;
337 + sflash->size = sflash->blocksize * sflash->numblocks;
338 + sflash->present = true;
339 +
340 + bcma_info(bus, "Found %s serial flash (size: %dKiB, blocksize: 0x%X, blocks: %d)\n",
341 + e->name, sflash->size / 1024, sflash->blocksize,
342 + sflash->numblocks);
343 +
344 + /* Prepare platform device, but don't register it yet. It's too early,
345 + * malloc (required by device_private_init) is not available yet. */
346 + bcma_sflash_dev.resource[0].end = bcma_sflash_dev.resource[0].start +
347 + sflash->size;
348 + bcma_sflash_dev.dev.platform_data = sflash;
349 +
350 return 0;
351 }
352 --- a/drivers/bcma/driver_mips.c
353 +++ b/drivers/bcma/driver_mips.c
354 @@ -181,47 +181,66 @@ EXPORT_SYMBOL(bcma_cpu_clock);
355 static void bcma_core_mips_flash_detect(struct bcma_drv_mips *mcore)
356 {
357 struct bcma_bus *bus = mcore->core->bus;
358 + struct bcma_drv_cc *cc = &bus->drv_cc;
359
360 - switch (bus->drv_cc.capabilities & BCMA_CC_CAP_FLASHT) {
361 + switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {
362 case BCMA_CC_FLASHT_STSER:
363 case BCMA_CC_FLASHT_ATSER:
364 bcma_debug(bus, "Found serial flash\n");
365 - bcma_sflash_init(&bus->drv_cc);
366 + bcma_sflash_init(cc);
367 break;
368 case BCMA_CC_FLASHT_PARA:
369 bcma_debug(bus, "Found parallel flash\n");
370 - bus->drv_cc.pflash.window = 0x1c000000;
371 - bus->drv_cc.pflash.window_size = 0x02000000;
372 + cc->pflash.present = true;
373 + cc->pflash.window = BCMA_SOC_FLASH2;
374 + cc->pflash.window_size = BCMA_SOC_FLASH2_SZ;
375
376 - if ((bcma_read32(bus->drv_cc.core, BCMA_CC_FLASH_CFG) &
377 + if ((bcma_read32(cc->core, BCMA_CC_FLASH_CFG) &
378 BCMA_CC_FLASH_CFG_DS) == 0)
379 - bus->drv_cc.pflash.buswidth = 1;
380 + cc->pflash.buswidth = 1;
381 else
382 - bus->drv_cc.pflash.buswidth = 2;
383 + cc->pflash.buswidth = 2;
384 break;
385 default:
386 bcma_err(bus, "Flash type not supported\n");
387 }
388
389 - if (bus->drv_cc.core->id.rev == 38 ||
390 + if (cc->core->id.rev == 38 ||
391 bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) {
392 - if (bus->drv_cc.capabilities & BCMA_CC_CAP_NFLASH) {
393 + if (cc->capabilities & BCMA_CC_CAP_NFLASH) {
394 bcma_debug(bus, "Found NAND flash\n");
395 - bcma_nflash_init(&bus->drv_cc);
396 + bcma_nflash_init(cc);
397 }
398 }
399 }
400
401 +void bcma_core_mips_early_init(struct bcma_drv_mips *mcore)
402 +{
403 + struct bcma_bus *bus = mcore->core->bus;
404 +
405 + if (mcore->early_setup_done)
406 + return;
407 +
408 + bcma_chipco_serial_init(&bus->drv_cc);
409 + bcma_core_mips_flash_detect(mcore);
410 +
411 + mcore->early_setup_done = true;
412 +}
413 +
414 void bcma_core_mips_init(struct bcma_drv_mips *mcore)
415 {
416 struct bcma_bus *bus;
417 struct bcma_device *core;
418 bus = mcore->core->bus;
419
420 + if (mcore->setup_done)
421 + return;
422 +
423 bcma_info(bus, "Initializing MIPS core...\n");
424
425 - if (!mcore->setup_done)
426 - mcore->assigned_irqs = 1;
427 + bcma_core_mips_early_init(mcore);
428 +
429 + mcore->assigned_irqs = 1;
430
431 /* Assign IRQs to all cores on the bus */
432 list_for_each_entry(core, &bus->cores, list) {
433 @@ -256,10 +275,5 @@ void bcma_core_mips_init(struct bcma_drv
434 bcma_info(bus, "IRQ reconfiguration done\n");
435 bcma_core_mips_dump_irq(bus);
436
437 - if (mcore->setup_done)
438 - return;
439 -
440 - bcma_chipco_serial_init(&bus->drv_cc);
441 - bcma_core_mips_flash_detect(mcore);
442 mcore->setup_done = true;
443 }
444 --- a/drivers/bcma/driver_pci.c
445 +++ b/drivers/bcma/driver_pci.c
446 @@ -51,7 +51,7 @@ static void bcma_pcie_mdio_set_phy(struc
447 v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
448 if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE)
449 break;
450 - msleep(1);
451 + usleep_range(1000, 2000);
452 }
453 }
454
455 @@ -92,7 +92,7 @@ static u16 bcma_pcie_mdio_read(struct bc
456 ret = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_DATA);
457 break;
458 }
459 - msleep(1);
460 + usleep_range(1000, 2000);
461 }
462 pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0);
463 return ret;
464 @@ -132,7 +132,7 @@ static void bcma_pcie_mdio_write(struct
465 v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
466 if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE)
467 break;
468 - msleep(1);
469 + usleep_range(1000, 2000);
470 }
471 pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0);
472 }
473 --- a/drivers/bcma/driver_pci_host.c
474 +++ b/drivers/bcma/driver_pci_host.c
475 @@ -35,11 +35,6 @@ bool __devinit bcma_core_pci_is_in_hostm
476 chipid_top != 0x5300)
477 return false;
478
479 - if (bus->sprom.boardflags_lo & BCMA_CORE_PCI_BFL_NOPCI) {
480 - bcma_info(bus, "This PCI core is disabled and not working\n");
481 - return false;
482 - }
483 -
484 bcma_core_enable(pc->core, 0);
485
486 return !mips_busprobe32(tmp, pc->core->io_addr);
487 @@ -396,6 +391,11 @@ void __devinit bcma_core_pci_hostmode_in
488
489 bcma_info(bus, "PCIEcore in host mode found\n");
490
491 + if (bus->sprom.boardflags_lo & BCMA_CORE_PCI_BFL_NOPCI) {
492 + bcma_info(bus, "This PCIE core is disabled and not working\n");
493 + return;
494 + }
495 +
496 pc_host = kzalloc(sizeof(*pc_host), GFP_KERNEL);
497 if (!pc_host) {
498 bcma_err(bus, "can not allocate memory");
499 @@ -425,9 +425,9 @@ void __devinit bcma_core_pci_hostmode_in
500 pc_host->io_resource.flags = IORESOURCE_IO | IORESOURCE_PCI_FIXED;
501
502 /* Reset RC */
503 - udelay(3000);
504 + usleep_range(3000, 5000);
505 pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST_OE);
506 - udelay(1000);
507 + usleep_range(1000, 2000);
508 pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST |
509 BCMA_CORE_PCI_CTL_RST_OE);
510
511 @@ -452,6 +452,8 @@ void __devinit bcma_core_pci_hostmode_in
512 pc_host->mem_resource.start = BCMA_SOC_PCI_MEM;
513 pc_host->mem_resource.end = BCMA_SOC_PCI_MEM +
514 BCMA_SOC_PCI_MEM_SZ - 1;
515 + pc_host->io_resource.start = 0x100;
516 + pc_host->io_resource.end = 0x47F;
517 pci_membase_1G = BCMA_SOC_PCIE_DMA_H32;
518 pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
519 tmp | BCMA_SOC_PCI_MEM);
520 @@ -459,6 +461,8 @@ void __devinit bcma_core_pci_hostmode_in
521 pc_host->mem_resource.start = BCMA_SOC_PCI1_MEM;
522 pc_host->mem_resource.end = BCMA_SOC_PCI1_MEM +
523 BCMA_SOC_PCI_MEM_SZ - 1;
524 + pc_host->io_resource.start = 0x480;
525 + pc_host->io_resource.end = 0x7FF;
526 pci_membase_1G = BCMA_SOC_PCIE1_DMA_H32;
527 pc_host->host_cfg_addr = BCMA_SOC_PCI1_CFG;
528 pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
529 @@ -481,7 +485,7 @@ void __devinit bcma_core_pci_hostmode_in
530 * before issuing configuration requests to PCI Express
531 * devices.
532 */
533 - udelay(100000);
534 + msleep(100);
535
536 bcma_core_pci_enable_crs(pc);
537
538 @@ -501,7 +505,7 @@ void __devinit bcma_core_pci_hostmode_in
539 set_io_port_base(pc_host->pci_controller.io_map_base);
540 /* Give some time to the PCI controller to configure itself with the new
541 * values. Not waiting at this point causes crashes of the machine. */
542 - mdelay(10);
543 + usleep_range(10000, 15000);
544 register_pci_controller(&pc_host->pci_controller);
545 return;
546 }
547 --- a/drivers/bcma/host_pci.c
548 +++ b/drivers/bcma/host_pci.c
549 @@ -77,8 +77,8 @@ static void bcma_host_pci_write32(struct
550 }
551
552 #ifdef CONFIG_BCMA_BLOCKIO
553 -void bcma_host_pci_block_read(struct bcma_device *core, void *buffer,
554 - size_t count, u16 offset, u8 reg_width)
555 +static void bcma_host_pci_block_read(struct bcma_device *core, void *buffer,
556 + size_t count, u16 offset, u8 reg_width)
557 {
558 void __iomem *addr = core->bus->mmio + offset;
559 if (core->bus->mapped_core != core)
560 @@ -100,8 +100,9 @@ void bcma_host_pci_block_read(struct bcm
561 }
562 }
563
564 -void bcma_host_pci_block_write(struct bcma_device *core, const void *buffer,
565 - size_t count, u16 offset, u8 reg_width)
566 +static void bcma_host_pci_block_write(struct bcma_device *core,
567 + const void *buffer, size_t count,
568 + u16 offset, u8 reg_width)
569 {
570 void __iomem *addr = core->bus->mmio + offset;
571 if (core->bus->mapped_core != core)
572 @@ -139,7 +140,7 @@ static void bcma_host_pci_awrite32(struc
573 iowrite32(value, core->bus->mmio + (1 * BCMA_CORE_SIZE) + offset);
574 }
575
576 -const struct bcma_host_ops bcma_host_pci_ops = {
577 +static const struct bcma_host_ops bcma_host_pci_ops = {
578 .read8 = bcma_host_pci_read8,
579 .read16 = bcma_host_pci_read16,
580 .read32 = bcma_host_pci_read32,
581 @@ -272,6 +273,7 @@ static DEFINE_PCI_DEVICE_TABLE(bcma_pci_
582 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4331) },
583 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4353) },
584 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4357) },
585 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4358) },
586 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4359) },
587 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4727) },
588 { 0, },
589 --- a/drivers/bcma/host_soc.c
590 +++ b/drivers/bcma/host_soc.c
591 @@ -143,7 +143,7 @@ static void bcma_host_soc_awrite32(struc
592 writel(value, core->io_wrap + offset);
593 }
594
595 -const struct bcma_host_ops bcma_host_soc_ops = {
596 +static const struct bcma_host_ops bcma_host_soc_ops = {
597 .read8 = bcma_host_soc_read8,
598 .read16 = bcma_host_soc_read16,
599 .read32 = bcma_host_soc_read32,
600 --- a/drivers/bcma/main.c
601 +++ b/drivers/bcma/main.c
602 @@ -7,6 +7,7 @@
603
604 #include "bcma_private.h"
605 #include <linux/module.h>
606 +#include <linux/platform_device.h>
607 #include <linux/bcma/bcma.h>
608 #include <linux/slab.h>
609
610 @@ -80,6 +81,18 @@ struct bcma_device *bcma_find_core(struc
611 }
612 EXPORT_SYMBOL_GPL(bcma_find_core);
613
614 +static struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
615 + u8 unit)
616 +{
617 + struct bcma_device *core;
618 +
619 + list_for_each_entry(core, &bus->cores, list) {
620 + if (core->id.id == coreid && core->core_unit == unit)
621 + return core;
622 + }
623 + return NULL;
624 +}
625 +
626 static void bcma_release_core_dev(struct device *dev)
627 {
628 struct bcma_device *core = container_of(dev, struct bcma_device, dev);
629 @@ -136,6 +149,22 @@ static int bcma_register_cores(struct bc
630 dev_id++;
631 }
632
633 +#ifdef CONFIG_BCMA_SFLASH
634 + if (bus->drv_cc.sflash.present) {
635 + err = platform_device_register(&bcma_sflash_dev);
636 + if (err)
637 + bcma_err(bus, "Error registering serial flash\n");
638 + }
639 +#endif
640 +
641 +#ifdef CONFIG_BCMA_NFLASH
642 + if (bus->drv_cc.nflash.present) {
643 + err = platform_device_register(&bcma_nflash_dev);
644 + if (err)
645 + bcma_err(bus, "Error registering NAND flash\n");
646 + }
647 +#endif
648 +
649 return 0;
650 }
651
652 @@ -166,6 +195,20 @@ int __devinit bcma_bus_register(struct b
653 return -1;
654 }
655
656 + /* Early init CC core */
657 + core = bcma_find_core(bus, bcma_cc_core_id(bus));
658 + if (core) {
659 + bus->drv_cc.core = core;
660 + bcma_core_chipcommon_early_init(&bus->drv_cc);
661 + }
662 +
663 + /* Try to get SPROM */
664 + err = bcma_sprom_get(bus);
665 + if (err == -ENOENT) {
666 + bcma_err(bus, "No SPROM available\n");
667 + } else if (err)
668 + bcma_err(bus, "Failed to get SPROM: %d\n", err);
669 +
670 /* Init CC core */
671 core = bcma_find_core(bus, bcma_cc_core_id(bus));
672 if (core) {
673 @@ -181,10 +224,17 @@ int __devinit bcma_bus_register(struct b
674 }
675
676 /* Init PCIE core */
677 - core = bcma_find_core(bus, BCMA_CORE_PCIE);
678 + core = bcma_find_core_unit(bus, BCMA_CORE_PCIE, 0);
679 + if (core) {
680 + bus->drv_pci[0].core = core;
681 + bcma_core_pci_init(&bus->drv_pci[0]);
682 + }
683 +
684 + /* Init PCIE core */
685 + core = bcma_find_core_unit(bus, BCMA_CORE_PCIE, 1);
686 if (core) {
687 - bus->drv_pci.core = core;
688 - bcma_core_pci_init(&bus->drv_pci);
689 + bus->drv_pci[1].core = core;
690 + bcma_core_pci_init(&bus->drv_pci[1]);
691 }
692
693 /* Init GBIT MAC COMMON core */
694 @@ -194,13 +244,6 @@ int __devinit bcma_bus_register(struct b
695 bcma_core_gmac_cmn_init(&bus->drv_gmac_cmn);
696 }
697
698 - /* Try to get SPROM */
699 - err = bcma_sprom_get(bus);
700 - if (err == -ENOENT) {
701 - bcma_err(bus, "No SPROM available\n");
702 - } else if (err)
703 - bcma_err(bus, "Failed to get SPROM: %d\n", err);
704 -
705 /* Register found cores */
706 bcma_register_cores(bus);
707
708 @@ -211,7 +254,17 @@ int __devinit bcma_bus_register(struct b
709
710 void bcma_bus_unregister(struct bcma_bus *bus)
711 {
712 + struct bcma_device *cores[3];
713 +
714 + cores[0] = bcma_find_core(bus, BCMA_CORE_MIPS_74K);
715 + cores[1] = bcma_find_core(bus, BCMA_CORE_PCIE);
716 + cores[2] = bcma_find_core(bus, BCMA_CORE_4706_MAC_GBIT_COMMON);
717 +
718 bcma_unregister_cores(bus);
719 +
720 + kfree(cores[2]);
721 + kfree(cores[1]);
722 + kfree(cores[0]);
723 }
724
725 int __init bcma_bus_early_register(struct bcma_bus *bus,
726 @@ -248,18 +301,18 @@ int __init bcma_bus_early_register(struc
727 return -1;
728 }
729
730 - /* Init CC core */
731 + /* Early init CC core */
732 core = bcma_find_core(bus, bcma_cc_core_id(bus));
733 if (core) {
734 bus->drv_cc.core = core;
735 - bcma_core_chipcommon_init(&bus->drv_cc);
736 + bcma_core_chipcommon_early_init(&bus->drv_cc);
737 }
738
739 - /* Init MIPS core */
740 + /* Early init MIPS core */
741 core = bcma_find_core(bus, BCMA_CORE_MIPS_74K);
742 if (core) {
743 bus->drv_mips.core = core;
744 - bcma_core_mips_init(&bus->drv_mips);
745 + bcma_core_mips_early_init(&bus->drv_mips);
746 }
747
748 bcma_info(bus, "Early bus registered\n");
749 --- a/drivers/bcma/sprom.c
750 +++ b/drivers/bcma/sprom.c
751 @@ -507,7 +507,9 @@ static bool bcma_sprom_onchip_available(
752 /* for these chips OTP is always available */
753 present = true;
754 break;
755 + case BCMA_CHIP_ID_BCM43227:
756 case BCMA_CHIP_ID_BCM43228:
757 + case BCMA_CHIP_ID_BCM43428:
758 present = chip_status & BCMA_CC_CHIPST_43228_OTP_PRESENT;
759 break;
760 default:
761 @@ -593,8 +595,11 @@ int bcma_sprom_get(struct bcma_bus *bus)
762 bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, true);
763
764 err = bcma_sprom_valid(sprom);
765 - if (err)
766 + if (err) {
767 + bcma_warn(bus, "invalid sprom read from the PCIe card, try to use fallback sprom\n");
768 + err = bcma_fill_sprom_with_fallback(bus, &bus->sprom);
769 goto out;
770 + }
771
772 bcma_sprom_extract_r8(bus, sprom);
773
774 --- a/include/linux/bcma/bcma.h
775 +++ b/include/linux/bcma/bcma.h
776 @@ -10,7 +10,7 @@
777 #include <linux/bcma/bcma_driver_gmac_cmn.h>
778 #include <linux/ssb/ssb.h> /* SPROM sharing */
779
780 -#include "bcma_regs.h"
781 +#include <linux/bcma/bcma_regs.h>
782
783 struct bcma_device;
784 struct bcma_bus;
785 @@ -251,7 +251,7 @@ struct bcma_bus {
786 u8 num;
787
788 struct bcma_drv_cc drv_cc;
789 - struct bcma_drv_pci drv_pci;
790 + struct bcma_drv_pci drv_pci[2];
791 struct bcma_drv_mips drv_mips;
792 struct bcma_drv_gmac_cmn drv_gmac_cmn;
793
794 --- a/include/linux/bcma/bcma_driver_chipcommon.h
795 +++ b/include/linux/bcma/bcma_driver_chipcommon.h
796 @@ -100,6 +100,7 @@
797 #define BCMA_CC_CHIPST_4706_SFLASH_TYPE BIT(2) /* 0: 8b-p/ST-s flash, 1: 16b-p/Atmal-s flash */
798 #define BCMA_CC_CHIPST_4706_MIPS_BENDIAN BIT(3) /* 0: little, 1: big endian */
799 #define BCMA_CC_CHIPST_4706_PCIE1_DISABLE BIT(5) /* PCIE1 enable strap pin */
800 +#define BCMA_CC_CHIPST_5357_NAND_BOOT BIT(4) /* NAND boot, valid for CC rev 38 and/or BCM5357 */
801 #define BCMA_CC_JCMD 0x0030 /* Rev >= 10 only */
802 #define BCMA_CC_JCMD_START 0x80000000
803 #define BCMA_CC_JCMD_BUSY 0x80000000
804 @@ -266,6 +267,29 @@
805 #define BCMA_CC_SROM_CONTROL_SIZE_16K 0x00000004
806 #define BCMA_CC_SROM_CONTROL_SIZE_SHIFT 1
807 #define BCMA_CC_SROM_CONTROL_PRESENT 0x00000001
808 +/* Block 0x140 - 0x190 registers are chipset specific */
809 +#define BCMA_CC_4706_FLASHSCFG 0x18C /* Flash struct configuration */
810 +#define BCMA_CC_4706_FLASHSCFG_MASK 0x000000ff
811 +#define BCMA_CC_4706_FLASHSCFG_SF1 0x00000001 /* 2nd serial flash present */
812 +#define BCMA_CC_4706_FLASHSCFG_PF1 0x00000002 /* 2nd parallel flash present */
813 +#define BCMA_CC_4706_FLASHSCFG_SF1_TYPE 0x00000004 /* 2nd serial flash type : 0 : ST, 1 : Atmel */
814 +#define BCMA_CC_4706_FLASHSCFG_NF1 0x00000008 /* 2nd NAND flash present */
815 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_MASK 0x000000f0
816 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_4MB 0x00000010 /* 4MB */
817 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_8MB 0x00000020 /* 8MB */
818 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_16MB 0x00000030 /* 16MB */
819 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_32MB 0x00000040 /* 32MB */
820 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_64MB 0x00000050 /* 64MB */
821 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_128MB 0x00000060 /* 128MB */
822 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_256MB 0x00000070 /* 256MB */
823 +/* NAND flash registers for BCM4706 (corerev = 31) */
824 +#define BCMA_CC_NFLASH_CTL 0x01A0
825 +#define BCMA_CC_NFLASH_CTL_ERR 0x08000000
826 +#define BCMA_CC_NFLASH_CONF 0x01A4
827 +#define BCMA_CC_NFLASH_COL_ADDR 0x01A8
828 +#define BCMA_CC_NFLASH_ROW_ADDR 0x01AC
829 +#define BCMA_CC_NFLASH_DATA 0x01B0
830 +#define BCMA_CC_NFLASH_WAITCNT0 0x01B4
831 /* 0x1E0 is defined as shared BCMA_CLKCTLST */
832 #define BCMA_CC_HW_WORKAROUND 0x01E4 /* Hardware workaround (rev >= 20) */
833 #define BCMA_CC_UART0_DATA 0x0300
834 @@ -325,6 +349,60 @@
835 #define BCMA_CC_PLLCTL_ADDR 0x0660
836 #define BCMA_CC_PLLCTL_DATA 0x0664
837 #define BCMA_CC_SPROM 0x0800 /* SPROM beginning */
838 +/* NAND flash MLC controller registers (corerev >= 38) */
839 +#define BCMA_CC_NAND_REVISION 0x0C00
840 +#define BCMA_CC_NAND_CMD_START 0x0C04
841 +#define BCMA_CC_NAND_CMD_ADDR_X 0x0C08
842 +#define BCMA_CC_NAND_CMD_ADDR 0x0C0C
843 +#define BCMA_CC_NAND_CMD_END_ADDR 0x0C10
844 +#define BCMA_CC_NAND_CS_NAND_SELECT 0x0C14
845 +#define BCMA_CC_NAND_CS_NAND_XOR 0x0C18
846 +#define BCMA_CC_NAND_SPARE_RD0 0x0C20
847 +#define BCMA_CC_NAND_SPARE_RD4 0x0C24
848 +#define BCMA_CC_NAND_SPARE_RD8 0x0C28
849 +#define BCMA_CC_NAND_SPARE_RD12 0x0C2C
850 +#define BCMA_CC_NAND_SPARE_WR0 0x0C30
851 +#define BCMA_CC_NAND_SPARE_WR4 0x0C34
852 +#define BCMA_CC_NAND_SPARE_WR8 0x0C38
853 +#define BCMA_CC_NAND_SPARE_WR12 0x0C3C
854 +#define BCMA_CC_NAND_ACC_CONTROL 0x0C40
855 +#define BCMA_CC_NAND_CONFIG 0x0C48
856 +#define BCMA_CC_NAND_TIMING_1 0x0C50
857 +#define BCMA_CC_NAND_TIMING_2 0x0C54
858 +#define BCMA_CC_NAND_SEMAPHORE 0x0C58
859 +#define BCMA_CC_NAND_DEVID 0x0C60
860 +#define BCMA_CC_NAND_DEVID_X 0x0C64
861 +#define BCMA_CC_NAND_BLOCK_LOCK_STATUS 0x0C68
862 +#define BCMA_CC_NAND_INTFC_STATUS 0x0C6C
863 +#define BCMA_CC_NAND_ECC_CORR_ADDR_X 0x0C70
864 +#define BCMA_CC_NAND_ECC_CORR_ADDR 0x0C74
865 +#define BCMA_CC_NAND_ECC_UNC_ADDR_X 0x0C78
866 +#define BCMA_CC_NAND_ECC_UNC_ADDR 0x0C7C
867 +#define BCMA_CC_NAND_READ_ERROR_COUNT 0x0C80
868 +#define BCMA_CC_NAND_CORR_STAT_THRESHOLD 0x0C84
869 +#define BCMA_CC_NAND_READ_ADDR_X 0x0C90
870 +#define BCMA_CC_NAND_READ_ADDR 0x0C94
871 +#define BCMA_CC_NAND_PAGE_PROGRAM_ADDR_X 0x0C98
872 +#define BCMA_CC_NAND_PAGE_PROGRAM_ADDR 0x0C9C
873 +#define BCMA_CC_NAND_COPY_BACK_ADDR_X 0x0CA0
874 +#define BCMA_CC_NAND_COPY_BACK_ADDR 0x0CA4
875 +#define BCMA_CC_NAND_BLOCK_ERASE_ADDR_X 0x0CA8
876 +#define BCMA_CC_NAND_BLOCK_ERASE_ADDR 0x0CAC
877 +#define BCMA_CC_NAND_INV_READ_ADDR_X 0x0CB0
878 +#define BCMA_CC_NAND_INV_READ_ADDR 0x0CB4
879 +#define BCMA_CC_NAND_BLK_WR_PROTECT 0x0CC0
880 +#define BCMA_CC_NAND_ACC_CONTROL_CS1 0x0CD0
881 +#define BCMA_CC_NAND_CONFIG_CS1 0x0CD4
882 +#define BCMA_CC_NAND_TIMING_1_CS1 0x0CD8
883 +#define BCMA_CC_NAND_TIMING_2_CS1 0x0CDC
884 +#define BCMA_CC_NAND_SPARE_RD16 0x0D30
885 +#define BCMA_CC_NAND_SPARE_RD20 0x0D34
886 +#define BCMA_CC_NAND_SPARE_RD24 0x0D38
887 +#define BCMA_CC_NAND_SPARE_RD28 0x0D3C
888 +#define BCMA_CC_NAND_CACHE_ADDR 0x0D40
889 +#define BCMA_CC_NAND_CACHE_DATA 0x0D44
890 +#define BCMA_CC_NAND_CTRL_CONFIG 0x0D48
891 +#define BCMA_CC_NAND_CTRL_STATUS 0x0D4C
892
893 /* Divider allocation in 4716/47162/5356 */
894 #define BCMA_CC_PMU5_MAINPLL_CPU 1
895 @@ -415,6 +493,13 @@
896 /* 4313 Chip specific ChipControl register bits */
897 #define BCMA_CCTRL_4313_12MA_LED_DRIVE 0x00000007 /* 12 mA drive strengh for later 4313 */
898
899 +/* BCM5357 ChipControl register bits */
900 +#define BCMA_CHIPCTL_5357_EXTPA BIT(14)
901 +#define BCMA_CHIPCTL_5357_ANT_MUX_2O3 BIT(15)
902 +#define BCMA_CHIPCTL_5357_NFLASH BIT(16)
903 +#define BCMA_CHIPCTL_5357_I2S_PINS_ENABLE BIT(18)
904 +#define BCMA_CHIPCTL_5357_I2CSPI_PINS_ENABLE BIT(19)
905 +
906 /* Data for the PMU, if available.
907 * Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU)
908 */
909 @@ -425,11 +510,35 @@ struct bcma_chipcommon_pmu {
910
911 #ifdef CONFIG_BCMA_DRIVER_MIPS
912 struct bcma_pflash {
913 + bool present;
914 u8 buswidth;
915 u32 window;
916 u32 window_size;
917 };
918
919 +#ifdef CONFIG_BCMA_SFLASH
920 +struct bcma_sflash {
921 + bool present;
922 + u32 window;
923 + u32 blocksize;
924 + u16 numblocks;
925 + u32 size;
926 +
927 + struct mtd_info *mtd;
928 +};
929 +#endif
930 +
931 +#ifdef CONFIG_BCMA_NFLASH
932 +struct mtd_info;
933 +
934 +struct bcma_nflash {
935 + bool present;
936 + bool boot; /* This is the flash the SoC boots from */
937 +
938 + struct mtd_info *mtd;
939 +};
940 +#endif
941 +
942 struct bcma_serial_port {
943 void *regs;
944 unsigned long clockspeed;
945 @@ -445,11 +554,18 @@ struct bcma_drv_cc {
946 u32 capabilities;
947 u32 capabilities_ext;
948 u8 setup_done:1;
949 + u8 early_setup_done:1;
950 /* Fast Powerup Delay constant */
951 u16 fast_pwrup_delay;
952 struct bcma_chipcommon_pmu pmu;
953 #ifdef CONFIG_BCMA_DRIVER_MIPS
954 struct bcma_pflash pflash;
955 +#ifdef CONFIG_BCMA_SFLASH
956 + struct bcma_sflash sflash;
957 +#endif
958 +#ifdef CONFIG_BCMA_NFLASH
959 + struct bcma_nflash nflash;
960 +#endif
961
962 int nr_serial_ports;
963 struct bcma_serial_port serial_ports[4];
964 @@ -470,6 +586,7 @@ struct bcma_drv_cc {
965 bcma_cc_write32(cc, offset, (bcma_cc_read32(cc, offset) & (mask)) | (set))
966
967 extern void bcma_core_chipcommon_init(struct bcma_drv_cc *cc);
968 +extern void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc);
969
970 extern void bcma_chipco_suspend(struct bcma_drv_cc *cc);
971 extern void bcma_chipco_resume(struct bcma_drv_cc *cc);
972 @@ -493,6 +610,7 @@ u32 bcma_chipco_gpio_polarity(struct bcm
973
974 /* PMU support */
975 extern void bcma_pmu_init(struct bcma_drv_cc *cc);
976 +extern void bcma_pmu_early_init(struct bcma_drv_cc *cc);
977
978 extern void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset,
979 u32 value);
980 --- a/include/linux/bcma/bcma_driver_mips.h
981 +++ b/include/linux/bcma/bcma_driver_mips.h
982 @@ -35,13 +35,16 @@ struct bcma_device;
983 struct bcma_drv_mips {
984 struct bcma_device *core;
985 u8 setup_done:1;
986 + u8 early_setup_done:1;
987 unsigned int assigned_irqs;
988 };
989
990 #ifdef CONFIG_BCMA_DRIVER_MIPS
991 extern void bcma_core_mips_init(struct bcma_drv_mips *mcore);
992 +extern void bcma_core_mips_early_init(struct bcma_drv_mips *mcore);
993 #else
994 static inline void bcma_core_mips_init(struct bcma_drv_mips *mcore) { }
995 +static inline void bcma_core_mips_early_init(struct bcma_drv_mips *mcore) { }
996 #endif
997
998 extern u32 bcma_cpu_clock(struct bcma_drv_mips *mcore);
999 --- a/include/linux/bcma/bcma_regs.h
1000 +++ b/include/linux/bcma/bcma_regs.h
1001 @@ -11,11 +11,13 @@
1002 #define BCMA_CLKCTLST_HAVEHTREQ 0x00000010 /* HT available request */
1003 #define BCMA_CLKCTLST_HWCROFF 0x00000020 /* Force HW clock request off */
1004 #define BCMA_CLKCTLST_EXTRESREQ 0x00000700 /* Mask of external resource requests */
1005 +#define BCMA_CLKCTLST_EXTRESREQ_SHIFT 8
1006 #define BCMA_CLKCTLST_HAVEALP 0x00010000 /* ALP available */
1007 #define BCMA_CLKCTLST_HAVEHT 0x00020000 /* HT available */
1008 #define BCMA_CLKCTLST_BP_ON_ALP 0x00040000 /* RO: running on ALP clock */
1009 #define BCMA_CLKCTLST_BP_ON_HT 0x00080000 /* RO: running on HT clock */
1010 #define BCMA_CLKCTLST_EXTRESST 0x07000000 /* Mask of external resource status */
1011 +#define BCMA_CLKCTLST_EXTRESST_SHIFT 24
1012 /* Is there any BCM4328 on BCMA bus? */
1013 #define BCMA_CLKCTLST_4328A0_HAVEHT 0x00010000 /* 4328a0 has reversed bits */
1014 #define BCMA_CLKCTLST_4328A0_HAVEALP 0x00020000 /* 4328a0 has reversed bits */
1015 @@ -83,4 +85,9 @@
1016 * (2 ZettaBytes), high 32 bits
1017 */
1018
1019 +#define BCMA_SOC_FLASH1 0x1fc00000 /* MIPS Flash Region 1 */
1020 +#define BCMA_SOC_FLASH1_SZ 0x00400000 /* MIPS Size of Flash Region 1 */
1021 +#define BCMA_SOC_FLASH2 0x1c000000 /* Flash Region 2 (region 1 shadowed here) */
1022 +#define BCMA_SOC_FLASH2_SZ 0x02000000 /* Size of Flash Region 2 */
1023 +
1024 #endif /* LINUX_BCMA_REGS_H_ */
Staging tree of dedeckeh