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update/fixup overlayfs patch
[openwrt/staging/chunkeey.git] / target / linux / generic / patches-3.6 / 025-bcma_backport.patch
1 --- a/arch/mips/bcm47xx/serial.c
2 +++ b/arch/mips/bcm47xx/serial.c
3 @@ -62,7 +62,7 @@ static int __init uart8250_init_bcma(voi
4
5 p->mapbase = (unsigned int) bcma_port->regs;
6 p->membase = (void *) bcma_port->regs;
7 - p->irq = bcma_port->irq + 2;
8 + p->irq = bcma_port->irq;
9 p->uartclk = bcma_port->baud_base;
10 p->regshift = bcma_port->reg_shift;
11 p->iotype = UPIO_MEM;
12 --- a/drivers/bcma/Kconfig
13 +++ b/drivers/bcma/Kconfig
14 @@ -26,6 +26,7 @@ config BCMA_HOST_PCI_POSSIBLE
15 config BCMA_HOST_PCI
16 bool "Support for BCMA on PCI-host bus"
17 depends on BCMA_HOST_PCI_POSSIBLE
18 + default y
19
20 config BCMA_DRIVER_PCI_HOSTMODE
21 bool "Driver for PCI core working in hostmode"
22 @@ -34,8 +35,14 @@ config BCMA_DRIVER_PCI_HOSTMODE
23 PCI core hostmode operation (external PCI bus).
24
25 config BCMA_HOST_SOC
26 - bool
27 - depends on BCMA_DRIVER_MIPS
28 + bool "Support for BCMA in a SoC"
29 + depends on BCMA
30 + help
31 + Host interface for a Broadcom AIX bus directly mapped into
32 + the memory. This only works with the Broadcom SoCs from the
33 + BCM47XX line.
34 +
35 + If unsure, say N
36
37 config BCMA_DRIVER_MIPS
38 bool "BCMA Broadcom MIPS core driver"
39 @@ -48,12 +55,12 @@ config BCMA_DRIVER_MIPS
40
41 config BCMA_SFLASH
42 bool
43 - depends on BCMA_DRIVER_MIPS && BROKEN
44 + depends on BCMA_DRIVER_MIPS
45 default y
46
47 config BCMA_NFLASH
48 bool
49 - depends on BCMA_DRIVER_MIPS && BROKEN
50 + depends on BCMA_DRIVER_MIPS
51 default y
52
53 config BCMA_DRIVER_GMAC_CMN
54 @@ -65,6 +72,14 @@ config BCMA_DRIVER_GMAC_CMN
55
56 If unsure, say N
57
58 +config BCMA_DRIVER_GPIO
59 + bool "BCMA GPIO driver"
60 + depends on BCMA && GPIOLIB
61 + help
62 + Driver to provide access to the GPIO pins of the bcma bus.
63 +
64 + If unsure, say N
65 +
66 config BCMA_DEBUG
67 bool "BCMA debugging"
68 depends on BCMA
69 --- a/drivers/bcma/Makefile
70 +++ b/drivers/bcma/Makefile
71 @@ -6,6 +6,7 @@ bcma-y += driver_pci.o
72 bcma-$(CONFIG_BCMA_DRIVER_PCI_HOSTMODE) += driver_pci_host.o
73 bcma-$(CONFIG_BCMA_DRIVER_MIPS) += driver_mips.o
74 bcma-$(CONFIG_BCMA_DRIVER_GMAC_CMN) += driver_gmac_cmn.o
75 +bcma-$(CONFIG_BCMA_DRIVER_GPIO) += driver_gpio.o
76 bcma-$(CONFIG_BCMA_HOST_PCI) += host_pci.o
77 bcma-$(CONFIG_BCMA_HOST_SOC) += host_soc.o
78 obj-$(CONFIG_BCMA) += bcma.o
79 --- a/drivers/bcma/bcma_private.h
80 +++ b/drivers/bcma/bcma_private.h
81 @@ -22,6 +22,8 @@
82 struct bcma_bus;
83
84 /* main.c */
85 +bool bcma_wait_value(struct bcma_device *core, u16 reg, u32 mask, u32 value,
86 + int timeout);
87 int __devinit bcma_bus_register(struct bcma_bus *bus);
88 void bcma_bus_unregister(struct bcma_bus *bus);
89 int __init bcma_bus_early_register(struct bcma_bus *bus,
90 @@ -31,6 +33,8 @@ int __init bcma_bus_early_register(struc
91 int bcma_bus_suspend(struct bcma_bus *bus);
92 int bcma_bus_resume(struct bcma_bus *bus);
93 #endif
94 +struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
95 + u8 unit);
96
97 /* scan.c */
98 int bcma_bus_scan(struct bcma_bus *bus);
99 @@ -45,15 +49,17 @@ int bcma_sprom_get(struct bcma_bus *bus)
100 /* driver_chipcommon.c */
101 #ifdef CONFIG_BCMA_DRIVER_MIPS
102 void bcma_chipco_serial_init(struct bcma_drv_cc *cc);
103 +extern struct platform_device bcma_pflash_dev;
104 #endif /* CONFIG_BCMA_DRIVER_MIPS */
105
106 /* driver_chipcommon_pmu.c */
107 -u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc);
108 -u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc);
109 +u32 bcma_pmu_get_alp_clock(struct bcma_drv_cc *cc);
110 +u32 bcma_pmu_get_cpu_clock(struct bcma_drv_cc *cc);
111
112 #ifdef CONFIG_BCMA_SFLASH
113 /* driver_chipcommon_sflash.c */
114 int bcma_sflash_init(struct bcma_drv_cc *cc);
115 +extern struct platform_device bcma_sflash_dev;
116 #else
117 static inline int bcma_sflash_init(struct bcma_drv_cc *cc)
118 {
119 @@ -65,6 +71,7 @@ static inline int bcma_sflash_init(struc
120 #ifdef CONFIG_BCMA_NFLASH
121 /* driver_chipcommon_nflash.c */
122 int bcma_nflash_init(struct bcma_drv_cc *cc);
123 +extern struct platform_device bcma_nflash_dev;
124 #else
125 static inline int bcma_nflash_init(struct bcma_drv_cc *cc)
126 {
127 @@ -82,9 +89,26 @@ extern void __exit bcma_host_pci_exit(vo
128 /* driver_pci.c */
129 u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address);
130
131 +extern int bcma_chipco_watchdog_register(struct bcma_drv_cc *cc);
132 +
133 #ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
134 bool __devinit bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc);
135 void __devinit bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc);
136 #endif /* CONFIG_BCMA_DRIVER_PCI_HOSTMODE */
137
138 +#ifdef CONFIG_BCMA_DRIVER_GPIO
139 +/* driver_gpio.c */
140 +int bcma_gpio_init(struct bcma_drv_cc *cc);
141 +int bcma_gpio_unregister(struct bcma_drv_cc *cc);
142 +#else
143 +static inline int bcma_gpio_init(struct bcma_drv_cc *cc)
144 +{
145 + return -ENOTSUPP;
146 +}
147 +static inline int bcma_gpio_unregister(struct bcma_drv_cc *cc)
148 +{
149 + return 0;
150 +}
151 +#endif /* CONFIG_BCMA_DRIVER_GPIO */
152 +
153 #endif
154 --- a/drivers/bcma/core.c
155 +++ b/drivers/bcma/core.c
156 @@ -9,6 +9,25 @@
157 #include <linux/export.h>
158 #include <linux/bcma/bcma.h>
159
160 +static bool bcma_core_wait_value(struct bcma_device *core, u16 reg, u32 mask,
161 + u32 value, int timeout)
162 +{
163 + unsigned long deadline = jiffies + timeout;
164 + u32 val;
165 +
166 + do {
167 + val = bcma_aread32(core, reg);
168 + if ((val & mask) == value)
169 + return true;
170 + cpu_relax();
171 + udelay(10);
172 + } while (!time_after_eq(jiffies, deadline));
173 +
174 + bcma_warn(core->bus, "Timeout waiting for register 0x%04X!\n", reg);
175 +
176 + return false;
177 +}
178 +
179 bool bcma_core_is_enabled(struct bcma_device *core)
180 {
181 if ((bcma_aread32(core, BCMA_IOCTL) & (BCMA_IOCTL_CLK | BCMA_IOCTL_FGC))
182 @@ -25,13 +44,15 @@ void bcma_core_disable(struct bcma_devic
183 if (bcma_aread32(core, BCMA_RESET_CTL) & BCMA_RESET_CTL_RESET)
184 return;
185
186 - bcma_awrite32(core, BCMA_IOCTL, flags);
187 - bcma_aread32(core, BCMA_IOCTL);
188 - udelay(10);
189 + bcma_core_wait_value(core, BCMA_RESET_ST, ~0, 0, 300);
190
191 bcma_awrite32(core, BCMA_RESET_CTL, BCMA_RESET_CTL_RESET);
192 bcma_aread32(core, BCMA_RESET_CTL);
193 udelay(1);
194 +
195 + bcma_awrite32(core, BCMA_IOCTL, flags);
196 + bcma_aread32(core, BCMA_IOCTL);
197 + udelay(10);
198 }
199 EXPORT_SYMBOL_GPL(bcma_core_disable);
200
201 @@ -43,6 +64,7 @@ int bcma_core_enable(struct bcma_device
202 bcma_aread32(core, BCMA_IOCTL);
203
204 bcma_awrite32(core, BCMA_RESET_CTL, 0);
205 + bcma_aread32(core, BCMA_RESET_CTL);
206 udelay(1);
207
208 bcma_awrite32(core, BCMA_IOCTL, (BCMA_IOCTL_CLK | flags));
209 @@ -65,7 +87,7 @@ void bcma_core_set_clockmode(struct bcma
210 switch (clkmode) {
211 case BCMA_CLKMODE_FAST:
212 bcma_set32(core, BCMA_CLKCTLST, BCMA_CLKCTLST_FORCEHT);
213 - udelay(64);
214 + usleep_range(64, 300);
215 for (i = 0; i < 1500; i++) {
216 if (bcma_read32(core, BCMA_CLKCTLST) &
217 BCMA_CLKCTLST_HAVEHT) {
218 @@ -104,7 +126,13 @@ void bcma_core_pll_ctl(struct bcma_devic
219 if (i)
220 bcma_err(core->bus, "PLL enable timeout\n");
221 } else {
222 - bcma_warn(core->bus, "Disabling PLL not supported yet!\n");
223 + /*
224 + * Mask the PLL but don't wait for it to be disabled. PLL may be
225 + * shared between cores and will be still up if there is another
226 + * core using it.
227 + */
228 + bcma_mask32(core, BCMA_CLKCTLST, ~req);
229 + bcma_read32(core, BCMA_CLKCTLST);
230 }
231 }
232 EXPORT_SYMBOL_GPL(bcma_core_pll_ctl);
233 --- a/drivers/bcma/driver_chipcommon.c
234 +++ b/drivers/bcma/driver_chipcommon.c
235 @@ -4,12 +4,15 @@
236 *
237 * Copyright 2005, Broadcom Corporation
238 * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
239 + * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
240 *
241 * Licensed under the GNU/GPL. See COPYING for details.
242 */
243
244 #include "bcma_private.h"
245 +#include <linux/bcm47xx_wdt.h>
246 #include <linux/export.h>
247 +#include <linux/platform_device.h>
248 #include <linux/bcma/bcma.h>
249
250 static inline u32 bcma_cc_write32_masked(struct bcma_drv_cc *cc, u16 offset,
251 @@ -22,23 +25,130 @@ static inline u32 bcma_cc_write32_masked
252 return value;
253 }
254
255 -void bcma_core_chipcommon_init(struct bcma_drv_cc *cc)
256 +u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc)
257 {
258 - u32 leddc_on = 10;
259 - u32 leddc_off = 90;
260 + if (cc->capabilities & BCMA_CC_CAP_PMU)
261 + return bcma_pmu_get_alp_clock(cc);
262
263 - if (cc->setup_done)
264 + return 20000000;
265 +}
266 +EXPORT_SYMBOL_GPL(bcma_chipco_get_alp_clock);
267 +
268 +static u32 bcma_chipco_watchdog_get_max_timer(struct bcma_drv_cc *cc)
269 +{
270 + struct bcma_bus *bus = cc->core->bus;
271 + u32 nb;
272 +
273 + if (cc->capabilities & BCMA_CC_CAP_PMU) {
274 + if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706)
275 + nb = 32;
276 + else if (cc->core->id.rev < 26)
277 + nb = 16;
278 + else
279 + nb = (cc->core->id.rev >= 37) ? 32 : 24;
280 + } else {
281 + nb = 28;
282 + }
283 + if (nb == 32)
284 + return 0xffffffff;
285 + else
286 + return (1 << nb) - 1;
287 +}
288 +
289 +static u32 bcma_chipco_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt,
290 + u32 ticks)
291 +{
292 + struct bcma_drv_cc *cc = bcm47xx_wdt_get_drvdata(wdt);
293 +
294 + return bcma_chipco_watchdog_timer_set(cc, ticks);
295 +}
296 +
297 +static u32 bcma_chipco_watchdog_timer_set_ms_wdt(struct bcm47xx_wdt *wdt,
298 + u32 ms)
299 +{
300 + struct bcma_drv_cc *cc = bcm47xx_wdt_get_drvdata(wdt);
301 + u32 ticks;
302 +
303 + ticks = bcma_chipco_watchdog_timer_set(cc, cc->ticks_per_ms * ms);
304 + return ticks / cc->ticks_per_ms;
305 +}
306 +
307 +static int bcma_chipco_watchdog_ticks_per_ms(struct bcma_drv_cc *cc)
308 +{
309 + struct bcma_bus *bus = cc->core->bus;
310 +
311 + if (cc->capabilities & BCMA_CC_CAP_PMU) {
312 + if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706)
313 + /* 4706 CC and PMU watchdogs are clocked at 1/4 of ALP clock */
314 + return bcma_chipco_get_alp_clock(cc) / 4000;
315 + else
316 + /* based on 32KHz ILP clock */
317 + return 32;
318 + } else {
319 + return bcma_chipco_get_alp_clock(cc) / 1000;
320 + }
321 +}
322 +
323 +int bcma_chipco_watchdog_register(struct bcma_drv_cc *cc)
324 +{
325 + struct bcm47xx_wdt wdt = {};
326 + struct platform_device *pdev;
327 +
328 + wdt.driver_data = cc;
329 + wdt.timer_set = bcma_chipco_watchdog_timer_set_wdt;
330 + wdt.timer_set_ms = bcma_chipco_watchdog_timer_set_ms_wdt;
331 + wdt.max_timer_ms = bcma_chipco_watchdog_get_max_timer(cc) / cc->ticks_per_ms;
332 +
333 + pdev = platform_device_register_data(NULL, "bcm47xx-wdt",
334 + cc->core->bus->num, &wdt,
335 + sizeof(wdt));
336 + if (IS_ERR(pdev))
337 + return PTR_ERR(pdev);
338 +
339 + cc->watchdog = pdev;
340 +
341 + return 0;
342 +}
343 +
344 +void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc)
345 +{
346 + if (cc->early_setup_done)
347 return;
348
349 + spin_lock_init(&cc->gpio_lock);
350 +
351 if (cc->core->id.rev >= 11)
352 cc->status = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
353 cc->capabilities = bcma_cc_read32(cc, BCMA_CC_CAP);
354 if (cc->core->id.rev >= 35)
355 cc->capabilities_ext = bcma_cc_read32(cc, BCMA_CC_CAP_EXT);
356
357 + if (cc->capabilities & BCMA_CC_CAP_PMU)
358 + bcma_pmu_early_init(cc);
359 +
360 + cc->early_setup_done = true;
361 +}
362 +
363 +void bcma_core_chipcommon_init(struct bcma_drv_cc *cc)
364 +{
365 + u32 leddc_on = 10;
366 + u32 leddc_off = 90;
367 +
368 + if (cc->setup_done)
369 + return;
370 +
371 + bcma_core_chipcommon_early_init(cc);
372 +
373 if (cc->core->id.rev >= 20) {
374 - bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, 0);
375 - bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, 0);
376 + u32 pullup = 0, pulldown = 0;
377 +
378 + if (cc->core->bus->chipinfo.id == BCMA_CHIP_ID_BCM43142) {
379 + pullup = 0x402e0;
380 + pulldown = 0x20500;
381 + }
382 +
383 + bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, pullup);
384 + bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, pulldown);
385 }
386
387 if (cc->capabilities & BCMA_CC_CAP_PMU)
388 @@ -56,15 +166,33 @@ void bcma_core_chipcommon_init(struct bc
389 ((leddc_on << BCMA_CC_GPIOTIMER_ONTIME_SHIFT) |
390 (leddc_off << BCMA_CC_GPIOTIMER_OFFTIME_SHIFT)));
391 }
392 + cc->ticks_per_ms = bcma_chipco_watchdog_ticks_per_ms(cc);
393
394 cc->setup_done = true;
395 }
396
397 /* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */
398 -void bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks)
399 +u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks)
400 {
401 - /* instant NMI */
402 - bcma_cc_write32(cc, BCMA_CC_WATCHDOG, ticks);
403 + u32 maxt;
404 + enum bcma_clkmode clkmode;
405 +
406 + maxt = bcma_chipco_watchdog_get_max_timer(cc);
407 + if (cc->capabilities & BCMA_CC_CAP_PMU) {
408 + if (ticks == 1)
409 + ticks = 2;
410 + else if (ticks > maxt)
411 + ticks = maxt;
412 + bcma_cc_write32(cc, BCMA_CC_PMU_WATCHDOG, ticks);
413 + } else {
414 + clkmode = ticks ? BCMA_CLKMODE_FAST : BCMA_CLKMODE_DYNAMIC;
415 + bcma_core_set_clockmode(cc->core, clkmode);
416 + if (ticks > maxt)
417 + ticks = maxt;
418 + /* instant NMI */
419 + bcma_cc_write32(cc, BCMA_CC_WATCHDOG, ticks);
420 + }
421 + return ticks;
422 }
423
424 void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value)
425 @@ -84,28 +212,99 @@ u32 bcma_chipco_gpio_in(struct bcma_drv_
426
427 u32 bcma_chipco_gpio_out(struct bcma_drv_cc *cc, u32 mask, u32 value)
428 {
429 - return bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUT, mask, value);
430 + unsigned long flags;
431 + u32 res;
432 +
433 + spin_lock_irqsave(&cc->gpio_lock, flags);
434 + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUT, mask, value);
435 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
436 +
437 + return res;
438 }
439 +EXPORT_SYMBOL_GPL(bcma_chipco_gpio_out);
440
441 u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value)
442 {
443 - return bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUTEN, mask, value);
444 + unsigned long flags;
445 + u32 res;
446 +
447 + spin_lock_irqsave(&cc->gpio_lock, flags);
448 + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUTEN, mask, value);
449 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
450 +
451 + return res;
452 }
453 +EXPORT_SYMBOL_GPL(bcma_chipco_gpio_outen);
454
455 +/*
456 + * If the bit is set to 0, chipcommon controlls this GPIO,
457 + * if the bit is set to 1, it is used by some part of the chip and not our code.
458 + */
459 u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value)
460 {
461 - return bcma_cc_write32_masked(cc, BCMA_CC_GPIOCTL, mask, value);
462 + unsigned long flags;
463 + u32 res;
464 +
465 + spin_lock_irqsave(&cc->gpio_lock, flags);
466 + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOCTL, mask, value);
467 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
468 +
469 + return res;
470 }
471 EXPORT_SYMBOL_GPL(bcma_chipco_gpio_control);
472
473 u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value)
474 {
475 - return bcma_cc_write32_masked(cc, BCMA_CC_GPIOIRQ, mask, value);
476 + unsigned long flags;
477 + u32 res;
478 +
479 + spin_lock_irqsave(&cc->gpio_lock, flags);
480 + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOIRQ, mask, value);
481 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
482 +
483 + return res;
484 }
485
486 u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value)
487 {
488 - return bcma_cc_write32_masked(cc, BCMA_CC_GPIOPOL, mask, value);
489 + unsigned long flags;
490 + u32 res;
491 +
492 + spin_lock_irqsave(&cc->gpio_lock, flags);
493 + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPOL, mask, value);
494 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
495 +
496 + return res;
497 +}
498 +
499 +u32 bcma_chipco_gpio_pullup(struct bcma_drv_cc *cc, u32 mask, u32 value)
500 +{
501 + unsigned long flags;
502 + u32 res;
503 +
504 + if (cc->core->id.rev < 20)
505 + return 0;
506 +
507 + spin_lock_irqsave(&cc->gpio_lock, flags);
508 + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPULLUP, mask, value);
509 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
510 +
511 + return res;
512 +}
513 +
514 +u32 bcma_chipco_gpio_pulldown(struct bcma_drv_cc *cc, u32 mask, u32 value)
515 +{
516 + unsigned long flags;
517 + u32 res;
518 +
519 + if (cc->core->id.rev < 20)
520 + return 0;
521 +
522 + spin_lock_irqsave(&cc->gpio_lock, flags);
523 + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPULLDOWN, mask, value);
524 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
525 +
526 + return res;
527 }
528
529 #ifdef CONFIG_BCMA_DRIVER_MIPS
530 @@ -118,8 +317,7 @@ void bcma_chipco_serial_init(struct bcma
531 struct bcma_serial_port *ports = cc->serial_ports;
532
533 if (ccrev >= 11 && ccrev != 15) {
534 - /* Fixed ALP clock */
535 - baud_base = bcma_pmu_alp_clock(cc);
536 + baud_base = bcma_chipco_get_alp_clock(cc);
537 if (ccrev >= 21) {
538 /* Turn off UART clock before switching clocksource. */
539 bcma_cc_write32(cc, BCMA_CC_CORECTL,
540 @@ -141,7 +339,7 @@ void bcma_chipco_serial_init(struct bcma
541 return;
542 }
543
544 - irq = bcma_core_mips_irq(cc->core);
545 + irq = bcma_core_irq(cc->core);
546
547 /* Determine the registers of the UARTs */
548 cc->nr_serial_ports = (cc->capabilities & BCMA_CC_CAP_NRUART);
549 --- a/drivers/bcma/driver_chipcommon_nflash.c
550 +++ b/drivers/bcma/driver_chipcommon_nflash.c
551 @@ -5,15 +5,40 @@
552 * Licensed under the GNU/GPL. See COPYING for details.
553 */
554
555 +#include "bcma_private.h"
556 +
557 +#include <linux/platform_device.h>
558 #include <linux/bcma/bcma.h>
559 -#include <linux/bcma/bcma_driver_chipcommon.h>
560 -#include <linux/delay.h>
561
562 -#include "bcma_private.h"
563 +struct platform_device bcma_nflash_dev = {
564 + .name = "bcma_nflash",
565 + .num_resources = 0,
566 +};
567
568 /* Initialize NAND flash access */
569 int bcma_nflash_init(struct bcma_drv_cc *cc)
570 {
571 - bcma_err(cc->core->bus, "NAND flash support is broken\n");
572 + struct bcma_bus *bus = cc->core->bus;
573 +
574 + if (bus->chipinfo.id != BCMA_CHIP_ID_BCM4706 &&
575 + cc->core->id.rev != 38) {
576 + bcma_err(bus, "NAND flash on unsupported board!\n");
577 + return -ENOTSUPP;
578 + }
579 +
580 + if (!(cc->capabilities & BCMA_CC_CAP_NFLASH)) {
581 + bcma_err(bus, "NAND flash not present according to ChipCommon\n");
582 + return -ENODEV;
583 + }
584 +
585 + cc->nflash.present = true;
586 + if (cc->core->id.rev == 38 &&
587 + (cc->status & BCMA_CC_CHIPST_5357_NAND_BOOT))
588 + cc->nflash.boot = true;
589 +
590 + /* Prepare platform device, but don't register it yet. It's too early,
591 + * malloc (required by device_private_init) is not available yet. */
592 + bcma_nflash_dev.dev.platform_data = &cc->nflash;
593 +
594 return 0;
595 }
596 --- a/drivers/bcma/driver_chipcommon_pmu.c
597 +++ b/drivers/bcma/driver_chipcommon_pmu.c
598 @@ -13,12 +13,13 @@
599 #include <linux/export.h>
600 #include <linux/bcma/bcma.h>
601
602 -static u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset)
603 +u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset)
604 {
605 bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
606 bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
607 return bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
608 }
609 +EXPORT_SYMBOL_GPL(bcma_chipco_pll_read);
610
611 void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset, u32 value)
612 {
613 @@ -55,6 +56,109 @@ void bcma_chipco_regctl_maskset(struct b
614 }
615 EXPORT_SYMBOL_GPL(bcma_chipco_regctl_maskset);
616
617 +static u32 bcma_pmu_xtalfreq(struct bcma_drv_cc *cc)
618 +{
619 + u32 ilp_ctl, alp_hz;
620 +
621 + if (!(bcma_cc_read32(cc, BCMA_CC_PMU_STAT) &
622 + BCMA_CC_PMU_STAT_EXT_LPO_AVAIL))
623 + return 0;
624 +
625 + bcma_cc_write32(cc, BCMA_CC_PMU_XTAL_FREQ,
626 + BIT(BCMA_CC_PMU_XTAL_FREQ_MEASURE_SHIFT));
627 + usleep_range(1000, 2000);
628 +
629 + ilp_ctl = bcma_cc_read32(cc, BCMA_CC_PMU_XTAL_FREQ);
630 + ilp_ctl &= BCMA_CC_PMU_XTAL_FREQ_ILPCTL_MASK;
631 +
632 + bcma_cc_write32(cc, BCMA_CC_PMU_XTAL_FREQ, 0);
633 +
634 + alp_hz = ilp_ctl * 32768 / 4;
635 + return (alp_hz + 50000) / 100000 * 100;
636 +}
637 +
638 +static void bcma_pmu2_pll_init0(struct bcma_drv_cc *cc, u32 xtalfreq)
639 +{
640 + struct bcma_bus *bus = cc->core->bus;
641 + u32 freq_tgt_target = 0, freq_tgt_current;
642 + u32 pll0, mask;
643 +
644 + switch (bus->chipinfo.id) {
645 + case BCMA_CHIP_ID_BCM43142:
646 + /* pmu2_xtaltab0_adfll_485 */
647 + switch (xtalfreq) {
648 + case 12000:
649 + freq_tgt_target = 0x50D52;
650 + break;
651 + case 20000:
652 + freq_tgt_target = 0x307FE;
653 + break;
654 + case 26000:
655 + freq_tgt_target = 0x254EA;
656 + break;
657 + case 37400:
658 + freq_tgt_target = 0x19EF8;
659 + break;
660 + case 52000:
661 + freq_tgt_target = 0x12A75;
662 + break;
663 + }
664 + break;
665 + }
666 +
667 + if (!freq_tgt_target) {
668 + bcma_err(bus, "Unknown TGT frequency for xtalfreq %d\n",
669 + xtalfreq);
670 + return;
671 + }
672 +
673 + pll0 = bcma_chipco_pll_read(cc, BCMA_CC_PMU15_PLL_PLLCTL0);
674 + freq_tgt_current = (pll0 & BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK) >>
675 + BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT;
676 +
677 + if (freq_tgt_current == freq_tgt_target) {
678 + bcma_debug(bus, "Target TGT frequency already set\n");
679 + return;
680 + }
681 +
682 + /* Turn off PLL */
683 + switch (bus->chipinfo.id) {
684 + case BCMA_CHIP_ID_BCM43142:
685 + mask = (u32)~(BCMA_RES_4314_HT_AVAIL |
686 + BCMA_RES_4314_MACPHY_CLK_AVAIL);
687 +
688 + bcma_cc_mask32(cc, BCMA_CC_PMU_MINRES_MSK, mask);
689 + bcma_cc_mask32(cc, BCMA_CC_PMU_MAXRES_MSK, mask);
690 + bcma_wait_value(cc->core, BCMA_CLKCTLST,
691 + BCMA_CLKCTLST_HAVEHT, 0, 20000);
692 + break;
693 + }
694 +
695 + pll0 &= ~BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK;
696 + pll0 |= freq_tgt_target << BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT;
697 + bcma_chipco_pll_write(cc, BCMA_CC_PMU15_PLL_PLLCTL0, pll0);
698 +
699 + /* Flush */
700 + if (cc->pmu.rev >= 2)
701 + bcma_cc_set32(cc, BCMA_CC_PMU_CTL, BCMA_CC_PMU_CTL_PLL_UPD);
702 +
703 + /* TODO: Do we need to update OTP? */
704 +}
705 +
706 +static void bcma_pmu_pll_init(struct bcma_drv_cc *cc)
707 +{
708 + struct bcma_bus *bus = cc->core->bus;
709 + u32 xtalfreq = bcma_pmu_xtalfreq(cc);
710 +
711 + switch (bus->chipinfo.id) {
712 + case BCMA_CHIP_ID_BCM43142:
713 + if (xtalfreq == 0)
714 + xtalfreq = 20000;
715 + bcma_pmu2_pll_init0(cc, xtalfreq);
716 + break;
717 + }
718 +}
719 +
720 static void bcma_pmu_resources_init(struct bcma_drv_cc *cc)
721 {
722 struct bcma_bus *bus = cc->core->bus;
723 @@ -65,6 +169,25 @@ static void bcma_pmu_resources_init(stru
724 min_msk = 0x200D;
725 max_msk = 0xFFFF;
726 break;
727 + case BCMA_CHIP_ID_BCM43142:
728 + min_msk = BCMA_RES_4314_LPLDO_PU |
729 + BCMA_RES_4314_PMU_SLEEP_DIS |
730 + BCMA_RES_4314_PMU_BG_PU |
731 + BCMA_RES_4314_CBUCK_LPOM_PU |
732 + BCMA_RES_4314_CBUCK_PFM_PU |
733 + BCMA_RES_4314_CLDO_PU |
734 + BCMA_RES_4314_LPLDO2_LVM |
735 + BCMA_RES_4314_WL_PMU_PU |
736 + BCMA_RES_4314_LDO3P3_PU |
737 + BCMA_RES_4314_OTP_PU |
738 + BCMA_RES_4314_WL_PWRSW_PU |
739 + BCMA_RES_4314_LQ_AVAIL |
740 + BCMA_RES_4314_LOGIC_RET |
741 + BCMA_RES_4314_MEM_SLEEP |
742 + BCMA_RES_4314_MACPHY_RET |
743 + BCMA_RES_4314_WL_CORE_READY;
744 + max_msk = 0x3FFFFFFF;
745 + break;
746 default:
747 bcma_debug(bus, "PMU resource config unknown or not needed for device 0x%04X\n",
748 bus->chipinfo.id);
749 @@ -76,7 +199,10 @@ static void bcma_pmu_resources_init(stru
750 if (max_msk)
751 bcma_cc_write32(cc, BCMA_CC_PMU_MAXRES_MSK, max_msk);
752
753 - /* Add some delay; allow resources to come up and settle. */
754 + /*
755 + * Add some delay; allow resources to come up and settle.
756 + * Delay is required for SoC (early init).
757 + */
758 mdelay(2);
759 }
760
761 @@ -101,7 +227,7 @@ void bcma_chipco_bcm4331_ext_pa_lines_ct
762 bcma_cc_write32(cc, BCMA_CC_CHIPCTL, val);
763 }
764
765 -void bcma_pmu_workarounds(struct bcma_drv_cc *cc)
766 +static void bcma_pmu_workarounds(struct bcma_drv_cc *cc)
767 {
768 struct bcma_bus *bus = cc->core->bus;
769
770 @@ -141,7 +267,7 @@ void bcma_pmu_workarounds(struct bcma_dr
771 }
772 }
773
774 -void bcma_pmu_init(struct bcma_drv_cc *cc)
775 +void bcma_pmu_early_init(struct bcma_drv_cc *cc)
776 {
777 u32 pmucap;
778
779 @@ -150,7 +276,10 @@ void bcma_pmu_init(struct bcma_drv_cc *c
780
781 bcma_debug(cc->core->bus, "Found rev %u PMU (capabilities 0x%08X)\n",
782 cc->pmu.rev, pmucap);
783 +}
784
785 +void bcma_pmu_init(struct bcma_drv_cc *cc)
786 +{
787 if (cc->pmu.rev == 1)
788 bcma_cc_mask32(cc, BCMA_CC_PMU_CTL,
789 ~BCMA_CC_PMU_CTL_NOILPONW);
790 @@ -158,28 +287,45 @@ void bcma_pmu_init(struct bcma_drv_cc *c
791 bcma_cc_set32(cc, BCMA_CC_PMU_CTL,
792 BCMA_CC_PMU_CTL_NOILPONW);
793
794 + bcma_pmu_pll_init(cc);
795 bcma_pmu_resources_init(cc);
796 bcma_pmu_workarounds(cc);
797 }
798
799 -u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc)
800 +u32 bcma_pmu_get_alp_clock(struct bcma_drv_cc *cc)
801 {
802 struct bcma_bus *bus = cc->core->bus;
803
804 switch (bus->chipinfo.id) {
805 + case BCMA_CHIP_ID_BCM4313:
806 + case BCMA_CHIP_ID_BCM43224:
807 + case BCMA_CHIP_ID_BCM43225:
808 + case BCMA_CHIP_ID_BCM43227:
809 + case BCMA_CHIP_ID_BCM43228:
810 + case BCMA_CHIP_ID_BCM4331:
811 + case BCMA_CHIP_ID_BCM43421:
812 + case BCMA_CHIP_ID_BCM43428:
813 + case BCMA_CHIP_ID_BCM43431:
814 case BCMA_CHIP_ID_BCM4716:
815 - case BCMA_CHIP_ID_BCM4748:
816 case BCMA_CHIP_ID_BCM47162:
817 - case BCMA_CHIP_ID_BCM4313:
818 - case BCMA_CHIP_ID_BCM5357:
819 + case BCMA_CHIP_ID_BCM4748:
820 case BCMA_CHIP_ID_BCM4749:
821 + case BCMA_CHIP_ID_BCM5357:
822 case BCMA_CHIP_ID_BCM53572:
823 + case BCMA_CHIP_ID_BCM6362:
824 /* always 20Mhz */
825 return 20000 * 1000;
826 - case BCMA_CHIP_ID_BCM5356:
827 case BCMA_CHIP_ID_BCM4706:
828 + case BCMA_CHIP_ID_BCM5356:
829 /* always 25Mhz */
830 return 25000 * 1000;
831 + case BCMA_CHIP_ID_BCM43460:
832 + case BCMA_CHIP_ID_BCM4352:
833 + case BCMA_CHIP_ID_BCM4360:
834 + if (cc->status & BCMA_CC_CHIPST_4360_XTAL_40MZ)
835 + return 40000 * 1000;
836 + else
837 + return 20000 * 1000;
838 default:
839 bcma_warn(bus, "No ALP clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
840 bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_ALP_CLOCK);
841 @@ -190,7 +336,7 @@ u32 bcma_pmu_alp_clock(struct bcma_drv_c
842 /* Find the output of the "m" pll divider given pll controls that start with
843 * pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc.
844 */
845 -static u32 bcma_pmu_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m)
846 +static u32 bcma_pmu_pll_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m)
847 {
848 u32 tmp, div, ndiv, p1, p2, fc;
849 struct bcma_bus *bus = cc->core->bus;
850 @@ -219,14 +365,14 @@ static u32 bcma_pmu_clock(struct bcma_dr
851 ndiv = (tmp & BCMA_CC_PPL_NDIV_MASK) >> BCMA_CC_PPL_NDIV_SHIFT;
852
853 /* Do calculation in Mhz */
854 - fc = bcma_pmu_alp_clock(cc) / 1000000;
855 + fc = bcma_pmu_get_alp_clock(cc) / 1000000;
856 fc = (p1 * ndiv * fc) / p2;
857
858 /* Return clock in Hertz */
859 return (fc / div) * 1000000;
860 }
861
862 -static u32 bcma_pmu_clock_bcm4706(struct bcma_drv_cc *cc, u32 pll0, u32 m)
863 +static u32 bcma_pmu_pll_clock_bcm4706(struct bcma_drv_cc *cc, u32 pll0, u32 m)
864 {
865 u32 tmp, ndiv, p1div, p2div;
866 u32 clock;
867 @@ -257,7 +403,7 @@ static u32 bcma_pmu_clock_bcm4706(struct
868 }
869
870 /* query bus clock frequency for PMU-enabled chipcommon */
871 -u32 bcma_pmu_get_clockcontrol(struct bcma_drv_cc *cc)
872 +u32 bcma_pmu_get_bus_clock(struct bcma_drv_cc *cc)
873 {
874 struct bcma_bus *bus = cc->core->bus;
875
876 @@ -265,40 +411,43 @@ u32 bcma_pmu_get_clockcontrol(struct bcm
877 case BCMA_CHIP_ID_BCM4716:
878 case BCMA_CHIP_ID_BCM4748:
879 case BCMA_CHIP_ID_BCM47162:
880 - return bcma_pmu_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0,
881 - BCMA_CC_PMU5_MAINPLL_SSB);
882 + return bcma_pmu_pll_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0,
883 + BCMA_CC_PMU5_MAINPLL_SSB);
884 case BCMA_CHIP_ID_BCM5356:
885 - return bcma_pmu_clock(cc, BCMA_CC_PMU5356_MAINPLL_PLL0,
886 - BCMA_CC_PMU5_MAINPLL_SSB);
887 + return bcma_pmu_pll_clock(cc, BCMA_CC_PMU5356_MAINPLL_PLL0,
888 + BCMA_CC_PMU5_MAINPLL_SSB);
889 case BCMA_CHIP_ID_BCM5357:
890 case BCMA_CHIP_ID_BCM4749:
891 - return bcma_pmu_clock(cc, BCMA_CC_PMU5357_MAINPLL_PLL0,
892 - BCMA_CC_PMU5_MAINPLL_SSB);
893 + return bcma_pmu_pll_clock(cc, BCMA_CC_PMU5357_MAINPLL_PLL0,
894 + BCMA_CC_PMU5_MAINPLL_SSB);
895 case BCMA_CHIP_ID_BCM4706:
896 - return bcma_pmu_clock_bcm4706(cc, BCMA_CC_PMU4706_MAINPLL_PLL0,
897 - BCMA_CC_PMU5_MAINPLL_SSB);
898 + return bcma_pmu_pll_clock_bcm4706(cc,
899 + BCMA_CC_PMU4706_MAINPLL_PLL0,
900 + BCMA_CC_PMU5_MAINPLL_SSB);
901 case BCMA_CHIP_ID_BCM53572:
902 return 75000000;
903 default:
904 - bcma_warn(bus, "No backplane clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
905 + bcma_warn(bus, "No bus clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
906 bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_HT_CLOCK);
907 }
908 return BCMA_CC_PMU_HT_CLOCK;
909 }
910 +EXPORT_SYMBOL_GPL(bcma_pmu_get_bus_clock);
911
912 /* query cpu clock frequency for PMU-enabled chipcommon */
913 -u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc)
914 +u32 bcma_pmu_get_cpu_clock(struct bcma_drv_cc *cc)
915 {
916 struct bcma_bus *bus = cc->core->bus;
917
918 if (bus->chipinfo.id == BCMA_CHIP_ID_BCM53572)
919 return 300000000;
920
921 + /* New PMUs can have different clock for bus and CPU */
922 if (cc->pmu.rev >= 5) {
923 u32 pll;
924 switch (bus->chipinfo.id) {
925 case BCMA_CHIP_ID_BCM4706:
926 - return bcma_pmu_clock_bcm4706(cc,
927 + return bcma_pmu_pll_clock_bcm4706(cc,
928 BCMA_CC_PMU4706_MAINPLL_PLL0,
929 BCMA_CC_PMU5_MAINPLL_CPU);
930 case BCMA_CHIP_ID_BCM5356:
931 @@ -313,10 +462,11 @@ u32 bcma_pmu_get_clockcpu(struct bcma_dr
932 break;
933 }
934
935 - return bcma_pmu_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU);
936 + return bcma_pmu_pll_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU);
937 }
938
939 - return bcma_pmu_get_clockcontrol(cc);
940 + /* On old PMUs CPU has the same clock as the bus */
941 + return bcma_pmu_get_bus_clock(cc);
942 }
943
944 static void bcma_pmu_spuravoid_pll_write(struct bcma_drv_cc *cc, u32 offset,
945 @@ -362,7 +512,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
946 tmp |= (bcm5357_bcm43236_ndiv[spuravoid]) << BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT;
947 bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp);
948
949 - tmp = 1 << 10;
950 + tmp = BCMA_CC_PMU_CTL_PLL_UPD;
951 break;
952
953 case BCMA_CHIP_ID_BCM4331:
954 @@ -383,7 +533,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
955 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
956 0x03000a08);
957 }
958 - tmp = 1 << 10;
959 + tmp = BCMA_CC_PMU_CTL_PLL_UPD;
960 break;
961
962 case BCMA_CHIP_ID_BCM43224:
963 @@ -416,7 +566,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
964 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
965 0x88888815);
966 }
967 - tmp = 1 << 10;
968 + tmp = BCMA_CC_PMU_CTL_PLL_UPD;
969 break;
970
971 case BCMA_CHIP_ID_BCM4716:
972 @@ -450,7 +600,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
973 0x88888815);
974 }
975
976 - tmp = 3 << 9;
977 + tmp = BCMA_CC_PMU_CTL_PLL_UPD | BCMA_CC_PMU_CTL_NOILPONW;
978 break;
979
980 case BCMA_CHIP_ID_BCM43227:
981 @@ -486,7 +636,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
982 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
983 0x88888815);
984 }
985 - tmp = 1 << 10;
986 + tmp = BCMA_CC_PMU_CTL_PLL_UPD;
987 break;
988 default:
989 bcma_err(bus, "Unknown spuravoidance settings for chip 0x%04X, not changing PLL\n",
990 --- a/drivers/bcma/driver_chipcommon_sflash.c
991 +++ b/drivers/bcma/driver_chipcommon_sflash.c
992 @@ -5,15 +5,161 @@
993 * Licensed under the GNU/GPL. See COPYING for details.
994 */
995
996 +#include "bcma_private.h"
997 +
998 +#include <linux/platform_device.h>
999 #include <linux/bcma/bcma.h>
1000 -#include <linux/bcma/bcma_driver_chipcommon.h>
1001 -#include <linux/delay.h>
1002
1003 -#include "bcma_private.h"
1004 +static struct resource bcma_sflash_resource = {
1005 + .name = "bcma_sflash",
1006 + .start = BCMA_SOC_FLASH2,
1007 + .end = 0,
1008 + .flags = IORESOURCE_MEM | IORESOURCE_READONLY,
1009 +};
1010 +
1011 +struct platform_device bcma_sflash_dev = {
1012 + .name = "bcma_sflash",
1013 + .resource = &bcma_sflash_resource,
1014 + .num_resources = 1,
1015 +};
1016 +
1017 +struct bcma_sflash_tbl_e {
1018 + char *name;
1019 + u32 id;
1020 + u32 blocksize;
1021 + u16 numblocks;
1022 +};
1023 +
1024 +static const struct bcma_sflash_tbl_e bcma_sflash_st_tbl[] = {
1025 + { "M25P20", 0x11, 0x10000, 4, },
1026 + { "M25P40", 0x12, 0x10000, 8, },
1027 +
1028 + { "M25P16", 0x14, 0x10000, 32, },
1029 + { "M25P32", 0x15, 0x10000, 64, },
1030 + { "M25P64", 0x16, 0x10000, 128, },
1031 + { "M25FL128", 0x17, 0x10000, 256, },
1032 + { 0 },
1033 +};
1034 +
1035 +static const struct bcma_sflash_tbl_e bcma_sflash_sst_tbl[] = {
1036 + { "SST25WF512", 1, 0x1000, 16, },
1037 + { "SST25VF512", 0x48, 0x1000, 16, },
1038 + { "SST25WF010", 2, 0x1000, 32, },
1039 + { "SST25VF010", 0x49, 0x1000, 32, },
1040 + { "SST25WF020", 3, 0x1000, 64, },
1041 + { "SST25VF020", 0x43, 0x1000, 64, },
1042 + { "SST25WF040", 4, 0x1000, 128, },
1043 + { "SST25VF040", 0x44, 0x1000, 128, },
1044 + { "SST25VF040B", 0x8d, 0x1000, 128, },
1045 + { "SST25WF080", 5, 0x1000, 256, },
1046 + { "SST25VF080B", 0x8e, 0x1000, 256, },
1047 + { "SST25VF016", 0x41, 0x1000, 512, },
1048 + { "SST25VF032", 0x4a, 0x1000, 1024, },
1049 + { "SST25VF064", 0x4b, 0x1000, 2048, },
1050 + { 0 },
1051 +};
1052 +
1053 +static const struct bcma_sflash_tbl_e bcma_sflash_at_tbl[] = {
1054 + { "AT45DB011", 0xc, 256, 512, },
1055 + { "AT45DB021", 0x14, 256, 1024, },
1056 + { "AT45DB041", 0x1c, 256, 2048, },
1057 + { "AT45DB081", 0x24, 256, 4096, },
1058 + { "AT45DB161", 0x2c, 512, 4096, },
1059 + { "AT45DB321", 0x34, 512, 8192, },
1060 + { "AT45DB642", 0x3c, 1024, 8192, },
1061 + { 0 },
1062 +};
1063 +
1064 +static void bcma_sflash_cmd(struct bcma_drv_cc *cc, u32 opcode)
1065 +{
1066 + int i;
1067 + bcma_cc_write32(cc, BCMA_CC_FLASHCTL,
1068 + BCMA_CC_FLASHCTL_START | opcode);
1069 + for (i = 0; i < 1000; i++) {
1070 + if (!(bcma_cc_read32(cc, BCMA_CC_FLASHCTL) &
1071 + BCMA_CC_FLASHCTL_BUSY))
1072 + return;
1073 + cpu_relax();
1074 + }
1075 + bcma_err(cc->core->bus, "SFLASH control command failed (timeout)!\n");
1076 +}
1077
1078 /* Initialize serial flash access */
1079 int bcma_sflash_init(struct bcma_drv_cc *cc)
1080 {
1081 - bcma_err(cc->core->bus, "Serial flash support is broken\n");
1082 + struct bcma_bus *bus = cc->core->bus;
1083 + struct bcma_sflash *sflash = &cc->sflash;
1084 + const struct bcma_sflash_tbl_e *e;
1085 + u32 id, id2;
1086 +
1087 + switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {
1088 + case BCMA_CC_FLASHT_STSER:
1089 + bcma_sflash_cmd(cc, BCMA_CC_FLASHCTL_ST_DP);
1090 +
1091 + bcma_cc_write32(cc, BCMA_CC_FLASHADDR, 0);
1092 + bcma_sflash_cmd(cc, BCMA_CC_FLASHCTL_ST_RES);
1093 + id = bcma_cc_read32(cc, BCMA_CC_FLASHDATA);
1094 +
1095 + bcma_cc_write32(cc, BCMA_CC_FLASHADDR, 1);
1096 + bcma_sflash_cmd(cc, BCMA_CC_FLASHCTL_ST_RES);
1097 + id2 = bcma_cc_read32(cc, BCMA_CC_FLASHDATA);
1098 +
1099 + switch (id) {
1100 + case 0xbf:
1101 + for (e = bcma_sflash_sst_tbl; e->name; e++) {
1102 + if (e->id == id2)
1103 + break;
1104 + }
1105 + break;
1106 + case 0x13:
1107 + return -ENOTSUPP;
1108 + default:
1109 + for (e = bcma_sflash_st_tbl; e->name; e++) {
1110 + if (e->id == id)
1111 + break;
1112 + }
1113 + break;
1114 + }
1115 + if (!e->name) {
1116 + bcma_err(bus, "Unsupported ST serial flash (id: 0x%X, id2: 0x%X)\n", id, id2);
1117 + return -ENOTSUPP;
1118 + }
1119 +
1120 + break;
1121 + case BCMA_CC_FLASHT_ATSER:
1122 + bcma_sflash_cmd(cc, BCMA_CC_FLASHCTL_AT_STATUS);
1123 + id = bcma_cc_read32(cc, BCMA_CC_FLASHDATA) & 0x3c;
1124 +
1125 + for (e = bcma_sflash_at_tbl; e->name; e++) {
1126 + if (e->id == id)
1127 + break;
1128 + }
1129 + if (!e->name) {
1130 + bcma_err(bus, "Unsupported Atmel serial flash (id: 0x%X)\n", id);
1131 + return -ENOTSUPP;
1132 + }
1133 +
1134 + break;
1135 + default:
1136 + bcma_err(bus, "Unsupported flash type\n");
1137 + return -ENOTSUPP;
1138 + }
1139 +
1140 + sflash->window = BCMA_SOC_FLASH2;
1141 + sflash->blocksize = e->blocksize;
1142 + sflash->numblocks = e->numblocks;
1143 + sflash->size = sflash->blocksize * sflash->numblocks;
1144 + sflash->present = true;
1145 +
1146 + bcma_info(bus, "Found %s serial flash (size: %dKiB, blocksize: 0x%X, blocks: %d)\n",
1147 + e->name, sflash->size / 1024, sflash->blocksize,
1148 + sflash->numblocks);
1149 +
1150 + /* Prepare platform device, but don't register it yet. It's too early,
1151 + * malloc (required by device_private_init) is not available yet. */
1152 + bcma_sflash_dev.resource[0].end = bcma_sflash_dev.resource[0].start +
1153 + sflash->size;
1154 + bcma_sflash_dev.dev.platform_data = sflash;
1155 +
1156 return 0;
1157 }
1158 --- /dev/null
1159 +++ b/drivers/bcma/driver_gpio.c
1160 @@ -0,0 +1,114 @@
1161 +/*
1162 + * Broadcom specific AMBA
1163 + * GPIO driver
1164 + *
1165 + * Copyright 2011, Broadcom Corporation
1166 + * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
1167 + *
1168 + * Licensed under the GNU/GPL. See COPYING for details.
1169 + */
1170 +
1171 +#include <linux/gpio.h>
1172 +#include <linux/export.h>
1173 +#include <linux/bcma/bcma.h>
1174 +
1175 +#include "bcma_private.h"
1176 +
1177 +static inline struct bcma_drv_cc *bcma_gpio_get_cc(struct gpio_chip *chip)
1178 +{
1179 + return container_of(chip, struct bcma_drv_cc, gpio);
1180 +}
1181 +
1182 +static int bcma_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
1183 +{
1184 + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
1185 +
1186 + return !!bcma_chipco_gpio_in(cc, 1 << gpio);
1187 +}
1188 +
1189 +static void bcma_gpio_set_value(struct gpio_chip *chip, unsigned gpio,
1190 + int value)
1191 +{
1192 + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
1193 +
1194 + bcma_chipco_gpio_out(cc, 1 << gpio, value ? 1 << gpio : 0);
1195 +}
1196 +
1197 +static int bcma_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
1198 +{
1199 + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
1200 +
1201 + bcma_chipco_gpio_outen(cc, 1 << gpio, 0);
1202 + return 0;
1203 +}
1204 +
1205 +static int bcma_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
1206 + int value)
1207 +{
1208 + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
1209 +
1210 + bcma_chipco_gpio_outen(cc, 1 << gpio, 1 << gpio);
1211 + bcma_chipco_gpio_out(cc, 1 << gpio, value ? 1 << gpio : 0);
1212 + return 0;
1213 +}
1214 +
1215 +static int bcma_gpio_request(struct gpio_chip *chip, unsigned gpio)
1216 +{
1217 + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
1218 +
1219 + bcma_chipco_gpio_control(cc, 1 << gpio, 0);
1220 + /* clear pulldown */
1221 + bcma_chipco_gpio_pulldown(cc, 1 << gpio, 0);
1222 + /* Set pullup */
1223 + bcma_chipco_gpio_pullup(cc, 1 << gpio, 1 << gpio);
1224 +
1225 + return 0;
1226 +}
1227 +
1228 +static void bcma_gpio_free(struct gpio_chip *chip, unsigned gpio)
1229 +{
1230 + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
1231 +
1232 + /* clear pullup */
1233 + bcma_chipco_gpio_pullup(cc, 1 << gpio, 0);
1234 +}
1235 +
1236 +static int bcma_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
1237 +{
1238 + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
1239 +
1240 + if (cc->core->bus->hosttype == BCMA_HOSTTYPE_SOC)
1241 + return bcma_core_irq(cc->core);
1242 + else
1243 + return -EINVAL;
1244 +}
1245 +
1246 +int bcma_gpio_init(struct bcma_drv_cc *cc)
1247 +{
1248 + struct gpio_chip *chip = &cc->gpio;
1249 +
1250 + chip->label = "bcma_gpio";
1251 + chip->owner = THIS_MODULE;
1252 + chip->request = bcma_gpio_request;
1253 + chip->free = bcma_gpio_free;
1254 + chip->get = bcma_gpio_get_value;
1255 + chip->set = bcma_gpio_set_value;
1256 + chip->direction_input = bcma_gpio_direction_input;
1257 + chip->direction_output = bcma_gpio_direction_output;
1258 + chip->to_irq = bcma_gpio_to_irq;
1259 + chip->ngpio = 16;
1260 + /* There is just one SoC in one device and its GPIO addresses should be
1261 + * deterministic to address them more easily. The other buses could get
1262 + * a random base number. */
1263 + if (cc->core->bus->hosttype == BCMA_HOSTTYPE_SOC)
1264 + chip->base = 0;
1265 + else
1266 + chip->base = -1;
1267 +
1268 + return gpiochip_add(chip);
1269 +}
1270 +
1271 +int bcma_gpio_unregister(struct bcma_drv_cc *cc)
1272 +{
1273 + return gpiochip_remove(&cc->gpio);
1274 +}
1275 --- a/drivers/bcma/driver_mips.c
1276 +++ b/drivers/bcma/driver_mips.c
1277 @@ -14,11 +14,33 @@
1278
1279 #include <linux/bcma/bcma.h>
1280
1281 +#include <linux/mtd/physmap.h>
1282 +#include <linux/platform_device.h>
1283 #include <linux/serial.h>
1284 #include <linux/serial_core.h>
1285 #include <linux/serial_reg.h>
1286 #include <linux/time.h>
1287
1288 +static const char * const part_probes[] = { "bcm47xxpart", NULL };
1289 +
1290 +static struct physmap_flash_data bcma_pflash_data = {
1291 + .part_probe_types = part_probes,
1292 +};
1293 +
1294 +static struct resource bcma_pflash_resource = {
1295 + .name = "bcma_pflash",
1296 + .flags = IORESOURCE_MEM,
1297 +};
1298 +
1299 +struct platform_device bcma_pflash_dev = {
1300 + .name = "physmap-flash",
1301 + .dev = {
1302 + .platform_data = &bcma_pflash_data,
1303 + },
1304 + .resource = &bcma_pflash_resource,
1305 + .num_resources = 1,
1306 +};
1307 +
1308 /* The 47162a0 hangs when reading MIPS DMP registers registers */
1309 static inline bool bcma_core_mips_bcm47162a0_quirk(struct bcma_device *dev)
1310 {
1311 @@ -74,28 +96,41 @@ static u32 bcma_core_mips_irqflag(struct
1312 return dev->core_index;
1313 flag = bcma_aread32(dev, BCMA_MIPS_OOBSELOUTA30);
1314
1315 - return flag & 0x1F;
1316 + if (flag)
1317 + return flag & 0x1F;
1318 + else
1319 + return 0x3f;
1320 }
1321
1322 /* Get the MIPS IRQ assignment for a specified device.
1323 * If unassigned, 0 is returned.
1324 + * If disabled, 5 is returned.
1325 + * If not supported, 6 is returned.
1326 */
1327 -unsigned int bcma_core_mips_irq(struct bcma_device *dev)
1328 +static unsigned int bcma_core_mips_irq(struct bcma_device *dev)
1329 {
1330 struct bcma_device *mdev = dev->bus->drv_mips.core;
1331 u32 irqflag;
1332 unsigned int irq;
1333
1334 irqflag = bcma_core_mips_irqflag(dev);
1335 + if (irqflag == 0x3f)
1336 + return 6;
1337
1338 - for (irq = 1; irq <= 4; irq++)
1339 + for (irq = 0; irq <= 4; irq++)
1340 if (bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(irq)) &
1341 (1 << irqflag))
1342 return irq;
1343
1344 - return 0;
1345 + return 5;
1346 +}
1347 +
1348 +unsigned int bcma_core_irq(struct bcma_device *dev)
1349 +{
1350 + unsigned int mips_irq = bcma_core_mips_irq(dev);
1351 + return mips_irq <= 4 ? mips_irq + 2 : 0;
1352 }
1353 -EXPORT_SYMBOL(bcma_core_mips_irq);
1354 +EXPORT_SYMBOL(bcma_core_irq);
1355
1356 static void bcma_core_mips_set_irq(struct bcma_device *dev, unsigned int irq)
1357 {
1358 @@ -114,8 +149,8 @@ static void bcma_core_mips_set_irq(struc
1359 bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0),
1360 bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0)) &
1361 ~(1 << irqflag));
1362 - else
1363 - bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(irq), 0);
1364 + else if (oldirq != 5)
1365 + bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(oldirq), 0);
1366
1367 /* assign the new one */
1368 if (irq == 0) {
1369 @@ -123,9 +158,9 @@ static void bcma_core_mips_set_irq(struc
1370 bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0)) |
1371 (1 << irqflag));
1372 } else {
1373 - u32 oldirqflag = bcma_read32(mdev,
1374 - BCMA_MIPS_MIPS74K_INTMASK(irq));
1375 - if (oldirqflag) {
1376 + u32 irqinitmask = bcma_read32(mdev,
1377 + BCMA_MIPS_MIPS74K_INTMASK(irq));
1378 + if (irqinitmask) {
1379 struct bcma_device *core;
1380
1381 /* backplane irq line is in use, find out who uses
1382 @@ -133,7 +168,7 @@ static void bcma_core_mips_set_irq(struc
1383 */
1384 list_for_each_entry(core, &bus->cores, list) {
1385 if ((1 << bcma_core_mips_irqflag(core)) ==
1386 - oldirqflag) {
1387 + irqinitmask) {
1388 bcma_core_mips_set_irq(core, 0);
1389 break;
1390 }
1391 @@ -143,15 +178,31 @@ static void bcma_core_mips_set_irq(struc
1392 1 << irqflag);
1393 }
1394
1395 - bcma_info(bus, "set_irq: core 0x%04x, irq %d => %d\n",
1396 - dev->id.id, oldirq + 2, irq + 2);
1397 + bcma_debug(bus, "set_irq: core 0x%04x, irq %d => %d\n",
1398 + dev->id.id, oldirq <= 4 ? oldirq + 2 : 0, irq + 2);
1399 +}
1400 +
1401 +static void bcma_core_mips_set_irq_name(struct bcma_bus *bus, unsigned int irq,
1402 + u16 coreid, u8 unit)
1403 +{
1404 + struct bcma_device *core;
1405 +
1406 + core = bcma_find_core_unit(bus, coreid, unit);
1407 + if (!core) {
1408 + bcma_warn(bus,
1409 + "Can not find core (id: 0x%x, unit %i) for IRQ configuration.\n",
1410 + coreid, unit);
1411 + return;
1412 + }
1413 +
1414 + bcma_core_mips_set_irq(core, irq);
1415 }
1416
1417 static void bcma_core_mips_print_irq(struct bcma_device *dev, unsigned int irq)
1418 {
1419 int i;
1420 static const char *irq_name[] = {"2(S)", "3", "4", "5", "6", "D", "I"};
1421 - printk(KERN_INFO KBUILD_MODNAME ": core 0x%04x, irq :", dev->id.id);
1422 + printk(KERN_DEBUG KBUILD_MODNAME ": core 0x%04x, irq :", dev->id.id);
1423 for (i = 0; i <= 6; i++)
1424 printk(" %s%s", irq_name[i], i == irq ? "*" : " ");
1425 printk("\n");
1426 @@ -171,7 +222,7 @@ u32 bcma_cpu_clock(struct bcma_drv_mips
1427 struct bcma_bus *bus = mcore->core->bus;
1428
1429 if (bus->drv_cc.capabilities & BCMA_CC_CAP_PMU)
1430 - return bcma_pmu_get_clockcpu(&bus->drv_cc);
1431 + return bcma_pmu_get_cpu_clock(&bus->drv_cc);
1432
1433 bcma_err(bus, "No PMU available, need this to get the cpu clock\n");
1434 return 0;
1435 @@ -181,85 +232,143 @@ EXPORT_SYMBOL(bcma_cpu_clock);
1436 static void bcma_core_mips_flash_detect(struct bcma_drv_mips *mcore)
1437 {
1438 struct bcma_bus *bus = mcore->core->bus;
1439 + struct bcma_drv_cc *cc = &bus->drv_cc;
1440 + struct bcma_pflash *pflash = &cc->pflash;
1441
1442 - switch (bus->drv_cc.capabilities & BCMA_CC_CAP_FLASHT) {
1443 + switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {
1444 case BCMA_CC_FLASHT_STSER:
1445 case BCMA_CC_FLASHT_ATSER:
1446 bcma_debug(bus, "Found serial flash\n");
1447 - bcma_sflash_init(&bus->drv_cc);
1448 + bcma_sflash_init(cc);
1449 break;
1450 case BCMA_CC_FLASHT_PARA:
1451 bcma_debug(bus, "Found parallel flash\n");
1452 - bus->drv_cc.pflash.window = 0x1c000000;
1453 - bus->drv_cc.pflash.window_size = 0x02000000;
1454 + pflash->present = true;
1455 + pflash->window = BCMA_SOC_FLASH2;
1456 + pflash->window_size = BCMA_SOC_FLASH2_SZ;
1457
1458 - if ((bcma_read32(bus->drv_cc.core, BCMA_CC_FLASH_CFG) &
1459 + if ((bcma_read32(cc->core, BCMA_CC_FLASH_CFG) &
1460 BCMA_CC_FLASH_CFG_DS) == 0)
1461 - bus->drv_cc.pflash.buswidth = 1;
1462 + pflash->buswidth = 1;
1463 else
1464 - bus->drv_cc.pflash.buswidth = 2;
1465 + pflash->buswidth = 2;
1466 +
1467 + bcma_pflash_data.width = pflash->buswidth;
1468 + bcma_pflash_resource.start = pflash->window;
1469 + bcma_pflash_resource.end = pflash->window + pflash->window_size;
1470 +
1471 break;
1472 default:
1473 bcma_err(bus, "Flash type not supported\n");
1474 }
1475
1476 - if (bus->drv_cc.core->id.rev == 38 ||
1477 + if (cc->core->id.rev == 38 ||
1478 bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) {
1479 - if (bus->drv_cc.capabilities & BCMA_CC_CAP_NFLASH) {
1480 + if (cc->capabilities & BCMA_CC_CAP_NFLASH) {
1481 bcma_debug(bus, "Found NAND flash\n");
1482 - bcma_nflash_init(&bus->drv_cc);
1483 + bcma_nflash_init(cc);
1484 }
1485 }
1486 }
1487
1488 +void bcma_core_mips_early_init(struct bcma_drv_mips *mcore)
1489 +{
1490 + struct bcma_bus *bus = mcore->core->bus;
1491 +
1492 + if (mcore->early_setup_done)
1493 + return;
1494 +
1495 + bcma_chipco_serial_init(&bus->drv_cc);
1496 + bcma_core_mips_flash_detect(mcore);
1497 +
1498 + mcore->early_setup_done = true;
1499 +}
1500 +
1501 +static void bcma_fix_i2s_irqflag(struct bcma_bus *bus)
1502 +{
1503 + struct bcma_device *cpu, *pcie, *i2s;
1504 +
1505 + /* Fixup the interrupts in 4716/4748 for i2s core (2010 Broadcom SDK)
1506 + * (IRQ flags > 7 are ignored when setting the interrupt masks)
1507 + */
1508 + if (bus->chipinfo.id != BCMA_CHIP_ID_BCM4716 &&
1509 + bus->chipinfo.id != BCMA_CHIP_ID_BCM4748)
1510 + return;
1511 +
1512 + cpu = bcma_find_core(bus, BCMA_CORE_MIPS_74K);
1513 + pcie = bcma_find_core(bus, BCMA_CORE_PCIE);
1514 + i2s = bcma_find_core(bus, BCMA_CORE_I2S);
1515 + if (cpu && pcie && i2s &&
1516 + bcma_aread32(cpu, BCMA_MIPS_OOBSELINA74) == 0x08060504 &&
1517 + bcma_aread32(pcie, BCMA_MIPS_OOBSELINA74) == 0x08060504 &&
1518 + bcma_aread32(i2s, BCMA_MIPS_OOBSELOUTA30) == 0x88) {
1519 + bcma_awrite32(cpu, BCMA_MIPS_OOBSELINA74, 0x07060504);
1520 + bcma_awrite32(pcie, BCMA_MIPS_OOBSELINA74, 0x07060504);
1521 + bcma_awrite32(i2s, BCMA_MIPS_OOBSELOUTA30, 0x87);
1522 + bcma_debug(bus,
1523 + "Moved i2s interrupt to oob line 7 instead of 8\n");
1524 + }
1525 +}
1526 +
1527 void bcma_core_mips_init(struct bcma_drv_mips *mcore)
1528 {
1529 struct bcma_bus *bus;
1530 struct bcma_device *core;
1531 bus = mcore->core->bus;
1532
1533 - bcma_info(bus, "Initializing MIPS core...\n");
1534 + if (mcore->setup_done)
1535 + return;
1536
1537 - if (!mcore->setup_done)
1538 - mcore->assigned_irqs = 1;
1539 + bcma_debug(bus, "Initializing MIPS core...\n");
1540
1541 - /* Assign IRQs to all cores on the bus */
1542 - list_for_each_entry(core, &bus->cores, list) {
1543 - int mips_irq;
1544 - if (core->irq)
1545 - continue;
1546 -
1547 - mips_irq = bcma_core_mips_irq(core);
1548 - if (mips_irq > 4)
1549 - core->irq = 0;
1550 - else
1551 - core->irq = mips_irq + 2;
1552 - if (core->irq > 5)
1553 - continue;
1554 - switch (core->id.id) {
1555 - case BCMA_CORE_PCI:
1556 - case BCMA_CORE_PCIE:
1557 - case BCMA_CORE_ETHERNET:
1558 - case BCMA_CORE_ETHERNET_GBIT:
1559 - case BCMA_CORE_MAC_GBIT:
1560 - case BCMA_CORE_80211:
1561 - case BCMA_CORE_USB20_HOST:
1562 - /* These devices get their own IRQ line if available,
1563 - * the rest goes on IRQ0
1564 - */
1565 - if (mcore->assigned_irqs <= 4)
1566 - bcma_core_mips_set_irq(core,
1567 - mcore->assigned_irqs++);
1568 - break;
1569 + bcma_core_mips_early_init(mcore);
1570 +
1571 + bcma_fix_i2s_irqflag(bus);
1572 +
1573 + switch (bus->chipinfo.id) {
1574 + case BCMA_CHIP_ID_BCM4716:
1575 + case BCMA_CHIP_ID_BCM4748:
1576 + bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0);
1577 + bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0);
1578 + bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_USB20_HOST, 0);
1579 + bcma_core_mips_set_irq_name(bus, 4, BCMA_CORE_PCIE, 0);
1580 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0);
1581 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_I2S, 0);
1582 + break;
1583 + case BCMA_CHIP_ID_BCM5356:
1584 + case BCMA_CHIP_ID_BCM47162:
1585 + case BCMA_CHIP_ID_BCM53572:
1586 + bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0);
1587 + bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0);
1588 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0);
1589 + break;
1590 + case BCMA_CHIP_ID_BCM5357:
1591 + case BCMA_CHIP_ID_BCM4749:
1592 + bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0);
1593 + bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0);
1594 + bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_USB20_HOST, 0);
1595 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0);
1596 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_I2S, 0);
1597 + break;
1598 + case BCMA_CHIP_ID_BCM4706:
1599 + bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_PCIE, 0);
1600 + bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_4706_MAC_GBIT,
1601 + 0);
1602 + bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_PCIE, 1);
1603 + bcma_core_mips_set_irq_name(bus, 4, BCMA_CORE_USB20_HOST, 0);
1604 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_4706_CHIPCOMMON,
1605 + 0);
1606 + break;
1607 + default:
1608 + list_for_each_entry(core, &bus->cores, list) {
1609 + core->irq = bcma_core_irq(core);
1610 }
1611 + bcma_err(bus,
1612 + "Unknown device (0x%x) found, can not configure IRQs\n",
1613 + bus->chipinfo.id);
1614 }
1615 - bcma_info(bus, "IRQ reconfiguration done\n");
1616 + bcma_debug(bus, "IRQ reconfiguration done\n");
1617 bcma_core_mips_dump_irq(bus);
1618
1619 - if (mcore->setup_done)
1620 - return;
1621 -
1622 - bcma_chipco_serial_init(&bus->drv_cc);
1623 - bcma_core_mips_flash_detect(mcore);
1624 mcore->setup_done = true;
1625 }
1626 --- a/drivers/bcma/driver_pci.c
1627 +++ b/drivers/bcma/driver_pci.c
1628 @@ -31,7 +31,7 @@ static void bcma_pcie_write(struct bcma_
1629 pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_DATA, data);
1630 }
1631
1632 -static void bcma_pcie_mdio_set_phy(struct bcma_drv_pci *pc, u8 phy)
1633 +static void bcma_pcie_mdio_set_phy(struct bcma_drv_pci *pc, u16 phy)
1634 {
1635 u32 v;
1636 int i;
1637 @@ -51,11 +51,11 @@ static void bcma_pcie_mdio_set_phy(struc
1638 v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
1639 if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE)
1640 break;
1641 - msleep(1);
1642 + usleep_range(1000, 2000);
1643 }
1644 }
1645
1646 -static u16 bcma_pcie_mdio_read(struct bcma_drv_pci *pc, u8 device, u8 address)
1647 +static u16 bcma_pcie_mdio_read(struct bcma_drv_pci *pc, u16 device, u8 address)
1648 {
1649 int max_retries = 10;
1650 u16 ret = 0;
1651 @@ -92,13 +92,13 @@ static u16 bcma_pcie_mdio_read(struct bc
1652 ret = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_DATA);
1653 break;
1654 }
1655 - msleep(1);
1656 + usleep_range(1000, 2000);
1657 }
1658 pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0);
1659 return ret;
1660 }
1661
1662 -static void bcma_pcie_mdio_write(struct bcma_drv_pci *pc, u8 device,
1663 +static void bcma_pcie_mdio_write(struct bcma_drv_pci *pc, u16 device,
1664 u8 address, u16 data)
1665 {
1666 int max_retries = 10;
1667 @@ -132,11 +132,18 @@ static void bcma_pcie_mdio_write(struct
1668 v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
1669 if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE)
1670 break;
1671 - msleep(1);
1672 + usleep_range(1000, 2000);
1673 }
1674 pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0);
1675 }
1676
1677 +static u16 bcma_pcie_mdio_writeread(struct bcma_drv_pci *pc, u16 device,
1678 + u8 address, u16 data)
1679 +{
1680 + bcma_pcie_mdio_write(pc, device, address, data);
1681 + return bcma_pcie_mdio_read(pc, device, address);
1682 +}
1683 +
1684 /**************************************************
1685 * Workarounds.
1686 **************************************************/
1687 @@ -229,6 +236,32 @@ void __devinit bcma_core_pci_init(struct
1688 bcma_core_pci_clientmode_init(pc);
1689 }
1690
1691 +void bcma_core_pci_power_save(struct bcma_bus *bus, bool up)
1692 +{
1693 + struct bcma_drv_pci *pc;
1694 + u16 data;
1695 +
1696 + if (bus->hosttype != BCMA_HOSTTYPE_PCI)
1697 + return;
1698 +
1699 + pc = &bus->drv_pci[0];
1700 +
1701 + if (pc->core->id.rev >= 15 && pc->core->id.rev <= 20) {
1702 + data = up ? 0x74 : 0x7C;
1703 + bcma_pcie_mdio_writeread(pc, BCMA_CORE_PCI_MDIO_BLK1,
1704 + BCMA_CORE_PCI_MDIO_BLK1_MGMT1, 0x7F64);
1705 + bcma_pcie_mdio_writeread(pc, BCMA_CORE_PCI_MDIO_BLK1,
1706 + BCMA_CORE_PCI_MDIO_BLK1_MGMT3, data);
1707 + } else if (pc->core->id.rev >= 21 && pc->core->id.rev <= 22) {
1708 + data = up ? 0x75 : 0x7D;
1709 + bcma_pcie_mdio_writeread(pc, BCMA_CORE_PCI_MDIO_BLK1,
1710 + BCMA_CORE_PCI_MDIO_BLK1_MGMT1, 0x7E65);
1711 + bcma_pcie_mdio_writeread(pc, BCMA_CORE_PCI_MDIO_BLK1,
1712 + BCMA_CORE_PCI_MDIO_BLK1_MGMT3, data);
1713 + }
1714 +}
1715 +EXPORT_SYMBOL_GPL(bcma_core_pci_power_save);
1716 +
1717 int bcma_core_pci_irq_ctl(struct bcma_drv_pci *pc, struct bcma_device *core,
1718 bool enable)
1719 {
1720 @@ -262,7 +295,7 @@ out:
1721 }
1722 EXPORT_SYMBOL_GPL(bcma_core_pci_irq_ctl);
1723
1724 -void bcma_core_pci_extend_L1timer(struct bcma_drv_pci *pc, bool extend)
1725 +static void bcma_core_pci_extend_L1timer(struct bcma_drv_pci *pc, bool extend)
1726 {
1727 u32 w;
1728
1729 @@ -274,4 +307,29 @@ void bcma_core_pci_extend_L1timer(struct
1730 bcma_pcie_write(pc, BCMA_CORE_PCI_DLLP_PMTHRESHREG, w);
1731 bcma_pcie_read(pc, BCMA_CORE_PCI_DLLP_PMTHRESHREG);
1732 }
1733 -EXPORT_SYMBOL_GPL(bcma_core_pci_extend_L1timer);
1734 +
1735 +void bcma_core_pci_up(struct bcma_bus *bus)
1736 +{
1737 + struct bcma_drv_pci *pc;
1738 +
1739 + if (bus->hosttype != BCMA_HOSTTYPE_PCI)
1740 + return;
1741 +
1742 + pc = &bus->drv_pci[0];
1743 +
1744 + bcma_core_pci_extend_L1timer(pc, true);
1745 +}
1746 +EXPORT_SYMBOL_GPL(bcma_core_pci_up);
1747 +
1748 +void bcma_core_pci_down(struct bcma_bus *bus)
1749 +{
1750 + struct bcma_drv_pci *pc;
1751 +
1752 + if (bus->hosttype != BCMA_HOSTTYPE_PCI)
1753 + return;
1754 +
1755 + pc = &bus->drv_pci[0];
1756 +
1757 + bcma_core_pci_extend_L1timer(pc, false);
1758 +}
1759 +EXPORT_SYMBOL_GPL(bcma_core_pci_down);
1760 --- a/drivers/bcma/driver_pci_host.c
1761 +++ b/drivers/bcma/driver_pci_host.c
1762 @@ -35,11 +35,6 @@ bool __devinit bcma_core_pci_is_in_hostm
1763 chipid_top != 0x5300)
1764 return false;
1765
1766 - if (bus->sprom.boardflags_lo & BCMA_CORE_PCI_BFL_NOPCI) {
1767 - bcma_info(bus, "This PCI core is disabled and not working\n");
1768 - return false;
1769 - }
1770 -
1771 bcma_core_enable(pc->core, 0);
1772
1773 return !mips_busprobe32(tmp, pc->core->io_addr);
1774 @@ -99,19 +94,19 @@ static int bcma_extpci_read_config(struc
1775 if (dev == 0) {
1776 /* we support only two functions on device 0 */
1777 if (func > 1)
1778 - return -EINVAL;
1779 + goto out;
1780
1781 /* accesses to config registers with offsets >= 256
1782 * requires indirect access.
1783 */
1784 if (off >= PCI_CONFIG_SPACE_SIZE) {
1785 addr = (func << 12);
1786 - addr |= (off & 0x0FFF);
1787 + addr |= (off & 0x0FFC);
1788 val = bcma_pcie_read_config(pc, addr);
1789 } else {
1790 addr = BCMA_CORE_PCI_PCICFG0;
1791 addr |= (func << 8);
1792 - addr |= (off & 0xfc);
1793 + addr |= (off & 0xFC);
1794 val = pcicore_read32(pc, addr);
1795 }
1796 } else {
1797 @@ -124,11 +119,9 @@ static int bcma_extpci_read_config(struc
1798 goto out;
1799
1800 if (mips_busprobe32(val, mmio)) {
1801 - val = 0xffffffff;
1802 + val = 0xFFFFFFFF;
1803 goto unmap;
1804 }
1805 -
1806 - val = readl(mmio);
1807 }
1808 val >>= (8 * (off & 3));
1809
1810 @@ -156,7 +149,7 @@ static int bcma_extpci_write_config(stru
1811 const void *buf, int len)
1812 {
1813 int err = -EINVAL;
1814 - u32 addr = 0, val = 0;
1815 + u32 addr, val;
1816 void __iomem *mmio = 0;
1817 u16 chipid = pc->core->bus->chipinfo.id;
1818
1819 @@ -164,16 +157,22 @@ static int bcma_extpci_write_config(stru
1820 if (unlikely(len != 1 && len != 2 && len != 4))
1821 goto out;
1822 if (dev == 0) {
1823 + /* we support only two functions on device 0 */
1824 + if (func > 1)
1825 + goto out;
1826 +
1827 /* accesses to config registers with offsets >= 256
1828 * requires indirect access.
1829 */
1830 - if (off < PCI_CONFIG_SPACE_SIZE) {
1831 - addr = pc->core->addr + BCMA_CORE_PCI_PCICFG0;
1832 + if (off >= PCI_CONFIG_SPACE_SIZE) {
1833 + addr = (func << 12);
1834 + addr |= (off & 0x0FFC);
1835 + val = bcma_pcie_read_config(pc, addr);
1836 + } else {
1837 + addr = BCMA_CORE_PCI_PCICFG0;
1838 addr |= (func << 8);
1839 - addr |= (off & 0xfc);
1840 - mmio = ioremap_nocache(addr, sizeof(val));
1841 - if (!mmio)
1842 - goto out;
1843 + addr |= (off & 0xFC);
1844 + val = pcicore_read32(pc, addr);
1845 }
1846 } else {
1847 addr = bcma_get_cfgspace_addr(pc, dev, func, off);
1848 @@ -185,19 +184,17 @@ static int bcma_extpci_write_config(stru
1849 goto out;
1850
1851 if (mips_busprobe32(val, mmio)) {
1852 - val = 0xffffffff;
1853 + val = 0xFFFFFFFF;
1854 goto unmap;
1855 }
1856 }
1857
1858 switch (len) {
1859 case 1:
1860 - val = readl(mmio);
1861 val &= ~(0xFF << (8 * (off & 3)));
1862 val |= *((const u8 *)buf) << (8 * (off & 3));
1863 break;
1864 case 2:
1865 - val = readl(mmio);
1866 val &= ~(0xFFFF << (8 * (off & 3)));
1867 val |= *((const u16 *)buf) << (8 * (off & 3));
1868 break;
1869 @@ -205,13 +202,14 @@ static int bcma_extpci_write_config(stru
1870 val = *((const u32 *)buf);
1871 break;
1872 }
1873 - if (dev == 0 && !addr) {
1874 + if (dev == 0) {
1875 /* accesses to config registers with offsets >= 256
1876 * requires indirect access.
1877 */
1878 - addr = (func << 12);
1879 - addr |= (off & 0x0FFF);
1880 - bcma_pcie_write_config(pc, addr, val);
1881 + if (off >= PCI_CONFIG_SPACE_SIZE)
1882 + bcma_pcie_write_config(pc, addr, val);
1883 + else
1884 + pcicore_write32(pc, addr, val);
1885 } else {
1886 writel(val, mmio);
1887
1888 @@ -282,7 +280,7 @@ static u8 __devinit bcma_find_pci_capabi
1889 /* check for Header type 0 */
1890 bcma_extpci_read_config(pc, dev, func, PCI_HEADER_TYPE, &byte_val,
1891 sizeof(u8));
1892 - if ((byte_val & 0x7f) != PCI_HEADER_TYPE_NORMAL)
1893 + if ((byte_val & 0x7F) != PCI_HEADER_TYPE_NORMAL)
1894 return cap_ptr;
1895
1896 /* check if the capability pointer field exists */
1897 @@ -396,12 +394,19 @@ void __devinit bcma_core_pci_hostmode_in
1898
1899 bcma_info(bus, "PCIEcore in host mode found\n");
1900
1901 + if (bus->sprom.boardflags_lo & BCMA_CORE_PCI_BFL_NOPCI) {
1902 + bcma_info(bus, "This PCIE core is disabled and not working\n");
1903 + return;
1904 + }
1905 +
1906 pc_host = kzalloc(sizeof(*pc_host), GFP_KERNEL);
1907 if (!pc_host) {
1908 bcma_err(bus, "can not allocate memory");
1909 return;
1910 }
1911
1912 + spin_lock_init(&pc_host->cfgspace_lock);
1913 +
1914 pc->host_controller = pc_host;
1915 pc_host->pci_controller.io_resource = &pc_host->io_resource;
1916 pc_host->pci_controller.mem_resource = &pc_host->mem_resource;
1917 @@ -425,9 +430,9 @@ void __devinit bcma_core_pci_hostmode_in
1918 pc_host->io_resource.flags = IORESOURCE_IO | IORESOURCE_PCI_FIXED;
1919
1920 /* Reset RC */
1921 - udelay(3000);
1922 + usleep_range(3000, 5000);
1923 pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST_OE);
1924 - udelay(1000);
1925 + msleep(50);
1926 pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST |
1927 BCMA_CORE_PCI_CTL_RST_OE);
1928
1929 @@ -452,6 +457,8 @@ void __devinit bcma_core_pci_hostmode_in
1930 pc_host->mem_resource.start = BCMA_SOC_PCI_MEM;
1931 pc_host->mem_resource.end = BCMA_SOC_PCI_MEM +
1932 BCMA_SOC_PCI_MEM_SZ - 1;
1933 + pc_host->io_resource.start = 0x100;
1934 + pc_host->io_resource.end = 0x47F;
1935 pci_membase_1G = BCMA_SOC_PCIE_DMA_H32;
1936 pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
1937 tmp | BCMA_SOC_PCI_MEM);
1938 @@ -459,6 +466,8 @@ void __devinit bcma_core_pci_hostmode_in
1939 pc_host->mem_resource.start = BCMA_SOC_PCI1_MEM;
1940 pc_host->mem_resource.end = BCMA_SOC_PCI1_MEM +
1941 BCMA_SOC_PCI_MEM_SZ - 1;
1942 + pc_host->io_resource.start = 0x480;
1943 + pc_host->io_resource.end = 0x7FF;
1944 pci_membase_1G = BCMA_SOC_PCIE1_DMA_H32;
1945 pc_host->host_cfg_addr = BCMA_SOC_PCI1_CFG;
1946 pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
1947 @@ -481,10 +490,21 @@ void __devinit bcma_core_pci_hostmode_in
1948 * before issuing configuration requests to PCI Express
1949 * devices.
1950 */
1951 - udelay(100000);
1952 + msleep(100);
1953
1954 bcma_core_pci_enable_crs(pc);
1955
1956 + if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706 ||
1957 + bus->chipinfo.id == BCMA_CHIP_ID_BCM4716) {
1958 + u16 val16;
1959 + bcma_extpci_read_config(pc, 0, 0, BCMA_CORE_PCI_CFG_DEVCTRL,
1960 + &val16, sizeof(val16));
1961 + val16 |= (2 << 5); /* Max payload size of 512 */
1962 + val16 |= (2 << 12); /* MRRS 512 */
1963 + bcma_extpci_write_config(pc, 0, 0, BCMA_CORE_PCI_CFG_DEVCTRL,
1964 + &val16, sizeof(val16));
1965 + }
1966 +
1967 /* Enable PCI bridge BAR0 memory & master access */
1968 tmp = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
1969 bcma_extpci_write_config(pc, 0, 0, PCI_COMMAND, &tmp, sizeof(tmp));
1970 @@ -501,7 +521,7 @@ void __devinit bcma_core_pci_hostmode_in
1971 set_io_port_base(pc_host->pci_controller.io_map_base);
1972 /* Give some time to the PCI controller to configure itself with the new
1973 * values. Not waiting at this point causes crashes of the machine. */
1974 - mdelay(10);
1975 + usleep_range(10000, 15000);
1976 register_pci_controller(&pc_host->pci_controller);
1977 return;
1978 }
1979 @@ -534,7 +554,7 @@ DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_
1980 static void bcma_core_pci_fixup_addresses(struct pci_dev *dev)
1981 {
1982 struct resource *res;
1983 - int pos;
1984 + int pos, err;
1985
1986 if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
1987 /* This is not a device on the PCI-core bridge. */
1988 @@ -547,8 +567,12 @@ static void bcma_core_pci_fixup_addresse
1989
1990 for (pos = 0; pos < 6; pos++) {
1991 res = &dev->resource[pos];
1992 - if (res->flags & (IORESOURCE_IO | IORESOURCE_MEM))
1993 - pci_assign_resource(dev, pos);
1994 + if (res->flags & (IORESOURCE_IO | IORESOURCE_MEM)) {
1995 + err = pci_assign_resource(dev, pos);
1996 + if (err)
1997 + pr_err("PCI: Problem fixing up the addresses on %s\n",
1998 + pci_name(dev));
1999 + }
2000 }
2001 }
2002 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, bcma_core_pci_fixup_addresses);
2003 @@ -558,6 +582,7 @@ DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI
2004 int bcma_core_pci_plat_dev_init(struct pci_dev *dev)
2005 {
2006 struct bcma_drv_pci_host *pc_host;
2007 + int readrq;
2008
2009 if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
2010 /* This is not a device on the PCI-core bridge. */
2011 @@ -569,9 +594,14 @@ int bcma_core_pci_plat_dev_init(struct p
2012 pr_info("PCI: Fixing up device %s\n", pci_name(dev));
2013
2014 /* Fix up interrupt lines */
2015 - dev->irq = bcma_core_mips_irq(pc_host->pdev->core) + 2;
2016 + dev->irq = bcma_core_irq(pc_host->pdev->core);
2017 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
2018
2019 + readrq = pcie_get_readrq(dev);
2020 + if (readrq > 128) {
2021 + pr_info("change PCIe max read request size from %i to 128\n", readrq);
2022 + pcie_set_readrq(dev, 128);
2023 + }
2024 return 0;
2025 }
2026 EXPORT_SYMBOL(bcma_core_pci_plat_dev_init);
2027 @@ -588,6 +618,6 @@ int bcma_core_pci_pcibios_map_irq(const
2028
2029 pc_host = container_of(dev->bus->ops, struct bcma_drv_pci_host,
2030 pci_ops);
2031 - return bcma_core_mips_irq(pc_host->pdev->core) + 2;
2032 + return bcma_core_irq(pc_host->pdev->core);
2033 }
2034 EXPORT_SYMBOL(bcma_core_pci_pcibios_map_irq);
2035 --- a/drivers/bcma/host_pci.c
2036 +++ b/drivers/bcma/host_pci.c
2037 @@ -77,8 +77,8 @@ static void bcma_host_pci_write32(struct
2038 }
2039
2040 #ifdef CONFIG_BCMA_BLOCKIO
2041 -void bcma_host_pci_block_read(struct bcma_device *core, void *buffer,
2042 - size_t count, u16 offset, u8 reg_width)
2043 +static void bcma_host_pci_block_read(struct bcma_device *core, void *buffer,
2044 + size_t count, u16 offset, u8 reg_width)
2045 {
2046 void __iomem *addr = core->bus->mmio + offset;
2047 if (core->bus->mapped_core != core)
2048 @@ -100,8 +100,9 @@ void bcma_host_pci_block_read(struct bcm
2049 }
2050 }
2051
2052 -void bcma_host_pci_block_write(struct bcma_device *core, const void *buffer,
2053 - size_t count, u16 offset, u8 reg_width)
2054 +static void bcma_host_pci_block_write(struct bcma_device *core,
2055 + const void *buffer, size_t count,
2056 + u16 offset, u8 reg_width)
2057 {
2058 void __iomem *addr = core->bus->mmio + offset;
2059 if (core->bus->mapped_core != core)
2060 @@ -139,7 +140,7 @@ static void bcma_host_pci_awrite32(struc
2061 iowrite32(value, core->bus->mmio + (1 * BCMA_CORE_SIZE) + offset);
2062 }
2063
2064 -const struct bcma_host_ops bcma_host_pci_ops = {
2065 +static const struct bcma_host_ops bcma_host_pci_ops = {
2066 .read8 = bcma_host_pci_read8,
2067 .read16 = bcma_host_pci_read16,
2068 .read32 = bcma_host_pci_read32,
2069 @@ -237,7 +238,7 @@ static void __devexit bcma_host_pci_remo
2070 pci_set_drvdata(dev, NULL);
2071 }
2072
2073 -#ifdef CONFIG_PM
2074 +#ifdef CONFIG_PM_SLEEP
2075 static int bcma_host_pci_suspend(struct device *dev)
2076 {
2077 struct pci_dev *pdev = to_pci_dev(dev);
2078 @@ -260,11 +261,11 @@ static SIMPLE_DEV_PM_OPS(bcma_pm_ops, bc
2079 bcma_host_pci_resume);
2080 #define BCMA_PM_OPS (&bcma_pm_ops)
2081
2082 -#else /* CONFIG_PM */
2083 +#else /* CONFIG_PM_SLEEP */
2084
2085 #define BCMA_PM_OPS NULL
2086
2087 -#endif /* CONFIG_PM */
2088 +#endif /* CONFIG_PM_SLEEP */
2089
2090 static DEFINE_PCI_DEVICE_TABLE(bcma_pci_bridge_tbl) = {
2091 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x0576) },
2092 @@ -272,7 +273,9 @@ static DEFINE_PCI_DEVICE_TABLE(bcma_pci_
2093 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4331) },
2094 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4353) },
2095 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4357) },
2096 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4358) },
2097 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4359) },
2098 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4365) },
2099 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4727) },
2100 { 0, },
2101 };
2102 --- a/drivers/bcma/host_soc.c
2103 +++ b/drivers/bcma/host_soc.c
2104 @@ -143,7 +143,7 @@ static void bcma_host_soc_awrite32(struc
2105 writel(value, core->io_wrap + offset);
2106 }
2107
2108 -const struct bcma_host_ops bcma_host_soc_ops = {
2109 +static const struct bcma_host_ops bcma_host_soc_ops = {
2110 .read8 = bcma_host_soc_read8,
2111 .read16 = bcma_host_soc_read16,
2112 .read32 = bcma_host_soc_read32,
2113 --- a/drivers/bcma/main.c
2114 +++ b/drivers/bcma/main.c
2115 @@ -7,6 +7,7 @@
2116
2117 #include "bcma_private.h"
2118 #include <linux/module.h>
2119 +#include <linux/platform_device.h>
2120 #include <linux/bcma/bcma.h>
2121 #include <linux/slab.h>
2122
2123 @@ -80,6 +81,37 @@ struct bcma_device *bcma_find_core(struc
2124 }
2125 EXPORT_SYMBOL_GPL(bcma_find_core);
2126
2127 +struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
2128 + u8 unit)
2129 +{
2130 + struct bcma_device *core;
2131 +
2132 + list_for_each_entry(core, &bus->cores, list) {
2133 + if (core->id.id == coreid && core->core_unit == unit)
2134 + return core;
2135 + }
2136 + return NULL;
2137 +}
2138 +
2139 +bool bcma_wait_value(struct bcma_device *core, u16 reg, u32 mask, u32 value,
2140 + int timeout)
2141 +{
2142 + unsigned long deadline = jiffies + timeout;
2143 + u32 val;
2144 +
2145 + do {
2146 + val = bcma_read32(core, reg);
2147 + if ((val & mask) == value)
2148 + return true;
2149 + cpu_relax();
2150 + udelay(10);
2151 + } while (!time_after_eq(jiffies, deadline));
2152 +
2153 + bcma_warn(core->bus, "Timeout waiting for register 0x%04X!\n", reg);
2154 +
2155 + return false;
2156 +}
2157 +
2158 static void bcma_release_core_dev(struct device *dev)
2159 {
2160 struct bcma_device *core = container_of(dev, struct bcma_device, dev);
2161 @@ -107,6 +139,11 @@ static int bcma_register_cores(struct bc
2162 continue;
2163 }
2164
2165 + /* Only first GMAC core on BCM4706 is connected and working */
2166 + if (core->id.id == BCMA_CORE_4706_MAC_GBIT &&
2167 + core->core_unit > 0)
2168 + continue;
2169 +
2170 core->dev.release = bcma_release_core_dev;
2171 core->dev.bus = &bcma_bus_type;
2172 dev_set_name(&core->dev, "bcma%d:%d", bus->num, dev_id);
2173 @@ -136,6 +173,41 @@ static int bcma_register_cores(struct bc
2174 dev_id++;
2175 }
2176
2177 +#ifdef CONFIG_BCMA_DRIVER_MIPS
2178 + if (bus->drv_cc.pflash.present) {
2179 + err = platform_device_register(&bcma_pflash_dev);
2180 + if (err)
2181 + bcma_err(bus, "Error registering parallel flash\n");
2182 + }
2183 +#endif
2184 +
2185 +#ifdef CONFIG_BCMA_SFLASH
2186 + if (bus->drv_cc.sflash.present) {
2187 + err = platform_device_register(&bcma_sflash_dev);
2188 + if (err)
2189 + bcma_err(bus, "Error registering serial flash\n");
2190 + }
2191 +#endif
2192 +
2193 +#ifdef CONFIG_BCMA_NFLASH
2194 + if (bus->drv_cc.nflash.present) {
2195 + err = platform_device_register(&bcma_nflash_dev);
2196 + if (err)
2197 + bcma_err(bus, "Error registering NAND flash\n");
2198 + }
2199 +#endif
2200 + err = bcma_gpio_init(&bus->drv_cc);
2201 + if (err == -ENOTSUPP)
2202 + bcma_debug(bus, "GPIO driver not activated\n");
2203 + else if (err)
2204 + bcma_err(bus, "Error registering GPIO driver: %i\n", err);
2205 +
2206 + if (bus->hosttype == BCMA_HOSTTYPE_SOC) {
2207 + err = bcma_chipco_watchdog_register(&bus->drv_cc);
2208 + if (err)
2209 + bcma_err(bus, "Error registering watchdog driver\n");
2210 + }
2211 +
2212 return 0;
2213 }
2214
2215 @@ -148,6 +220,8 @@ static void bcma_unregister_cores(struct
2216 if (core->dev_registered)
2217 device_unregister(&core->dev);
2218 }
2219 + if (bus->hosttype == BCMA_HOSTTYPE_SOC)
2220 + platform_device_unregister(bus->drv_cc.watchdog);
2221 }
2222
2223 int __devinit bcma_bus_register(struct bcma_bus *bus)
2224 @@ -163,9 +237,23 @@ int __devinit bcma_bus_register(struct b
2225 err = bcma_bus_scan(bus);
2226 if (err) {
2227 bcma_err(bus, "Failed to scan: %d\n", err);
2228 - return -1;
2229 + return err;
2230 }
2231
2232 + /* Early init CC core */
2233 + core = bcma_find_core(bus, bcma_cc_core_id(bus));
2234 + if (core) {
2235 + bus->drv_cc.core = core;
2236 + bcma_core_chipcommon_early_init(&bus->drv_cc);
2237 + }
2238 +
2239 + /* Try to get SPROM */
2240 + err = bcma_sprom_get(bus);
2241 + if (err == -ENOENT) {
2242 + bcma_err(bus, "No SPROM available\n");
2243 + } else if (err)
2244 + bcma_err(bus, "Failed to get SPROM: %d\n", err);
2245 +
2246 /* Init CC core */
2247 core = bcma_find_core(bus, bcma_cc_core_id(bus));
2248 if (core) {
2249 @@ -181,10 +269,17 @@ int __devinit bcma_bus_register(struct b
2250 }
2251
2252 /* Init PCIE core */
2253 - core = bcma_find_core(bus, BCMA_CORE_PCIE);
2254 + core = bcma_find_core_unit(bus, BCMA_CORE_PCIE, 0);
2255 if (core) {
2256 - bus->drv_pci.core = core;
2257 - bcma_core_pci_init(&bus->drv_pci);
2258 + bus->drv_pci[0].core = core;
2259 + bcma_core_pci_init(&bus->drv_pci[0]);
2260 + }
2261 +
2262 + /* Init PCIE core */
2263 + core = bcma_find_core_unit(bus, BCMA_CORE_PCIE, 1);
2264 + if (core) {
2265 + bus->drv_pci[1].core = core;
2266 + bcma_core_pci_init(&bus->drv_pci[1]);
2267 }
2268
2269 /* Init GBIT MAC COMMON core */
2270 @@ -194,13 +289,6 @@ int __devinit bcma_bus_register(struct b
2271 bcma_core_gmac_cmn_init(&bus->drv_gmac_cmn);
2272 }
2273
2274 - /* Try to get SPROM */
2275 - err = bcma_sprom_get(bus);
2276 - if (err == -ENOENT) {
2277 - bcma_err(bus, "No SPROM available\n");
2278 - } else if (err)
2279 - bcma_err(bus, "Failed to get SPROM: %d\n", err);
2280 -
2281 /* Register found cores */
2282 bcma_register_cores(bus);
2283
2284 @@ -211,7 +299,24 @@ int __devinit bcma_bus_register(struct b
2285
2286 void bcma_bus_unregister(struct bcma_bus *bus)
2287 {
2288 + struct bcma_device *cores[3];
2289 + int err;
2290 +
2291 + err = bcma_gpio_unregister(&bus->drv_cc);
2292 + if (err == -EBUSY)
2293 + bcma_err(bus, "Some GPIOs are still in use.\n");
2294 + else if (err)
2295 + bcma_err(bus, "Can not unregister GPIO driver: %i\n", err);
2296 +
2297 + cores[0] = bcma_find_core(bus, BCMA_CORE_MIPS_74K);
2298 + cores[1] = bcma_find_core(bus, BCMA_CORE_PCIE);
2299 + cores[2] = bcma_find_core(bus, BCMA_CORE_4706_MAC_GBIT_COMMON);
2300 +
2301 bcma_unregister_cores(bus);
2302 +
2303 + kfree(cores[2]);
2304 + kfree(cores[1]);
2305 + kfree(cores[0]);
2306 }
2307
2308 int __init bcma_bus_early_register(struct bcma_bus *bus,
2309 @@ -248,18 +353,18 @@ int __init bcma_bus_early_register(struc
2310 return -1;
2311 }
2312
2313 - /* Init CC core */
2314 + /* Early init CC core */
2315 core = bcma_find_core(bus, bcma_cc_core_id(bus));
2316 if (core) {
2317 bus->drv_cc.core = core;
2318 - bcma_core_chipcommon_init(&bus->drv_cc);
2319 + bcma_core_chipcommon_early_init(&bus->drv_cc);
2320 }
2321
2322 - /* Init MIPS core */
2323 + /* Early init MIPS core */
2324 core = bcma_find_core(bus, BCMA_CORE_MIPS_74K);
2325 if (core) {
2326 bus->drv_mips.core = core;
2327 - bcma_core_mips_init(&bus->drv_mips);
2328 + bcma_core_mips_early_init(&bus->drv_mips);
2329 }
2330
2331 bcma_info(bus, "Early bus registered\n");
2332 --- a/drivers/bcma/scan.c
2333 +++ b/drivers/bcma/scan.c
2334 @@ -32,6 +32,18 @@ static const struct bcma_device_id_name
2335 { BCMA_CORE_4706_CHIPCOMMON, "BCM4706 ChipCommon" },
2336 { BCMA_CORE_4706_SOC_RAM, "BCM4706 SOC RAM" },
2337 { BCMA_CORE_4706_MAC_GBIT, "BCM4706 GBit MAC" },
2338 + { BCMA_CORE_PCIEG2, "PCIe Gen 2" },
2339 + { BCMA_CORE_DMA, "DMA" },
2340 + { BCMA_CORE_SDIO3, "SDIO3" },
2341 + { BCMA_CORE_USB20, "USB 2.0" },
2342 + { BCMA_CORE_USB30, "USB 3.0" },
2343 + { BCMA_CORE_A9JTAG, "ARM Cortex A9 JTAG" },
2344 + { BCMA_CORE_DDR23, "Denali DDR2/DDR3 memory controller" },
2345 + { BCMA_CORE_ROM, "ROM" },
2346 + { BCMA_CORE_NAND, "NAND flash controller" },
2347 + { BCMA_CORE_QSPI, "SPI flash controller" },
2348 + { BCMA_CORE_CHIPCOMMON_B, "Chipcommon B" },
2349 + { BCMA_CORE_ARMCA9, "ARM Cortex A9 core (ihost)" },
2350 { BCMA_CORE_AMEMC, "AMEMC (DDR)" },
2351 { BCMA_CORE_ALTA, "ALTA (I2S)" },
2352 { BCMA_CORE_INVALID, "Invalid" },
2353 @@ -84,6 +96,8 @@ static const struct bcma_device_id_name
2354 { BCMA_CORE_I2S, "I2S" },
2355 { BCMA_CORE_SDR_DDR1_MEM_CTL, "SDR/DDR1 Memory Controller" },
2356 { BCMA_CORE_SHIM, "SHIM" },
2357 + { BCMA_CORE_PCIE2, "PCIe Gen2" },
2358 + { BCMA_CORE_ARM_CR4, "ARM CR4" },
2359 { BCMA_CORE_DEFAULT, "Default" },
2360 };
2361
2362 @@ -137,19 +151,19 @@ static void bcma_scan_switch_core(struct
2363 addr);
2364 }
2365
2366 -static u32 bcma_erom_get_ent(struct bcma_bus *bus, u32 **eromptr)
2367 +static u32 bcma_erom_get_ent(struct bcma_bus *bus, u32 __iomem **eromptr)
2368 {
2369 u32 ent = readl(*eromptr);
2370 (*eromptr)++;
2371 return ent;
2372 }
2373
2374 -static void bcma_erom_push_ent(u32 **eromptr)
2375 +static void bcma_erom_push_ent(u32 __iomem **eromptr)
2376 {
2377 (*eromptr)--;
2378 }
2379
2380 -static s32 bcma_erom_get_ci(struct bcma_bus *bus, u32 **eromptr)
2381 +static s32 bcma_erom_get_ci(struct bcma_bus *bus, u32 __iomem **eromptr)
2382 {
2383 u32 ent = bcma_erom_get_ent(bus, eromptr);
2384 if (!(ent & SCAN_ER_VALID))
2385 @@ -159,14 +173,14 @@ static s32 bcma_erom_get_ci(struct bcma_
2386 return ent;
2387 }
2388
2389 -static bool bcma_erom_is_end(struct bcma_bus *bus, u32 **eromptr)
2390 +static bool bcma_erom_is_end(struct bcma_bus *bus, u32 __iomem **eromptr)
2391 {
2392 u32 ent = bcma_erom_get_ent(bus, eromptr);
2393 bcma_erom_push_ent(eromptr);
2394 return (ent == (SCAN_ER_TAG_END | SCAN_ER_VALID));
2395 }
2396
2397 -static bool bcma_erom_is_bridge(struct bcma_bus *bus, u32 **eromptr)
2398 +static bool bcma_erom_is_bridge(struct bcma_bus *bus, u32 __iomem **eromptr)
2399 {
2400 u32 ent = bcma_erom_get_ent(bus, eromptr);
2401 bcma_erom_push_ent(eromptr);
2402 @@ -175,7 +189,7 @@ static bool bcma_erom_is_bridge(struct b
2403 ((ent & SCAN_ADDR_TYPE) == SCAN_ADDR_TYPE_BRIDGE));
2404 }
2405
2406 -static void bcma_erom_skip_component(struct bcma_bus *bus, u32 **eromptr)
2407 +static void bcma_erom_skip_component(struct bcma_bus *bus, u32 __iomem **eromptr)
2408 {
2409 u32 ent;
2410 while (1) {
2411 @@ -189,7 +203,7 @@ static void bcma_erom_skip_component(str
2412 bcma_erom_push_ent(eromptr);
2413 }
2414
2415 -static s32 bcma_erom_get_mst_port(struct bcma_bus *bus, u32 **eromptr)
2416 +static s32 bcma_erom_get_mst_port(struct bcma_bus *bus, u32 __iomem **eromptr)
2417 {
2418 u32 ent = bcma_erom_get_ent(bus, eromptr);
2419 if (!(ent & SCAN_ER_VALID))
2420 @@ -199,7 +213,7 @@ static s32 bcma_erom_get_mst_port(struct
2421 return ent;
2422 }
2423
2424 -static s32 bcma_erom_get_addr_desc(struct bcma_bus *bus, u32 **eromptr,
2425 +static u32 bcma_erom_get_addr_desc(struct bcma_bus *bus, u32 __iomem **eromptr,
2426 u32 type, u8 port)
2427 {
2428 u32 addrl, addrh, sizel, sizeh = 0;
2429 @@ -211,7 +225,7 @@ static s32 bcma_erom_get_addr_desc(struc
2430 ((ent & SCAN_ADDR_TYPE) != type) ||
2431 (((ent & SCAN_ADDR_PORT) >> SCAN_ADDR_PORT_SHIFT) != port)) {
2432 bcma_erom_push_ent(eromptr);
2433 - return -EINVAL;
2434 + return (u32)-EINVAL;
2435 }
2436
2437 addrl = ent & SCAN_ADDR_ADDR;
2438 @@ -255,11 +269,13 @@ static struct bcma_device *bcma_find_cor
2439 return NULL;
2440 }
2441
2442 +#define IS_ERR_VALUE_U32(x) ((x) >= (u32)-MAX_ERRNO)
2443 +
2444 static int bcma_get_next_core(struct bcma_bus *bus, u32 __iomem **eromptr,
2445 struct bcma_device_id *match, int core_num,
2446 struct bcma_device *core)
2447 {
2448 - s32 tmp;
2449 + u32 tmp;
2450 u8 i, j;
2451 s32 cia, cib;
2452 u8 ports[2], wrappers[2];
2453 @@ -337,11 +353,11 @@ static int bcma_get_next_core(struct bcm
2454 * the main register space for the core
2455 */
2456 tmp = bcma_erom_get_addr_desc(bus, eromptr, SCAN_ADDR_TYPE_SLAVE, 0);
2457 - if (tmp <= 0) {
2458 + if (tmp == 0 || IS_ERR_VALUE_U32(tmp)) {
2459 /* Try again to see if it is a bridge */
2460 tmp = bcma_erom_get_addr_desc(bus, eromptr,
2461 SCAN_ADDR_TYPE_BRIDGE, 0);
2462 - if (tmp <= 0) {
2463 + if (tmp == 0 || IS_ERR_VALUE_U32(tmp)) {
2464 return -EILSEQ;
2465 } else {
2466 bcma_info(bus, "Bridge found\n");
2467 @@ -355,7 +371,7 @@ static int bcma_get_next_core(struct bcm
2468 for (j = 0; ; j++) {
2469 tmp = bcma_erom_get_addr_desc(bus, eromptr,
2470 SCAN_ADDR_TYPE_SLAVE, i);
2471 - if (tmp < 0) {
2472 + if (IS_ERR_VALUE_U32(tmp)) {
2473 /* no more entries for port _i_ */
2474 /* pr_debug("erom: slave port %d "
2475 * "has %d descriptors\n", i, j); */
2476 @@ -372,7 +388,7 @@ static int bcma_get_next_core(struct bcm
2477 for (j = 0; ; j++) {
2478 tmp = bcma_erom_get_addr_desc(bus, eromptr,
2479 SCAN_ADDR_TYPE_MWRAP, i);
2480 - if (tmp < 0) {
2481 + if (IS_ERR_VALUE_U32(tmp)) {
2482 /* no more entries for port _i_ */
2483 /* pr_debug("erom: master wrapper %d "
2484 * "has %d descriptors\n", i, j); */
2485 @@ -390,7 +406,7 @@ static int bcma_get_next_core(struct bcm
2486 for (j = 0; ; j++) {
2487 tmp = bcma_erom_get_addr_desc(bus, eromptr,
2488 SCAN_ADDR_TYPE_SWRAP, i + hack);
2489 - if (tmp < 0) {
2490 + if (IS_ERR_VALUE_U32(tmp)) {
2491 /* no more entries for port _i_ */
2492 /* pr_debug("erom: master wrapper %d "
2493 * has %d descriptors\n", i, j); */
2494 --- a/drivers/bcma/sprom.c
2495 +++ b/drivers/bcma/sprom.c
2496 @@ -72,12 +72,12 @@ fail:
2497 * R/W ops.
2498 **************************************************/
2499
2500 -static void bcma_sprom_read(struct bcma_bus *bus, u16 offset, u16 *sprom)
2501 +static void bcma_sprom_read(struct bcma_bus *bus, u16 offset, u16 *sprom,
2502 + size_t words)
2503 {
2504 int i;
2505 - for (i = 0; i < SSB_SPROMSIZE_WORDS_R4; i++)
2506 - sprom[i] = bcma_read16(bus->drv_cc.core,
2507 - offset + (i * 2));
2508 + for (i = 0; i < words; i++)
2509 + sprom[i] = bcma_read16(bus->drv_cc.core, offset + (i * 2));
2510 }
2511
2512 /**************************************************
2513 @@ -124,29 +124,29 @@ static inline u8 bcma_crc8(u8 crc, u8 da
2514 return t[crc ^ data];
2515 }
2516
2517 -static u8 bcma_sprom_crc(const u16 *sprom)
2518 +static u8 bcma_sprom_crc(const u16 *sprom, size_t words)
2519 {
2520 int word;
2521 u8 crc = 0xFF;
2522
2523 - for (word = 0; word < SSB_SPROMSIZE_WORDS_R4 - 1; word++) {
2524 + for (word = 0; word < words - 1; word++) {
2525 crc = bcma_crc8(crc, sprom[word] & 0x00FF);
2526 crc = bcma_crc8(crc, (sprom[word] & 0xFF00) >> 8);
2527 }
2528 - crc = bcma_crc8(crc, sprom[SSB_SPROMSIZE_WORDS_R4 - 1] & 0x00FF);
2529 + crc = bcma_crc8(crc, sprom[words - 1] & 0x00FF);
2530 crc ^= 0xFF;
2531
2532 return crc;
2533 }
2534
2535 -static int bcma_sprom_check_crc(const u16 *sprom)
2536 +static int bcma_sprom_check_crc(const u16 *sprom, size_t words)
2537 {
2538 u8 crc;
2539 u8 expected_crc;
2540 u16 tmp;
2541
2542 - crc = bcma_sprom_crc(sprom);
2543 - tmp = sprom[SSB_SPROMSIZE_WORDS_R4 - 1] & SSB_SPROM_REVISION_CRC;
2544 + crc = bcma_sprom_crc(sprom, words);
2545 + tmp = sprom[words - 1] & SSB_SPROM_REVISION_CRC;
2546 expected_crc = tmp >> SSB_SPROM_REVISION_CRC_SHIFT;
2547 if (crc != expected_crc)
2548 return -EPROTO;
2549 @@ -154,21 +154,25 @@ static int bcma_sprom_check_crc(const u1
2550 return 0;
2551 }
2552
2553 -static int bcma_sprom_valid(const u16 *sprom)
2554 +static int bcma_sprom_valid(struct bcma_bus *bus, const u16 *sprom,
2555 + size_t words)
2556 {
2557 u16 revision;
2558 int err;
2559
2560 - err = bcma_sprom_check_crc(sprom);
2561 + err = bcma_sprom_check_crc(sprom, words);
2562 if (err)
2563 return err;
2564
2565 - revision = sprom[SSB_SPROMSIZE_WORDS_R4 - 1] & SSB_SPROM_REVISION_REV;
2566 - if (revision != 8 && revision != 9) {
2567 + revision = sprom[words - 1] & SSB_SPROM_REVISION_REV;
2568 + if (revision != 8 && revision != 9 && revision != 10) {
2569 pr_err("Unsupported SPROM revision: %d\n", revision);
2570 return -ENOENT;
2571 }
2572
2573 + bus->sprom.revision = revision;
2574 + bcma_debug(bus, "Found SPROM revision %d\n", revision);
2575 +
2576 return 0;
2577 }
2578
2579 @@ -208,15 +212,13 @@ static void bcma_sprom_extract_r8(struct
2580 BUILD_BUG_ON(ARRAY_SIZE(pwr_info_offset) !=
2581 ARRAY_SIZE(bus->sprom.core_pwr_info));
2582
2583 - bus->sprom.revision = sprom[SSB_SPROMSIZE_WORDS_R4 - 1] &
2584 - SSB_SPROM_REVISION_REV;
2585 -
2586 for (i = 0; i < 3; i++) {
2587 v = sprom[SPOFF(SSB_SPROM8_IL0MAC) + i];
2588 *(((__be16 *)bus->sprom.il0mac) + i) = cpu_to_be16(v);
2589 }
2590
2591 SPEX(board_rev, SSB_SPROM8_BOARDREV, ~0, 0);
2592 + SPEX(board_type, SSB_SPROM1_SPID, ~0, 0);
2593
2594 SPEX(txpid2g[0], SSB_SPROM4_TXPID2G01, SSB_SPROM4_TXPID2G0,
2595 SSB_SPROM4_TXPID2G0_SHIFT);
2596 @@ -501,13 +503,15 @@ static bool bcma_sprom_onchip_available(
2597 case BCMA_CHIP_ID_BCM4331:
2598 present = chip_status & BCMA_CC_CHIPST_4331_OTP_PRESENT;
2599 break;
2600 -
2601 + case BCMA_CHIP_ID_BCM43142:
2602 case BCMA_CHIP_ID_BCM43224:
2603 case BCMA_CHIP_ID_BCM43225:
2604 /* for these chips OTP is always available */
2605 present = true;
2606 break;
2607 + case BCMA_CHIP_ID_BCM43227:
2608 case BCMA_CHIP_ID_BCM43228:
2609 + case BCMA_CHIP_ID_BCM43428:
2610 present = chip_status & BCMA_CC_CHIPST_43228_OTP_PRESENT;
2611 break;
2612 default:
2613 @@ -547,7 +551,9 @@ int bcma_sprom_get(struct bcma_bus *bus)
2614 {
2615 u16 offset = BCMA_CC_SPROM;
2616 u16 *sprom;
2617 - int err = 0;
2618 + size_t sprom_sizes[] = { SSB_SPROMSIZE_WORDS_R4,
2619 + SSB_SPROMSIZE_WORDS_R10, };
2620 + int i, err = 0;
2621
2622 if (!bus->drv_cc.core)
2623 return -EOPNOTSUPP;
2624 @@ -576,29 +582,37 @@ int bcma_sprom_get(struct bcma_bus *bus)
2625 }
2626 }
2627
2628 - sprom = kcalloc(SSB_SPROMSIZE_WORDS_R4, sizeof(u16),
2629 - GFP_KERNEL);
2630 - if (!sprom)
2631 - return -ENOMEM;
2632 -
2633 if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4331 ||
2634 bus->chipinfo.id == BCMA_CHIP_ID_BCM43431)
2635 bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, false);
2636
2637 bcma_debug(bus, "SPROM offset 0x%x\n", offset);
2638 - bcma_sprom_read(bus, offset, sprom);
2639 + for (i = 0; i < ARRAY_SIZE(sprom_sizes); i++) {
2640 + size_t words = sprom_sizes[i];
2641 +
2642 + sprom = kcalloc(words, sizeof(u16), GFP_KERNEL);
2643 + if (!sprom)
2644 + return -ENOMEM;
2645 +
2646 + bcma_sprom_read(bus, offset, sprom, words);
2647 + err = bcma_sprom_valid(bus, sprom, words);
2648 + if (!err)
2649 + break;
2650 +
2651 + kfree(sprom);
2652 + }
2653
2654 if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4331 ||
2655 bus->chipinfo.id == BCMA_CHIP_ID_BCM43431)
2656 bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, true);
2657
2658 - err = bcma_sprom_valid(sprom);
2659 - if (err)
2660 - goto out;
2661 -
2662 - bcma_sprom_extract_r8(bus, sprom);
2663 + if (err) {
2664 + bcma_warn(bus, "Invalid SPROM read from the PCIe card, trying to use fallback SPROM\n");
2665 + err = bcma_fill_sprom_with_fallback(bus, &bus->sprom);
2666 + } else {
2667 + bcma_sprom_extract_r8(bus, sprom);
2668 + kfree(sprom);
2669 + }
2670
2671 -out:
2672 - kfree(sprom);
2673 return err;
2674 }
2675 --- a/include/linux/bcma/bcma.h
2676 +++ b/include/linux/bcma/bcma.h
2677 @@ -10,7 +10,7 @@
2678 #include <linux/bcma/bcma_driver_gmac_cmn.h>
2679 #include <linux/ssb/ssb.h> /* SPROM sharing */
2680
2681 -#include "bcma_regs.h"
2682 +#include <linux/bcma/bcma_regs.h>
2683
2684 struct bcma_device;
2685 struct bcma_bus;
2686 @@ -72,7 +72,19 @@ struct bcma_host_ops {
2687 /* Core-ID values. */
2688 #define BCMA_CORE_OOB_ROUTER 0x367 /* Out of band */
2689 #define BCMA_CORE_4706_CHIPCOMMON 0x500
2690 +#define BCMA_CORE_PCIEG2 0x501
2691 +#define BCMA_CORE_DMA 0x502
2692 +#define BCMA_CORE_SDIO3 0x503
2693 +#define BCMA_CORE_USB20 0x504
2694 +#define BCMA_CORE_USB30 0x505
2695 +#define BCMA_CORE_A9JTAG 0x506
2696 +#define BCMA_CORE_DDR23 0x507
2697 +#define BCMA_CORE_ROM 0x508
2698 +#define BCMA_CORE_NAND 0x509
2699 +#define BCMA_CORE_QSPI 0x50A
2700 +#define BCMA_CORE_CHIPCOMMON_B 0x50B
2701 #define BCMA_CORE_4706_SOC_RAM 0x50E
2702 +#define BCMA_CORE_ARMCA9 0x510
2703 #define BCMA_CORE_4706_MAC_GBIT 0x52D
2704 #define BCMA_CORE_AMEMC 0x52E /* DDR1/2 memory controller core */
2705 #define BCMA_CORE_ALTA 0x534 /* I2S core */
2706 @@ -134,12 +146,17 @@ struct bcma_host_ops {
2707 #define BCMA_CORE_I2S 0x834
2708 #define BCMA_CORE_SDR_DDR1_MEM_CTL 0x835 /* SDR/DDR1 memory controller core */
2709 #define BCMA_CORE_SHIM 0x837 /* SHIM component in ubus/6362 */
2710 +#define BCMA_CORE_PHY_AC 0x83B
2711 +#define BCMA_CORE_PCIE2 0x83C /* PCI Express Gen2 */
2712 +#define BCMA_CORE_USB30_DEV 0x83D
2713 +#define BCMA_CORE_ARM_CR4 0x83E
2714 #define BCMA_CORE_DEFAULT 0xFFF
2715
2716 #define BCMA_MAX_NR_CORES 16
2717
2718 /* Chip IDs of PCIe devices */
2719 #define BCMA_CHIP_ID_BCM4313 0x4313
2720 +#define BCMA_CHIP_ID_BCM43142 43142
2721 #define BCMA_CHIP_ID_BCM43224 43224
2722 #define BCMA_PKG_ID_BCM43224_FAB_CSM 0x8
2723 #define BCMA_PKG_ID_BCM43224_FAB_SMIC 0xa
2724 @@ -157,6 +174,7 @@ struct bcma_host_ops {
2725
2726 /* Chip IDs of SoCs */
2727 #define BCMA_CHIP_ID_BCM4706 0x5300
2728 +#define BCMA_PKG_ID_BCM4706L 1
2729 #define BCMA_CHIP_ID_BCM4716 0x4716
2730 #define BCMA_PKG_ID_BCM4716 8
2731 #define BCMA_PKG_ID_BCM4717 9
2732 @@ -166,7 +184,70 @@ struct bcma_host_ops {
2733 #define BCMA_CHIP_ID_BCM4749 0x4749
2734 #define BCMA_CHIP_ID_BCM5356 0x5356
2735 #define BCMA_CHIP_ID_BCM5357 0x5357
2736 +#define BCMA_PKG_ID_BCM5358 9
2737 +#define BCMA_PKG_ID_BCM47186 10
2738 +#define BCMA_PKG_ID_BCM5357 11
2739 #define BCMA_CHIP_ID_BCM53572 53572
2740 +#define BCMA_PKG_ID_BCM47188 9
2741 +#define BCMA_CHIP_ID_BCM4707 53010
2742 +#define BCMA_PKG_ID_BCM4707 1
2743 +#define BCMA_PKG_ID_BCM4708 2
2744 +#define BCMA_PKG_ID_BCM4709 0
2745 +#define BCMA_CHIP_ID_BCM53018 53018
2746 +
2747 +/* Board types (on PCI usually equals to the subsystem dev id) */
2748 +/* BCM4313 */
2749 +#define BCMA_BOARD_TYPE_BCM94313BU 0X050F
2750 +#define BCMA_BOARD_TYPE_BCM94313HM 0X0510
2751 +#define BCMA_BOARD_TYPE_BCM94313EPA 0X0511
2752 +#define BCMA_BOARD_TYPE_BCM94313HMG 0X051C
2753 +/* BCM4716 */
2754 +#define BCMA_BOARD_TYPE_BCM94716NR2 0X04CD
2755 +/* BCM43224 */
2756 +#define BCMA_BOARD_TYPE_BCM943224X21 0X056E
2757 +#define BCMA_BOARD_TYPE_BCM943224X21_FCC 0X00D1
2758 +#define BCMA_BOARD_TYPE_BCM943224X21B 0X00E9
2759 +#define BCMA_BOARD_TYPE_BCM943224M93 0X008B
2760 +#define BCMA_BOARD_TYPE_BCM943224M93A 0X0090
2761 +#define BCMA_BOARD_TYPE_BCM943224X16 0X0093
2762 +#define BCMA_BOARD_TYPE_BCM94322X9 0X008D
2763 +#define BCMA_BOARD_TYPE_BCM94322M35E 0X008E
2764 +/* BCM43228 */
2765 +#define BCMA_BOARD_TYPE_BCM943228BU8 0X0540
2766 +#define BCMA_BOARD_TYPE_BCM943228BU9 0X0541
2767 +#define BCMA_BOARD_TYPE_BCM943228BU 0X0542
2768 +#define BCMA_BOARD_TYPE_BCM943227HM4L 0X0543
2769 +#define BCMA_BOARD_TYPE_BCM943227HMB 0X0544
2770 +#define BCMA_BOARD_TYPE_BCM943228HM4L 0X0545
2771 +#define BCMA_BOARD_TYPE_BCM943228SD 0X0573
2772 +/* BCM4331 */
2773 +#define BCMA_BOARD_TYPE_BCM94331X19 0X00D6
2774 +#define BCMA_BOARD_TYPE_BCM94331X28 0X00E4
2775 +#define BCMA_BOARD_TYPE_BCM94331X28B 0X010E
2776 +#define BCMA_BOARD_TYPE_BCM94331PCIEBT3AX 0X00E4
2777 +#define BCMA_BOARD_TYPE_BCM94331X12_2G 0X00EC
2778 +#define BCMA_BOARD_TYPE_BCM94331X12_5G 0X00ED
2779 +#define BCMA_BOARD_TYPE_BCM94331X29B 0X00EF
2780 +#define BCMA_BOARD_TYPE_BCM94331CSAX 0X00EF
2781 +#define BCMA_BOARD_TYPE_BCM94331X19C 0X00F5
2782 +#define BCMA_BOARD_TYPE_BCM94331X33 0X00F4
2783 +#define BCMA_BOARD_TYPE_BCM94331BU 0X0523
2784 +#define BCMA_BOARD_TYPE_BCM94331S9BU 0X0524
2785 +#define BCMA_BOARD_TYPE_BCM94331MC 0X0525
2786 +#define BCMA_BOARD_TYPE_BCM94331MCI 0X0526
2787 +#define BCMA_BOARD_TYPE_BCM94331PCIEBT4 0X0527
2788 +#define BCMA_BOARD_TYPE_BCM94331HM 0X0574
2789 +#define BCMA_BOARD_TYPE_BCM94331PCIEDUAL 0X059B
2790 +#define BCMA_BOARD_TYPE_BCM94331MCH5 0X05A9
2791 +#define BCMA_BOARD_TYPE_BCM94331CS 0X05C6
2792 +#define BCMA_BOARD_TYPE_BCM94331CD 0X05DA
2793 +/* BCM53572 */
2794 +#define BCMA_BOARD_TYPE_BCM953572BU 0X058D
2795 +#define BCMA_BOARD_TYPE_BCM953572NR2 0X058E
2796 +#define BCMA_BOARD_TYPE_BCM947188NR2 0X058F
2797 +#define BCMA_BOARD_TYPE_BCM953572SDRNR2 0X0590
2798 +/* BCM43142 */
2799 +#define BCMA_BOARD_TYPE_BCM943142HM 0X05E0
2800
2801 struct bcma_device {
2802 struct bcma_bus *bus;
2803 @@ -251,7 +332,7 @@ struct bcma_bus {
2804 u8 num;
2805
2806 struct bcma_drv_cc drv_cc;
2807 - struct bcma_drv_pci drv_pci;
2808 + struct bcma_drv_pci drv_pci[2];
2809 struct bcma_drv_mips drv_mips;
2810 struct bcma_drv_gmac_cmn drv_gmac_cmn;
2811
2812 @@ -345,6 +426,7 @@ extern void bcma_core_set_clockmode(stru
2813 enum bcma_clkmode clkmode);
2814 extern void bcma_core_pll_ctl(struct bcma_device *core, u32 req, u32 status,
2815 bool on);
2816 +extern u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset);
2817 #define BCMA_DMA_TRANSLATION_MASK 0xC0000000
2818 #define BCMA_DMA_TRANSLATION_NONE 0x00000000
2819 #define BCMA_DMA_TRANSLATION_DMA32_CMT 0x40000000 /* Client Mode Translation for 32-bit DMA */
2820 --- a/include/linux/bcma/bcma_driver_chipcommon.h
2821 +++ b/include/linux/bcma/bcma_driver_chipcommon.h
2822 @@ -1,6 +1,9 @@
2823 #ifndef LINUX_BCMA_DRIVER_CC_H_
2824 #define LINUX_BCMA_DRIVER_CC_H_
2825
2826 +#include <linux/platform_device.h>
2827 +#include <linux/gpio.h>
2828 +
2829 /** ChipCommon core registers. **/
2830 #define BCMA_CC_ID 0x0000
2831 #define BCMA_CC_ID_ID 0x0000FFFF
2832 @@ -24,7 +27,7 @@
2833 #define BCMA_CC_FLASHT_NONE 0x00000000 /* No flash */
2834 #define BCMA_CC_FLASHT_STSER 0x00000100 /* ST serial flash */
2835 #define BCMA_CC_FLASHT_ATSER 0x00000200 /* Atmel serial flash */
2836 -#define BCMA_CC_FLASHT_NFLASH 0x00000200 /* NAND flash */
2837 +#define BCMA_CC_FLASHT_NAND 0x00000300 /* NAND flash */
2838 #define BCMA_CC_FLASHT_PARA 0x00000700 /* Parallel flash */
2839 #define BCMA_CC_CAP_PLLT 0x00038000 /* PLL Type */
2840 #define BCMA_PLLTYPE_NONE 0x00000000
2841 @@ -100,6 +103,8 @@
2842 #define BCMA_CC_CHIPST_4706_SFLASH_TYPE BIT(2) /* 0: 8b-p/ST-s flash, 1: 16b-p/Atmal-s flash */
2843 #define BCMA_CC_CHIPST_4706_MIPS_BENDIAN BIT(3) /* 0: little, 1: big endian */
2844 #define BCMA_CC_CHIPST_4706_PCIE1_DISABLE BIT(5) /* PCIE1 enable strap pin */
2845 +#define BCMA_CC_CHIPST_5357_NAND_BOOT BIT(4) /* NAND boot, valid for CC rev 38 and/or BCM5357 */
2846 +#define BCMA_CC_CHIPST_4360_XTAL_40MZ 0x00000001
2847 #define BCMA_CC_JCMD 0x0030 /* Rev >= 10 only */
2848 #define BCMA_CC_JCMD_START 0x80000000
2849 #define BCMA_CC_JCMD_BUSY 0x80000000
2850 @@ -266,6 +271,29 @@
2851 #define BCMA_CC_SROM_CONTROL_SIZE_16K 0x00000004
2852 #define BCMA_CC_SROM_CONTROL_SIZE_SHIFT 1
2853 #define BCMA_CC_SROM_CONTROL_PRESENT 0x00000001
2854 +/* Block 0x140 - 0x190 registers are chipset specific */
2855 +#define BCMA_CC_4706_FLASHSCFG 0x18C /* Flash struct configuration */
2856 +#define BCMA_CC_4706_FLASHSCFG_MASK 0x000000ff
2857 +#define BCMA_CC_4706_FLASHSCFG_SF1 0x00000001 /* 2nd serial flash present */
2858 +#define BCMA_CC_4706_FLASHSCFG_PF1 0x00000002 /* 2nd parallel flash present */
2859 +#define BCMA_CC_4706_FLASHSCFG_SF1_TYPE 0x00000004 /* 2nd serial flash type : 0 : ST, 1 : Atmel */
2860 +#define BCMA_CC_4706_FLASHSCFG_NF1 0x00000008 /* 2nd NAND flash present */
2861 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_MASK 0x000000f0
2862 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_4MB 0x00000010 /* 4MB */
2863 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_8MB 0x00000020 /* 8MB */
2864 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_16MB 0x00000030 /* 16MB */
2865 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_32MB 0x00000040 /* 32MB */
2866 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_64MB 0x00000050 /* 64MB */
2867 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_128MB 0x00000060 /* 128MB */
2868 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_256MB 0x00000070 /* 256MB */
2869 +/* NAND flash registers for BCM4706 (corerev = 31) */
2870 +#define BCMA_CC_NFLASH_CTL 0x01A0
2871 +#define BCMA_CC_NFLASH_CTL_ERR 0x08000000
2872 +#define BCMA_CC_NFLASH_CONF 0x01A4
2873 +#define BCMA_CC_NFLASH_COL_ADDR 0x01A8
2874 +#define BCMA_CC_NFLASH_ROW_ADDR 0x01AC
2875 +#define BCMA_CC_NFLASH_DATA 0x01B0
2876 +#define BCMA_CC_NFLASH_WAITCNT0 0x01B4
2877 /* 0x1E0 is defined as shared BCMA_CLKCTLST */
2878 #define BCMA_CC_HW_WORKAROUND 0x01E4 /* Hardware workaround (rev >= 20) */
2879 #define BCMA_CC_UART0_DATA 0x0300
2880 @@ -288,6 +316,9 @@
2881 #define BCMA_CC_PMU_CTL 0x0600 /* PMU control */
2882 #define BCMA_CC_PMU_CTL_ILP_DIV 0xFFFF0000 /* ILP div mask */
2883 #define BCMA_CC_PMU_CTL_ILP_DIV_SHIFT 16
2884 +#define BCMA_CC_PMU_CTL_RES 0x00006000 /* reset control mask */
2885 +#define BCMA_CC_PMU_CTL_RES_SHIFT 13
2886 +#define BCMA_CC_PMU_CTL_RES_RELOAD 0x2 /* reload POR values */
2887 #define BCMA_CC_PMU_CTL_PLL_UPD 0x00000400
2888 #define BCMA_CC_PMU_CTL_NOILPONW 0x00000200 /* No ILP on wait */
2889 #define BCMA_CC_PMU_CTL_HTREQEN 0x00000100 /* HT req enable */
2890 @@ -299,6 +330,8 @@
2891 #define BCMA_CC_PMU_CAP 0x0604 /* PMU capabilities */
2892 #define BCMA_CC_PMU_CAP_REVISION 0x000000FF /* Revision mask */
2893 #define BCMA_CC_PMU_STAT 0x0608 /* PMU status */
2894 +#define BCMA_CC_PMU_STAT_EXT_LPO_AVAIL 0x00000100
2895 +#define BCMA_CC_PMU_STAT_WDRESET 0x00000080
2896 #define BCMA_CC_PMU_STAT_INTPEND 0x00000040 /* Interrupt pending */
2897 #define BCMA_CC_PMU_STAT_SBCLKST 0x00000030 /* Backplane clock status? */
2898 #define BCMA_CC_PMU_STAT_HAVEALP 0x00000008 /* ALP available */
2899 @@ -324,7 +357,66 @@
2900 #define BCMA_CC_REGCTL_DATA 0x065C
2901 #define BCMA_CC_PLLCTL_ADDR 0x0660
2902 #define BCMA_CC_PLLCTL_DATA 0x0664
2903 +#define BCMA_CC_PMU_STRAPOPT 0x0668 /* (corerev >= 28) */
2904 +#define BCMA_CC_PMU_XTAL_FREQ 0x066C /* (pmurev >= 10) */
2905 +#define BCMA_CC_PMU_XTAL_FREQ_ILPCTL_MASK 0x00001FFF
2906 +#define BCMA_CC_PMU_XTAL_FREQ_MEASURE_MASK 0x80000000
2907 +#define BCMA_CC_PMU_XTAL_FREQ_MEASURE_SHIFT 31
2908 #define BCMA_CC_SPROM 0x0800 /* SPROM beginning */
2909 +/* NAND flash MLC controller registers (corerev >= 38) */
2910 +#define BCMA_CC_NAND_REVISION 0x0C00
2911 +#define BCMA_CC_NAND_CMD_START 0x0C04
2912 +#define BCMA_CC_NAND_CMD_ADDR_X 0x0C08
2913 +#define BCMA_CC_NAND_CMD_ADDR 0x0C0C
2914 +#define BCMA_CC_NAND_CMD_END_ADDR 0x0C10
2915 +#define BCMA_CC_NAND_CS_NAND_SELECT 0x0C14
2916 +#define BCMA_CC_NAND_CS_NAND_XOR 0x0C18
2917 +#define BCMA_CC_NAND_SPARE_RD0 0x0C20
2918 +#define BCMA_CC_NAND_SPARE_RD4 0x0C24
2919 +#define BCMA_CC_NAND_SPARE_RD8 0x0C28
2920 +#define BCMA_CC_NAND_SPARE_RD12 0x0C2C
2921 +#define BCMA_CC_NAND_SPARE_WR0 0x0C30
2922 +#define BCMA_CC_NAND_SPARE_WR4 0x0C34
2923 +#define BCMA_CC_NAND_SPARE_WR8 0x0C38
2924 +#define BCMA_CC_NAND_SPARE_WR12 0x0C3C
2925 +#define BCMA_CC_NAND_ACC_CONTROL 0x0C40
2926 +#define BCMA_CC_NAND_CONFIG 0x0C48
2927 +#define BCMA_CC_NAND_TIMING_1 0x0C50
2928 +#define BCMA_CC_NAND_TIMING_2 0x0C54
2929 +#define BCMA_CC_NAND_SEMAPHORE 0x0C58
2930 +#define BCMA_CC_NAND_DEVID 0x0C60
2931 +#define BCMA_CC_NAND_DEVID_X 0x0C64
2932 +#define BCMA_CC_NAND_BLOCK_LOCK_STATUS 0x0C68
2933 +#define BCMA_CC_NAND_INTFC_STATUS 0x0C6C
2934 +#define BCMA_CC_NAND_ECC_CORR_ADDR_X 0x0C70
2935 +#define BCMA_CC_NAND_ECC_CORR_ADDR 0x0C74
2936 +#define BCMA_CC_NAND_ECC_UNC_ADDR_X 0x0C78
2937 +#define BCMA_CC_NAND_ECC_UNC_ADDR 0x0C7C
2938 +#define BCMA_CC_NAND_READ_ERROR_COUNT 0x0C80
2939 +#define BCMA_CC_NAND_CORR_STAT_THRESHOLD 0x0C84
2940 +#define BCMA_CC_NAND_READ_ADDR_X 0x0C90
2941 +#define BCMA_CC_NAND_READ_ADDR 0x0C94
2942 +#define BCMA_CC_NAND_PAGE_PROGRAM_ADDR_X 0x0C98
2943 +#define BCMA_CC_NAND_PAGE_PROGRAM_ADDR 0x0C9C
2944 +#define BCMA_CC_NAND_COPY_BACK_ADDR_X 0x0CA0
2945 +#define BCMA_CC_NAND_COPY_BACK_ADDR 0x0CA4
2946 +#define BCMA_CC_NAND_BLOCK_ERASE_ADDR_X 0x0CA8
2947 +#define BCMA_CC_NAND_BLOCK_ERASE_ADDR 0x0CAC
2948 +#define BCMA_CC_NAND_INV_READ_ADDR_X 0x0CB0
2949 +#define BCMA_CC_NAND_INV_READ_ADDR 0x0CB4
2950 +#define BCMA_CC_NAND_BLK_WR_PROTECT 0x0CC0
2951 +#define BCMA_CC_NAND_ACC_CONTROL_CS1 0x0CD0
2952 +#define BCMA_CC_NAND_CONFIG_CS1 0x0CD4
2953 +#define BCMA_CC_NAND_TIMING_1_CS1 0x0CD8
2954 +#define BCMA_CC_NAND_TIMING_2_CS1 0x0CDC
2955 +#define BCMA_CC_NAND_SPARE_RD16 0x0D30
2956 +#define BCMA_CC_NAND_SPARE_RD20 0x0D34
2957 +#define BCMA_CC_NAND_SPARE_RD24 0x0D38
2958 +#define BCMA_CC_NAND_SPARE_RD28 0x0D3C
2959 +#define BCMA_CC_NAND_CACHE_ADDR 0x0D40
2960 +#define BCMA_CC_NAND_CACHE_DATA 0x0D44
2961 +#define BCMA_CC_NAND_CTRL_CONFIG 0x0D48
2962 +#define BCMA_CC_NAND_CTRL_STATUS 0x0D4C
2963
2964 /* Divider allocation in 4716/47162/5356 */
2965 #define BCMA_CC_PMU5_MAINPLL_CPU 1
2966 @@ -350,6 +442,23 @@
2967 #define BCMA_CC_PMU6_4706_PROC_NDIV_MODE_MASK 0x00000007
2968 #define BCMA_CC_PMU6_4706_PROC_NDIV_MODE_SHIFT 0
2969
2970 +/* PMU rev 15 */
2971 +#define BCMA_CC_PMU15_PLL_PLLCTL0 0
2972 +#define BCMA_CC_PMU15_PLL_PC0_CLKSEL_MASK 0x00000003
2973 +#define BCMA_CC_PMU15_PLL_PC0_CLKSEL_SHIFT 0
2974 +#define BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK 0x003FFFFC
2975 +#define BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT 2
2976 +#define BCMA_CC_PMU15_PLL_PC0_PRESCALE_MASK 0x00C00000
2977 +#define BCMA_CC_PMU15_PLL_PC0_PRESCALE_SHIFT 22
2978 +#define BCMA_CC_PMU15_PLL_PC0_KPCTRL_MASK 0x07000000
2979 +#define BCMA_CC_PMU15_PLL_PC0_KPCTRL_SHIFT 24
2980 +#define BCMA_CC_PMU15_PLL_PC0_FCNTCTRL_MASK 0x38000000
2981 +#define BCMA_CC_PMU15_PLL_PC0_FCNTCTRL_SHIFT 27
2982 +#define BCMA_CC_PMU15_PLL_PC0_FDCMODE_MASK 0x40000000
2983 +#define BCMA_CC_PMU15_PLL_PC0_FDCMODE_SHIFT 30
2984 +#define BCMA_CC_PMU15_PLL_PC0_CTRLBIAS_MASK 0x80000000
2985 +#define BCMA_CC_PMU15_PLL_PC0_CTRLBIAS_SHIFT 31
2986 +
2987 /* ALP clock on pre-PMU chips */
2988 #define BCMA_CC_PMU_ALP_CLOCK 20000000
2989 /* HT clock for systems with PMU-enabled chipcommon */
2990 @@ -415,6 +524,44 @@
2991 /* 4313 Chip specific ChipControl register bits */
2992 #define BCMA_CCTRL_4313_12MA_LED_DRIVE 0x00000007 /* 12 mA drive strengh for later 4313 */
2993
2994 +/* BCM5357 ChipControl register bits */
2995 +#define BCMA_CHIPCTL_5357_EXTPA BIT(14)
2996 +#define BCMA_CHIPCTL_5357_ANT_MUX_2O3 BIT(15)
2997 +#define BCMA_CHIPCTL_5357_NFLASH BIT(16)
2998 +#define BCMA_CHIPCTL_5357_I2S_PINS_ENABLE BIT(18)
2999 +#define BCMA_CHIPCTL_5357_I2CSPI_PINS_ENABLE BIT(19)
3000 +
3001 +#define BCMA_RES_4314_LPLDO_PU BIT(0)
3002 +#define BCMA_RES_4314_PMU_SLEEP_DIS BIT(1)
3003 +#define BCMA_RES_4314_PMU_BG_PU BIT(2)
3004 +#define BCMA_RES_4314_CBUCK_LPOM_PU BIT(3)
3005 +#define BCMA_RES_4314_CBUCK_PFM_PU BIT(4)
3006 +#define BCMA_RES_4314_CLDO_PU BIT(5)
3007 +#define BCMA_RES_4314_LPLDO2_LVM BIT(6)
3008 +#define BCMA_RES_4314_WL_PMU_PU BIT(7)
3009 +#define BCMA_RES_4314_LNLDO_PU BIT(8)
3010 +#define BCMA_RES_4314_LDO3P3_PU BIT(9)
3011 +#define BCMA_RES_4314_OTP_PU BIT(10)
3012 +#define BCMA_RES_4314_XTAL_PU BIT(11)
3013 +#define BCMA_RES_4314_WL_PWRSW_PU BIT(12)
3014 +#define BCMA_RES_4314_LQ_AVAIL BIT(13)
3015 +#define BCMA_RES_4314_LOGIC_RET BIT(14)
3016 +#define BCMA_RES_4314_MEM_SLEEP BIT(15)
3017 +#define BCMA_RES_4314_MACPHY_RET BIT(16)
3018 +#define BCMA_RES_4314_WL_CORE_READY BIT(17)
3019 +#define BCMA_RES_4314_ILP_REQ BIT(18)
3020 +#define BCMA_RES_4314_ALP_AVAIL BIT(19)
3021 +#define BCMA_RES_4314_MISC_PWRSW_PU BIT(20)
3022 +#define BCMA_RES_4314_SYNTH_PWRSW_PU BIT(21)
3023 +#define BCMA_RES_4314_RX_PWRSW_PU BIT(22)
3024 +#define BCMA_RES_4314_RADIO_PU BIT(23)
3025 +#define BCMA_RES_4314_VCO_LDO_PU BIT(24)
3026 +#define BCMA_RES_4314_AFE_LDO_PU BIT(25)
3027 +#define BCMA_RES_4314_RX_LDO_PU BIT(26)
3028 +#define BCMA_RES_4314_TX_LDO_PU BIT(27)
3029 +#define BCMA_RES_4314_HT_AVAIL BIT(28)
3030 +#define BCMA_RES_4314_MACPHY_CLK_AVAIL BIT(29)
3031 +
3032 /* Data for the PMU, if available.
3033 * Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU)
3034 */
3035 @@ -425,11 +572,36 @@ struct bcma_chipcommon_pmu {
3036
3037 #ifdef CONFIG_BCMA_DRIVER_MIPS
3038 struct bcma_pflash {
3039 + bool present;
3040 u8 buswidth;
3041 u32 window;
3042 u32 window_size;
3043 };
3044
3045 +#ifdef CONFIG_BCMA_SFLASH
3046 +struct bcma_sflash {
3047 + bool present;
3048 + u32 window;
3049 + u32 blocksize;
3050 + u16 numblocks;
3051 + u32 size;
3052 +
3053 + struct mtd_info *mtd;
3054 + void *priv;
3055 +};
3056 +#endif
3057 +
3058 +#ifdef CONFIG_BCMA_NFLASH
3059 +struct mtd_info;
3060 +
3061 +struct bcma_nflash {
3062 + bool present;
3063 + bool boot; /* This is the flash the SoC boots from */
3064 +
3065 + struct mtd_info *mtd;
3066 +};
3067 +#endif
3068 +
3069 struct bcma_serial_port {
3070 void *regs;
3071 unsigned long clockspeed;
3072 @@ -445,15 +617,30 @@ struct bcma_drv_cc {
3073 u32 capabilities;
3074 u32 capabilities_ext;
3075 u8 setup_done:1;
3076 + u8 early_setup_done:1;
3077 /* Fast Powerup Delay constant */
3078 u16 fast_pwrup_delay;
3079 struct bcma_chipcommon_pmu pmu;
3080 #ifdef CONFIG_BCMA_DRIVER_MIPS
3081 struct bcma_pflash pflash;
3082 +#ifdef CONFIG_BCMA_SFLASH
3083 + struct bcma_sflash sflash;
3084 +#endif
3085 +#ifdef CONFIG_BCMA_NFLASH
3086 + struct bcma_nflash nflash;
3087 +#endif
3088
3089 int nr_serial_ports;
3090 struct bcma_serial_port serial_ports[4];
3091 #endif /* CONFIG_BCMA_DRIVER_MIPS */
3092 + u32 ticks_per_ms;
3093 + struct platform_device *watchdog;
3094 +
3095 + /* Lock for GPIO register access. */
3096 + spinlock_t gpio_lock;
3097 +#ifdef CONFIG_BCMA_DRIVER_GPIO
3098 + struct gpio_chip gpio;
3099 +#endif
3100 };
3101
3102 /* Register access */
3103 @@ -470,14 +657,16 @@ struct bcma_drv_cc {
3104 bcma_cc_write32(cc, offset, (bcma_cc_read32(cc, offset) & (mask)) | (set))
3105
3106 extern void bcma_core_chipcommon_init(struct bcma_drv_cc *cc);
3107 +extern void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc);
3108
3109 extern void bcma_chipco_suspend(struct bcma_drv_cc *cc);
3110 extern void bcma_chipco_resume(struct bcma_drv_cc *cc);
3111
3112 void bcma_chipco_bcm4331_ext_pa_lines_ctl(struct bcma_drv_cc *cc, bool enable);
3113
3114 -extern void bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc,
3115 - u32 ticks);
3116 +extern u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks);
3117 +
3118 +extern u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc);
3119
3120 void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value);
3121
3122 @@ -490,9 +679,12 @@ u32 bcma_chipco_gpio_outen(struct bcma_d
3123 u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value);
3124 u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value);
3125 u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value);
3126 +u32 bcma_chipco_gpio_pullup(struct bcma_drv_cc *cc, u32 mask, u32 value);
3127 +u32 bcma_chipco_gpio_pulldown(struct bcma_drv_cc *cc, u32 mask, u32 value);
3128
3129 /* PMU support */
3130 extern void bcma_pmu_init(struct bcma_drv_cc *cc);
3131 +extern void bcma_pmu_early_init(struct bcma_drv_cc *cc);
3132
3133 extern void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset,
3134 u32 value);
3135 @@ -504,4 +696,6 @@ extern void bcma_chipco_regctl_maskset(s
3136 u32 offset, u32 mask, u32 set);
3137 extern void bcma_pmu_spuravoid_pllupdate(struct bcma_drv_cc *cc, int spuravoid);
3138
3139 +extern u32 bcma_pmu_get_bus_clock(struct bcma_drv_cc *cc);
3140 +
3141 #endif /* LINUX_BCMA_DRIVER_CC_H_ */
3142 --- a/include/linux/bcma/bcma_driver_mips.h
3143 +++ b/include/linux/bcma/bcma_driver_mips.h
3144 @@ -28,6 +28,7 @@
3145 #define BCMA_MIPS_MIPS74K_GPIOEN 0x0048
3146 #define BCMA_MIPS_MIPS74K_CLKCTLST 0x01E0
3147
3148 +#define BCMA_MIPS_OOBSELINA74 0x004
3149 #define BCMA_MIPS_OOBSELOUTA30 0x100
3150
3151 struct bcma_device;
3152 @@ -35,17 +36,24 @@ struct bcma_device;
3153 struct bcma_drv_mips {
3154 struct bcma_device *core;
3155 u8 setup_done:1;
3156 - unsigned int assigned_irqs;
3157 + u8 early_setup_done:1;
3158 };
3159
3160 #ifdef CONFIG_BCMA_DRIVER_MIPS
3161 extern void bcma_core_mips_init(struct bcma_drv_mips *mcore);
3162 +extern void bcma_core_mips_early_init(struct bcma_drv_mips *mcore);
3163 +
3164 +extern unsigned int bcma_core_irq(struct bcma_device *core);
3165 #else
3166 static inline void bcma_core_mips_init(struct bcma_drv_mips *mcore) { }
3167 +static inline void bcma_core_mips_early_init(struct bcma_drv_mips *mcore) { }
3168 +
3169 +static inline unsigned int bcma_core_irq(struct bcma_device *core)
3170 +{
3171 + return 0;
3172 +}
3173 #endif
3174
3175 extern u32 bcma_cpu_clock(struct bcma_drv_mips *mcore);
3176
3177 -extern unsigned int bcma_core_mips_irq(struct bcma_device *dev);
3178 -
3179 #endif /* LINUX_BCMA_DRIVER_MIPS_H_ */
3180 --- a/include/linux/bcma/bcma_driver_pci.h
3181 +++ b/include/linux/bcma/bcma_driver_pci.h
3182 @@ -179,10 +179,33 @@ struct pci_dev;
3183 #define BCMA_CORE_PCI_CFG_FUN_MASK 7 /* Function mask */
3184 #define BCMA_CORE_PCI_CFG_OFF_MASK 0xfff /* Register mask */
3185
3186 +#define BCMA_CORE_PCI_CFG_DEVCTRL 0xd8
3187 +
3188 +#define BCMA_CORE_PCI_
3189 +
3190 +/* MDIO devices (SERDES modules) */
3191 +#define BCMA_CORE_PCI_MDIO_IEEE0 0x000
3192 +#define BCMA_CORE_PCI_MDIO_IEEE1 0x001
3193 +#define BCMA_CORE_PCI_MDIO_BLK0 0x800
3194 +#define BCMA_CORE_PCI_MDIO_BLK1 0x801
3195 +#define BCMA_CORE_PCI_MDIO_BLK1_MGMT0 0x16
3196 +#define BCMA_CORE_PCI_MDIO_BLK1_MGMT1 0x17
3197 +#define BCMA_CORE_PCI_MDIO_BLK1_MGMT2 0x18
3198 +#define BCMA_CORE_PCI_MDIO_BLK1_MGMT3 0x19
3199 +#define BCMA_CORE_PCI_MDIO_BLK1_MGMT4 0x1A
3200 +#define BCMA_CORE_PCI_MDIO_BLK2 0x802
3201 +#define BCMA_CORE_PCI_MDIO_BLK3 0x803
3202 +#define BCMA_CORE_PCI_MDIO_BLK4 0x804
3203 +#define BCMA_CORE_PCI_MDIO_TXPLL 0x808 /* TXPLL register block idx */
3204 +#define BCMA_CORE_PCI_MDIO_TXCTRL0 0x820
3205 +#define BCMA_CORE_PCI_MDIO_SERDESID 0x831
3206 +#define BCMA_CORE_PCI_MDIO_RXCTRL0 0x840
3207 +
3208 /* PCIE Root Capability Register bits (Host mode only) */
3209 #define BCMA_CORE_PCI_RC_CRS_VISIBILITY 0x0001
3210
3211 struct bcma_drv_pci;
3212 +struct bcma_bus;
3213
3214 #ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
3215 struct bcma_drv_pci_host {
3216 @@ -217,7 +240,9 @@ struct bcma_drv_pci {
3217 extern void __devinit bcma_core_pci_init(struct bcma_drv_pci *pc);
3218 extern int bcma_core_pci_irq_ctl(struct bcma_drv_pci *pc,
3219 struct bcma_device *core, bool enable);
3220 -extern void bcma_core_pci_extend_L1timer(struct bcma_drv_pci *pc, bool extend);
3221 +extern void bcma_core_pci_up(struct bcma_bus *bus);
3222 +extern void bcma_core_pci_down(struct bcma_bus *bus);
3223 +extern void bcma_core_pci_power_save(struct bcma_bus *bus, bool up);
3224
3225 extern int bcma_core_pci_pcibios_map_irq(const struct pci_dev *dev);
3226 extern int bcma_core_pci_plat_dev_init(struct pci_dev *dev);
3227 --- a/include/linux/bcma/bcma_regs.h
3228 +++ b/include/linux/bcma/bcma_regs.h
3229 @@ -11,11 +11,13 @@
3230 #define BCMA_CLKCTLST_HAVEHTREQ 0x00000010 /* HT available request */
3231 #define BCMA_CLKCTLST_HWCROFF 0x00000020 /* Force HW clock request off */
3232 #define BCMA_CLKCTLST_EXTRESREQ 0x00000700 /* Mask of external resource requests */
3233 +#define BCMA_CLKCTLST_EXTRESREQ_SHIFT 8
3234 #define BCMA_CLKCTLST_HAVEALP 0x00010000 /* ALP available */
3235 #define BCMA_CLKCTLST_HAVEHT 0x00020000 /* HT available */
3236 #define BCMA_CLKCTLST_BP_ON_ALP 0x00040000 /* RO: running on ALP clock */
3237 #define BCMA_CLKCTLST_BP_ON_HT 0x00080000 /* RO: running on HT clock */
3238 #define BCMA_CLKCTLST_EXTRESST 0x07000000 /* Mask of external resource status */
3239 +#define BCMA_CLKCTLST_EXTRESST_SHIFT 24
3240 /* Is there any BCM4328 on BCMA bus? */
3241 #define BCMA_CLKCTLST_4328A0_HAVEHT 0x00010000 /* 4328a0 has reversed bits */
3242 #define BCMA_CLKCTLST_4328A0_HAVEALP 0x00020000 /* 4328a0 has reversed bits */
3243 @@ -35,6 +37,7 @@
3244 #define BCMA_IOST_BIST_DONE 0x8000
3245 #define BCMA_RESET_CTL 0x0800
3246 #define BCMA_RESET_CTL_RESET 0x0001
3247 +#define BCMA_RESET_ST 0x0804
3248
3249 /* BCMA PCI config space registers. */
3250 #define BCMA_PCI_PMCSR 0x44
3251 @@ -83,4 +86,9 @@
3252 * (2 ZettaBytes), high 32 bits
3253 */
3254
3255 +#define BCMA_SOC_FLASH1 0x1fc00000 /* MIPS Flash Region 1 */
3256 +#define BCMA_SOC_FLASH1_SZ 0x00400000 /* MIPS Size of Flash Region 1 */
3257 +#define BCMA_SOC_FLASH2 0x1c000000 /* Flash Region 2 (region 1 shadowed here) */
3258 +#define BCMA_SOC_FLASH2_SZ 0x02000000 /* Size of Flash Region 2 */
3259 +
3260 #endif /* LINUX_BCMA_REGS_H_ */
3261 --- a/drivers/net/wireless/b43/main.c
3262 +++ b/drivers/net/wireless/b43/main.c
3263 @@ -4622,7 +4622,7 @@ static int b43_wireless_core_init(struct
3264 switch (dev->dev->bus_type) {
3265 #ifdef CONFIG_B43_BCMA
3266 case B43_BUS_BCMA:
3267 - bcma_core_pci_irq_ctl(&dev->dev->bdev->bus->drv_pci,
3268 + bcma_core_pci_irq_ctl(&dev->dev->bdev->bus->drv_pci[0],
3269 dev->dev->bdev, true);
3270 break;
3271 #endif
3272 --- a/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c
3273 +++ b/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c
3274 @@ -688,27 +688,6 @@ bool ai_clkctl_cc(struct si_pub *sih, en
3275 return mode == BCMA_CLKMODE_FAST;
3276 }
3277
3278 -void ai_pci_up(struct si_pub *sih)
3279 -{
3280 - struct si_info *sii;
3281 -
3282 - sii = container_of(sih, struct si_info, pub);
3283 -
3284 - if (sii->icbus->hosttype == BCMA_HOSTTYPE_PCI)
3285 - bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci, true);
3286 -}
3287 -
3288 -/* Unconfigure and/or apply various WARs when going down */
3289 -void ai_pci_down(struct si_pub *sih)
3290 -{
3291 - struct si_info *sii;
3292 -
3293 - sii = container_of(sih, struct si_info, pub);
3294 -
3295 - if (sii->icbus->hosttype == BCMA_HOSTTYPE_PCI)
3296 - bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci, false);
3297 -}
3298 -
3299 /* Enable BT-COEX & Ex-PA for 4313 */
3300 void ai_epa_4313war(struct si_pub *sih)
3301 {
3302 --- a/drivers/net/wireless/brcm80211/brcmsmac/main.c
3303 +++ b/drivers/net/wireless/brcm80211/brcmsmac/main.c
3304 @@ -4689,7 +4689,7 @@ static int brcms_b_attach(struct brcms_c
3305 brcms_c_coredisable(wlc_hw);
3306
3307 /* Match driver "down" state */
3308 - ai_pci_down(wlc_hw->sih);
3309 + bcma_core_pci_down(wlc_hw->d11core->bus);
3310
3311 /* turn off pll and xtal to match driver "down" state */
3312 brcms_b_xtal(wlc_hw, OFF);
3313 @@ -5077,7 +5077,7 @@ static int brcms_b_up_prep(struct brcms_
3314 * Configure pci/pcmcia here instead of in brcms_c_attach()
3315 * to allow mfg hotswap: down, hotswap (chip power cycle), up.
3316 */
3317 - bcma_core_pci_irq_ctl(&wlc_hw->d11core->bus->drv_pci, wlc_hw->d11core,
3318 + bcma_core_pci_irq_ctl(&wlc_hw->d11core->bus->drv_pci[0], wlc_hw->d11core,
3319 true);
3320
3321 /*
3322 @@ -5087,12 +5087,12 @@ static int brcms_b_up_prep(struct brcms_
3323 */
3324 if (brcms_b_radio_read_hwdisabled(wlc_hw)) {
3325 /* put SB PCI in down state again */
3326 - ai_pci_down(wlc_hw->sih);
3327 + bcma_core_pci_down(wlc_hw->d11core->bus);
3328 brcms_b_xtal(wlc_hw, OFF);
3329 return -ENOMEDIUM;
3330 }
3331
3332 - ai_pci_up(wlc_hw->sih);
3333 + bcma_core_pci_up(wlc_hw->d11core->bus);
3334
3335 /* reset the d11 core */
3336 brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS);
3337 @@ -5295,7 +5295,7 @@ static int brcms_b_down_finish(struct br
3338
3339 /* turn off primary xtal and pll */
3340 if (!wlc_hw->noreset) {
3341 - ai_pci_down(wlc_hw->sih);
3342 + bcma_core_pci_down(wlc_hw->d11core->bus);
3343 brcms_b_xtal(wlc_hw, OFF);
3344 }
3345 }
3346 --- a/drivers/net/wireless/brcm80211/brcmsmac/aiutils.h
3347 +++ b/drivers/net/wireless/brcm80211/brcmsmac/aiutils.h
3348 @@ -183,9 +183,6 @@ extern u16 ai_clkctl_fast_pwrup_delay(st
3349 extern bool ai_clkctl_cc(struct si_pub *sih, enum bcma_clkmode mode);
3350 extern bool ai_deviceremoved(struct si_pub *sih);
3351
3352 -extern void ai_pci_down(struct si_pub *sih);
3353 -extern void ai_pci_up(struct si_pub *sih);
3354 -
3355 /* Enable Ex-PA for 4313 */
3356 extern void ai_epa_4313war(struct si_pub *sih);
3357
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