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brcm47xx: add support for kernel 3.6
[openwrt/staging/dedeckeh.git] / target / linux / generic / patches-3.6 / 025-bcma_backport.patch
1 --- a/arch/mips/bcm47xx/nvram.c
2 +++ b/arch/mips/bcm47xx/nvram.c
3 @@ -43,8 +43,8 @@ static void early_nvram_init(void)
4 #ifdef CONFIG_BCM47XX_SSB
5 case BCM47XX_BUS_TYPE_SSB:
6 mcore_ssb = &bcm47xx_bus.ssb.mipscore;
7 - base = mcore_ssb->flash_window;
8 - lim = mcore_ssb->flash_window_size;
9 + base = mcore_ssb->pflash.window;
10 + lim = mcore_ssb->pflash.window_size;
11 break;
12 #endif
13 #ifdef CONFIG_BCM47XX_BCMA
14 --- a/arch/mips/bcm47xx/wgt634u.c
15 +++ b/arch/mips/bcm47xx/wgt634u.c
16 @@ -156,10 +156,10 @@ static int __init wgt634u_init(void)
17 SSB_CHIPCO_IRQ_GPIO);
18 }
19
20 - wgt634u_flash_data.width = mcore->flash_buswidth;
21 - wgt634u_flash_resource.start = mcore->flash_window;
22 - wgt634u_flash_resource.end = mcore->flash_window
23 - + mcore->flash_window_size
24 + wgt634u_flash_data.width = mcore->pflash.buswidth;
25 + wgt634u_flash_resource.start = mcore->pflash.window;
26 + wgt634u_flash_resource.end = mcore->pflash.window
27 + + mcore->pflash.window_size
28 - 1;
29 return platform_add_devices(wgt634u_devices,
30 ARRAY_SIZE(wgt634u_devices));
31 --- a/drivers/bcma/Kconfig
32 +++ b/drivers/bcma/Kconfig
33 @@ -48,12 +48,12 @@ config BCMA_DRIVER_MIPS
34
35 config BCMA_SFLASH
36 bool
37 - depends on BCMA_DRIVER_MIPS && BROKEN
38 + depends on BCMA_DRIVER_MIPS
39 default y
40
41 config BCMA_NFLASH
42 bool
43 - depends on BCMA_DRIVER_MIPS && BROKEN
44 + depends on BCMA_DRIVER_MIPS
45 default y
46
47 config BCMA_DRIVER_GMAC_CMN
48 --- a/drivers/bcma/bcma_private.h
49 +++ b/drivers/bcma/bcma_private.h
50 @@ -54,6 +54,7 @@ u32 bcma_pmu_get_clockcpu(struct bcma_dr
51 #ifdef CONFIG_BCMA_SFLASH
52 /* driver_chipcommon_sflash.c */
53 int bcma_sflash_init(struct bcma_drv_cc *cc);
54 +extern struct platform_device bcma_sflash_dev;
55 #else
56 static inline int bcma_sflash_init(struct bcma_drv_cc *cc)
57 {
58 @@ -65,6 +66,7 @@ static inline int bcma_sflash_init(struc
59 #ifdef CONFIG_BCMA_NFLASH
60 /* driver_chipcommon_nflash.c */
61 int bcma_nflash_init(struct bcma_drv_cc *cc);
62 +extern struct platform_device bcma_nflash_dev;
63 #else
64 static inline int bcma_nflash_init(struct bcma_drv_cc *cc)
65 {
66 --- a/drivers/bcma/core.c
67 +++ b/drivers/bcma/core.c
68 @@ -65,7 +65,7 @@ void bcma_core_set_clockmode(struct bcma
69 switch (clkmode) {
70 case BCMA_CLKMODE_FAST:
71 bcma_set32(core, BCMA_CLKCTLST, BCMA_CLKCTLST_FORCEHT);
72 - udelay(64);
73 + usleep_range(64, 300);
74 for (i = 0; i < 1500; i++) {
75 if (bcma_read32(core, BCMA_CLKCTLST) &
76 BCMA_CLKCTLST_HAVEHT) {
77 --- a/drivers/bcma/driver_chipcommon.c
78 +++ b/drivers/bcma/driver_chipcommon.c
79 @@ -22,12 +22,9 @@ static inline u32 bcma_cc_write32_masked
80 return value;
81 }
82
83 -void bcma_core_chipcommon_init(struct bcma_drv_cc *cc)
84 +void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc)
85 {
86 - u32 leddc_on = 10;
87 - u32 leddc_off = 90;
88 -
89 - if (cc->setup_done)
90 + if (cc->early_setup_done)
91 return;
92
93 if (cc->core->id.rev >= 11)
94 @@ -36,6 +33,22 @@ void bcma_core_chipcommon_init(struct bc
95 if (cc->core->id.rev >= 35)
96 cc->capabilities_ext = bcma_cc_read32(cc, BCMA_CC_CAP_EXT);
97
98 + if (cc->capabilities & BCMA_CC_CAP_PMU)
99 + bcma_pmu_early_init(cc);
100 +
101 + cc->early_setup_done = true;
102 +}
103 +
104 +void bcma_core_chipcommon_init(struct bcma_drv_cc *cc)
105 +{
106 + u32 leddc_on = 10;
107 + u32 leddc_off = 90;
108 +
109 + if (cc->setup_done)
110 + return;
111 +
112 + bcma_core_chipcommon_early_init(cc);
113 +
114 if (cc->core->id.rev >= 20) {
115 bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, 0);
116 bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, 0);
117 --- a/drivers/bcma/driver_chipcommon_nflash.c
118 +++ b/drivers/bcma/driver_chipcommon_nflash.c
119 @@ -5,15 +5,40 @@
120 * Licensed under the GNU/GPL. See COPYING for details.
121 */
122
123 +#include <linux/platform_device.h>
124 #include <linux/bcma/bcma.h>
125 -#include <linux/bcma/bcma_driver_chipcommon.h>
126 -#include <linux/delay.h>
127
128 #include "bcma_private.h"
129
130 +struct platform_device bcma_nflash_dev = {
131 + .name = "bcma_nflash",
132 + .num_resources = 0,
133 +};
134 +
135 /* Initialize NAND flash access */
136 int bcma_nflash_init(struct bcma_drv_cc *cc)
137 {
138 - bcma_err(cc->core->bus, "NAND flash support is broken\n");
139 + struct bcma_bus *bus = cc->core->bus;
140 +
141 + if (bus->chipinfo.id != BCMA_CHIP_ID_BCM4706 &&
142 + cc->core->id.rev != 0x38) {
143 + bcma_err(bus, "NAND flash on unsupported board!\n");
144 + return -ENOTSUPP;
145 + }
146 +
147 + if (!(cc->capabilities & BCMA_CC_CAP_NFLASH)) {
148 + bcma_err(bus, "NAND flash not present according to ChipCommon\n");
149 + return -ENODEV;
150 + }
151 +
152 + cc->nflash.present = true;
153 + if (cc->core->id.rev == 38 &&
154 + (cc->status & BCMA_CC_CHIPST_5357_NAND_BOOT))
155 + cc->nflash.boot = true;
156 +
157 + /* Prepare platform device, but don't register it yet. It's too early,
158 + * malloc (required by device_private_init) is not available yet. */
159 + bcma_nflash_dev.dev.platform_data = &cc->nflash;
160 +
161 return 0;
162 }
163 --- a/drivers/bcma/driver_chipcommon_pmu.c
164 +++ b/drivers/bcma/driver_chipcommon_pmu.c
165 @@ -76,7 +76,10 @@ static void bcma_pmu_resources_init(stru
166 if (max_msk)
167 bcma_cc_write32(cc, BCMA_CC_PMU_MAXRES_MSK, max_msk);
168
169 - /* Add some delay; allow resources to come up and settle. */
170 + /*
171 + * Add some delay; allow resources to come up and settle.
172 + * Delay is required for SoC (early init).
173 + */
174 mdelay(2);
175 }
176
177 @@ -101,7 +104,7 @@ void bcma_chipco_bcm4331_ext_pa_lines_ct
178 bcma_cc_write32(cc, BCMA_CC_CHIPCTL, val);
179 }
180
181 -void bcma_pmu_workarounds(struct bcma_drv_cc *cc)
182 +static void bcma_pmu_workarounds(struct bcma_drv_cc *cc)
183 {
184 struct bcma_bus *bus = cc->core->bus;
185
186 @@ -141,7 +144,7 @@ void bcma_pmu_workarounds(struct bcma_dr
187 }
188 }
189
190 -void bcma_pmu_init(struct bcma_drv_cc *cc)
191 +void bcma_pmu_early_init(struct bcma_drv_cc *cc)
192 {
193 u32 pmucap;
194
195 @@ -150,7 +153,10 @@ void bcma_pmu_init(struct bcma_drv_cc *c
196
197 bcma_debug(cc->core->bus, "Found rev %u PMU (capabilities 0x%08X)\n",
198 cc->pmu.rev, pmucap);
199 +}
200
201 +void bcma_pmu_init(struct bcma_drv_cc *cc)
202 +{
203 if (cc->pmu.rev == 1)
204 bcma_cc_mask32(cc, BCMA_CC_PMU_CTL,
205 ~BCMA_CC_PMU_CTL_NOILPONW);
206 @@ -257,7 +263,7 @@ static u32 bcma_pmu_clock_bcm4706(struct
207 }
208
209 /* query bus clock frequency for PMU-enabled chipcommon */
210 -u32 bcma_pmu_get_clockcontrol(struct bcma_drv_cc *cc)
211 +static u32 bcma_pmu_get_clockcontrol(struct bcma_drv_cc *cc)
212 {
213 struct bcma_bus *bus = cc->core->bus;
214
215 --- a/drivers/bcma/driver_chipcommon_sflash.c
216 +++ b/drivers/bcma/driver_chipcommon_sflash.c
217 @@ -5,15 +5,161 @@
218 * Licensed under the GNU/GPL. See COPYING for details.
219 */
220
221 +#include <linux/platform_device.h>
222 #include <linux/bcma/bcma.h>
223 -#include <linux/bcma/bcma_driver_chipcommon.h>
224 -#include <linux/delay.h>
225
226 #include "bcma_private.h"
227
228 +static struct resource bcma_sflash_resource = {
229 + .name = "bcma_sflash",
230 + .start = BCMA_SOC_FLASH2,
231 + .end = 0,
232 + .flags = IORESOURCE_MEM | IORESOURCE_READONLY,
233 +};
234 +
235 +struct platform_device bcma_sflash_dev = {
236 + .name = "bcma_sflash",
237 + .resource = &bcma_sflash_resource,
238 + .num_resources = 1,
239 +};
240 +
241 +struct bcma_sflash_tbl_e {
242 + char *name;
243 + u32 id;
244 + u32 blocksize;
245 + u16 numblocks;
246 +};
247 +
248 +static struct bcma_sflash_tbl_e bcma_sflash_st_tbl[] = {
249 + { "M25P20", 0x11, 0x10000, 4, },
250 + { "M25P40", 0x12, 0x10000, 8, },
251 +
252 + { "M25P16", 0x14, 0x10000, 32, },
253 + { "M25P32", 0x14, 0x10000, 64, },
254 + { "M25P64", 0x16, 0x10000, 128, },
255 + { "M25FL128", 0x17, 0x10000, 256, },
256 + { 0 },
257 +};
258 +
259 +static struct bcma_sflash_tbl_e bcma_sflash_sst_tbl[] = {
260 + { "SST25WF512", 1, 0x1000, 16, },
261 + { "SST25VF512", 0x48, 0x1000, 16, },
262 + { "SST25WF010", 2, 0x1000, 32, },
263 + { "SST25VF010", 0x49, 0x1000, 32, },
264 + { "SST25WF020", 3, 0x1000, 64, },
265 + { "SST25VF020", 0x43, 0x1000, 64, },
266 + { "SST25WF040", 4, 0x1000, 128, },
267 + { "SST25VF040", 0x44, 0x1000, 128, },
268 + { "SST25VF040B", 0x8d, 0x1000, 128, },
269 + { "SST25WF080", 5, 0x1000, 256, },
270 + { "SST25VF080B", 0x8e, 0x1000, 256, },
271 + { "SST25VF016", 0x41, 0x1000, 512, },
272 + { "SST25VF032", 0x4a, 0x1000, 1024, },
273 + { "SST25VF064", 0x4b, 0x1000, 2048, },
274 + { 0 },
275 +};
276 +
277 +static struct bcma_sflash_tbl_e bcma_sflash_at_tbl[] = {
278 + { "AT45DB011", 0xc, 256, 512, },
279 + { "AT45DB021", 0x14, 256, 1024, },
280 + { "AT45DB041", 0x1c, 256, 2048, },
281 + { "AT45DB081", 0x24, 256, 4096, },
282 + { "AT45DB161", 0x2c, 512, 4096, },
283 + { "AT45DB321", 0x34, 512, 8192, },
284 + { "AT45DB642", 0x3c, 1024, 8192, },
285 + { 0 },
286 +};
287 +
288 +static void bcma_sflash_cmd(struct bcma_drv_cc *cc, u32 opcode)
289 +{
290 + int i;
291 + bcma_cc_write32(cc, BCMA_CC_FLASHCTL,
292 + BCMA_CC_FLASHCTL_START | opcode);
293 + for (i = 0; i < 1000; i++) {
294 + if (!(bcma_cc_read32(cc, BCMA_CC_FLASHCTL) &
295 + BCMA_CC_FLASHCTL_BUSY))
296 + return;
297 + cpu_relax();
298 + }
299 + bcma_err(cc->core->bus, "SFLASH control command failed (timeout)!\n");
300 +}
301 +
302 /* Initialize serial flash access */
303 int bcma_sflash_init(struct bcma_drv_cc *cc)
304 {
305 - bcma_err(cc->core->bus, "Serial flash support is broken\n");
306 + struct bcma_bus *bus = cc->core->bus;
307 + struct bcma_sflash *sflash = &cc->sflash;
308 + struct bcma_sflash_tbl_e *e;
309 + u32 id, id2;
310 +
311 + switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {
312 + case BCMA_CC_FLASHT_STSER:
313 + bcma_sflash_cmd(cc, BCMA_CC_FLASHCTL_ST_DP);
314 +
315 + bcma_cc_write32(cc, BCMA_CC_FLASHADDR, 0);
316 + bcma_sflash_cmd(cc, BCMA_CC_FLASHCTL_ST_RES);
317 + id = bcma_cc_read32(cc, BCMA_CC_FLASHDATA);
318 +
319 + bcma_cc_write32(cc, BCMA_CC_FLASHADDR, 1);
320 + bcma_sflash_cmd(cc, BCMA_CC_FLASHCTL_ST_RES);
321 + id2 = bcma_cc_read32(cc, BCMA_CC_FLASHDATA);
322 +
323 + switch (id) {
324 + case 0xbf:
325 + for (e = bcma_sflash_sst_tbl; e->name; e++) {
326 + if (e->id == id2)
327 + break;
328 + }
329 + break;
330 + case 0x13:
331 + return -ENOTSUPP;
332 + default:
333 + for (e = bcma_sflash_st_tbl; e->name; e++) {
334 + if (e->id == id)
335 + break;
336 + }
337 + break;
338 + }
339 + if (!e->name) {
340 + bcma_err(bus, "Unsupported ST serial flash (id: 0x%X, id2: 0x%X)\n", id, id2);
341 + return -ENOTSUPP;
342 + }
343 +
344 + break;
345 + case BCMA_CC_FLASHT_ATSER:
346 + bcma_sflash_cmd(cc, BCMA_CC_FLASHCTL_AT_STATUS);
347 + id = bcma_cc_read32(cc, BCMA_CC_FLASHDATA) & 0x3c;
348 +
349 + for (e = bcma_sflash_at_tbl; e->name; e++) {
350 + if (e->id == id)
351 + break;
352 + }
353 + if (!e->name) {
354 + bcma_err(bus, "Unsupported Atmel serial flash (id: 0x%X)\n", id);
355 + return -ENOTSUPP;
356 + }
357 +
358 + break;
359 + default:
360 + bcma_err(bus, "Unsupported flash type\n");
361 + return -ENOTSUPP;
362 + }
363 +
364 + sflash->window = BCMA_SOC_FLASH2;
365 + sflash->blocksize = e->blocksize;
366 + sflash->numblocks = e->numblocks;
367 + sflash->size = sflash->blocksize * sflash->numblocks;
368 + sflash->present = true;
369 +
370 + bcma_info(bus, "Found %s serial flash (size: %dKiB, blocksize: 0x%X, blocks: %d)\n",
371 + e->name, sflash->size / 1024, sflash->blocksize,
372 + sflash->numblocks);
373 +
374 + /* Prepare platform device, but don't register it yet. It's too early,
375 + * malloc (required by device_private_init) is not available yet. */
376 + bcma_sflash_dev.resource[0].end = bcma_sflash_dev.resource[0].start +
377 + sflash->size;
378 + bcma_sflash_dev.dev.platform_data = sflash;
379 +
380 return 0;
381 }
382 --- a/drivers/bcma/driver_mips.c
383 +++ b/drivers/bcma/driver_mips.c
384 @@ -181,47 +181,66 @@ EXPORT_SYMBOL(bcma_cpu_clock);
385 static void bcma_core_mips_flash_detect(struct bcma_drv_mips *mcore)
386 {
387 struct bcma_bus *bus = mcore->core->bus;
388 + struct bcma_drv_cc *cc = &bus->drv_cc;
389
390 - switch (bus->drv_cc.capabilities & BCMA_CC_CAP_FLASHT) {
391 + switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {
392 case BCMA_CC_FLASHT_STSER:
393 case BCMA_CC_FLASHT_ATSER:
394 bcma_debug(bus, "Found serial flash\n");
395 - bcma_sflash_init(&bus->drv_cc);
396 + bcma_sflash_init(cc);
397 break;
398 case BCMA_CC_FLASHT_PARA:
399 bcma_debug(bus, "Found parallel flash\n");
400 - bus->drv_cc.pflash.window = 0x1c000000;
401 - bus->drv_cc.pflash.window_size = 0x02000000;
402 + cc->pflash.present = true;
403 + cc->pflash.window = BCMA_SOC_FLASH2;
404 + cc->pflash.window_size = BCMA_SOC_FLASH2_SZ;
405
406 - if ((bcma_read32(bus->drv_cc.core, BCMA_CC_FLASH_CFG) &
407 + if ((bcma_read32(cc->core, BCMA_CC_FLASH_CFG) &
408 BCMA_CC_FLASH_CFG_DS) == 0)
409 - bus->drv_cc.pflash.buswidth = 1;
410 + cc->pflash.buswidth = 1;
411 else
412 - bus->drv_cc.pflash.buswidth = 2;
413 + cc->pflash.buswidth = 2;
414 break;
415 default:
416 bcma_err(bus, "Flash type not supported\n");
417 }
418
419 - if (bus->drv_cc.core->id.rev == 38 ||
420 + if (cc->core->id.rev == 38 ||
421 bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) {
422 - if (bus->drv_cc.capabilities & BCMA_CC_CAP_NFLASH) {
423 + if (cc->capabilities & BCMA_CC_CAP_NFLASH) {
424 bcma_debug(bus, "Found NAND flash\n");
425 - bcma_nflash_init(&bus->drv_cc);
426 + bcma_nflash_init(cc);
427 }
428 }
429 }
430
431 +void bcma_core_mips_early_init(struct bcma_drv_mips *mcore)
432 +{
433 + struct bcma_bus *bus = mcore->core->bus;
434 +
435 + if (mcore->early_setup_done)
436 + return;
437 +
438 + bcma_chipco_serial_init(&bus->drv_cc);
439 + bcma_core_mips_flash_detect(mcore);
440 +
441 + mcore->early_setup_done = true;
442 +}
443 +
444 void bcma_core_mips_init(struct bcma_drv_mips *mcore)
445 {
446 struct bcma_bus *bus;
447 struct bcma_device *core;
448 bus = mcore->core->bus;
449
450 + if (mcore->setup_done)
451 + return;
452 +
453 bcma_info(bus, "Initializing MIPS core...\n");
454
455 - if (!mcore->setup_done)
456 - mcore->assigned_irqs = 1;
457 + bcma_core_mips_early_init(mcore);
458 +
459 + mcore->assigned_irqs = 1;
460
461 /* Assign IRQs to all cores on the bus */
462 list_for_each_entry(core, &bus->cores, list) {
463 @@ -256,10 +275,5 @@ void bcma_core_mips_init(struct bcma_drv
464 bcma_info(bus, "IRQ reconfiguration done\n");
465 bcma_core_mips_dump_irq(bus);
466
467 - if (mcore->setup_done)
468 - return;
469 -
470 - bcma_chipco_serial_init(&bus->drv_cc);
471 - bcma_core_mips_flash_detect(mcore);
472 mcore->setup_done = true;
473 }
474 --- a/drivers/bcma/driver_pci.c
475 +++ b/drivers/bcma/driver_pci.c
476 @@ -51,7 +51,7 @@ static void bcma_pcie_mdio_set_phy(struc
477 v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
478 if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE)
479 break;
480 - msleep(1);
481 + usleep_range(1000, 2000);
482 }
483 }
484
485 @@ -92,7 +92,7 @@ static u16 bcma_pcie_mdio_read(struct bc
486 ret = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_DATA);
487 break;
488 }
489 - msleep(1);
490 + usleep_range(1000, 2000);
491 }
492 pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0);
493 return ret;
494 @@ -132,7 +132,7 @@ static void bcma_pcie_mdio_write(struct
495 v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
496 if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE)
497 break;
498 - msleep(1);
499 + usleep_range(1000, 2000);
500 }
501 pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0);
502 }
503 --- a/drivers/bcma/driver_pci_host.c
504 +++ b/drivers/bcma/driver_pci_host.c
505 @@ -35,11 +35,6 @@ bool __devinit bcma_core_pci_is_in_hostm
506 chipid_top != 0x5300)
507 return false;
508
509 - if (bus->sprom.boardflags_lo & BCMA_CORE_PCI_BFL_NOPCI) {
510 - bcma_info(bus, "This PCI core is disabled and not working\n");
511 - return false;
512 - }
513 -
514 bcma_core_enable(pc->core, 0);
515
516 return !mips_busprobe32(tmp, pc->core->io_addr);
517 @@ -396,6 +391,11 @@ void __devinit bcma_core_pci_hostmode_in
518
519 bcma_info(bus, "PCIEcore in host mode found\n");
520
521 + if (bus->sprom.boardflags_lo & BCMA_CORE_PCI_BFL_NOPCI) {
522 + bcma_info(bus, "This PCIE core is disabled and not working\n");
523 + return;
524 + }
525 +
526 pc_host = kzalloc(sizeof(*pc_host), GFP_KERNEL);
527 if (!pc_host) {
528 bcma_err(bus, "can not allocate memory");
529 @@ -425,9 +425,9 @@ void __devinit bcma_core_pci_hostmode_in
530 pc_host->io_resource.flags = IORESOURCE_IO | IORESOURCE_PCI_FIXED;
531
532 /* Reset RC */
533 - udelay(3000);
534 + usleep_range(3000, 5000);
535 pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST_OE);
536 - udelay(1000);
537 + usleep_range(1000, 2000);
538 pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST |
539 BCMA_CORE_PCI_CTL_RST_OE);
540
541 @@ -452,6 +452,8 @@ void __devinit bcma_core_pci_hostmode_in
542 pc_host->mem_resource.start = BCMA_SOC_PCI_MEM;
543 pc_host->mem_resource.end = BCMA_SOC_PCI_MEM +
544 BCMA_SOC_PCI_MEM_SZ - 1;
545 + pc_host->io_resource.start = 0x100;
546 + pc_host->io_resource.end = 0x47F;
547 pci_membase_1G = BCMA_SOC_PCIE_DMA_H32;
548 pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
549 tmp | BCMA_SOC_PCI_MEM);
550 @@ -459,6 +461,8 @@ void __devinit bcma_core_pci_hostmode_in
551 pc_host->mem_resource.start = BCMA_SOC_PCI1_MEM;
552 pc_host->mem_resource.end = BCMA_SOC_PCI1_MEM +
553 BCMA_SOC_PCI_MEM_SZ - 1;
554 + pc_host->io_resource.start = 0x480;
555 + pc_host->io_resource.end = 0x7FF;
556 pci_membase_1G = BCMA_SOC_PCIE1_DMA_H32;
557 pc_host->host_cfg_addr = BCMA_SOC_PCI1_CFG;
558 pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
559 @@ -481,7 +485,7 @@ void __devinit bcma_core_pci_hostmode_in
560 * before issuing configuration requests to PCI Express
561 * devices.
562 */
563 - udelay(100000);
564 + msleep(100);
565
566 bcma_core_pci_enable_crs(pc);
567
568 @@ -501,7 +505,7 @@ void __devinit bcma_core_pci_hostmode_in
569 set_io_port_base(pc_host->pci_controller.io_map_base);
570 /* Give some time to the PCI controller to configure itself with the new
571 * values. Not waiting at this point causes crashes of the machine. */
572 - mdelay(10);
573 + usleep_range(10000, 15000);
574 register_pci_controller(&pc_host->pci_controller);
575 return;
576 }
577 --- a/drivers/bcma/host_pci.c
578 +++ b/drivers/bcma/host_pci.c
579 @@ -77,8 +77,8 @@ static void bcma_host_pci_write32(struct
580 }
581
582 #ifdef CONFIG_BCMA_BLOCKIO
583 -void bcma_host_pci_block_read(struct bcma_device *core, void *buffer,
584 - size_t count, u16 offset, u8 reg_width)
585 +static void bcma_host_pci_block_read(struct bcma_device *core, void *buffer,
586 + size_t count, u16 offset, u8 reg_width)
587 {
588 void __iomem *addr = core->bus->mmio + offset;
589 if (core->bus->mapped_core != core)
590 @@ -100,8 +100,9 @@ void bcma_host_pci_block_read(struct bcm
591 }
592 }
593
594 -void bcma_host_pci_block_write(struct bcma_device *core, const void *buffer,
595 - size_t count, u16 offset, u8 reg_width)
596 +static void bcma_host_pci_block_write(struct bcma_device *core,
597 + const void *buffer, size_t count,
598 + u16 offset, u8 reg_width)
599 {
600 void __iomem *addr = core->bus->mmio + offset;
601 if (core->bus->mapped_core != core)
602 @@ -139,7 +140,7 @@ static void bcma_host_pci_awrite32(struc
603 iowrite32(value, core->bus->mmio + (1 * BCMA_CORE_SIZE) + offset);
604 }
605
606 -const struct bcma_host_ops bcma_host_pci_ops = {
607 +static const struct bcma_host_ops bcma_host_pci_ops = {
608 .read8 = bcma_host_pci_read8,
609 .read16 = bcma_host_pci_read16,
610 .read32 = bcma_host_pci_read32,
611 @@ -272,6 +273,7 @@ static DEFINE_PCI_DEVICE_TABLE(bcma_pci_
612 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4331) },
613 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4353) },
614 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4357) },
615 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4358) },
616 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4359) },
617 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4727) },
618 { 0, },
619 --- a/drivers/bcma/host_soc.c
620 +++ b/drivers/bcma/host_soc.c
621 @@ -143,7 +143,7 @@ static void bcma_host_soc_awrite32(struc
622 writel(value, core->io_wrap + offset);
623 }
624
625 -const struct bcma_host_ops bcma_host_soc_ops = {
626 +static const struct bcma_host_ops bcma_host_soc_ops = {
627 .read8 = bcma_host_soc_read8,
628 .read16 = bcma_host_soc_read16,
629 .read32 = bcma_host_soc_read32,
630 --- a/drivers/bcma/main.c
631 +++ b/drivers/bcma/main.c
632 @@ -7,6 +7,7 @@
633
634 #include "bcma_private.h"
635 #include <linux/module.h>
636 +#include <linux/platform_device.h>
637 #include <linux/bcma/bcma.h>
638 #include <linux/slab.h>
639
640 @@ -80,6 +81,18 @@ struct bcma_device *bcma_find_core(struc
641 }
642 EXPORT_SYMBOL_GPL(bcma_find_core);
643
644 +static struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
645 + u8 unit)
646 +{
647 + struct bcma_device *core;
648 +
649 + list_for_each_entry(core, &bus->cores, list) {
650 + if (core->id.id == coreid && core->core_unit == unit)
651 + return core;
652 + }
653 + return NULL;
654 +}
655 +
656 static void bcma_release_core_dev(struct device *dev)
657 {
658 struct bcma_device *core = container_of(dev, struct bcma_device, dev);
659 @@ -136,6 +149,22 @@ static int bcma_register_cores(struct bc
660 dev_id++;
661 }
662
663 +#ifdef CONFIG_BCMA_SFLASH
664 + if (bus->drv_cc.sflash.present) {
665 + err = platform_device_register(&bcma_sflash_dev);
666 + if (err)
667 + bcma_err(bus, "Error registering serial flash\n");
668 + }
669 +#endif
670 +
671 +#ifdef CONFIG_BCMA_NFLASH
672 + if (bus->drv_cc.nflash.present) {
673 + err = platform_device_register(&bcma_nflash_dev);
674 + if (err)
675 + bcma_err(bus, "Error registering NAND flash\n");
676 + }
677 +#endif
678 +
679 return 0;
680 }
681
682 @@ -166,6 +195,20 @@ int __devinit bcma_bus_register(struct b
683 return -1;
684 }
685
686 + /* Early init CC core */
687 + core = bcma_find_core(bus, bcma_cc_core_id(bus));
688 + if (core) {
689 + bus->drv_cc.core = core;
690 + bcma_core_chipcommon_early_init(&bus->drv_cc);
691 + }
692 +
693 + /* Try to get SPROM */
694 + err = bcma_sprom_get(bus);
695 + if (err == -ENOENT) {
696 + bcma_err(bus, "No SPROM available\n");
697 + } else if (err)
698 + bcma_err(bus, "Failed to get SPROM: %d\n", err);
699 +
700 /* Init CC core */
701 core = bcma_find_core(bus, bcma_cc_core_id(bus));
702 if (core) {
703 @@ -181,10 +224,17 @@ int __devinit bcma_bus_register(struct b
704 }
705
706 /* Init PCIE core */
707 - core = bcma_find_core(bus, BCMA_CORE_PCIE);
708 + core = bcma_find_core_unit(bus, BCMA_CORE_PCIE, 0);
709 + if (core) {
710 + bus->drv_pci[0].core = core;
711 + bcma_core_pci_init(&bus->drv_pci[0]);
712 + }
713 +
714 + /* Init PCIE core */
715 + core = bcma_find_core_unit(bus, BCMA_CORE_PCIE, 1);
716 if (core) {
717 - bus->drv_pci.core = core;
718 - bcma_core_pci_init(&bus->drv_pci);
719 + bus->drv_pci[1].core = core;
720 + bcma_core_pci_init(&bus->drv_pci[1]);
721 }
722
723 /* Init GBIT MAC COMMON core */
724 @@ -194,13 +244,6 @@ int __devinit bcma_bus_register(struct b
725 bcma_core_gmac_cmn_init(&bus->drv_gmac_cmn);
726 }
727
728 - /* Try to get SPROM */
729 - err = bcma_sprom_get(bus);
730 - if (err == -ENOENT) {
731 - bcma_err(bus, "No SPROM available\n");
732 - } else if (err)
733 - bcma_err(bus, "Failed to get SPROM: %d\n", err);
734 -
735 /* Register found cores */
736 bcma_register_cores(bus);
737
738 @@ -211,7 +254,17 @@ int __devinit bcma_bus_register(struct b
739
740 void bcma_bus_unregister(struct bcma_bus *bus)
741 {
742 + struct bcma_device *cores[3];
743 +
744 + cores[0] = bcma_find_core(bus, BCMA_CORE_MIPS_74K);
745 + cores[1] = bcma_find_core(bus, BCMA_CORE_PCIE);
746 + cores[2] = bcma_find_core(bus, BCMA_CORE_4706_MAC_GBIT_COMMON);
747 +
748 bcma_unregister_cores(bus);
749 +
750 + kfree(cores[2]);
751 + kfree(cores[1]);
752 + kfree(cores[0]);
753 }
754
755 int __init bcma_bus_early_register(struct bcma_bus *bus,
756 @@ -248,18 +301,18 @@ int __init bcma_bus_early_register(struc
757 return -1;
758 }
759
760 - /* Init CC core */
761 + /* Early init CC core */
762 core = bcma_find_core(bus, bcma_cc_core_id(bus));
763 if (core) {
764 bus->drv_cc.core = core;
765 - bcma_core_chipcommon_init(&bus->drv_cc);
766 + bcma_core_chipcommon_early_init(&bus->drv_cc);
767 }
768
769 - /* Init MIPS core */
770 + /* Early init MIPS core */
771 core = bcma_find_core(bus, BCMA_CORE_MIPS_74K);
772 if (core) {
773 bus->drv_mips.core = core;
774 - bcma_core_mips_init(&bus->drv_mips);
775 + bcma_core_mips_early_init(&bus->drv_mips);
776 }
777
778 bcma_info(bus, "Early bus registered\n");
779 --- a/drivers/bcma/sprom.c
780 +++ b/drivers/bcma/sprom.c
781 @@ -507,7 +507,9 @@ static bool bcma_sprom_onchip_available(
782 /* for these chips OTP is always available */
783 present = true;
784 break;
785 + case BCMA_CHIP_ID_BCM43227:
786 case BCMA_CHIP_ID_BCM43228:
787 + case BCMA_CHIP_ID_BCM43428:
788 present = chip_status & BCMA_CC_CHIPST_43228_OTP_PRESENT;
789 break;
790 default:
791 @@ -593,8 +595,11 @@ int bcma_sprom_get(struct bcma_bus *bus)
792 bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, true);
793
794 err = bcma_sprom_valid(sprom);
795 - if (err)
796 + if (err) {
797 + bcma_warn(bus, "invalid sprom read from the PCIe card, try to use fallback sprom\n");
798 + err = bcma_fill_sprom_with_fallback(bus, &bus->sprom);
799 goto out;
800 + }
801
802 bcma_sprom_extract_r8(bus, sprom);
803
804 --- a/include/linux/bcma/bcma.h
805 +++ b/include/linux/bcma/bcma.h
806 @@ -10,7 +10,7 @@
807 #include <linux/bcma/bcma_driver_gmac_cmn.h>
808 #include <linux/ssb/ssb.h> /* SPROM sharing */
809
810 -#include "bcma_regs.h"
811 +#include <linux/bcma/bcma_regs.h>
812
813 struct bcma_device;
814 struct bcma_bus;
815 @@ -251,7 +251,7 @@ struct bcma_bus {
816 u8 num;
817
818 struct bcma_drv_cc drv_cc;
819 - struct bcma_drv_pci drv_pci;
820 + struct bcma_drv_pci drv_pci[2];
821 struct bcma_drv_mips drv_mips;
822 struct bcma_drv_gmac_cmn drv_gmac_cmn;
823
824 --- a/include/linux/bcma/bcma_driver_chipcommon.h
825 +++ b/include/linux/bcma/bcma_driver_chipcommon.h
826 @@ -100,6 +100,7 @@
827 #define BCMA_CC_CHIPST_4706_SFLASH_TYPE BIT(2) /* 0: 8b-p/ST-s flash, 1: 16b-p/Atmal-s flash */
828 #define BCMA_CC_CHIPST_4706_MIPS_BENDIAN BIT(3) /* 0: little, 1: big endian */
829 #define BCMA_CC_CHIPST_4706_PCIE1_DISABLE BIT(5) /* PCIE1 enable strap pin */
830 +#define BCMA_CC_CHIPST_5357_NAND_BOOT BIT(4) /* NAND boot, valid for CC rev 38 and/or BCM5357 */
831 #define BCMA_CC_JCMD 0x0030 /* Rev >= 10 only */
832 #define BCMA_CC_JCMD_START 0x80000000
833 #define BCMA_CC_JCMD_BUSY 0x80000000
834 @@ -266,6 +267,29 @@
835 #define BCMA_CC_SROM_CONTROL_SIZE_16K 0x00000004
836 #define BCMA_CC_SROM_CONTROL_SIZE_SHIFT 1
837 #define BCMA_CC_SROM_CONTROL_PRESENT 0x00000001
838 +/* Block 0x140 - 0x190 registers are chipset specific */
839 +#define BCMA_CC_4706_FLASHSCFG 0x18C /* Flash struct configuration */
840 +#define BCMA_CC_4706_FLASHSCFG_MASK 0x000000ff
841 +#define BCMA_CC_4706_FLASHSCFG_SF1 0x00000001 /* 2nd serial flash present */
842 +#define BCMA_CC_4706_FLASHSCFG_PF1 0x00000002 /* 2nd parallel flash present */
843 +#define BCMA_CC_4706_FLASHSCFG_SF1_TYPE 0x00000004 /* 2nd serial flash type : 0 : ST, 1 : Atmel */
844 +#define BCMA_CC_4706_FLASHSCFG_NF1 0x00000008 /* 2nd NAND flash present */
845 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_MASK 0x000000f0
846 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_4MB 0x00000010 /* 4MB */
847 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_8MB 0x00000020 /* 8MB */
848 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_16MB 0x00000030 /* 16MB */
849 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_32MB 0x00000040 /* 32MB */
850 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_64MB 0x00000050 /* 64MB */
851 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_128MB 0x00000060 /* 128MB */
852 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_256MB 0x00000070 /* 256MB */
853 +/* NAND flash registers for BCM4706 (corerev = 31) */
854 +#define BCMA_CC_NFLASH_CTL 0x01A0
855 +#define BCMA_CC_NFLASH_CTL_ERR 0x08000000
856 +#define BCMA_CC_NFLASH_CONF 0x01A4
857 +#define BCMA_CC_NFLASH_COL_ADDR 0x01A8
858 +#define BCMA_CC_NFLASH_ROW_ADDR 0x01AC
859 +#define BCMA_CC_NFLASH_DATA 0x01B0
860 +#define BCMA_CC_NFLASH_WAITCNT0 0x01B4
861 /* 0x1E0 is defined as shared BCMA_CLKCTLST */
862 #define BCMA_CC_HW_WORKAROUND 0x01E4 /* Hardware workaround (rev >= 20) */
863 #define BCMA_CC_UART0_DATA 0x0300
864 @@ -325,6 +349,60 @@
865 #define BCMA_CC_PLLCTL_ADDR 0x0660
866 #define BCMA_CC_PLLCTL_DATA 0x0664
867 #define BCMA_CC_SPROM 0x0800 /* SPROM beginning */
868 +/* NAND flash MLC controller registers (corerev >= 38) */
869 +#define BCMA_CC_NAND_REVISION 0x0C00
870 +#define BCMA_CC_NAND_CMD_START 0x0C04
871 +#define BCMA_CC_NAND_CMD_ADDR_X 0x0C08
872 +#define BCMA_CC_NAND_CMD_ADDR 0x0C0C
873 +#define BCMA_CC_NAND_CMD_END_ADDR 0x0C10
874 +#define BCMA_CC_NAND_CS_NAND_SELECT 0x0C14
875 +#define BCMA_CC_NAND_CS_NAND_XOR 0x0C18
876 +#define BCMA_CC_NAND_SPARE_RD0 0x0C20
877 +#define BCMA_CC_NAND_SPARE_RD4 0x0C24
878 +#define BCMA_CC_NAND_SPARE_RD8 0x0C28
879 +#define BCMA_CC_NAND_SPARE_RD12 0x0C2C
880 +#define BCMA_CC_NAND_SPARE_WR0 0x0C30
881 +#define BCMA_CC_NAND_SPARE_WR4 0x0C34
882 +#define BCMA_CC_NAND_SPARE_WR8 0x0C38
883 +#define BCMA_CC_NAND_SPARE_WR12 0x0C3C
884 +#define BCMA_CC_NAND_ACC_CONTROL 0x0C40
885 +#define BCMA_CC_NAND_CONFIG 0x0C48
886 +#define BCMA_CC_NAND_TIMING_1 0x0C50
887 +#define BCMA_CC_NAND_TIMING_2 0x0C54
888 +#define BCMA_CC_NAND_SEMAPHORE 0x0C58
889 +#define BCMA_CC_NAND_DEVID 0x0C60
890 +#define BCMA_CC_NAND_DEVID_X 0x0C64
891 +#define BCMA_CC_NAND_BLOCK_LOCK_STATUS 0x0C68
892 +#define BCMA_CC_NAND_INTFC_STATUS 0x0C6C
893 +#define BCMA_CC_NAND_ECC_CORR_ADDR_X 0x0C70
894 +#define BCMA_CC_NAND_ECC_CORR_ADDR 0x0C74
895 +#define BCMA_CC_NAND_ECC_UNC_ADDR_X 0x0C78
896 +#define BCMA_CC_NAND_ECC_UNC_ADDR 0x0C7C
897 +#define BCMA_CC_NAND_READ_ERROR_COUNT 0x0C80
898 +#define BCMA_CC_NAND_CORR_STAT_THRESHOLD 0x0C84
899 +#define BCMA_CC_NAND_READ_ADDR_X 0x0C90
900 +#define BCMA_CC_NAND_READ_ADDR 0x0C94
901 +#define BCMA_CC_NAND_PAGE_PROGRAM_ADDR_X 0x0C98
902 +#define BCMA_CC_NAND_PAGE_PROGRAM_ADDR 0x0C9C
903 +#define BCMA_CC_NAND_COPY_BACK_ADDR_X 0x0CA0
904 +#define BCMA_CC_NAND_COPY_BACK_ADDR 0x0CA4
905 +#define BCMA_CC_NAND_BLOCK_ERASE_ADDR_X 0x0CA8
906 +#define BCMA_CC_NAND_BLOCK_ERASE_ADDR 0x0CAC
907 +#define BCMA_CC_NAND_INV_READ_ADDR_X 0x0CB0
908 +#define BCMA_CC_NAND_INV_READ_ADDR 0x0CB4
909 +#define BCMA_CC_NAND_BLK_WR_PROTECT 0x0CC0
910 +#define BCMA_CC_NAND_ACC_CONTROL_CS1 0x0CD0
911 +#define BCMA_CC_NAND_CONFIG_CS1 0x0CD4
912 +#define BCMA_CC_NAND_TIMING_1_CS1 0x0CD8
913 +#define BCMA_CC_NAND_TIMING_2_CS1 0x0CDC
914 +#define BCMA_CC_NAND_SPARE_RD16 0x0D30
915 +#define BCMA_CC_NAND_SPARE_RD20 0x0D34
916 +#define BCMA_CC_NAND_SPARE_RD24 0x0D38
917 +#define BCMA_CC_NAND_SPARE_RD28 0x0D3C
918 +#define BCMA_CC_NAND_CACHE_ADDR 0x0D40
919 +#define BCMA_CC_NAND_CACHE_DATA 0x0D44
920 +#define BCMA_CC_NAND_CTRL_CONFIG 0x0D48
921 +#define BCMA_CC_NAND_CTRL_STATUS 0x0D4C
922
923 /* Divider allocation in 4716/47162/5356 */
924 #define BCMA_CC_PMU5_MAINPLL_CPU 1
925 @@ -415,6 +493,13 @@
926 /* 4313 Chip specific ChipControl register bits */
927 #define BCMA_CCTRL_4313_12MA_LED_DRIVE 0x00000007 /* 12 mA drive strengh for later 4313 */
928
929 +/* BCM5357 ChipControl register bits */
930 +#define BCMA_CHIPCTL_5357_EXTPA BIT(14)
931 +#define BCMA_CHIPCTL_5357_ANT_MUX_2O3 BIT(15)
932 +#define BCMA_CHIPCTL_5357_NFLASH BIT(16)
933 +#define BCMA_CHIPCTL_5357_I2S_PINS_ENABLE BIT(18)
934 +#define BCMA_CHIPCTL_5357_I2CSPI_PINS_ENABLE BIT(19)
935 +
936 /* Data for the PMU, if available.
937 * Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU)
938 */
939 @@ -425,11 +510,35 @@ struct bcma_chipcommon_pmu {
940
941 #ifdef CONFIG_BCMA_DRIVER_MIPS
942 struct bcma_pflash {
943 + bool present;
944 u8 buswidth;
945 u32 window;
946 u32 window_size;
947 };
948
949 +#ifdef CONFIG_BCMA_SFLASH
950 +struct bcma_sflash {
951 + bool present;
952 + u32 window;
953 + u32 blocksize;
954 + u16 numblocks;
955 + u32 size;
956 +
957 + struct mtd_info *mtd;
958 +};
959 +#endif
960 +
961 +#ifdef CONFIG_BCMA_NFLASH
962 +struct mtd_info;
963 +
964 +struct bcma_nflash {
965 + bool present;
966 + bool boot; /* This is the flash the SoC boots from */
967 +
968 + struct mtd_info *mtd;
969 +};
970 +#endif
971 +
972 struct bcma_serial_port {
973 void *regs;
974 unsigned long clockspeed;
975 @@ -445,11 +554,18 @@ struct bcma_drv_cc {
976 u32 capabilities;
977 u32 capabilities_ext;
978 u8 setup_done:1;
979 + u8 early_setup_done:1;
980 /* Fast Powerup Delay constant */
981 u16 fast_pwrup_delay;
982 struct bcma_chipcommon_pmu pmu;
983 #ifdef CONFIG_BCMA_DRIVER_MIPS
984 struct bcma_pflash pflash;
985 +#ifdef CONFIG_BCMA_SFLASH
986 + struct bcma_sflash sflash;
987 +#endif
988 +#ifdef CONFIG_BCMA_NFLASH
989 + struct bcma_nflash nflash;
990 +#endif
991
992 int nr_serial_ports;
993 struct bcma_serial_port serial_ports[4];
994 @@ -470,6 +586,7 @@ struct bcma_drv_cc {
995 bcma_cc_write32(cc, offset, (bcma_cc_read32(cc, offset) & (mask)) | (set))
996
997 extern void bcma_core_chipcommon_init(struct bcma_drv_cc *cc);
998 +extern void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc);
999
1000 extern void bcma_chipco_suspend(struct bcma_drv_cc *cc);
1001 extern void bcma_chipco_resume(struct bcma_drv_cc *cc);
1002 @@ -493,6 +610,7 @@ u32 bcma_chipco_gpio_polarity(struct bcm
1003
1004 /* PMU support */
1005 extern void bcma_pmu_init(struct bcma_drv_cc *cc);
1006 +extern void bcma_pmu_early_init(struct bcma_drv_cc *cc);
1007
1008 extern void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset,
1009 u32 value);
1010 --- a/include/linux/bcma/bcma_driver_mips.h
1011 +++ b/include/linux/bcma/bcma_driver_mips.h
1012 @@ -35,13 +35,16 @@ struct bcma_device;
1013 struct bcma_drv_mips {
1014 struct bcma_device *core;
1015 u8 setup_done:1;
1016 + u8 early_setup_done:1;
1017 unsigned int assigned_irqs;
1018 };
1019
1020 #ifdef CONFIG_BCMA_DRIVER_MIPS
1021 extern void bcma_core_mips_init(struct bcma_drv_mips *mcore);
1022 +extern void bcma_core_mips_early_init(struct bcma_drv_mips *mcore);
1023 #else
1024 static inline void bcma_core_mips_init(struct bcma_drv_mips *mcore) { }
1025 +static inline void bcma_core_mips_early_init(struct bcma_drv_mips *mcore) { }
1026 #endif
1027
1028 extern u32 bcma_cpu_clock(struct bcma_drv_mips *mcore);
1029 --- a/include/linux/bcma/bcma_regs.h
1030 +++ b/include/linux/bcma/bcma_regs.h
1031 @@ -11,11 +11,13 @@
1032 #define BCMA_CLKCTLST_HAVEHTREQ 0x00000010 /* HT available request */
1033 #define BCMA_CLKCTLST_HWCROFF 0x00000020 /* Force HW clock request off */
1034 #define BCMA_CLKCTLST_EXTRESREQ 0x00000700 /* Mask of external resource requests */
1035 +#define BCMA_CLKCTLST_EXTRESREQ_SHIFT 8
1036 #define BCMA_CLKCTLST_HAVEALP 0x00010000 /* ALP available */
1037 #define BCMA_CLKCTLST_HAVEHT 0x00020000 /* HT available */
1038 #define BCMA_CLKCTLST_BP_ON_ALP 0x00040000 /* RO: running on ALP clock */
1039 #define BCMA_CLKCTLST_BP_ON_HT 0x00080000 /* RO: running on HT clock */
1040 #define BCMA_CLKCTLST_EXTRESST 0x07000000 /* Mask of external resource status */
1041 +#define BCMA_CLKCTLST_EXTRESST_SHIFT 24
1042 /* Is there any BCM4328 on BCMA bus? */
1043 #define BCMA_CLKCTLST_4328A0_HAVEHT 0x00010000 /* 4328a0 has reversed bits */
1044 #define BCMA_CLKCTLST_4328A0_HAVEALP 0x00020000 /* 4328a0 has reversed bits */
1045 @@ -83,4 +85,9 @@
1046 * (2 ZettaBytes), high 32 bits
1047 */
1048
1049 +#define BCMA_SOC_FLASH1 0x1fc00000 /* MIPS Flash Region 1 */
1050 +#define BCMA_SOC_FLASH1_SZ 0x00400000 /* MIPS Size of Flash Region 1 */
1051 +#define BCMA_SOC_FLASH2 0x1c000000 /* Flash Region 2 (region 1 shadowed here) */
1052 +#define BCMA_SOC_FLASH2_SZ 0x02000000 /* Size of Flash Region 2 */
1053 +
1054 #endif /* LINUX_BCMA_REGS_H_ */
1055 --- a/drivers/net/wireless/b43/main.c
1056 +++ b/drivers/net/wireless/b43/main.c
1057 @@ -4622,7 +4622,7 @@ static int b43_wireless_core_init(struct
1058 switch (dev->dev->bus_type) {
1059 #ifdef CONFIG_B43_BCMA
1060 case B43_BUS_BCMA:
1061 - bcma_core_pci_irq_ctl(&dev->dev->bdev->bus->drv_pci,
1062 + bcma_core_pci_irq_ctl(&dev->dev->bdev->bus->drv_pci[0],
1063 dev->dev->bdev, true);
1064 break;
1065 #endif
1066 --- a/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c
1067 +++ b/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c
1068 @@ -695,7 +695,7 @@ void ai_pci_up(struct si_pub *sih)
1069 sii = container_of(sih, struct si_info, pub);
1070
1071 if (sii->icbus->hosttype == BCMA_HOSTTYPE_PCI)
1072 - bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci, true);
1073 + bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci[0], true);
1074 }
1075
1076 /* Unconfigure and/or apply various WARs when going down */
1077 @@ -706,7 +706,7 @@ void ai_pci_down(struct si_pub *sih)
1078 sii = container_of(sih, struct si_info, pub);
1079
1080 if (sii->icbus->hosttype == BCMA_HOSTTYPE_PCI)
1081 - bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci, false);
1082 + bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci[0], false);
1083 }
1084
1085 /* Enable BT-COEX & Ex-PA for 4313 */
1086 --- a/drivers/net/wireless/brcm80211/brcmsmac/main.c
1087 +++ b/drivers/net/wireless/brcm80211/brcmsmac/main.c
1088 @@ -5077,7 +5077,7 @@ static int brcms_b_up_prep(struct brcms_
1089 * Configure pci/pcmcia here instead of in brcms_c_attach()
1090 * to allow mfg hotswap: down, hotswap (chip power cycle), up.
1091 */
1092 - bcma_core_pci_irq_ctl(&wlc_hw->d11core->bus->drv_pci, wlc_hw->d11core,
1093 + bcma_core_pci_irq_ctl(&wlc_hw->d11core->bus->drv_pci[0], wlc_hw->d11core,
1094 true);
1095
1096 /*
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